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cpu: Turn cpu_has_work() into a CPUClass hook
[mirror_qemu.git] / target-i386 / seg_helper.c
1 /*
2 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
4 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "qemu/log.h"
23 #include "helper.h"
24
25 //#define DEBUG_PCALL
26
27 #if !defined(CONFIG_USER_ONLY)
28 #include "exec/softmmu_exec.h"
29 #endif /* !defined(CONFIG_USER_ONLY) */
30
31 #ifdef DEBUG_PCALL
32 # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
33 # define LOG_PCALL_STATE(cpu) \
34 log_cpu_state_mask(CPU_LOG_PCALL, (cpu), CPU_DUMP_CCOP)
35 #else
36 # define LOG_PCALL(...) do { } while (0)
37 # define LOG_PCALL_STATE(cpu) do { } while (0)
38 #endif
39
40 /* return non zero if error */
41 static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr,
42 uint32_t *e2_ptr, int selector)
43 {
44 SegmentCache *dt;
45 int index;
46 target_ulong ptr;
47
48 if (selector & 0x4) {
49 dt = &env->ldt;
50 } else {
51 dt = &env->gdt;
52 }
53 index = selector & ~7;
54 if ((index + 7) > dt->limit) {
55 return -1;
56 }
57 ptr = dt->base + index;
58 *e1_ptr = cpu_ldl_kernel(env, ptr);
59 *e2_ptr = cpu_ldl_kernel(env, ptr + 4);
60 return 0;
61 }
62
63 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
64 {
65 unsigned int limit;
66
67 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
68 if (e2 & DESC_G_MASK) {
69 limit = (limit << 12) | 0xfff;
70 }
71 return limit;
72 }
73
74 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
75 {
76 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000);
77 }
78
79 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
80 uint32_t e2)
81 {
82 sc->base = get_seg_base(e1, e2);
83 sc->limit = get_seg_limit(e1, e2);
84 sc->flags = e2;
85 }
86
87 /* init the segment cache in vm86 mode. */
88 static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
89 {
90 selector &= 0xffff;
91 cpu_x86_load_seg_cache(env, seg, selector,
92 (selector << 4), 0xffff, 0);
93 }
94
95 static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
96 uint32_t *esp_ptr, int dpl)
97 {
98 int type, index, shift;
99
100 #if 0
101 {
102 int i;
103 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
104 for (i = 0; i < env->tr.limit; i++) {
105 printf("%02x ", env->tr.base[i]);
106 if ((i & 7) == 7) {
107 printf("\n");
108 }
109 }
110 printf("\n");
111 }
112 #endif
113
114 if (!(env->tr.flags & DESC_P_MASK)) {
115 cpu_abort(env, "invalid tss");
116 }
117 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
118 if ((type & 7) != 1) {
119 cpu_abort(env, "invalid tss type");
120 }
121 shift = type >> 3;
122 index = (dpl * 4 + 2) << shift;
123 if (index + (4 << shift) - 1 > env->tr.limit) {
124 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
125 }
126 if (shift == 0) {
127 *esp_ptr = cpu_lduw_kernel(env, env->tr.base + index);
128 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2);
129 } else {
130 *esp_ptr = cpu_ldl_kernel(env, env->tr.base + index);
131 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4);
132 }
133 }
134
135 /* XXX: merge with load_seg() */
136 static void tss_load_seg(CPUX86State *env, int seg_reg, int selector)
137 {
138 uint32_t e1, e2;
139 int rpl, dpl, cpl;
140
141 if ((selector & 0xfffc) != 0) {
142 if (load_segment(env, &e1, &e2, selector) != 0) {
143 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
144 }
145 if (!(e2 & DESC_S_MASK)) {
146 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
147 }
148 rpl = selector & 3;
149 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
150 cpl = env->hflags & HF_CPL_MASK;
151 if (seg_reg == R_CS) {
152 if (!(e2 & DESC_CS_MASK)) {
153 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
154 }
155 /* XXX: is it correct? */
156 if (dpl != rpl) {
157 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
158 }
159 if ((e2 & DESC_C_MASK) && dpl > rpl) {
160 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
161 }
162 } else if (seg_reg == R_SS) {
163 /* SS must be writable data */
164 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
165 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
166 }
167 if (dpl != cpl || dpl != rpl) {
168 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
169 }
170 } else {
171 /* not readable code */
172 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
173 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
174 }
175 /* if data or non conforming code, checks the rights */
176 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
177 if (dpl < cpl || dpl < rpl) {
178 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
179 }
180 }
181 }
182 if (!(e2 & DESC_P_MASK)) {
183 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
184 }
185 cpu_x86_load_seg_cache(env, seg_reg, selector,
186 get_seg_base(e1, e2),
187 get_seg_limit(e1, e2),
188 e2);
189 } else {
190 if (seg_reg == R_SS || seg_reg == R_CS) {
191 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
192 }
193 }
194 }
195
196 #define SWITCH_TSS_JMP 0
197 #define SWITCH_TSS_IRET 1
198 #define SWITCH_TSS_CALL 2
199
200 /* XXX: restore CPU state in registers (PowerPC case) */
201 static void switch_tss(CPUX86State *env, int tss_selector,
202 uint32_t e1, uint32_t e2, int source,
203 uint32_t next_eip)
204 {
205 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
206 target_ulong tss_base;
207 uint32_t new_regs[8], new_segs[6];
208 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
209 uint32_t old_eflags, eflags_mask;
210 SegmentCache *dt;
211 int index;
212 target_ulong ptr;
213
214 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
215 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
216 source);
217
218 /* if task gate, we read the TSS segment and we load it */
219 if (type == 5) {
220 if (!(e2 & DESC_P_MASK)) {
221 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
222 }
223 tss_selector = e1 >> 16;
224 if (tss_selector & 4) {
225 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
226 }
227 if (load_segment(env, &e1, &e2, tss_selector) != 0) {
228 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
229 }
230 if (e2 & DESC_S_MASK) {
231 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
232 }
233 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
234 if ((type & 7) != 1) {
235 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
236 }
237 }
238
239 if (!(e2 & DESC_P_MASK)) {
240 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
241 }
242
243 if (type & 8) {
244 tss_limit_max = 103;
245 } else {
246 tss_limit_max = 43;
247 }
248 tss_limit = get_seg_limit(e1, e2);
249 tss_base = get_seg_base(e1, e2);
250 if ((tss_selector & 4) != 0 ||
251 tss_limit < tss_limit_max) {
252 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
253 }
254 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
255 if (old_type & 8) {
256 old_tss_limit_max = 103;
257 } else {
258 old_tss_limit_max = 43;
259 }
260
261 /* read all the registers from the new TSS */
262 if (type & 8) {
263 /* 32 bit */
264 new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c);
265 new_eip = cpu_ldl_kernel(env, tss_base + 0x20);
266 new_eflags = cpu_ldl_kernel(env, tss_base + 0x24);
267 for (i = 0; i < 8; i++) {
268 new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4));
269 }
270 for (i = 0; i < 6; i++) {
271 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4));
272 }
273 new_ldt = cpu_lduw_kernel(env, tss_base + 0x60);
274 new_trap = cpu_ldl_kernel(env, tss_base + 0x64);
275 } else {
276 /* 16 bit */
277 new_cr3 = 0;
278 new_eip = cpu_lduw_kernel(env, tss_base + 0x0e);
279 new_eflags = cpu_lduw_kernel(env, tss_base + 0x10);
280 for (i = 0; i < 8; i++) {
281 new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) |
282 0xffff0000;
283 }
284 for (i = 0; i < 4; i++) {
285 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4));
286 }
287 new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a);
288 new_segs[R_FS] = 0;
289 new_segs[R_GS] = 0;
290 new_trap = 0;
291 }
292 /* XXX: avoid a compiler warning, see
293 http://support.amd.com/us/Processor_TechDocs/24593.pdf
294 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
295 (void)new_trap;
296
297 /* NOTE: we must avoid memory exceptions during the task switch,
298 so we make dummy accesses before */
299 /* XXX: it can still fail in some cases, so a bigger hack is
300 necessary to valid the TLB after having done the accesses */
301
302 v1 = cpu_ldub_kernel(env, env->tr.base);
303 v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max);
304 cpu_stb_kernel(env, env->tr.base, v1);
305 cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2);
306
307 /* clear busy bit (it is restartable) */
308 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
309 target_ulong ptr;
310 uint32_t e2;
311
312 ptr = env->gdt.base + (env->tr.selector & ~7);
313 e2 = cpu_ldl_kernel(env, ptr + 4);
314 e2 &= ~DESC_TSS_BUSY_MASK;
315 cpu_stl_kernel(env, ptr + 4, e2);
316 }
317 old_eflags = cpu_compute_eflags(env);
318 if (source == SWITCH_TSS_IRET) {
319 old_eflags &= ~NT_MASK;
320 }
321
322 /* save the current state in the old TSS */
323 if (type & 8) {
324 /* 32 bit */
325 cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
326 cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
327 cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]);
328 cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
329 cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
330 cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
331 cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]);
332 cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
333 cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI]);
334 cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI]);
335 for (i = 0; i < 6; i++) {
336 cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4),
337 env->segs[i].selector);
338 }
339 } else {
340 /* 16 bit */
341 cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
342 cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
343 cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]);
344 cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
345 cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
346 cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
347 cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]);
348 cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
349 cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI]);
350 cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI]);
351 for (i = 0; i < 4; i++) {
352 cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4),
353 env->segs[i].selector);
354 }
355 }
356
357 /* now if an exception occurs, it will occurs in the next task
358 context */
359
360 if (source == SWITCH_TSS_CALL) {
361 cpu_stw_kernel(env, tss_base, env->tr.selector);
362 new_eflags |= NT_MASK;
363 }
364
365 /* set busy bit */
366 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
367 target_ulong ptr;
368 uint32_t e2;
369
370 ptr = env->gdt.base + (tss_selector & ~7);
371 e2 = cpu_ldl_kernel(env, ptr + 4);
372 e2 |= DESC_TSS_BUSY_MASK;
373 cpu_stl_kernel(env, ptr + 4, e2);
374 }
375
376 /* set the new CPU state */
377 /* from this point, any exception which occurs can give problems */
378 env->cr[0] |= CR0_TS_MASK;
379 env->hflags |= HF_TS_MASK;
380 env->tr.selector = tss_selector;
381 env->tr.base = tss_base;
382 env->tr.limit = tss_limit;
383 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
384
385 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
386 cpu_x86_update_cr3(env, new_cr3);
387 }
388
389 /* load all registers without an exception, then reload them with
390 possible exception */
391 env->eip = new_eip;
392 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
393 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
394 if (!(type & 8)) {
395 eflags_mask &= 0xffff;
396 }
397 cpu_load_eflags(env, new_eflags, eflags_mask);
398 /* XXX: what to do in 16 bit case? */
399 env->regs[R_EAX] = new_regs[0];
400 env->regs[R_ECX] = new_regs[1];
401 env->regs[R_EDX] = new_regs[2];
402 env->regs[R_EBX] = new_regs[3];
403 env->regs[R_ESP] = new_regs[4];
404 env->regs[R_EBP] = new_regs[5];
405 env->regs[R_ESI] = new_regs[6];
406 env->regs[R_EDI] = new_regs[7];
407 if (new_eflags & VM_MASK) {
408 for (i = 0; i < 6; i++) {
409 load_seg_vm(env, i, new_segs[i]);
410 }
411 /* in vm86, CPL is always 3 */
412 cpu_x86_set_cpl(env, 3);
413 } else {
414 /* CPL is set the RPL of CS */
415 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
416 /* first just selectors as the rest may trigger exceptions */
417 for (i = 0; i < 6; i++) {
418 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
419 }
420 }
421
422 env->ldt.selector = new_ldt & ~4;
423 env->ldt.base = 0;
424 env->ldt.limit = 0;
425 env->ldt.flags = 0;
426
427 /* load the LDT */
428 if (new_ldt & 4) {
429 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
430 }
431
432 if ((new_ldt & 0xfffc) != 0) {
433 dt = &env->gdt;
434 index = new_ldt & ~7;
435 if ((index + 7) > dt->limit) {
436 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
437 }
438 ptr = dt->base + index;
439 e1 = cpu_ldl_kernel(env, ptr);
440 e2 = cpu_ldl_kernel(env, ptr + 4);
441 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
442 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
443 }
444 if (!(e2 & DESC_P_MASK)) {
445 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
446 }
447 load_seg_cache_raw_dt(&env->ldt, e1, e2);
448 }
449
450 /* load the segments */
451 if (!(new_eflags & VM_MASK)) {
452 tss_load_seg(env, R_CS, new_segs[R_CS]);
453 tss_load_seg(env, R_SS, new_segs[R_SS]);
454 tss_load_seg(env, R_ES, new_segs[R_ES]);
455 tss_load_seg(env, R_DS, new_segs[R_DS]);
456 tss_load_seg(env, R_FS, new_segs[R_FS]);
457 tss_load_seg(env, R_GS, new_segs[R_GS]);
458 }
459
460 /* check that env->eip is in the CS segment limits */
461 if (new_eip > env->segs[R_CS].limit) {
462 /* XXX: different exception if CALL? */
463 raise_exception_err(env, EXCP0D_GPF, 0);
464 }
465
466 #ifndef CONFIG_USER_ONLY
467 /* reset local breakpoints */
468 if (env->dr[7] & DR7_LOCAL_BP_MASK) {
469 for (i = 0; i < DR7_MAX_BP; i++) {
470 if (hw_local_breakpoint_enabled(env->dr[7], i) &&
471 !hw_global_breakpoint_enabled(env->dr[7], i)) {
472 hw_breakpoint_remove(env, i);
473 }
474 }
475 env->dr[7] &= ~DR7_LOCAL_BP_MASK;
476 }
477 #endif
478 }
479
480 static inline unsigned int get_sp_mask(unsigned int e2)
481 {
482 if (e2 & DESC_B_MASK) {
483 return 0xffffffff;
484 } else {
485 return 0xffff;
486 }
487 }
488
489 static int exception_has_error_code(int intno)
490 {
491 switch (intno) {
492 case 8:
493 case 10:
494 case 11:
495 case 12:
496 case 13:
497 case 14:
498 case 17:
499 return 1;
500 }
501 return 0;
502 }
503
504 #ifdef TARGET_X86_64
505 #define SET_ESP(val, sp_mask) \
506 do { \
507 if ((sp_mask) == 0xffff) { \
508 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
509 ((val) & 0xffff); \
510 } else if ((sp_mask) == 0xffffffffLL) { \
511 env->regs[R_ESP] = (uint32_t)(val); \
512 } else { \
513 env->regs[R_ESP] = (val); \
514 } \
515 } while (0)
516 #else
517 #define SET_ESP(val, sp_mask) \
518 do { \
519 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
520 ((val) & (sp_mask)); \
521 } while (0)
522 #endif
523
524 /* in 64-bit machines, this can overflow. So this segment addition macro
525 * can be used to trim the value to 32-bit whenever needed */
526 #define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
527
528 /* XXX: add a is_user flag to have proper security support */
529 #define PUSHW(ssp, sp, sp_mask, val) \
530 { \
531 sp -= 2; \
532 cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \
533 }
534
535 #define PUSHL(ssp, sp, sp_mask, val) \
536 { \
537 sp -= 4; \
538 cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \
539 }
540
541 #define POPW(ssp, sp, sp_mask, val) \
542 { \
543 val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \
544 sp += 2; \
545 }
546
547 #define POPL(ssp, sp, sp_mask, val) \
548 { \
549 val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \
550 sp += 4; \
551 }
552
553 /* protected mode interrupt */
554 static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
555 int error_code, unsigned int next_eip,
556 int is_hw)
557 {
558 SegmentCache *dt;
559 target_ulong ptr, ssp;
560 int type, dpl, selector, ss_dpl, cpl;
561 int has_error_code, new_stack, shift;
562 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
563 uint32_t old_eip, sp_mask;
564
565 has_error_code = 0;
566 if (!is_int && !is_hw) {
567 has_error_code = exception_has_error_code(intno);
568 }
569 if (is_int) {
570 old_eip = next_eip;
571 } else {
572 old_eip = env->eip;
573 }
574
575 dt = &env->idt;
576 if (intno * 8 + 7 > dt->limit) {
577 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
578 }
579 ptr = dt->base + intno * 8;
580 e1 = cpu_ldl_kernel(env, ptr);
581 e2 = cpu_ldl_kernel(env, ptr + 4);
582 /* check gate type */
583 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
584 switch (type) {
585 case 5: /* task gate */
586 /* must do that check here to return the correct error code */
587 if (!(e2 & DESC_P_MASK)) {
588 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
589 }
590 switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
591 if (has_error_code) {
592 int type;
593 uint32_t mask;
594
595 /* push the error code */
596 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
597 shift = type >> 3;
598 if (env->segs[R_SS].flags & DESC_B_MASK) {
599 mask = 0xffffffff;
600 } else {
601 mask = 0xffff;
602 }
603 esp = (env->regs[R_ESP] - (2 << shift)) & mask;
604 ssp = env->segs[R_SS].base + esp;
605 if (shift) {
606 cpu_stl_kernel(env, ssp, error_code);
607 } else {
608 cpu_stw_kernel(env, ssp, error_code);
609 }
610 SET_ESP(esp, mask);
611 }
612 return;
613 case 6: /* 286 interrupt gate */
614 case 7: /* 286 trap gate */
615 case 14: /* 386 interrupt gate */
616 case 15: /* 386 trap gate */
617 break;
618 default:
619 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
620 break;
621 }
622 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
623 cpl = env->hflags & HF_CPL_MASK;
624 /* check privilege if software int */
625 if (is_int && dpl < cpl) {
626 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
627 }
628 /* check valid bit */
629 if (!(e2 & DESC_P_MASK)) {
630 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
631 }
632 selector = e1 >> 16;
633 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
634 if ((selector & 0xfffc) == 0) {
635 raise_exception_err(env, EXCP0D_GPF, 0);
636 }
637 if (load_segment(env, &e1, &e2, selector) != 0) {
638 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
639 }
640 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
641 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
642 }
643 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
644 if (dpl > cpl) {
645 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
646 }
647 if (!(e2 & DESC_P_MASK)) {
648 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
649 }
650 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
651 /* to inner privilege */
652 get_ss_esp_from_tss(env, &ss, &esp, dpl);
653 if ((ss & 0xfffc) == 0) {
654 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
655 }
656 if ((ss & 3) != dpl) {
657 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
658 }
659 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
660 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
661 }
662 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
663 if (ss_dpl != dpl) {
664 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
665 }
666 if (!(ss_e2 & DESC_S_MASK) ||
667 (ss_e2 & DESC_CS_MASK) ||
668 !(ss_e2 & DESC_W_MASK)) {
669 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
670 }
671 if (!(ss_e2 & DESC_P_MASK)) {
672 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
673 }
674 new_stack = 1;
675 sp_mask = get_sp_mask(ss_e2);
676 ssp = get_seg_base(ss_e1, ss_e2);
677 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
678 /* to same privilege */
679 if (env->eflags & VM_MASK) {
680 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
681 }
682 new_stack = 0;
683 sp_mask = get_sp_mask(env->segs[R_SS].flags);
684 ssp = env->segs[R_SS].base;
685 esp = env->regs[R_ESP];
686 dpl = cpl;
687 } else {
688 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
689 new_stack = 0; /* avoid warning */
690 sp_mask = 0; /* avoid warning */
691 ssp = 0; /* avoid warning */
692 esp = 0; /* avoid warning */
693 }
694
695 shift = type >> 3;
696
697 #if 0
698 /* XXX: check that enough room is available */
699 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
700 if (env->eflags & VM_MASK) {
701 push_size += 8;
702 }
703 push_size <<= shift;
704 #endif
705 if (shift == 1) {
706 if (new_stack) {
707 if (env->eflags & VM_MASK) {
708 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
709 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
710 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
711 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
712 }
713 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
714 PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
715 }
716 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
717 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
718 PUSHL(ssp, esp, sp_mask, old_eip);
719 if (has_error_code) {
720 PUSHL(ssp, esp, sp_mask, error_code);
721 }
722 } else {
723 if (new_stack) {
724 if (env->eflags & VM_MASK) {
725 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
726 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
727 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
728 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
729 }
730 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
731 PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
732 }
733 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
734 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
735 PUSHW(ssp, esp, sp_mask, old_eip);
736 if (has_error_code) {
737 PUSHW(ssp, esp, sp_mask, error_code);
738 }
739 }
740
741 if (new_stack) {
742 if (env->eflags & VM_MASK) {
743 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
744 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
745 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
746 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
747 }
748 ss = (ss & ~3) | dpl;
749 cpu_x86_load_seg_cache(env, R_SS, ss,
750 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
751 }
752 SET_ESP(esp, sp_mask);
753
754 selector = (selector & ~3) | dpl;
755 cpu_x86_load_seg_cache(env, R_CS, selector,
756 get_seg_base(e1, e2),
757 get_seg_limit(e1, e2),
758 e2);
759 cpu_x86_set_cpl(env, dpl);
760 env->eip = offset;
761
762 /* interrupt gate clear IF mask */
763 if ((type & 1) == 0) {
764 env->eflags &= ~IF_MASK;
765 }
766 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
767 }
768
769 #ifdef TARGET_X86_64
770
771 #define PUSHQ(sp, val) \
772 { \
773 sp -= 8; \
774 cpu_stq_kernel(env, sp, (val)); \
775 }
776
777 #define POPQ(sp, val) \
778 { \
779 val = cpu_ldq_kernel(env, sp); \
780 sp += 8; \
781 }
782
783 static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
784 {
785 int index;
786
787 #if 0
788 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
789 env->tr.base, env->tr.limit);
790 #endif
791
792 if (!(env->tr.flags & DESC_P_MASK)) {
793 cpu_abort(env, "invalid tss");
794 }
795 index = 8 * level + 4;
796 if ((index + 7) > env->tr.limit) {
797 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
798 }
799 return cpu_ldq_kernel(env, env->tr.base + index);
800 }
801
802 /* 64 bit interrupt */
803 static void do_interrupt64(CPUX86State *env, int intno, int is_int,
804 int error_code, target_ulong next_eip, int is_hw)
805 {
806 SegmentCache *dt;
807 target_ulong ptr;
808 int type, dpl, selector, cpl, ist;
809 int has_error_code, new_stack;
810 uint32_t e1, e2, e3, ss;
811 target_ulong old_eip, esp, offset;
812
813 has_error_code = 0;
814 if (!is_int && !is_hw) {
815 has_error_code = exception_has_error_code(intno);
816 }
817 if (is_int) {
818 old_eip = next_eip;
819 } else {
820 old_eip = env->eip;
821 }
822
823 dt = &env->idt;
824 if (intno * 16 + 15 > dt->limit) {
825 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
826 }
827 ptr = dt->base + intno * 16;
828 e1 = cpu_ldl_kernel(env, ptr);
829 e2 = cpu_ldl_kernel(env, ptr + 4);
830 e3 = cpu_ldl_kernel(env, ptr + 8);
831 /* check gate type */
832 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
833 switch (type) {
834 case 14: /* 386 interrupt gate */
835 case 15: /* 386 trap gate */
836 break;
837 default:
838 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
839 break;
840 }
841 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
842 cpl = env->hflags & HF_CPL_MASK;
843 /* check privilege if software int */
844 if (is_int && dpl < cpl) {
845 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
846 }
847 /* check valid bit */
848 if (!(e2 & DESC_P_MASK)) {
849 raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2);
850 }
851 selector = e1 >> 16;
852 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
853 ist = e2 & 7;
854 if ((selector & 0xfffc) == 0) {
855 raise_exception_err(env, EXCP0D_GPF, 0);
856 }
857
858 if (load_segment(env, &e1, &e2, selector) != 0) {
859 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
860 }
861 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
862 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
863 }
864 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
865 if (dpl > cpl) {
866 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
867 }
868 if (!(e2 & DESC_P_MASK)) {
869 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
870 }
871 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
872 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
873 }
874 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
875 /* to inner privilege */
876 if (ist != 0) {
877 esp = get_rsp_from_tss(env, ist + 3);
878 } else {
879 esp = get_rsp_from_tss(env, dpl);
880 }
881 esp &= ~0xfLL; /* align stack */
882 ss = 0;
883 new_stack = 1;
884 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
885 /* to same privilege */
886 if (env->eflags & VM_MASK) {
887 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
888 }
889 new_stack = 0;
890 if (ist != 0) {
891 esp = get_rsp_from_tss(env, ist + 3);
892 } else {
893 esp = env->regs[R_ESP];
894 }
895 esp &= ~0xfLL; /* align stack */
896 dpl = cpl;
897 } else {
898 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
899 new_stack = 0; /* avoid warning */
900 esp = 0; /* avoid warning */
901 }
902
903 PUSHQ(esp, env->segs[R_SS].selector);
904 PUSHQ(esp, env->regs[R_ESP]);
905 PUSHQ(esp, cpu_compute_eflags(env));
906 PUSHQ(esp, env->segs[R_CS].selector);
907 PUSHQ(esp, old_eip);
908 if (has_error_code) {
909 PUSHQ(esp, error_code);
910 }
911
912 if (new_stack) {
913 ss = 0 | dpl;
914 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
915 }
916 env->regs[R_ESP] = esp;
917
918 selector = (selector & ~3) | dpl;
919 cpu_x86_load_seg_cache(env, R_CS, selector,
920 get_seg_base(e1, e2),
921 get_seg_limit(e1, e2),
922 e2);
923 cpu_x86_set_cpl(env, dpl);
924 env->eip = offset;
925
926 /* interrupt gate clear IF mask */
927 if ((type & 1) == 0) {
928 env->eflags &= ~IF_MASK;
929 }
930 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
931 }
932 #endif
933
934 #ifdef TARGET_X86_64
935 #if defined(CONFIG_USER_ONLY)
936 void helper_syscall(CPUX86State *env, int next_eip_addend)
937 {
938 env->exception_index = EXCP_SYSCALL;
939 env->exception_next_eip = env->eip + next_eip_addend;
940 cpu_loop_exit(env);
941 }
942 #else
943 void helper_syscall(CPUX86State *env, int next_eip_addend)
944 {
945 int selector;
946
947 if (!(env->efer & MSR_EFER_SCE)) {
948 raise_exception_err(env, EXCP06_ILLOP, 0);
949 }
950 selector = (env->star >> 32) & 0xffff;
951 if (env->hflags & HF_LMA_MASK) {
952 int code64;
953
954 env->regs[R_ECX] = env->eip + next_eip_addend;
955 env->regs[11] = cpu_compute_eflags(env);
956
957 code64 = env->hflags & HF_CS64_MASK;
958
959 cpu_x86_set_cpl(env, 0);
960 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
961 0, 0xffffffff,
962 DESC_G_MASK | DESC_P_MASK |
963 DESC_S_MASK |
964 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
965 DESC_L_MASK);
966 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
967 0, 0xffffffff,
968 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
969 DESC_S_MASK |
970 DESC_W_MASK | DESC_A_MASK);
971 env->eflags &= ~env->fmask;
972 cpu_load_eflags(env, env->eflags, 0);
973 if (code64) {
974 env->eip = env->lstar;
975 } else {
976 env->eip = env->cstar;
977 }
978 } else {
979 env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
980
981 cpu_x86_set_cpl(env, 0);
982 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
983 0, 0xffffffff,
984 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
985 DESC_S_MASK |
986 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
987 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
988 0, 0xffffffff,
989 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
990 DESC_S_MASK |
991 DESC_W_MASK | DESC_A_MASK);
992 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
993 env->eip = (uint32_t)env->star;
994 }
995 }
996 #endif
997 #endif
998
999 #ifdef TARGET_X86_64
1000 void helper_sysret(CPUX86State *env, int dflag)
1001 {
1002 int cpl, selector;
1003
1004 if (!(env->efer & MSR_EFER_SCE)) {
1005 raise_exception_err(env, EXCP06_ILLOP, 0);
1006 }
1007 cpl = env->hflags & HF_CPL_MASK;
1008 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1009 raise_exception_err(env, EXCP0D_GPF, 0);
1010 }
1011 selector = (env->star >> 48) & 0xffff;
1012 if (env->hflags & HF_LMA_MASK) {
1013 if (dflag == 2) {
1014 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1015 0, 0xffffffff,
1016 DESC_G_MASK | DESC_P_MASK |
1017 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1018 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1019 DESC_L_MASK);
1020 env->eip = env->regs[R_ECX];
1021 } else {
1022 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1023 0, 0xffffffff,
1024 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1025 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1026 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1027 env->eip = (uint32_t)env->regs[R_ECX];
1028 }
1029 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1030 0, 0xffffffff,
1031 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1032 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1033 DESC_W_MASK | DESC_A_MASK);
1034 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
1035 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
1036 NT_MASK);
1037 cpu_x86_set_cpl(env, 3);
1038 } else {
1039 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1040 0, 0xffffffff,
1041 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1042 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1043 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1044 env->eip = (uint32_t)env->regs[R_ECX];
1045 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1046 0, 0xffffffff,
1047 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1048 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1049 DESC_W_MASK | DESC_A_MASK);
1050 env->eflags |= IF_MASK;
1051 cpu_x86_set_cpl(env, 3);
1052 }
1053 }
1054 #endif
1055
1056 /* real mode interrupt */
1057 static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
1058 int error_code, unsigned int next_eip)
1059 {
1060 SegmentCache *dt;
1061 target_ulong ptr, ssp;
1062 int selector;
1063 uint32_t offset, esp;
1064 uint32_t old_cs, old_eip;
1065
1066 /* real mode (simpler!) */
1067 dt = &env->idt;
1068 if (intno * 4 + 3 > dt->limit) {
1069 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
1070 }
1071 ptr = dt->base + intno * 4;
1072 offset = cpu_lduw_kernel(env, ptr);
1073 selector = cpu_lduw_kernel(env, ptr + 2);
1074 esp = env->regs[R_ESP];
1075 ssp = env->segs[R_SS].base;
1076 if (is_int) {
1077 old_eip = next_eip;
1078 } else {
1079 old_eip = env->eip;
1080 }
1081 old_cs = env->segs[R_CS].selector;
1082 /* XXX: use SS segment size? */
1083 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
1084 PUSHW(ssp, esp, 0xffff, old_cs);
1085 PUSHW(ssp, esp, 0xffff, old_eip);
1086
1087 /* update processor state */
1088 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
1089 env->eip = offset;
1090 env->segs[R_CS].selector = selector;
1091 env->segs[R_CS].base = (selector << 4);
1092 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1093 }
1094
1095 #if defined(CONFIG_USER_ONLY)
1096 /* fake user mode interrupt */
1097 static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
1098 int error_code, target_ulong next_eip)
1099 {
1100 SegmentCache *dt;
1101 target_ulong ptr;
1102 int dpl, cpl, shift;
1103 uint32_t e2;
1104
1105 dt = &env->idt;
1106 if (env->hflags & HF_LMA_MASK) {
1107 shift = 4;
1108 } else {
1109 shift = 3;
1110 }
1111 ptr = dt->base + (intno << shift);
1112 e2 = cpu_ldl_kernel(env, ptr + 4);
1113
1114 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1115 cpl = env->hflags & HF_CPL_MASK;
1116 /* check privilege if software int */
1117 if (is_int && dpl < cpl) {
1118 raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
1119 }
1120
1121 /* Since we emulate only user space, we cannot do more than
1122 exiting the emulation with the suitable exception and error
1123 code */
1124 if (is_int) {
1125 env->eip = next_eip;
1126 }
1127 }
1128
1129 #else
1130
1131 static void handle_even_inj(CPUX86State *env, int intno, int is_int,
1132 int error_code, int is_hw, int rm)
1133 {
1134 CPUState *cs = CPU(x86_env_get_cpu(env));
1135 uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
1136 control.event_inj));
1137
1138 if (!(event_inj & SVM_EVTINJ_VALID)) {
1139 int type;
1140
1141 if (is_int) {
1142 type = SVM_EVTINJ_TYPE_SOFT;
1143 } else {
1144 type = SVM_EVTINJ_TYPE_EXEPT;
1145 }
1146 event_inj = intno | type | SVM_EVTINJ_VALID;
1147 if (!rm && exception_has_error_code(intno)) {
1148 event_inj |= SVM_EVTINJ_VALID_ERR;
1149 stl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
1150 control.event_inj_err),
1151 error_code);
1152 }
1153 stl_phys(cs->as,
1154 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1155 event_inj);
1156 }
1157 }
1158 #endif
1159
1160 /*
1161 * Begin execution of an interruption. is_int is TRUE if coming from
1162 * the int instruction. next_eip is the env->eip value AFTER the interrupt
1163 * instruction. It is only relevant if is_int is TRUE.
1164 */
1165 static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
1166 int error_code, target_ulong next_eip, int is_hw)
1167 {
1168 CPUX86State *env = &cpu->env;
1169
1170 if (qemu_loglevel_mask(CPU_LOG_INT)) {
1171 if ((env->cr[0] & CR0_PE_MASK)) {
1172 static int count;
1173
1174 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1175 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1176 count, intno, error_code, is_int,
1177 env->hflags & HF_CPL_MASK,
1178 env->segs[R_CS].selector, env->eip,
1179 (int)env->segs[R_CS].base + env->eip,
1180 env->segs[R_SS].selector, env->regs[R_ESP]);
1181 if (intno == 0x0e) {
1182 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
1183 } else {
1184 qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
1185 }
1186 qemu_log("\n");
1187 log_cpu_state(CPU(cpu), CPU_DUMP_CCOP);
1188 #if 0
1189 {
1190 int i;
1191 target_ulong ptr;
1192
1193 qemu_log(" code=");
1194 ptr = env->segs[R_CS].base + env->eip;
1195 for (i = 0; i < 16; i++) {
1196 qemu_log(" %02x", ldub(ptr + i));
1197 }
1198 qemu_log("\n");
1199 }
1200 #endif
1201 count++;
1202 }
1203 }
1204 if (env->cr[0] & CR0_PE_MASK) {
1205 #if !defined(CONFIG_USER_ONLY)
1206 if (env->hflags & HF_SVMI_MASK) {
1207 handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
1208 }
1209 #endif
1210 #ifdef TARGET_X86_64
1211 if (env->hflags & HF_LMA_MASK) {
1212 do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw);
1213 } else
1214 #endif
1215 {
1216 do_interrupt_protected(env, intno, is_int, error_code, next_eip,
1217 is_hw);
1218 }
1219 } else {
1220 #if !defined(CONFIG_USER_ONLY)
1221 if (env->hflags & HF_SVMI_MASK) {
1222 handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
1223 }
1224 #endif
1225 do_interrupt_real(env, intno, is_int, error_code, next_eip);
1226 }
1227
1228 #if !defined(CONFIG_USER_ONLY)
1229 if (env->hflags & HF_SVMI_MASK) {
1230 CPUState *cs = CPU(cpu);
1231 uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb +
1232 offsetof(struct vmcb,
1233 control.event_inj));
1234
1235 stl_phys(cs->as,
1236 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1237 event_inj & ~SVM_EVTINJ_VALID);
1238 }
1239 #endif
1240 }
1241
1242 void x86_cpu_do_interrupt(CPUState *cs)
1243 {
1244 X86CPU *cpu = X86_CPU(cs);
1245 CPUX86State *env = &cpu->env;
1246
1247 #if defined(CONFIG_USER_ONLY)
1248 /* if user mode only, we simulate a fake exception
1249 which will be handled outside the cpu execution
1250 loop */
1251 do_interrupt_user(env, env->exception_index,
1252 env->exception_is_int,
1253 env->error_code,
1254 env->exception_next_eip);
1255 /* successfully delivered */
1256 env->old_exception = -1;
1257 #else
1258 /* simulate a real cpu exception. On i386, it can
1259 trigger new exceptions, but we do not handle
1260 double or triple faults yet. */
1261 do_interrupt_all(cpu, env->exception_index,
1262 env->exception_is_int,
1263 env->error_code,
1264 env->exception_next_eip, 0);
1265 /* successfully delivered */
1266 env->old_exception = -1;
1267 #endif
1268 }
1269
1270 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
1271 {
1272 do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw);
1273 }
1274
1275 void helper_enter_level(CPUX86State *env, int level, int data32,
1276 target_ulong t1)
1277 {
1278 target_ulong ssp;
1279 uint32_t esp_mask, esp, ebp;
1280
1281 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1282 ssp = env->segs[R_SS].base;
1283 ebp = env->regs[R_EBP];
1284 esp = env->regs[R_ESP];
1285 if (data32) {
1286 /* 32 bit */
1287 esp -= 4;
1288 while (--level) {
1289 esp -= 4;
1290 ebp -= 4;
1291 cpu_stl_data(env, ssp + (esp & esp_mask),
1292 cpu_ldl_data(env, ssp + (ebp & esp_mask)));
1293 }
1294 esp -= 4;
1295 cpu_stl_data(env, ssp + (esp & esp_mask), t1);
1296 } else {
1297 /* 16 bit */
1298 esp -= 2;
1299 while (--level) {
1300 esp -= 2;
1301 ebp -= 2;
1302 cpu_stw_data(env, ssp + (esp & esp_mask),
1303 cpu_lduw_data(env, ssp + (ebp & esp_mask)));
1304 }
1305 esp -= 2;
1306 cpu_stw_data(env, ssp + (esp & esp_mask), t1);
1307 }
1308 }
1309
1310 #ifdef TARGET_X86_64
1311 void helper_enter64_level(CPUX86State *env, int level, int data64,
1312 target_ulong t1)
1313 {
1314 target_ulong esp, ebp;
1315
1316 ebp = env->regs[R_EBP];
1317 esp = env->regs[R_ESP];
1318
1319 if (data64) {
1320 /* 64 bit */
1321 esp -= 8;
1322 while (--level) {
1323 esp -= 8;
1324 ebp -= 8;
1325 cpu_stq_data(env, esp, cpu_ldq_data(env, ebp));
1326 }
1327 esp -= 8;
1328 cpu_stq_data(env, esp, t1);
1329 } else {
1330 /* 16 bit */
1331 esp -= 2;
1332 while (--level) {
1333 esp -= 2;
1334 ebp -= 2;
1335 cpu_stw_data(env, esp, cpu_lduw_data(env, ebp));
1336 }
1337 esp -= 2;
1338 cpu_stw_data(env, esp, t1);
1339 }
1340 }
1341 #endif
1342
1343 void helper_lldt(CPUX86State *env, int selector)
1344 {
1345 SegmentCache *dt;
1346 uint32_t e1, e2;
1347 int index, entry_limit;
1348 target_ulong ptr;
1349
1350 selector &= 0xffff;
1351 if ((selector & 0xfffc) == 0) {
1352 /* XXX: NULL selector case: invalid LDT */
1353 env->ldt.base = 0;
1354 env->ldt.limit = 0;
1355 } else {
1356 if (selector & 0x4) {
1357 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1358 }
1359 dt = &env->gdt;
1360 index = selector & ~7;
1361 #ifdef TARGET_X86_64
1362 if (env->hflags & HF_LMA_MASK) {
1363 entry_limit = 15;
1364 } else
1365 #endif
1366 {
1367 entry_limit = 7;
1368 }
1369 if ((index + entry_limit) > dt->limit) {
1370 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1371 }
1372 ptr = dt->base + index;
1373 e1 = cpu_ldl_kernel(env, ptr);
1374 e2 = cpu_ldl_kernel(env, ptr + 4);
1375 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
1376 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1377 }
1378 if (!(e2 & DESC_P_MASK)) {
1379 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1380 }
1381 #ifdef TARGET_X86_64
1382 if (env->hflags & HF_LMA_MASK) {
1383 uint32_t e3;
1384
1385 e3 = cpu_ldl_kernel(env, ptr + 8);
1386 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1387 env->ldt.base |= (target_ulong)e3 << 32;
1388 } else
1389 #endif
1390 {
1391 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1392 }
1393 }
1394 env->ldt.selector = selector;
1395 }
1396
1397 void helper_ltr(CPUX86State *env, int selector)
1398 {
1399 SegmentCache *dt;
1400 uint32_t e1, e2;
1401 int index, type, entry_limit;
1402 target_ulong ptr;
1403
1404 selector &= 0xffff;
1405 if ((selector & 0xfffc) == 0) {
1406 /* NULL selector case: invalid TR */
1407 env->tr.base = 0;
1408 env->tr.limit = 0;
1409 env->tr.flags = 0;
1410 } else {
1411 if (selector & 0x4) {
1412 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1413 }
1414 dt = &env->gdt;
1415 index = selector & ~7;
1416 #ifdef TARGET_X86_64
1417 if (env->hflags & HF_LMA_MASK) {
1418 entry_limit = 15;
1419 } else
1420 #endif
1421 {
1422 entry_limit = 7;
1423 }
1424 if ((index + entry_limit) > dt->limit) {
1425 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1426 }
1427 ptr = dt->base + index;
1428 e1 = cpu_ldl_kernel(env, ptr);
1429 e2 = cpu_ldl_kernel(env, ptr + 4);
1430 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1431 if ((e2 & DESC_S_MASK) ||
1432 (type != 1 && type != 9)) {
1433 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1434 }
1435 if (!(e2 & DESC_P_MASK)) {
1436 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1437 }
1438 #ifdef TARGET_X86_64
1439 if (env->hflags & HF_LMA_MASK) {
1440 uint32_t e3, e4;
1441
1442 e3 = cpu_ldl_kernel(env, ptr + 8);
1443 e4 = cpu_ldl_kernel(env, ptr + 12);
1444 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) {
1445 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1446 }
1447 load_seg_cache_raw_dt(&env->tr, e1, e2);
1448 env->tr.base |= (target_ulong)e3 << 32;
1449 } else
1450 #endif
1451 {
1452 load_seg_cache_raw_dt(&env->tr, e1, e2);
1453 }
1454 e2 |= DESC_TSS_BUSY_MASK;
1455 cpu_stl_kernel(env, ptr + 4, e2);
1456 }
1457 env->tr.selector = selector;
1458 }
1459
1460 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1461 void helper_load_seg(CPUX86State *env, int seg_reg, int selector)
1462 {
1463 uint32_t e1, e2;
1464 int cpl, dpl, rpl;
1465 SegmentCache *dt;
1466 int index;
1467 target_ulong ptr;
1468
1469 selector &= 0xffff;
1470 cpl = env->hflags & HF_CPL_MASK;
1471 if ((selector & 0xfffc) == 0) {
1472 /* null selector case */
1473 if (seg_reg == R_SS
1474 #ifdef TARGET_X86_64
1475 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1476 #endif
1477 ) {
1478 raise_exception_err(env, EXCP0D_GPF, 0);
1479 }
1480 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1481 } else {
1482
1483 if (selector & 0x4) {
1484 dt = &env->ldt;
1485 } else {
1486 dt = &env->gdt;
1487 }
1488 index = selector & ~7;
1489 if ((index + 7) > dt->limit) {
1490 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1491 }
1492 ptr = dt->base + index;
1493 e1 = cpu_ldl_kernel(env, ptr);
1494 e2 = cpu_ldl_kernel(env, ptr + 4);
1495
1496 if (!(e2 & DESC_S_MASK)) {
1497 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1498 }
1499 rpl = selector & 3;
1500 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1501 if (seg_reg == R_SS) {
1502 /* must be writable segment */
1503 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
1504 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1505 }
1506 if (rpl != cpl || dpl != cpl) {
1507 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1508 }
1509 } else {
1510 /* must be readable segment */
1511 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
1512 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1513 }
1514
1515 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1516 /* if not conforming code, test rights */
1517 if (dpl < cpl || dpl < rpl) {
1518 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1519 }
1520 }
1521 }
1522
1523 if (!(e2 & DESC_P_MASK)) {
1524 if (seg_reg == R_SS) {
1525 raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc);
1526 } else {
1527 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1528 }
1529 }
1530
1531 /* set the access bit if not already set */
1532 if (!(e2 & DESC_A_MASK)) {
1533 e2 |= DESC_A_MASK;
1534 cpu_stl_kernel(env, ptr + 4, e2);
1535 }
1536
1537 cpu_x86_load_seg_cache(env, seg_reg, selector,
1538 get_seg_base(e1, e2),
1539 get_seg_limit(e1, e2),
1540 e2);
1541 #if 0
1542 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1543 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1544 #endif
1545 }
1546 }
1547
1548 /* protected mode jump */
1549 void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
1550 int next_eip_addend)
1551 {
1552 int gate_cs, type;
1553 uint32_t e1, e2, cpl, dpl, rpl, limit;
1554 target_ulong next_eip;
1555
1556 if ((new_cs & 0xfffc) == 0) {
1557 raise_exception_err(env, EXCP0D_GPF, 0);
1558 }
1559 if (load_segment(env, &e1, &e2, new_cs) != 0) {
1560 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1561 }
1562 cpl = env->hflags & HF_CPL_MASK;
1563 if (e2 & DESC_S_MASK) {
1564 if (!(e2 & DESC_CS_MASK)) {
1565 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1566 }
1567 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1568 if (e2 & DESC_C_MASK) {
1569 /* conforming code segment */
1570 if (dpl > cpl) {
1571 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1572 }
1573 } else {
1574 /* non conforming code segment */
1575 rpl = new_cs & 3;
1576 if (rpl > cpl) {
1577 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1578 }
1579 if (dpl != cpl) {
1580 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1581 }
1582 }
1583 if (!(e2 & DESC_P_MASK)) {
1584 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1585 }
1586 limit = get_seg_limit(e1, e2);
1587 if (new_eip > limit &&
1588 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) {
1589 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1590 }
1591 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1592 get_seg_base(e1, e2), limit, e2);
1593 env->eip = new_eip;
1594 } else {
1595 /* jump to call or task gate */
1596 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1597 rpl = new_cs & 3;
1598 cpl = env->hflags & HF_CPL_MASK;
1599 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1600 switch (type) {
1601 case 1: /* 286 TSS */
1602 case 9: /* 386 TSS */
1603 case 5: /* task gate */
1604 if (dpl < cpl || dpl < rpl) {
1605 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1606 }
1607 next_eip = env->eip + next_eip_addend;
1608 switch_tss(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1609 CC_OP = CC_OP_EFLAGS;
1610 break;
1611 case 4: /* 286 call gate */
1612 case 12: /* 386 call gate */
1613 if ((dpl < cpl) || (dpl < rpl)) {
1614 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1615 }
1616 if (!(e2 & DESC_P_MASK)) {
1617 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1618 }
1619 gate_cs = e1 >> 16;
1620 new_eip = (e1 & 0xffff);
1621 if (type == 12) {
1622 new_eip |= (e2 & 0xffff0000);
1623 }
1624 if (load_segment(env, &e1, &e2, gate_cs) != 0) {
1625 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1626 }
1627 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1628 /* must be code segment */
1629 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1630 (DESC_S_MASK | DESC_CS_MASK))) {
1631 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1632 }
1633 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1634 (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
1635 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1636 }
1637 if (!(e2 & DESC_P_MASK)) {
1638 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1639 }
1640 limit = get_seg_limit(e1, e2);
1641 if (new_eip > limit) {
1642 raise_exception_err(env, EXCP0D_GPF, 0);
1643 }
1644 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1645 get_seg_base(e1, e2), limit, e2);
1646 env->eip = new_eip;
1647 break;
1648 default:
1649 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1650 break;
1651 }
1652 }
1653 }
1654
1655 /* real mode call */
1656 void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1,
1657 int shift, int next_eip)
1658 {
1659 int new_eip;
1660 uint32_t esp, esp_mask;
1661 target_ulong ssp;
1662
1663 new_eip = new_eip1;
1664 esp = env->regs[R_ESP];
1665 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1666 ssp = env->segs[R_SS].base;
1667 if (shift) {
1668 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1669 PUSHL(ssp, esp, esp_mask, next_eip);
1670 } else {
1671 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1672 PUSHW(ssp, esp, esp_mask, next_eip);
1673 }
1674
1675 SET_ESP(esp, esp_mask);
1676 env->eip = new_eip;
1677 env->segs[R_CS].selector = new_cs;
1678 env->segs[R_CS].base = (new_cs << 4);
1679 }
1680
1681 /* protected mode call */
1682 void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
1683 int shift, int next_eip_addend)
1684 {
1685 int new_stack, i;
1686 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1687 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
1688 uint32_t val, limit, old_sp_mask;
1689 target_ulong ssp, old_ssp, next_eip;
1690
1691 next_eip = env->eip + next_eip_addend;
1692 LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
1693 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
1694 if ((new_cs & 0xfffc) == 0) {
1695 raise_exception_err(env, EXCP0D_GPF, 0);
1696 }
1697 if (load_segment(env, &e1, &e2, new_cs) != 0) {
1698 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1699 }
1700 cpl = env->hflags & HF_CPL_MASK;
1701 LOG_PCALL("desc=%08x:%08x\n", e1, e2);
1702 if (e2 & DESC_S_MASK) {
1703 if (!(e2 & DESC_CS_MASK)) {
1704 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1705 }
1706 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1707 if (e2 & DESC_C_MASK) {
1708 /* conforming code segment */
1709 if (dpl > cpl) {
1710 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1711 }
1712 } else {
1713 /* non conforming code segment */
1714 rpl = new_cs & 3;
1715 if (rpl > cpl) {
1716 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1717 }
1718 if (dpl != cpl) {
1719 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1720 }
1721 }
1722 if (!(e2 & DESC_P_MASK)) {
1723 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1724 }
1725
1726 #ifdef TARGET_X86_64
1727 /* XXX: check 16/32 bit cases in long mode */
1728 if (shift == 2) {
1729 target_ulong rsp;
1730
1731 /* 64 bit case */
1732 rsp = env->regs[R_ESP];
1733 PUSHQ(rsp, env->segs[R_CS].selector);
1734 PUSHQ(rsp, next_eip);
1735 /* from this point, not restartable */
1736 env->regs[R_ESP] = rsp;
1737 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1738 get_seg_base(e1, e2),
1739 get_seg_limit(e1, e2), e2);
1740 env->eip = new_eip;
1741 } else
1742 #endif
1743 {
1744 sp = env->regs[R_ESP];
1745 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1746 ssp = env->segs[R_SS].base;
1747 if (shift) {
1748 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1749 PUSHL(ssp, sp, sp_mask, next_eip);
1750 } else {
1751 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1752 PUSHW(ssp, sp, sp_mask, next_eip);
1753 }
1754
1755 limit = get_seg_limit(e1, e2);
1756 if (new_eip > limit) {
1757 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1758 }
1759 /* from this point, not restartable */
1760 SET_ESP(sp, sp_mask);
1761 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1762 get_seg_base(e1, e2), limit, e2);
1763 env->eip = new_eip;
1764 }
1765 } else {
1766 /* check gate type */
1767 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1768 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1769 rpl = new_cs & 3;
1770 switch (type) {
1771 case 1: /* available 286 TSS */
1772 case 9: /* available 386 TSS */
1773 case 5: /* task gate */
1774 if (dpl < cpl || dpl < rpl) {
1775 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1776 }
1777 switch_tss(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1778 CC_OP = CC_OP_EFLAGS;
1779 return;
1780 case 4: /* 286 call gate */
1781 case 12: /* 386 call gate */
1782 break;
1783 default:
1784 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1785 break;
1786 }
1787 shift = type >> 3;
1788
1789 if (dpl < cpl || dpl < rpl) {
1790 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1791 }
1792 /* check valid bit */
1793 if (!(e2 & DESC_P_MASK)) {
1794 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1795 }
1796 selector = e1 >> 16;
1797 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1798 param_count = e2 & 0x1f;
1799 if ((selector & 0xfffc) == 0) {
1800 raise_exception_err(env, EXCP0D_GPF, 0);
1801 }
1802
1803 if (load_segment(env, &e1, &e2, selector) != 0) {
1804 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1805 }
1806 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
1807 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1808 }
1809 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1810 if (dpl > cpl) {
1811 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1812 }
1813 if (!(e2 & DESC_P_MASK)) {
1814 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1815 }
1816
1817 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1818 /* to inner privilege */
1819 get_ss_esp_from_tss(env, &ss, &sp, dpl);
1820 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
1821 TARGET_FMT_lx "\n", ss, sp, param_count,
1822 env->regs[R_ESP]);
1823 if ((ss & 0xfffc) == 0) {
1824 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1825 }
1826 if ((ss & 3) != dpl) {
1827 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1828 }
1829 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
1830 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1831 }
1832 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1833 if (ss_dpl != dpl) {
1834 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1835 }
1836 if (!(ss_e2 & DESC_S_MASK) ||
1837 (ss_e2 & DESC_CS_MASK) ||
1838 !(ss_e2 & DESC_W_MASK)) {
1839 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1840 }
1841 if (!(ss_e2 & DESC_P_MASK)) {
1842 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1843 }
1844
1845 /* push_size = ((param_count * 2) + 8) << shift; */
1846
1847 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1848 old_ssp = env->segs[R_SS].base;
1849
1850 sp_mask = get_sp_mask(ss_e2);
1851 ssp = get_seg_base(ss_e1, ss_e2);
1852 if (shift) {
1853 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
1854 PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
1855 for (i = param_count - 1; i >= 0; i--) {
1856 val = cpu_ldl_kernel(env, old_ssp +
1857 ((env->regs[R_ESP] + i * 4) &
1858 old_sp_mask));
1859 PUSHL(ssp, sp, sp_mask, val);
1860 }
1861 } else {
1862 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
1863 PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
1864 for (i = param_count - 1; i >= 0; i--) {
1865 val = cpu_lduw_kernel(env, old_ssp +
1866 ((env->regs[R_ESP] + i * 2) &
1867 old_sp_mask));
1868 PUSHW(ssp, sp, sp_mask, val);
1869 }
1870 }
1871 new_stack = 1;
1872 } else {
1873 /* to same privilege */
1874 sp = env->regs[R_ESP];
1875 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1876 ssp = env->segs[R_SS].base;
1877 /* push_size = (4 << shift); */
1878 new_stack = 0;
1879 }
1880
1881 if (shift) {
1882 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1883 PUSHL(ssp, sp, sp_mask, next_eip);
1884 } else {
1885 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1886 PUSHW(ssp, sp, sp_mask, next_eip);
1887 }
1888
1889 /* from this point, not restartable */
1890
1891 if (new_stack) {
1892 ss = (ss & ~3) | dpl;
1893 cpu_x86_load_seg_cache(env, R_SS, ss,
1894 ssp,
1895 get_seg_limit(ss_e1, ss_e2),
1896 ss_e2);
1897 }
1898
1899 selector = (selector & ~3) | dpl;
1900 cpu_x86_load_seg_cache(env, R_CS, selector,
1901 get_seg_base(e1, e2),
1902 get_seg_limit(e1, e2),
1903 e2);
1904 cpu_x86_set_cpl(env, dpl);
1905 SET_ESP(sp, sp_mask);
1906 env->eip = offset;
1907 }
1908 }
1909
1910 /* real and vm86 mode iret */
1911 void helper_iret_real(CPUX86State *env, int shift)
1912 {
1913 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1914 target_ulong ssp;
1915 int eflags_mask;
1916
1917 sp_mask = 0xffff; /* XXXX: use SS segment size? */
1918 sp = env->regs[R_ESP];
1919 ssp = env->segs[R_SS].base;
1920 if (shift == 1) {
1921 /* 32 bits */
1922 POPL(ssp, sp, sp_mask, new_eip);
1923 POPL(ssp, sp, sp_mask, new_cs);
1924 new_cs &= 0xffff;
1925 POPL(ssp, sp, sp_mask, new_eflags);
1926 } else {
1927 /* 16 bits */
1928 POPW(ssp, sp, sp_mask, new_eip);
1929 POPW(ssp, sp, sp_mask, new_cs);
1930 POPW(ssp, sp, sp_mask, new_eflags);
1931 }
1932 env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
1933 env->segs[R_CS].selector = new_cs;
1934 env->segs[R_CS].base = (new_cs << 4);
1935 env->eip = new_eip;
1936 if (env->eflags & VM_MASK) {
1937 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK |
1938 NT_MASK;
1939 } else {
1940 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK |
1941 RF_MASK | NT_MASK;
1942 }
1943 if (shift == 0) {
1944 eflags_mask &= 0xffff;
1945 }
1946 cpu_load_eflags(env, new_eflags, eflags_mask);
1947 env->hflags2 &= ~HF2_NMI_MASK;
1948 }
1949
1950 static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl)
1951 {
1952 int dpl;
1953 uint32_t e2;
1954
1955 /* XXX: on x86_64, we do not want to nullify FS and GS because
1956 they may still contain a valid base. I would be interested to
1957 know how a real x86_64 CPU behaves */
1958 if ((seg_reg == R_FS || seg_reg == R_GS) &&
1959 (env->segs[seg_reg].selector & 0xfffc) == 0) {
1960 return;
1961 }
1962
1963 e2 = env->segs[seg_reg].flags;
1964 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1965 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1966 /* data or non conforming code segment */
1967 if (dpl < cpl) {
1968 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
1969 }
1970 }
1971 }
1972
1973 /* protected mode iret */
1974 static inline void helper_ret_protected(CPUX86State *env, int shift,
1975 int is_iret, int addend)
1976 {
1977 uint32_t new_cs, new_eflags, new_ss;
1978 uint32_t new_es, new_ds, new_fs, new_gs;
1979 uint32_t e1, e2, ss_e1, ss_e2;
1980 int cpl, dpl, rpl, eflags_mask, iopl;
1981 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
1982
1983 #ifdef TARGET_X86_64
1984 if (shift == 2) {
1985 sp_mask = -1;
1986 } else
1987 #endif
1988 {
1989 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1990 }
1991 sp = env->regs[R_ESP];
1992 ssp = env->segs[R_SS].base;
1993 new_eflags = 0; /* avoid warning */
1994 #ifdef TARGET_X86_64
1995 if (shift == 2) {
1996 POPQ(sp, new_eip);
1997 POPQ(sp, new_cs);
1998 new_cs &= 0xffff;
1999 if (is_iret) {
2000 POPQ(sp, new_eflags);
2001 }
2002 } else
2003 #endif
2004 {
2005 if (shift == 1) {
2006 /* 32 bits */
2007 POPL(ssp, sp, sp_mask, new_eip);
2008 POPL(ssp, sp, sp_mask, new_cs);
2009 new_cs &= 0xffff;
2010 if (is_iret) {
2011 POPL(ssp, sp, sp_mask, new_eflags);
2012 if (new_eflags & VM_MASK) {
2013 goto return_to_vm86;
2014 }
2015 }
2016 } else {
2017 /* 16 bits */
2018 POPW(ssp, sp, sp_mask, new_eip);
2019 POPW(ssp, sp, sp_mask, new_cs);
2020 if (is_iret) {
2021 POPW(ssp, sp, sp_mask, new_eflags);
2022 }
2023 }
2024 }
2025 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2026 new_cs, new_eip, shift, addend);
2027 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
2028 if ((new_cs & 0xfffc) == 0) {
2029 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2030 }
2031 if (load_segment(env, &e1, &e2, new_cs) != 0) {
2032 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2033 }
2034 if (!(e2 & DESC_S_MASK) ||
2035 !(e2 & DESC_CS_MASK)) {
2036 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2037 }
2038 cpl = env->hflags & HF_CPL_MASK;
2039 rpl = new_cs & 3;
2040 if (rpl < cpl) {
2041 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2042 }
2043 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2044 if (e2 & DESC_C_MASK) {
2045 if (dpl > rpl) {
2046 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2047 }
2048 } else {
2049 if (dpl != rpl) {
2050 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2051 }
2052 }
2053 if (!(e2 & DESC_P_MASK)) {
2054 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
2055 }
2056
2057 sp += addend;
2058 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2059 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2060 /* return to same privilege level */
2061 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2062 get_seg_base(e1, e2),
2063 get_seg_limit(e1, e2),
2064 e2);
2065 } else {
2066 /* return to different privilege level */
2067 #ifdef TARGET_X86_64
2068 if (shift == 2) {
2069 POPQ(sp, new_esp);
2070 POPQ(sp, new_ss);
2071 new_ss &= 0xffff;
2072 } else
2073 #endif
2074 {
2075 if (shift == 1) {
2076 /* 32 bits */
2077 POPL(ssp, sp, sp_mask, new_esp);
2078 POPL(ssp, sp, sp_mask, new_ss);
2079 new_ss &= 0xffff;
2080 } else {
2081 /* 16 bits */
2082 POPW(ssp, sp, sp_mask, new_esp);
2083 POPW(ssp, sp, sp_mask, new_ss);
2084 }
2085 }
2086 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
2087 new_ss, new_esp);
2088 if ((new_ss & 0xfffc) == 0) {
2089 #ifdef TARGET_X86_64
2090 /* NULL ss is allowed in long mode if cpl != 3 */
2091 /* XXX: test CS64? */
2092 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2093 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2094 0, 0xffffffff,
2095 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2096 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2097 DESC_W_MASK | DESC_A_MASK);
2098 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
2099 } else
2100 #endif
2101 {
2102 raise_exception_err(env, EXCP0D_GPF, 0);
2103 }
2104 } else {
2105 if ((new_ss & 3) != rpl) {
2106 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2107 }
2108 if (load_segment(env, &ss_e1, &ss_e2, new_ss) != 0) {
2109 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2110 }
2111 if (!(ss_e2 & DESC_S_MASK) ||
2112 (ss_e2 & DESC_CS_MASK) ||
2113 !(ss_e2 & DESC_W_MASK)) {
2114 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2115 }
2116 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2117 if (dpl != rpl) {
2118 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2119 }
2120 if (!(ss_e2 & DESC_P_MASK)) {
2121 raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc);
2122 }
2123 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2124 get_seg_base(ss_e1, ss_e2),
2125 get_seg_limit(ss_e1, ss_e2),
2126 ss_e2);
2127 }
2128
2129 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2130 get_seg_base(e1, e2),
2131 get_seg_limit(e1, e2),
2132 e2);
2133 cpu_x86_set_cpl(env, rpl);
2134 sp = new_esp;
2135 #ifdef TARGET_X86_64
2136 if (env->hflags & HF_CS64_MASK) {
2137 sp_mask = -1;
2138 } else
2139 #endif
2140 {
2141 sp_mask = get_sp_mask(ss_e2);
2142 }
2143
2144 /* validate data segments */
2145 validate_seg(env, R_ES, rpl);
2146 validate_seg(env, R_DS, rpl);
2147 validate_seg(env, R_FS, rpl);
2148 validate_seg(env, R_GS, rpl);
2149
2150 sp += addend;
2151 }
2152 SET_ESP(sp, sp_mask);
2153 env->eip = new_eip;
2154 if (is_iret) {
2155 /* NOTE: 'cpl' is the _old_ CPL */
2156 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2157 if (cpl == 0) {
2158 eflags_mask |= IOPL_MASK;
2159 }
2160 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2161 if (cpl <= iopl) {
2162 eflags_mask |= IF_MASK;
2163 }
2164 if (shift == 0) {
2165 eflags_mask &= 0xffff;
2166 }
2167 cpu_load_eflags(env, new_eflags, eflags_mask);
2168 }
2169 return;
2170
2171 return_to_vm86:
2172 POPL(ssp, sp, sp_mask, new_esp);
2173 POPL(ssp, sp, sp_mask, new_ss);
2174 POPL(ssp, sp, sp_mask, new_es);
2175 POPL(ssp, sp, sp_mask, new_ds);
2176 POPL(ssp, sp, sp_mask, new_fs);
2177 POPL(ssp, sp, sp_mask, new_gs);
2178
2179 /* modify processor state */
2180 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
2181 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK |
2182 VIP_MASK);
2183 load_seg_vm(env, R_CS, new_cs & 0xffff);
2184 cpu_x86_set_cpl(env, 3);
2185 load_seg_vm(env, R_SS, new_ss & 0xffff);
2186 load_seg_vm(env, R_ES, new_es & 0xffff);
2187 load_seg_vm(env, R_DS, new_ds & 0xffff);
2188 load_seg_vm(env, R_FS, new_fs & 0xffff);
2189 load_seg_vm(env, R_GS, new_gs & 0xffff);
2190
2191 env->eip = new_eip & 0xffff;
2192 env->regs[R_ESP] = new_esp;
2193 }
2194
2195 void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
2196 {
2197 int tss_selector, type;
2198 uint32_t e1, e2;
2199
2200 /* specific case for TSS */
2201 if (env->eflags & NT_MASK) {
2202 #ifdef TARGET_X86_64
2203 if (env->hflags & HF_LMA_MASK) {
2204 raise_exception_err(env, EXCP0D_GPF, 0);
2205 }
2206 #endif
2207 tss_selector = cpu_lduw_kernel(env, env->tr.base + 0);
2208 if (tss_selector & 4) {
2209 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2210 }
2211 if (load_segment(env, &e1, &e2, tss_selector) != 0) {
2212 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2213 }
2214 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2215 /* NOTE: we check both segment and busy TSS */
2216 if (type != 3) {
2217 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2218 }
2219 switch_tss(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2220 } else {
2221 helper_ret_protected(env, shift, 1, 0);
2222 }
2223 env->hflags2 &= ~HF2_NMI_MASK;
2224 }
2225
2226 void helper_lret_protected(CPUX86State *env, int shift, int addend)
2227 {
2228 helper_ret_protected(env, shift, 0, addend);
2229 }
2230
2231 void helper_sysenter(CPUX86State *env)
2232 {
2233 if (env->sysenter_cs == 0) {
2234 raise_exception_err(env, EXCP0D_GPF, 0);
2235 }
2236 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2237 cpu_x86_set_cpl(env, 0);
2238
2239 #ifdef TARGET_X86_64
2240 if (env->hflags & HF_LMA_MASK) {
2241 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2242 0, 0xffffffff,
2243 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2244 DESC_S_MASK |
2245 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2246 DESC_L_MASK);
2247 } else
2248 #endif
2249 {
2250 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2251 0, 0xffffffff,
2252 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2253 DESC_S_MASK |
2254 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2255 }
2256 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2257 0, 0xffffffff,
2258 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2259 DESC_S_MASK |
2260 DESC_W_MASK | DESC_A_MASK);
2261 env->regs[R_ESP] = env->sysenter_esp;
2262 env->eip = env->sysenter_eip;
2263 }
2264
2265 void helper_sysexit(CPUX86State *env, int dflag)
2266 {
2267 int cpl;
2268
2269 cpl = env->hflags & HF_CPL_MASK;
2270 if (env->sysenter_cs == 0 || cpl != 0) {
2271 raise_exception_err(env, EXCP0D_GPF, 0);
2272 }
2273 cpu_x86_set_cpl(env, 3);
2274 #ifdef TARGET_X86_64
2275 if (dflag == 2) {
2276 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) |
2277 3, 0, 0xffffffff,
2278 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2279 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2280 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2281 DESC_L_MASK);
2282 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) |
2283 3, 0, 0xffffffff,
2284 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2285 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2286 DESC_W_MASK | DESC_A_MASK);
2287 } else
2288 #endif
2289 {
2290 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) |
2291 3, 0, 0xffffffff,
2292 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2293 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2294 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2295 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) |
2296 3, 0, 0xffffffff,
2297 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2298 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2299 DESC_W_MASK | DESC_A_MASK);
2300 }
2301 env->regs[R_ESP] = env->regs[R_ECX];
2302 env->eip = env->regs[R_EDX];
2303 }
2304
2305 target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
2306 {
2307 unsigned int limit;
2308 uint32_t e1, e2, eflags, selector;
2309 int rpl, dpl, cpl, type;
2310
2311 selector = selector1 & 0xffff;
2312 eflags = cpu_cc_compute_all(env, CC_OP);
2313 if ((selector & 0xfffc) == 0) {
2314 goto fail;
2315 }
2316 if (load_segment(env, &e1, &e2, selector) != 0) {
2317 goto fail;
2318 }
2319 rpl = selector & 3;
2320 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2321 cpl = env->hflags & HF_CPL_MASK;
2322 if (e2 & DESC_S_MASK) {
2323 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2324 /* conforming */
2325 } else {
2326 if (dpl < cpl || dpl < rpl) {
2327 goto fail;
2328 }
2329 }
2330 } else {
2331 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2332 switch (type) {
2333 case 1:
2334 case 2:
2335 case 3:
2336 case 9:
2337 case 11:
2338 break;
2339 default:
2340 goto fail;
2341 }
2342 if (dpl < cpl || dpl < rpl) {
2343 fail:
2344 CC_SRC = eflags & ~CC_Z;
2345 return 0;
2346 }
2347 }
2348 limit = get_seg_limit(e1, e2);
2349 CC_SRC = eflags | CC_Z;
2350 return limit;
2351 }
2352
2353 target_ulong helper_lar(CPUX86State *env, target_ulong selector1)
2354 {
2355 uint32_t e1, e2, eflags, selector;
2356 int rpl, dpl, cpl, type;
2357
2358 selector = selector1 & 0xffff;
2359 eflags = cpu_cc_compute_all(env, CC_OP);
2360 if ((selector & 0xfffc) == 0) {
2361 goto fail;
2362 }
2363 if (load_segment(env, &e1, &e2, selector) != 0) {
2364 goto fail;
2365 }
2366 rpl = selector & 3;
2367 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2368 cpl = env->hflags & HF_CPL_MASK;
2369 if (e2 & DESC_S_MASK) {
2370 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2371 /* conforming */
2372 } else {
2373 if (dpl < cpl || dpl < rpl) {
2374 goto fail;
2375 }
2376 }
2377 } else {
2378 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2379 switch (type) {
2380 case 1:
2381 case 2:
2382 case 3:
2383 case 4:
2384 case 5:
2385 case 9:
2386 case 11:
2387 case 12:
2388 break;
2389 default:
2390 goto fail;
2391 }
2392 if (dpl < cpl || dpl < rpl) {
2393 fail:
2394 CC_SRC = eflags & ~CC_Z;
2395 return 0;
2396 }
2397 }
2398 CC_SRC = eflags | CC_Z;
2399 return e2 & 0x00f0ff00;
2400 }
2401
2402 void helper_verr(CPUX86State *env, target_ulong selector1)
2403 {
2404 uint32_t e1, e2, eflags, selector;
2405 int rpl, dpl, cpl;
2406
2407 selector = selector1 & 0xffff;
2408 eflags = cpu_cc_compute_all(env, CC_OP);
2409 if ((selector & 0xfffc) == 0) {
2410 goto fail;
2411 }
2412 if (load_segment(env, &e1, &e2, selector) != 0) {
2413 goto fail;
2414 }
2415 if (!(e2 & DESC_S_MASK)) {
2416 goto fail;
2417 }
2418 rpl = selector & 3;
2419 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2420 cpl = env->hflags & HF_CPL_MASK;
2421 if (e2 & DESC_CS_MASK) {
2422 if (!(e2 & DESC_R_MASK)) {
2423 goto fail;
2424 }
2425 if (!(e2 & DESC_C_MASK)) {
2426 if (dpl < cpl || dpl < rpl) {
2427 goto fail;
2428 }
2429 }
2430 } else {
2431 if (dpl < cpl || dpl < rpl) {
2432 fail:
2433 CC_SRC = eflags & ~CC_Z;
2434 return;
2435 }
2436 }
2437 CC_SRC = eflags | CC_Z;
2438 }
2439
2440 void helper_verw(CPUX86State *env, target_ulong selector1)
2441 {
2442 uint32_t e1, e2, eflags, selector;
2443 int rpl, dpl, cpl;
2444
2445 selector = selector1 & 0xffff;
2446 eflags = cpu_cc_compute_all(env, CC_OP);
2447 if ((selector & 0xfffc) == 0) {
2448 goto fail;
2449 }
2450 if (load_segment(env, &e1, &e2, selector) != 0) {
2451 goto fail;
2452 }
2453 if (!(e2 & DESC_S_MASK)) {
2454 goto fail;
2455 }
2456 rpl = selector & 3;
2457 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2458 cpl = env->hflags & HF_CPL_MASK;
2459 if (e2 & DESC_CS_MASK) {
2460 goto fail;
2461 } else {
2462 if (dpl < cpl || dpl < rpl) {
2463 goto fail;
2464 }
2465 if (!(e2 & DESC_W_MASK)) {
2466 fail:
2467 CC_SRC = eflags & ~CC_Z;
2468 return;
2469 }
2470 }
2471 CC_SRC = eflags | CC_Z;
2472 }
2473
2474 #if defined(CONFIG_USER_ONLY)
2475 void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
2476 {
2477 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
2478 selector &= 0xffff;
2479 cpu_x86_load_seg_cache(env, seg_reg, selector,
2480 (selector << 4), 0xffff, 0);
2481 } else {
2482 helper_load_seg(env, seg_reg, selector);
2483 }
2484 }
2485 #endif
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