4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
42 #define CODE64(s) ((s)->code64)
43 #define REX_X(s) ((s)->rex_x)
44 #define REX_B(s) ((s)->rex_b)
59 //#define MACRO_TEST 1
61 /* global register indexes */
62 static TCGv_ptr cpu_env
;
64 static TCGv cpu_cc_src
, cpu_cc_dst
, cpu_cc_srcT
;
65 static TCGv_i32 cpu_cc_op
;
66 static TCGv cpu_regs
[CPU_NB_REGS
];
69 /* local register indexes (only used inside old micro ops) */
70 static TCGv cpu_tmp0
, cpu_tmp4
;
71 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
72 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
73 static TCGv_i64 cpu_tmp1_i64
;
76 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
78 #include "exec/gen-icount.h"
81 static int x86_64_hregs
;
84 typedef struct DisasContext
{
85 /* current insn context */
86 int override
; /* -1 if no override */
89 target_ulong pc
; /* pc = eip + cs_base */
90 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
91 static state change (stop translation) */
92 /* current block context */
93 target_ulong cs_base
; /* base of CS segment */
94 int pe
; /* protected mode */
95 int code32
; /* 32 bit code segment */
97 int lma
; /* long mode active */
98 int code64
; /* 64 bit code segment */
101 int ss32
; /* 32 bit stack segment */
102 CCOp cc_op
; /* current CC operation */
104 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
105 int f_st
; /* currently unused */
106 int vm86
; /* vm86 mode */
109 int tf
; /* TF cpu flag */
110 int singlestep_enabled
; /* "hardware" single step enabled */
111 int jmp_opt
; /* use direct block chaining for direct jumps */
112 int mem_index
; /* select memory access functions */
113 uint64_t flags
; /* all execution flags */
114 struct TranslationBlock
*tb
;
115 int popl_esp_hack
; /* for correct popl with esp base handling */
116 int rip_offset
; /* only used in x86_64, but left for simplicity */
118 int cpuid_ext_features
;
119 int cpuid_ext2_features
;
120 int cpuid_ext3_features
;
121 int cpuid_7_0_ebx_features
;
124 static void gen_eob(DisasContext
*s
);
125 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
126 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
127 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
);
129 /* i386 arith/logic operations */
149 OP_SHL1
, /* undocumented */
173 /* I386 int registers */
174 OR_EAX
, /* MUST be even numbered */
183 OR_TMP0
= 16, /* temporary operand register */
185 OR_A0
, /* temporary register used when doing address evaluation */
194 /* Bit set if the global variable is live after setting CC_OP to X. */
195 static const uint8_t cc_op_live
[CC_OP_NB
] = {
196 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
,
197 [CC_OP_EFLAGS
] = USES_CC_SRC
,
198 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
199 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
200 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
202 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
204 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
206 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
207 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
210 static void set_cc_op(DisasContext
*s
, CCOp op
)
214 if (s
->cc_op
== op
) {
218 /* Discard CC computation that will no longer be used. */
219 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
220 if (dead
& USES_CC_DST
) {
221 tcg_gen_discard_tl(cpu_cc_dst
);
223 if (dead
& USES_CC_SRC
) {
224 tcg_gen_discard_tl(cpu_cc_src
);
226 if (dead
& USES_CC_SRCT
) {
227 tcg_gen_discard_tl(cpu_cc_srcT
);
231 /* The DYNAMIC setting is translator only, and should never be
232 stored. Thus we always consider it clean. */
233 s
->cc_op_dirty
= (op
!= CC_OP_DYNAMIC
);
236 static void gen_update_cc_op(DisasContext
*s
)
238 if (s
->cc_op_dirty
) {
239 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
240 s
->cc_op_dirty
= false;
244 static inline void gen_op_movl_T0_0(void)
246 tcg_gen_movi_tl(cpu_T
[0], 0);
249 static inline void gen_op_movl_T0_im(int32_t val
)
251 tcg_gen_movi_tl(cpu_T
[0], val
);
254 static inline void gen_op_movl_T0_imu(uint32_t val
)
256 tcg_gen_movi_tl(cpu_T
[0], val
);
259 static inline void gen_op_movl_T1_im(int32_t val
)
261 tcg_gen_movi_tl(cpu_T
[1], val
);
264 static inline void gen_op_movl_T1_imu(uint32_t val
)
266 tcg_gen_movi_tl(cpu_T
[1], val
);
269 static inline void gen_op_movl_A0_im(uint32_t val
)
271 tcg_gen_movi_tl(cpu_A0
, val
);
275 static inline void gen_op_movq_A0_im(int64_t val
)
277 tcg_gen_movi_tl(cpu_A0
, val
);
281 static inline void gen_movtl_T0_im(target_ulong val
)
283 tcg_gen_movi_tl(cpu_T
[0], val
);
286 static inline void gen_movtl_T1_im(target_ulong val
)
288 tcg_gen_movi_tl(cpu_T
[1], val
);
291 static inline void gen_op_andl_T0_ffff(void)
293 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
296 static inline void gen_op_andl_T0_im(uint32_t val
)
298 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
301 static inline void gen_op_movl_T0_T1(void)
303 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
306 static inline void gen_op_andl_A0_ffff(void)
308 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
313 #define NB_OP_SIZES 4
315 #else /* !TARGET_X86_64 */
317 #define NB_OP_SIZES 3
319 #endif /* !TARGET_X86_64 */
321 #if defined(HOST_WORDS_BIGENDIAN)
322 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
323 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
324 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
325 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
326 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
328 #define REG_B_OFFSET 0
329 #define REG_H_OFFSET 1
330 #define REG_W_OFFSET 0
331 #define REG_L_OFFSET 0
332 #define REG_LH_OFFSET 4
335 /* In instruction encodings for byte register accesses the
336 * register number usually indicates "low 8 bits of register N";
337 * however there are some special cases where N 4..7 indicates
338 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
339 * true for this special case, false otherwise.
341 static inline bool byte_reg_is_xH(int reg
)
347 if (reg
>= 8 || x86_64_hregs
) {
354 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
358 if (!byte_reg_is_xH(reg
)) {
359 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
361 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
365 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
367 default: /* XXX this shouldn't be reached; abort? */
369 /* For x86_64, this sets the higher half of register to zero.
370 For i386, this is equivalent to a mov. */
371 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
375 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
381 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
383 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
386 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
388 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
391 static inline void gen_op_mov_reg_A0(int size
, int reg
)
395 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_A0
, 0, 16);
397 default: /* XXX this shouldn't be reached; abort? */
399 /* For x86_64, this sets the higher half of register to zero.
400 For i386, this is equivalent to a mov. */
401 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
405 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
411 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
413 if (ot
== OT_BYTE
&& byte_reg_is_xH(reg
)) {
414 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
415 tcg_gen_ext8u_tl(t0
, t0
);
417 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
421 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
423 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
426 static inline void gen_op_movl_A0_reg(int reg
)
428 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
431 static inline void gen_op_addl_A0_im(int32_t val
)
433 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
435 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
440 static inline void gen_op_addq_A0_im(int64_t val
)
442 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
446 static void gen_add_A0_im(DisasContext
*s
, int val
)
450 gen_op_addq_A0_im(val
);
453 gen_op_addl_A0_im(val
);
456 static inline void gen_op_addl_T0_T1(void)
458 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
461 static inline void gen_op_jmp_T0(void)
463 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
466 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
470 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
471 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
474 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
475 /* For x86_64, this sets the higher half of register to zero.
476 For i386, this is equivalent to a nop. */
477 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
478 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
482 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
488 static inline void gen_op_add_reg_T0(int size
, int reg
)
492 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
493 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
496 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
497 /* For x86_64, this sets the higher half of register to zero.
498 For i386, this is equivalent to a nop. */
499 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
500 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
504 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
510 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
512 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
514 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
515 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
516 /* For x86_64, this sets the higher half of register to zero.
517 For i386, this is equivalent to a nop. */
518 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
521 static inline void gen_op_movl_A0_seg(int reg
)
523 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
526 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
528 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
531 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
532 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
534 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
535 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
538 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
543 static inline void gen_op_movq_A0_seg(int reg
)
545 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
548 static inline void gen_op_addq_A0_seg(int reg
)
550 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
551 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
554 static inline void gen_op_movq_A0_reg(int reg
)
556 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
559 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
561 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
563 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
564 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
568 static inline void gen_op_lds_T0_A0(int idx
)
570 int mem_index
= (idx
>> 2) - 1;
573 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
576 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
580 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
585 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
587 int mem_index
= (idx
>> 2) - 1;
590 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
593 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
596 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
600 /* Should never happen on 32-bit targets. */
602 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
608 /* XXX: always use ldu or lds */
609 static inline void gen_op_ld_T0_A0(int idx
)
611 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
614 static inline void gen_op_ldu_T0_A0(int idx
)
616 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
619 static inline void gen_op_ld_T1_A0(int idx
)
621 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
624 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
626 int mem_index
= (idx
>> 2) - 1;
629 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
632 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
635 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
639 /* Should never happen on 32-bit targets. */
641 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
647 static inline void gen_op_st_T0_A0(int idx
)
649 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
652 static inline void gen_op_st_T1_A0(int idx
)
654 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
657 static inline void gen_jmp_im(target_ulong pc
)
659 tcg_gen_movi_tl(cpu_tmp0
, pc
);
660 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
663 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
667 override
= s
->override
;
671 gen_op_movq_A0_seg(override
);
672 gen_op_addq_A0_reg_sN(0, R_ESI
);
674 gen_op_movq_A0_reg(R_ESI
);
680 if (s
->addseg
&& override
< 0)
683 gen_op_movl_A0_seg(override
);
684 gen_op_addl_A0_reg_sN(0, R_ESI
);
686 gen_op_movl_A0_reg(R_ESI
);
689 /* 16 address, always override */
692 gen_op_movl_A0_reg(R_ESI
);
693 gen_op_andl_A0_ffff();
694 gen_op_addl_A0_seg(s
, override
);
698 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
702 gen_op_movq_A0_reg(R_EDI
);
707 gen_op_movl_A0_seg(R_ES
);
708 gen_op_addl_A0_reg_sN(0, R_EDI
);
710 gen_op_movl_A0_reg(R_EDI
);
713 gen_op_movl_A0_reg(R_EDI
);
714 gen_op_andl_A0_ffff();
715 gen_op_addl_A0_seg(s
, R_ES
);
719 static inline void gen_op_movl_T0_Dshift(int ot
)
721 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
722 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
725 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, int size
, bool sign
)
730 tcg_gen_ext8s_tl(dst
, src
);
732 tcg_gen_ext8u_tl(dst
, src
);
737 tcg_gen_ext16s_tl(dst
, src
);
739 tcg_gen_ext16u_tl(dst
, src
);
745 tcg_gen_ext32s_tl(dst
, src
);
747 tcg_gen_ext32u_tl(dst
, src
);
756 static void gen_extu(int ot
, TCGv reg
)
758 gen_ext_tl(reg
, reg
, ot
, false);
761 static void gen_exts(int ot
, TCGv reg
)
763 gen_ext_tl(reg
, reg
, ot
, true);
766 static inline void gen_op_jnz_ecx(int size
, int label1
)
768 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
769 gen_extu(size
+ 1, cpu_tmp0
);
770 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
773 static inline void gen_op_jz_ecx(int size
, int label1
)
775 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
776 gen_extu(size
+ 1, cpu_tmp0
);
777 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
780 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
784 gen_helper_inb(v
, n
);
787 gen_helper_inw(v
, n
);
790 gen_helper_inl(v
, n
);
795 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
799 gen_helper_outb(v
, n
);
802 gen_helper_outw(v
, n
);
805 gen_helper_outl(v
, n
);
810 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
814 target_ulong next_eip
;
817 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
821 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
824 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
827 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
830 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
834 if(s
->flags
& HF_SVMI_MASK
) {
839 svm_flags
|= (1 << (4 + ot
));
840 next_eip
= s
->pc
- s
->cs_base
;
841 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
842 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
843 tcg_const_i32(svm_flags
),
844 tcg_const_i32(next_eip
- cur_eip
));
848 static inline void gen_movs(DisasContext
*s
, int ot
)
850 gen_string_movl_A0_ESI(s
);
851 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
852 gen_string_movl_A0_EDI(s
);
853 gen_op_st_T0_A0(ot
+ s
->mem_index
);
854 gen_op_movl_T0_Dshift(ot
);
855 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
856 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
859 static void gen_op_update1_cc(void)
861 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
864 static void gen_op_update2_cc(void)
866 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
867 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
870 static inline void gen_op_testl_T0_T1_cc(void)
872 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
875 static void gen_op_update_neg_cc(void)
877 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
878 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
879 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
882 /* compute all eflags to cc_src */
883 static void gen_compute_eflags(DisasContext
*s
)
885 if (s
->cc_op
== CC_OP_EFLAGS
) {
889 gen_helper_cc_compute_all(cpu_tmp2_i32
, cpu_env
, cpu_cc_op
);
890 set_cc_op(s
, CC_OP_EFLAGS
);
891 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
894 typedef struct CCPrepare
{
904 /* compute eflags.C to reg */
905 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
911 case CC_OP_SUBB
... CC_OP_SUBQ
:
912 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
913 size
= s
->cc_op
- CC_OP_SUBB
;
914 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
915 /* If no temporary was used, be careful not to alias t1 and t0. */
916 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
917 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
921 case CC_OP_ADDB
... CC_OP_ADDQ
:
922 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
923 size
= s
->cc_op
- CC_OP_ADDB
;
924 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
925 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
927 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
928 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
930 case CC_OP_SBBB
... CC_OP_SBBQ
:
931 /* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */
932 size
= s
->cc_op
- CC_OP_SBBB
;
933 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
934 if (TCGV_EQUAL(t1
, reg
) && TCGV_EQUAL(reg
, cpu_cc_src
)) {
935 tcg_gen_mov_tl(cpu_tmp0
, cpu_cc_src
);
939 tcg_gen_add_tl(reg
, cpu_cc_dst
, cpu_cc_src
);
940 tcg_gen_addi_tl(reg
, reg
, 1);
945 case CC_OP_ADCB
... CC_OP_ADCQ
:
946 /* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
947 size
= s
->cc_op
- CC_OP_ADCB
;
948 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
949 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
951 return (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= t0
,
952 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
954 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
955 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
957 case CC_OP_INCB
... CC_OP_INCQ
:
958 case CC_OP_DECB
... CC_OP_DECQ
:
959 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
960 .mask
= -1, .no_setcond
= true };
962 case CC_OP_SHLB
... CC_OP_SHLQ
:
963 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
964 size
= s
->cc_op
- CC_OP_SHLB
;
965 shift
= (8 << size
) - 1;
966 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
967 .mask
= (target_ulong
)1 << shift
};
969 case CC_OP_MULB
... CC_OP_MULQ
:
970 return (CCPrepare
) { .cond
= TCG_COND_NE
,
971 .reg
= cpu_cc_src
, .mask
= -1 };
974 case CC_OP_SARB
... CC_OP_SARQ
:
976 return (CCPrepare
) { .cond
= TCG_COND_NE
,
977 .reg
= cpu_cc_src
, .mask
= CC_C
};
980 /* The need to compute only C from CC_OP_DYNAMIC is important
981 in efficiently implementing e.g. INC at the start of a TB. */
983 gen_helper_cc_compute_c(cpu_tmp2_i32
, cpu_env
, cpu_cc_op
);
984 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
985 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
986 .mask
= -1, .no_setcond
= true };
990 /* compute eflags.P to reg */
991 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
993 gen_compute_eflags(s
);
994 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
998 /* compute eflags.S to reg */
999 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
1003 gen_compute_eflags(s
);
1006 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1010 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1011 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
1012 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
1017 /* compute eflags.O to reg */
1018 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
1020 gen_compute_eflags(s
);
1021 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1025 /* compute eflags.Z to reg */
1026 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
1030 gen_compute_eflags(s
);
1033 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1037 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1038 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
1039 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
1044 /* perform a conditional store into register 'reg' according to jump opcode
1045 value 'b'. In the fast case, T0 is guaranted not to be used. */
1046 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
1048 int inv
, jcc_op
, size
, cond
;
1053 jcc_op
= (b
>> 1) & 7;
1056 case CC_OP_SUBB
... CC_OP_SUBQ
:
1057 /* We optimize relational operators for the cmp/jcc case. */
1058 size
= s
->cc_op
- CC_OP_SUBB
;
1061 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
1062 gen_extu(size
, cpu_tmp4
);
1063 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
1064 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
1065 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1074 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
1075 gen_exts(size
, cpu_tmp4
);
1076 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1077 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
1078 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1088 /* This actually generates good code for JC, JZ and JS. */
1091 cc
= gen_prepare_eflags_o(s
, reg
);
1094 cc
= gen_prepare_eflags_c(s
, reg
);
1097 cc
= gen_prepare_eflags_z(s
, reg
);
1100 gen_compute_eflags(s
);
1101 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1102 .mask
= CC_Z
| CC_C
};
1105 cc
= gen_prepare_eflags_s(s
, reg
);
1108 cc
= gen_prepare_eflags_p(s
, reg
);
1111 gen_compute_eflags(s
);
1112 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1115 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1116 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1117 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1122 gen_compute_eflags(s
);
1123 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1126 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1127 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1128 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1129 .mask
= CC_S
| CC_Z
};
1136 cc
.cond
= tcg_invert_cond(cc
.cond
);
1141 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1143 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1145 if (cc
.no_setcond
) {
1146 if (cc
.cond
== TCG_COND_EQ
) {
1147 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1149 tcg_gen_mov_tl(reg
, cc
.reg
);
1154 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1155 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1156 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1157 tcg_gen_andi_tl(reg
, reg
, 1);
1160 if (cc
.mask
!= -1) {
1161 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1165 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1167 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1171 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1173 gen_setcc1(s
, JCC_B
<< 1, reg
);
1176 /* generate a conditional jump to label 'l1' according to jump opcode
1177 value 'b'. In the fast case, T0 is guaranted not to be used. */
1178 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1180 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1182 if (cc
.mask
!= -1) {
1183 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1187 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1189 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1193 /* Generate a conditional jump to label 'l1' according to jump opcode
1194 value 'b'. In the fast case, T0 is guaranted not to be used.
1195 A translation block must end soon. */
1196 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1198 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1200 gen_update_cc_op(s
);
1201 if (cc
.mask
!= -1) {
1202 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1205 set_cc_op(s
, CC_OP_DYNAMIC
);
1207 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1209 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1213 /* XXX: does not work with gdbstub "ice" single step - not a
1215 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1219 l1
= gen_new_label();
1220 l2
= gen_new_label();
1221 gen_op_jnz_ecx(s
->aflag
, l1
);
1223 gen_jmp_tb(s
, next_eip
, 1);
1228 static inline void gen_stos(DisasContext
*s
, int ot
)
1230 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1231 gen_string_movl_A0_EDI(s
);
1232 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1233 gen_op_movl_T0_Dshift(ot
);
1234 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1237 static inline void gen_lods(DisasContext
*s
, int ot
)
1239 gen_string_movl_A0_ESI(s
);
1240 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1241 gen_op_mov_reg_T0(ot
, R_EAX
);
1242 gen_op_movl_T0_Dshift(ot
);
1243 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1246 static inline void gen_scas(DisasContext
*s
, int ot
)
1248 gen_string_movl_A0_EDI(s
);
1249 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1250 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1251 gen_op_movl_T0_Dshift(ot
);
1252 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1255 static inline void gen_cmps(DisasContext
*s
, int ot
)
1257 gen_string_movl_A0_EDI(s
);
1258 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1259 gen_string_movl_A0_ESI(s
);
1260 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1261 gen_op_movl_T0_Dshift(ot
);
1262 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1263 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1266 static inline void gen_ins(DisasContext
*s
, int ot
)
1270 gen_string_movl_A0_EDI(s
);
1271 /* Note: we must do this dummy write first to be restartable in
1272 case of page fault. */
1274 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1275 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1276 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1277 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1278 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1279 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1280 gen_op_movl_T0_Dshift(ot
);
1281 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1286 static inline void gen_outs(DisasContext
*s
, int ot
)
1290 gen_string_movl_A0_ESI(s
);
1291 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1293 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1294 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1295 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1296 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1297 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1299 gen_op_movl_T0_Dshift(ot
);
1300 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1305 /* same method as Valgrind : we generate jumps to current or next
1307 #define GEN_REPZ(op) \
1308 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1309 target_ulong cur_eip, target_ulong next_eip) \
1312 gen_update_cc_op(s); \
1313 l2 = gen_jz_ecx_string(s, next_eip); \
1314 gen_ ## op(s, ot); \
1315 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1316 /* a loop would cause two single step exceptions if ECX = 1 \
1317 before rep string_insn */ \
1319 gen_op_jz_ecx(s->aflag, l2); \
1320 gen_jmp(s, cur_eip); \
1323 #define GEN_REPZ2(op) \
1324 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1325 target_ulong cur_eip, \
1326 target_ulong next_eip, \
1330 gen_update_cc_op(s); \
1331 l2 = gen_jz_ecx_string(s, next_eip); \
1332 gen_ ## op(s, ot); \
1333 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1334 gen_update_cc_op(s); \
1335 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1337 gen_op_jz_ecx(s->aflag, l2); \
1338 gen_jmp(s, cur_eip); \
1349 static void gen_helper_fp_arith_ST0_FT0(int op
)
1353 gen_helper_fadd_ST0_FT0(cpu_env
);
1356 gen_helper_fmul_ST0_FT0(cpu_env
);
1359 gen_helper_fcom_ST0_FT0(cpu_env
);
1362 gen_helper_fcom_ST0_FT0(cpu_env
);
1365 gen_helper_fsub_ST0_FT0(cpu_env
);
1368 gen_helper_fsubr_ST0_FT0(cpu_env
);
1371 gen_helper_fdiv_ST0_FT0(cpu_env
);
1374 gen_helper_fdivr_ST0_FT0(cpu_env
);
1379 /* NOTE the exception in "r" op ordering */
1380 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1382 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1385 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1388 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1391 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1394 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1397 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1400 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1405 /* if d == OR_TMP0, it means memory operand (address in A0) */
1406 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1409 gen_op_mov_TN_reg(ot
, 0, d
);
1411 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1415 gen_compute_eflags_c(s1
, cpu_tmp4
);
1416 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1417 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1419 gen_op_mov_reg_T0(ot
, d
);
1421 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1422 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1423 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1424 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1425 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1426 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1427 set_cc_op(s1
, CC_OP_DYNAMIC
);
1431 * No need to store cpu_cc_srcT, because it is used only
1432 * when the cc_op is known.
1434 gen_compute_eflags_c(s1
, cpu_tmp4
);
1435 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1436 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1438 gen_op_mov_reg_T0(ot
, d
);
1440 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1441 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1442 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1443 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1444 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1445 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1446 set_cc_op(s1
, CC_OP_DYNAMIC
);
1449 gen_op_addl_T0_T1();
1451 gen_op_mov_reg_T0(ot
, d
);
1453 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1454 gen_op_update2_cc();
1455 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1458 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1459 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1461 gen_op_mov_reg_T0(ot
, d
);
1463 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1464 gen_op_update2_cc();
1465 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1469 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1471 gen_op_mov_reg_T0(ot
, d
);
1473 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1474 gen_op_update1_cc();
1475 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1478 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1480 gen_op_mov_reg_T0(ot
, d
);
1482 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1483 gen_op_update1_cc();
1484 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1487 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1489 gen_op_mov_reg_T0(ot
, d
);
1491 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1492 gen_op_update1_cc();
1493 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1496 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1497 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1498 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1499 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1504 /* if d == OR_TMP0, it means memory operand (address in A0) */
1505 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1508 gen_op_mov_TN_reg(ot
, 0, d
);
1510 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1511 gen_compute_eflags_c(s1
, cpu_cc_src
);
1513 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1514 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1516 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1517 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1520 gen_op_mov_reg_T0(ot
, d
);
1522 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1523 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1526 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1527 int is_right
, int is_arith
)
1533 if (ot
== OT_QUAD
) {
1540 if (op1
== OR_TMP0
) {
1541 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1543 gen_op_mov_TN_reg(ot
, 0, op1
);
1546 t0
= tcg_temp_local_new();
1547 t1
= tcg_temp_local_new();
1548 t2
= tcg_temp_local_new();
1550 tcg_gen_andi_tl(t2
, cpu_T
[1], mask
);
1554 gen_exts(ot
, cpu_T
[0]);
1555 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1556 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], t2
);
1558 gen_extu(ot
, cpu_T
[0]);
1559 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1560 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], t2
);
1563 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1564 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], t2
);
1568 if (op1
== OR_TMP0
) {
1569 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1571 gen_op_mov_reg_T0(ot
, op1
);
1574 /* Update eflags data because we cannot predict flags afterward. */
1575 gen_update_cc_op(s
);
1576 set_cc_op(s
, CC_OP_DYNAMIC
);
1578 tcg_gen_mov_tl(t1
, cpu_T
[0]);
1580 shift_label
= gen_new_label();
1581 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, shift_label
);
1583 tcg_gen_addi_tl(t2
, t2
, -1);
1584 tcg_gen_mov_tl(cpu_cc_dst
, t1
);
1588 tcg_gen_sar_tl(cpu_cc_src
, t0
, t2
);
1590 tcg_gen_shr_tl(cpu_cc_src
, t0
, t2
);
1593 tcg_gen_shl_tl(cpu_cc_src
, t0
, t2
);
1597 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1599 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1602 gen_set_label(shift_label
);
1609 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1610 int is_right
, int is_arith
)
1621 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1623 gen_op_mov_TN_reg(ot
, 0, op1
);
1629 gen_exts(ot
, cpu_T
[0]);
1630 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1631 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1633 gen_extu(ot
, cpu_T
[0]);
1634 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1635 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1638 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1639 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1645 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1647 gen_op_mov_reg_T0(ot
, op1
);
1649 /* update eflags if non zero shift */
1651 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1652 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1653 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1657 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1660 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1662 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1665 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1669 int label1
, label2
, data_bits
;
1670 TCGv t0
, t1
, t2
, a0
;
1672 /* XXX: inefficient, but we must use local temps */
1673 t0
= tcg_temp_local_new();
1674 t1
= tcg_temp_local_new();
1675 t2
= tcg_temp_local_new();
1676 a0
= tcg_temp_local_new();
1684 if (op1
== OR_TMP0
) {
1685 tcg_gen_mov_tl(a0
, cpu_A0
);
1686 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1688 gen_op_mov_v_reg(ot
, t0
, op1
);
1691 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1693 tcg_gen_andi_tl(t1
, t1
, mask
);
1695 /* Must test zero case to avoid using undefined behaviour in TCG
1697 label1
= gen_new_label();
1698 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1701 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1703 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1706 tcg_gen_mov_tl(t2
, t0
);
1708 data_bits
= 8 << ot
;
1709 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1710 fix TCG definition) */
1712 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1713 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1714 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1716 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1717 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1718 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1720 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1722 gen_set_label(label1
);
1724 if (op1
== OR_TMP0
) {
1725 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1727 gen_op_mov_reg_v(ot
, op1
, t0
);
1730 /* update eflags. It is needed anyway most of the time, do it always. */
1731 gen_compute_eflags(s
);
1732 assert(s
->cc_op
== CC_OP_EFLAGS
);
1734 label2
= gen_new_label();
1735 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1737 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1738 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1739 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1740 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1741 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1743 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1745 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1746 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1748 gen_set_label(label2
);
1756 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1763 /* XXX: inefficient, but we must use local temps */
1764 t0
= tcg_temp_local_new();
1765 t1
= tcg_temp_local_new();
1766 a0
= tcg_temp_local_new();
1774 if (op1
== OR_TMP0
) {
1775 tcg_gen_mov_tl(a0
, cpu_A0
);
1776 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1778 gen_op_mov_v_reg(ot
, t0
, op1
);
1782 tcg_gen_mov_tl(t1
, t0
);
1785 data_bits
= 8 << ot
;
1787 int shift
= op2
& ((1 << (3 + ot
)) - 1);
1789 tcg_gen_shri_tl(cpu_tmp4
, t0
, shift
);
1790 tcg_gen_shli_tl(t0
, t0
, data_bits
- shift
);
1793 tcg_gen_shli_tl(cpu_tmp4
, t0
, shift
);
1794 tcg_gen_shri_tl(t0
, t0
, data_bits
- shift
);
1796 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1800 if (op1
== OR_TMP0
) {
1801 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1803 gen_op_mov_reg_v(ot
, op1
, t0
);
1808 gen_compute_eflags(s
);
1809 assert(s
->cc_op
== CC_OP_EFLAGS
);
1811 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1812 tcg_gen_xor_tl(cpu_tmp0
, t1
, t0
);
1813 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1814 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1815 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1817 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1819 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1820 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1828 /* XXX: add faster immediate = 1 case */
1829 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1832 gen_compute_eflags(s
);
1833 assert(s
->cc_op
== CC_OP_EFLAGS
);
1837 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1839 gen_op_mov_TN_reg(ot
, 0, op1
);
1844 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1847 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1850 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1852 #ifdef TARGET_X86_64
1854 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1861 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1864 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1867 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1869 #ifdef TARGET_X86_64
1871 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1878 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1880 gen_op_mov_reg_T0(ot
, op1
);
1883 /* XXX: add faster immediate case */
1884 static void gen_shiftd_rm_T1(DisasContext
*s
, int ot
, int op1
,
1885 int is_right
, TCGv count
)
1887 int label1
, label2
, data_bits
;
1889 TCGv t0
, t1
, t2
, a0
;
1891 t0
= tcg_temp_local_new();
1892 t1
= tcg_temp_local_new();
1893 t2
= tcg_temp_local_new();
1894 a0
= tcg_temp_local_new();
1902 if (op1
== OR_TMP0
) {
1903 tcg_gen_mov_tl(a0
, cpu_A0
);
1904 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1906 gen_op_mov_v_reg(ot
, t0
, op1
);
1909 tcg_gen_andi_tl(t2
, count
, mask
);
1910 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1912 /* Must test zero case to avoid using undefined behaviour in TCG
1914 label1
= gen_new_label();
1915 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
1917 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
1918 if (ot
== OT_WORD
) {
1919 /* Note: we implement the Intel behaviour for shift count > 16 */
1921 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1922 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
1923 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1924 tcg_gen_ext32u_tl(t0
, t0
);
1926 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1928 /* only needed if count > 16, but a test would complicate */
1929 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1930 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
1932 tcg_gen_shr_tl(t0
, t0
, t2
);
1934 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1936 /* XXX: not optimal */
1937 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1938 tcg_gen_shli_tl(t1
, t1
, 16);
1939 tcg_gen_or_tl(t1
, t1
, t0
);
1940 tcg_gen_ext32u_tl(t1
, t1
);
1942 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1943 tcg_gen_subfi_tl(cpu_tmp0
, 32, cpu_tmp5
);
1944 tcg_gen_shr_tl(cpu_tmp5
, t1
, cpu_tmp0
);
1945 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp5
);
1947 tcg_gen_shl_tl(t0
, t0
, t2
);
1948 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1949 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1950 tcg_gen_or_tl(t0
, t0
, t1
);
1953 data_bits
= 8 << ot
;
1956 tcg_gen_ext32u_tl(t0
, t0
);
1958 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1960 tcg_gen_shr_tl(t0
, t0
, t2
);
1961 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1962 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
1963 tcg_gen_or_tl(t0
, t0
, t1
);
1967 tcg_gen_ext32u_tl(t1
, t1
);
1969 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1971 tcg_gen_shl_tl(t0
, t0
, t2
);
1972 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1973 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1974 tcg_gen_or_tl(t0
, t0
, t1
);
1977 tcg_gen_mov_tl(t1
, cpu_tmp4
);
1979 gen_set_label(label1
);
1981 if (op1
== OR_TMP0
) {
1982 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1984 gen_op_mov_reg_v(ot
, op1
, t0
);
1987 /* Update eflags data because we cannot predict flags afterward. */
1988 gen_update_cc_op(s
);
1989 set_cc_op(s
, CC_OP_DYNAMIC
);
1991 label2
= gen_new_label();
1992 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
1994 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1995 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1997 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1999 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
2001 gen_set_label(label2
);
2009 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
2012 gen_op_mov_TN_reg(ot
, 1, s
);
2015 gen_rot_rm_T1(s1
, ot
, d
, 0);
2018 gen_rot_rm_T1(s1
, ot
, d
, 1);
2022 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
2025 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
2028 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
2031 gen_rotc_rm_T1(s1
, ot
, d
, 0);
2034 gen_rotc_rm_T1(s1
, ot
, d
, 1);
2039 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
2043 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
2046 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
2050 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
2053 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
2056 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
2059 /* currently not optimized */
2060 gen_op_movl_T1_im(c
);
2061 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
2066 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2067 int *reg_ptr
, int *offset_ptr
)
2075 int mod
, rm
, code
, override
, must_add_seg
;
2077 override
= s
->override
;
2078 must_add_seg
= s
->addseg
;
2081 mod
= (modrm
>> 6) & 3;
2093 code
= cpu_ldub_code(env
, s
->pc
++);
2094 scale
= (code
>> 6) & 3;
2095 index
= ((code
>> 3) & 7) | REX_X(s
);
2102 if ((base
& 7) == 5) {
2104 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2106 if (CODE64(s
) && !havesib
) {
2107 disp
+= s
->pc
+ s
->rip_offset
;
2114 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2118 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2124 /* for correct popl handling with esp */
2125 if (base
== 4 && s
->popl_esp_hack
)
2126 disp
+= s
->popl_esp_hack
;
2127 #ifdef TARGET_X86_64
2128 if (s
->aflag
== 2) {
2129 gen_op_movq_A0_reg(base
);
2131 gen_op_addq_A0_im(disp
);
2136 gen_op_movl_A0_reg(base
);
2138 gen_op_addl_A0_im(disp
);
2141 #ifdef TARGET_X86_64
2142 if (s
->aflag
== 2) {
2143 gen_op_movq_A0_im(disp
);
2147 gen_op_movl_A0_im(disp
);
2150 /* index == 4 means no index */
2151 if (havesib
&& (index
!= 4)) {
2152 #ifdef TARGET_X86_64
2153 if (s
->aflag
== 2) {
2154 gen_op_addq_A0_reg_sN(scale
, index
);
2158 gen_op_addl_A0_reg_sN(scale
, index
);
2163 if (base
== R_EBP
|| base
== R_ESP
)
2168 #ifdef TARGET_X86_64
2169 if (s
->aflag
== 2) {
2170 gen_op_addq_A0_seg(override
);
2174 gen_op_addl_A0_seg(s
, override
);
2181 disp
= cpu_lduw_code(env
, s
->pc
);
2183 gen_op_movl_A0_im(disp
);
2184 rm
= 0; /* avoid SS override */
2191 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2195 disp
= cpu_lduw_code(env
, s
->pc
);
2201 gen_op_movl_A0_reg(R_EBX
);
2202 gen_op_addl_A0_reg_sN(0, R_ESI
);
2205 gen_op_movl_A0_reg(R_EBX
);
2206 gen_op_addl_A0_reg_sN(0, R_EDI
);
2209 gen_op_movl_A0_reg(R_EBP
);
2210 gen_op_addl_A0_reg_sN(0, R_ESI
);
2213 gen_op_movl_A0_reg(R_EBP
);
2214 gen_op_addl_A0_reg_sN(0, R_EDI
);
2217 gen_op_movl_A0_reg(R_ESI
);
2220 gen_op_movl_A0_reg(R_EDI
);
2223 gen_op_movl_A0_reg(R_EBP
);
2227 gen_op_movl_A0_reg(R_EBX
);
2231 gen_op_addl_A0_im(disp
);
2232 gen_op_andl_A0_ffff();
2236 if (rm
== 2 || rm
== 3 || rm
== 6)
2241 gen_op_addl_A0_seg(s
, override
);
2251 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2253 int mod
, rm
, base
, code
;
2255 mod
= (modrm
>> 6) & 3;
2265 code
= cpu_ldub_code(env
, s
->pc
++);
2301 /* used for LEA and MOV AX, mem */
2302 static void gen_add_A0_ds_seg(DisasContext
*s
)
2304 int override
, must_add_seg
;
2305 must_add_seg
= s
->addseg
;
2307 if (s
->override
>= 0) {
2308 override
= s
->override
;
2312 #ifdef TARGET_X86_64
2314 gen_op_addq_A0_seg(override
);
2318 gen_op_addl_A0_seg(s
, override
);
2323 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2325 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2326 int ot
, int reg
, int is_store
)
2328 int mod
, rm
, opreg
, disp
;
2330 mod
= (modrm
>> 6) & 3;
2331 rm
= (modrm
& 7) | REX_B(s
);
2335 gen_op_mov_TN_reg(ot
, 0, reg
);
2336 gen_op_mov_reg_T0(ot
, rm
);
2338 gen_op_mov_TN_reg(ot
, 0, rm
);
2340 gen_op_mov_reg_T0(ot
, reg
);
2343 gen_lea_modrm(env
, s
, modrm
, &opreg
, &disp
);
2346 gen_op_mov_TN_reg(ot
, 0, reg
);
2347 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2349 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2351 gen_op_mov_reg_T0(ot
, reg
);
2356 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, int ot
)
2362 ret
= cpu_ldub_code(env
, s
->pc
);
2366 ret
= cpu_lduw_code(env
, s
->pc
);
2371 ret
= cpu_ldl_code(env
, s
->pc
);
2378 static inline int insn_const_size(unsigned int ot
)
2386 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2388 TranslationBlock
*tb
;
2391 pc
= s
->cs_base
+ eip
;
2393 /* NOTE: we handle the case where the TB spans two pages here */
2394 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2395 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2396 /* jump to same page: we can use a direct jump */
2397 tcg_gen_goto_tb(tb_num
);
2399 tcg_gen_exit_tb((tcg_target_long
)tb
+ tb_num
);
2401 /* jump to another page: currently not optimized */
2407 static inline void gen_jcc(DisasContext
*s
, int b
,
2408 target_ulong val
, target_ulong next_eip
)
2413 l1
= gen_new_label();
2416 gen_goto_tb(s
, 0, next_eip
);
2419 gen_goto_tb(s
, 1, val
);
2420 s
->is_jmp
= DISAS_TB_JUMP
;
2422 l1
= gen_new_label();
2423 l2
= gen_new_label();
2426 gen_jmp_im(next_eip
);
2436 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, int ot
, int b
,
2441 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2443 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2444 if (cc
.mask
!= -1) {
2445 TCGv t0
= tcg_temp_new();
2446 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2450 cc
.reg2
= tcg_const_tl(cc
.imm
);
2453 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2454 cpu_T
[0], cpu_regs
[reg
]);
2455 gen_op_mov_reg_T0(ot
, reg
);
2457 if (cc
.mask
!= -1) {
2458 tcg_temp_free(cc
.reg
);
2461 tcg_temp_free(cc
.reg2
);
2465 static inline void gen_op_movl_T0_seg(int seg_reg
)
2467 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2468 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2471 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2473 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2474 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2475 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2476 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2477 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2478 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2481 /* move T0 to seg_reg and compute if the CPU state may change. Never
2482 call this function with seg_reg == R_CS */
2483 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2485 if (s
->pe
&& !s
->vm86
) {
2486 /* XXX: optimize by finding processor state dynamically */
2487 gen_update_cc_op(s
);
2488 gen_jmp_im(cur_eip
);
2489 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2490 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2491 /* abort translation because the addseg value may change or
2492 because ss32 may change. For R_SS, translation must always
2493 stop as a special handling must be done to disable hardware
2494 interrupts for the next instruction */
2495 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2496 s
->is_jmp
= DISAS_TB_JUMP
;
2498 gen_op_movl_seg_T0_vm(seg_reg
);
2499 if (seg_reg
== R_SS
)
2500 s
->is_jmp
= DISAS_TB_JUMP
;
2504 static inline int svm_is_rep(int prefixes
)
2506 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2510 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2511 uint32_t type
, uint64_t param
)
2513 /* no SVM activated; fast case */
2514 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2516 gen_update_cc_op(s
);
2517 gen_jmp_im(pc_start
- s
->cs_base
);
2518 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2519 tcg_const_i64(param
));
2523 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2525 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2528 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2530 #ifdef TARGET_X86_64
2532 gen_op_add_reg_im(2, R_ESP
, addend
);
2536 gen_op_add_reg_im(1, R_ESP
, addend
);
2538 gen_op_add_reg_im(0, R_ESP
, addend
);
2542 /* generate a push. It depends on ss32, addseg and dflag */
2543 static void gen_push_T0(DisasContext
*s
)
2545 #ifdef TARGET_X86_64
2547 gen_op_movq_A0_reg(R_ESP
);
2549 gen_op_addq_A0_im(-8);
2550 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2552 gen_op_addq_A0_im(-2);
2553 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2555 gen_op_mov_reg_A0(2, R_ESP
);
2559 gen_op_movl_A0_reg(R_ESP
);
2561 gen_op_addl_A0_im(-2);
2563 gen_op_addl_A0_im(-4);
2566 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2567 gen_op_addl_A0_seg(s
, R_SS
);
2570 gen_op_andl_A0_ffff();
2571 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2572 gen_op_addl_A0_seg(s
, R_SS
);
2574 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2575 if (s
->ss32
&& !s
->addseg
)
2576 gen_op_mov_reg_A0(1, R_ESP
);
2578 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2582 /* generate a push. It depends on ss32, addseg and dflag */
2583 /* slower version for T1, only used for call Ev */
2584 static void gen_push_T1(DisasContext
*s
)
2586 #ifdef TARGET_X86_64
2588 gen_op_movq_A0_reg(R_ESP
);
2590 gen_op_addq_A0_im(-8);
2591 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2593 gen_op_addq_A0_im(-2);
2594 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2596 gen_op_mov_reg_A0(2, R_ESP
);
2600 gen_op_movl_A0_reg(R_ESP
);
2602 gen_op_addl_A0_im(-2);
2604 gen_op_addl_A0_im(-4);
2607 gen_op_addl_A0_seg(s
, R_SS
);
2610 gen_op_andl_A0_ffff();
2611 gen_op_addl_A0_seg(s
, R_SS
);
2613 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2615 if (s
->ss32
&& !s
->addseg
)
2616 gen_op_mov_reg_A0(1, R_ESP
);
2618 gen_stack_update(s
, (-2) << s
->dflag
);
2622 /* two step pop is necessary for precise exceptions */
2623 static void gen_pop_T0(DisasContext
*s
)
2625 #ifdef TARGET_X86_64
2627 gen_op_movq_A0_reg(R_ESP
);
2628 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2632 gen_op_movl_A0_reg(R_ESP
);
2635 gen_op_addl_A0_seg(s
, R_SS
);
2637 gen_op_andl_A0_ffff();
2638 gen_op_addl_A0_seg(s
, R_SS
);
2640 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2644 static void gen_pop_update(DisasContext
*s
)
2646 #ifdef TARGET_X86_64
2647 if (CODE64(s
) && s
->dflag
) {
2648 gen_stack_update(s
, 8);
2652 gen_stack_update(s
, 2 << s
->dflag
);
2656 static void gen_stack_A0(DisasContext
*s
)
2658 gen_op_movl_A0_reg(R_ESP
);
2660 gen_op_andl_A0_ffff();
2661 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2663 gen_op_addl_A0_seg(s
, R_SS
);
2666 /* NOTE: wrap around in 16 bit not fully handled */
2667 static void gen_pusha(DisasContext
*s
)
2670 gen_op_movl_A0_reg(R_ESP
);
2671 gen_op_addl_A0_im(-16 << s
->dflag
);
2673 gen_op_andl_A0_ffff();
2674 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2676 gen_op_addl_A0_seg(s
, R_SS
);
2677 for(i
= 0;i
< 8; i
++) {
2678 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2679 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2680 gen_op_addl_A0_im(2 << s
->dflag
);
2682 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2685 /* NOTE: wrap around in 16 bit not fully handled */
2686 static void gen_popa(DisasContext
*s
)
2689 gen_op_movl_A0_reg(R_ESP
);
2691 gen_op_andl_A0_ffff();
2692 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2693 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2695 gen_op_addl_A0_seg(s
, R_SS
);
2696 for(i
= 0;i
< 8; i
++) {
2697 /* ESP is not reloaded */
2699 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2700 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2702 gen_op_addl_A0_im(2 << s
->dflag
);
2704 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2707 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2712 #ifdef TARGET_X86_64
2714 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2717 gen_op_movl_A0_reg(R_ESP
);
2718 gen_op_addq_A0_im(-opsize
);
2719 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2722 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2723 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2725 /* XXX: must save state */
2726 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2727 tcg_const_i32((ot
== OT_QUAD
)),
2730 gen_op_mov_reg_T1(ot
, R_EBP
);
2731 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2732 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2736 ot
= s
->dflag
+ OT_WORD
;
2737 opsize
= 2 << s
->dflag
;
2739 gen_op_movl_A0_reg(R_ESP
);
2740 gen_op_addl_A0_im(-opsize
);
2742 gen_op_andl_A0_ffff();
2743 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2745 gen_op_addl_A0_seg(s
, R_SS
);
2747 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2748 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2750 /* XXX: must save state */
2751 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2752 tcg_const_i32(s
->dflag
),
2755 gen_op_mov_reg_T1(ot
, R_EBP
);
2756 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2757 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2761 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2763 gen_update_cc_op(s
);
2764 gen_jmp_im(cur_eip
);
2765 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2766 s
->is_jmp
= DISAS_TB_JUMP
;
2769 /* an interrupt is different from an exception because of the
2771 static void gen_interrupt(DisasContext
*s
, int intno
,
2772 target_ulong cur_eip
, target_ulong next_eip
)
2774 gen_update_cc_op(s
);
2775 gen_jmp_im(cur_eip
);
2776 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2777 tcg_const_i32(next_eip
- cur_eip
));
2778 s
->is_jmp
= DISAS_TB_JUMP
;
2781 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2783 gen_update_cc_op(s
);
2784 gen_jmp_im(cur_eip
);
2785 gen_helper_debug(cpu_env
);
2786 s
->is_jmp
= DISAS_TB_JUMP
;
2789 /* generate a generic end of block. Trace exception is also generated
2791 static void gen_eob(DisasContext
*s
)
2793 gen_update_cc_op(s
);
2794 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2795 gen_helper_reset_inhibit_irq(cpu_env
);
2797 if (s
->tb
->flags
& HF_RF_MASK
) {
2798 gen_helper_reset_rf(cpu_env
);
2800 if (s
->singlestep_enabled
) {
2801 gen_helper_debug(cpu_env
);
2803 gen_helper_single_step(cpu_env
);
2807 s
->is_jmp
= DISAS_TB_JUMP
;
2810 /* generate a jump to eip. No segment change must happen before as a
2811 direct call to the next block may occur */
2812 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2814 gen_update_cc_op(s
);
2815 set_cc_op(s
, CC_OP_DYNAMIC
);
2817 gen_goto_tb(s
, tb_num
, eip
);
2818 s
->is_jmp
= DISAS_TB_JUMP
;
2825 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2827 gen_jmp_tb(s
, eip
, 0);
2830 static inline void gen_ldq_env_A0(int idx
, int offset
)
2832 int mem_index
= (idx
>> 2) - 1;
2833 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2834 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2837 static inline void gen_stq_env_A0(int idx
, int offset
)
2839 int mem_index
= (idx
>> 2) - 1;
2840 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2841 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2844 static inline void gen_ldo_env_A0(int idx
, int offset
)
2846 int mem_index
= (idx
>> 2) - 1;
2847 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2848 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2849 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2850 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2851 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2854 static inline void gen_sto_env_A0(int idx
, int offset
)
2856 int mem_index
= (idx
>> 2) - 1;
2857 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2858 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2859 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2860 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2861 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2864 static inline void gen_op_movo(int d_offset
, int s_offset
)
2866 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2867 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2868 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2869 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2872 static inline void gen_op_movq(int d_offset
, int s_offset
)
2874 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2875 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2878 static inline void gen_op_movl(int d_offset
, int s_offset
)
2880 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2881 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2884 static inline void gen_op_movq_env_0(int d_offset
)
2886 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2887 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2890 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2891 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2892 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2893 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2894 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2895 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2897 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2898 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2901 #define SSE_SPECIAL ((void *)1)
2902 #define SSE_DUMMY ((void *)2)
2904 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2905 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2906 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2908 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2909 /* 3DNow! extensions */
2910 [0x0e] = { SSE_DUMMY
}, /* femms */
2911 [0x0f] = { SSE_DUMMY
}, /* pf... */
2912 /* pure SSE operations */
2913 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2914 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2915 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2916 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2917 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2918 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2919 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2920 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2922 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2923 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2924 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2925 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2926 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2927 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2928 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2929 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2930 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2931 [0x51] = SSE_FOP(sqrt
),
2932 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2933 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2934 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2935 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2936 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2937 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2938 [0x58] = SSE_FOP(add
),
2939 [0x59] = SSE_FOP(mul
),
2940 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2941 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2942 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2943 [0x5c] = SSE_FOP(sub
),
2944 [0x5d] = SSE_FOP(min
),
2945 [0x5e] = SSE_FOP(div
),
2946 [0x5f] = SSE_FOP(max
),
2948 [0xc2] = SSE_FOP(cmpeq
),
2949 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2950 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2952 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2953 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2955 /* MMX ops and their SSE extensions */
2956 [0x60] = MMX_OP2(punpcklbw
),
2957 [0x61] = MMX_OP2(punpcklwd
),
2958 [0x62] = MMX_OP2(punpckldq
),
2959 [0x63] = MMX_OP2(packsswb
),
2960 [0x64] = MMX_OP2(pcmpgtb
),
2961 [0x65] = MMX_OP2(pcmpgtw
),
2962 [0x66] = MMX_OP2(pcmpgtl
),
2963 [0x67] = MMX_OP2(packuswb
),
2964 [0x68] = MMX_OP2(punpckhbw
),
2965 [0x69] = MMX_OP2(punpckhwd
),
2966 [0x6a] = MMX_OP2(punpckhdq
),
2967 [0x6b] = MMX_OP2(packssdw
),
2968 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2969 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2970 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2971 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2972 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2973 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2974 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2975 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2976 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2977 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2978 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2979 [0x74] = MMX_OP2(pcmpeqb
),
2980 [0x75] = MMX_OP2(pcmpeqw
),
2981 [0x76] = MMX_OP2(pcmpeql
),
2982 [0x77] = { SSE_DUMMY
}, /* emms */
2983 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2984 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2985 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2986 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2987 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2988 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2989 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2990 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2991 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2992 [0xd1] = MMX_OP2(psrlw
),
2993 [0xd2] = MMX_OP2(psrld
),
2994 [0xd3] = MMX_OP2(psrlq
),
2995 [0xd4] = MMX_OP2(paddq
),
2996 [0xd5] = MMX_OP2(pmullw
),
2997 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2998 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2999 [0xd8] = MMX_OP2(psubusb
),
3000 [0xd9] = MMX_OP2(psubusw
),
3001 [0xda] = MMX_OP2(pminub
),
3002 [0xdb] = MMX_OP2(pand
),
3003 [0xdc] = MMX_OP2(paddusb
),
3004 [0xdd] = MMX_OP2(paddusw
),
3005 [0xde] = MMX_OP2(pmaxub
),
3006 [0xdf] = MMX_OP2(pandn
),
3007 [0xe0] = MMX_OP2(pavgb
),
3008 [0xe1] = MMX_OP2(psraw
),
3009 [0xe2] = MMX_OP2(psrad
),
3010 [0xe3] = MMX_OP2(pavgw
),
3011 [0xe4] = MMX_OP2(pmulhuw
),
3012 [0xe5] = MMX_OP2(pmulhw
),
3013 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
3014 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
3015 [0xe8] = MMX_OP2(psubsb
),
3016 [0xe9] = MMX_OP2(psubsw
),
3017 [0xea] = MMX_OP2(pminsw
),
3018 [0xeb] = MMX_OP2(por
),
3019 [0xec] = MMX_OP2(paddsb
),
3020 [0xed] = MMX_OP2(paddsw
),
3021 [0xee] = MMX_OP2(pmaxsw
),
3022 [0xef] = MMX_OP2(pxor
),
3023 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
3024 [0xf1] = MMX_OP2(psllw
),
3025 [0xf2] = MMX_OP2(pslld
),
3026 [0xf3] = MMX_OP2(psllq
),
3027 [0xf4] = MMX_OP2(pmuludq
),
3028 [0xf5] = MMX_OP2(pmaddwd
),
3029 [0xf6] = MMX_OP2(psadbw
),
3030 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
3031 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
3032 [0xf8] = MMX_OP2(psubb
),
3033 [0xf9] = MMX_OP2(psubw
),
3034 [0xfa] = MMX_OP2(psubl
),
3035 [0xfb] = MMX_OP2(psubq
),
3036 [0xfc] = MMX_OP2(paddb
),
3037 [0xfd] = MMX_OP2(paddw
),
3038 [0xfe] = MMX_OP2(paddl
),
3041 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
3042 [0 + 2] = MMX_OP2(psrlw
),
3043 [0 + 4] = MMX_OP2(psraw
),
3044 [0 + 6] = MMX_OP2(psllw
),
3045 [8 + 2] = MMX_OP2(psrld
),
3046 [8 + 4] = MMX_OP2(psrad
),
3047 [8 + 6] = MMX_OP2(pslld
),
3048 [16 + 2] = MMX_OP2(psrlq
),
3049 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
3050 [16 + 6] = MMX_OP2(psllq
),
3051 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
3054 static const SSEFunc_0_epi sse_op_table3ai
[] = {
3055 gen_helper_cvtsi2ss
,
3059 #ifdef TARGET_X86_64
3060 static const SSEFunc_0_epl sse_op_table3aq
[] = {
3061 gen_helper_cvtsq2ss
,
3066 static const SSEFunc_i_ep sse_op_table3bi
[] = {
3067 gen_helper_cvttss2si
,
3068 gen_helper_cvtss2si
,
3069 gen_helper_cvttsd2si
,
3073 #ifdef TARGET_X86_64
3074 static const SSEFunc_l_ep sse_op_table3bq
[] = {
3075 gen_helper_cvttss2sq
,
3076 gen_helper_cvtss2sq
,
3077 gen_helper_cvttsd2sq
,
3082 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
3093 static const SSEFunc_0_epp sse_op_table5
[256] = {
3094 [0x0c] = gen_helper_pi2fw
,
3095 [0x0d] = gen_helper_pi2fd
,
3096 [0x1c] = gen_helper_pf2iw
,
3097 [0x1d] = gen_helper_pf2id
,
3098 [0x8a] = gen_helper_pfnacc
,
3099 [0x8e] = gen_helper_pfpnacc
,
3100 [0x90] = gen_helper_pfcmpge
,
3101 [0x94] = gen_helper_pfmin
,
3102 [0x96] = gen_helper_pfrcp
,
3103 [0x97] = gen_helper_pfrsqrt
,
3104 [0x9a] = gen_helper_pfsub
,
3105 [0x9e] = gen_helper_pfadd
,
3106 [0xa0] = gen_helper_pfcmpgt
,
3107 [0xa4] = gen_helper_pfmax
,
3108 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
3109 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
3110 [0xaa] = gen_helper_pfsubr
,
3111 [0xae] = gen_helper_pfacc
,
3112 [0xb0] = gen_helper_pfcmpeq
,
3113 [0xb4] = gen_helper_pfmul
,
3114 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3115 [0xb7] = gen_helper_pmulhrw_mmx
,
3116 [0xbb] = gen_helper_pswapd
,
3117 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3120 struct SSEOpHelper_epp
{
3121 SSEFunc_0_epp op
[2];
3125 struct SSEOpHelper_eppi
{
3126 SSEFunc_0_eppi op
[2];
3130 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3131 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3132 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3133 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3135 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
3136 [0x00] = SSSE3_OP(pshufb
),
3137 [0x01] = SSSE3_OP(phaddw
),
3138 [0x02] = SSSE3_OP(phaddd
),
3139 [0x03] = SSSE3_OP(phaddsw
),
3140 [0x04] = SSSE3_OP(pmaddubsw
),
3141 [0x05] = SSSE3_OP(phsubw
),
3142 [0x06] = SSSE3_OP(phsubd
),
3143 [0x07] = SSSE3_OP(phsubsw
),
3144 [0x08] = SSSE3_OP(psignb
),
3145 [0x09] = SSSE3_OP(psignw
),
3146 [0x0a] = SSSE3_OP(psignd
),
3147 [0x0b] = SSSE3_OP(pmulhrsw
),
3148 [0x10] = SSE41_OP(pblendvb
),
3149 [0x14] = SSE41_OP(blendvps
),
3150 [0x15] = SSE41_OP(blendvpd
),
3151 [0x17] = SSE41_OP(ptest
),
3152 [0x1c] = SSSE3_OP(pabsb
),
3153 [0x1d] = SSSE3_OP(pabsw
),
3154 [0x1e] = SSSE3_OP(pabsd
),
3155 [0x20] = SSE41_OP(pmovsxbw
),
3156 [0x21] = SSE41_OP(pmovsxbd
),
3157 [0x22] = SSE41_OP(pmovsxbq
),
3158 [0x23] = SSE41_OP(pmovsxwd
),
3159 [0x24] = SSE41_OP(pmovsxwq
),
3160 [0x25] = SSE41_OP(pmovsxdq
),
3161 [0x28] = SSE41_OP(pmuldq
),
3162 [0x29] = SSE41_OP(pcmpeqq
),
3163 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3164 [0x2b] = SSE41_OP(packusdw
),
3165 [0x30] = SSE41_OP(pmovzxbw
),
3166 [0x31] = SSE41_OP(pmovzxbd
),
3167 [0x32] = SSE41_OP(pmovzxbq
),
3168 [0x33] = SSE41_OP(pmovzxwd
),
3169 [0x34] = SSE41_OP(pmovzxwq
),
3170 [0x35] = SSE41_OP(pmovzxdq
),
3171 [0x37] = SSE42_OP(pcmpgtq
),
3172 [0x38] = SSE41_OP(pminsb
),
3173 [0x39] = SSE41_OP(pminsd
),
3174 [0x3a] = SSE41_OP(pminuw
),
3175 [0x3b] = SSE41_OP(pminud
),
3176 [0x3c] = SSE41_OP(pmaxsb
),
3177 [0x3d] = SSE41_OP(pmaxsd
),
3178 [0x3e] = SSE41_OP(pmaxuw
),
3179 [0x3f] = SSE41_OP(pmaxud
),
3180 [0x40] = SSE41_OP(pmulld
),
3181 [0x41] = SSE41_OP(phminposuw
),
3184 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
3185 [0x08] = SSE41_OP(roundps
),
3186 [0x09] = SSE41_OP(roundpd
),
3187 [0x0a] = SSE41_OP(roundss
),
3188 [0x0b] = SSE41_OP(roundsd
),
3189 [0x0c] = SSE41_OP(blendps
),
3190 [0x0d] = SSE41_OP(blendpd
),
3191 [0x0e] = SSE41_OP(pblendw
),
3192 [0x0f] = SSSE3_OP(palignr
),
3193 [0x14] = SSE41_SPECIAL
, /* pextrb */
3194 [0x15] = SSE41_SPECIAL
, /* pextrw */
3195 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3196 [0x17] = SSE41_SPECIAL
, /* extractps */
3197 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3198 [0x21] = SSE41_SPECIAL
, /* insertps */
3199 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3200 [0x40] = SSE41_OP(dpps
),
3201 [0x41] = SSE41_OP(dppd
),
3202 [0x42] = SSE41_OP(mpsadbw
),
3203 [0x60] = SSE42_OP(pcmpestrm
),
3204 [0x61] = SSE42_OP(pcmpestri
),
3205 [0x62] = SSE42_OP(pcmpistrm
),
3206 [0x63] = SSE42_OP(pcmpistri
),
3209 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
3210 target_ulong pc_start
, int rex_r
)
3212 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3213 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
3214 SSEFunc_0_epp sse_fn_epp
;
3215 SSEFunc_0_eppi sse_fn_eppi
;
3216 SSEFunc_0_ppi sse_fn_ppi
;
3217 SSEFunc_0_eppt sse_fn_eppt
;
3220 if (s
->prefix
& PREFIX_DATA
)
3222 else if (s
->prefix
& PREFIX_REPZ
)
3224 else if (s
->prefix
& PREFIX_REPNZ
)
3228 sse_fn_epp
= sse_op_table1
[b
][b1
];
3232 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3242 /* simple MMX/SSE operation */
3243 if (s
->flags
& HF_TS_MASK
) {
3244 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3247 if (s
->flags
& HF_EM_MASK
) {
3249 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3252 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3253 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3256 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3259 gen_helper_emms(cpu_env
);
3264 gen_helper_emms(cpu_env
);
3267 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3268 the static cpu state) */
3270 gen_helper_enter_mmx(cpu_env
);
3273 modrm
= cpu_ldub_code(env
, s
->pc
++);
3274 reg
= ((modrm
>> 3) & 7);
3277 mod
= (modrm
>> 6) & 3;
3278 if (sse_fn_epp
== SSE_SPECIAL
) {
3281 case 0x0e7: /* movntq */
3284 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3285 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3287 case 0x1e7: /* movntdq */
3288 case 0x02b: /* movntps */
3289 case 0x12b: /* movntps */
3292 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3293 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3295 case 0x3f0: /* lddqu */
3298 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3299 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3301 case 0x22b: /* movntss */
3302 case 0x32b: /* movntsd */
3305 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3307 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,
3310 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3311 xmm_regs
[reg
].XMM_L(0)));
3312 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3315 case 0x6e: /* movd mm, ea */
3316 #ifdef TARGET_X86_64
3317 if (s
->dflag
== 2) {
3318 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3319 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3323 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3324 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3325 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3326 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3327 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3330 case 0x16e: /* movd xmm, ea */
3331 #ifdef TARGET_X86_64
3332 if (s
->dflag
== 2) {
3333 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3334 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3335 offsetof(CPUX86State
,xmm_regs
[reg
]));
3336 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3340 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3341 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3342 offsetof(CPUX86State
,xmm_regs
[reg
]));
3343 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3344 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3347 case 0x6f: /* movq mm, ea */
3349 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3350 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3353 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3354 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3355 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3356 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3359 case 0x010: /* movups */
3360 case 0x110: /* movupd */
3361 case 0x028: /* movaps */
3362 case 0x128: /* movapd */
3363 case 0x16f: /* movdqa xmm, ea */
3364 case 0x26f: /* movdqu xmm, ea */
3366 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3367 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3369 rm
= (modrm
& 7) | REX_B(s
);
3370 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3371 offsetof(CPUX86State
,xmm_regs
[rm
]));
3374 case 0x210: /* movss xmm, ea */
3376 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3377 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3378 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3380 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3381 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3382 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3384 rm
= (modrm
& 7) | REX_B(s
);
3385 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3386 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3389 case 0x310: /* movsd xmm, ea */
3391 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3392 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3394 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3395 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3397 rm
= (modrm
& 7) | REX_B(s
);
3398 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3399 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3402 case 0x012: /* movlps */
3403 case 0x112: /* movlpd */
3405 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3406 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3409 rm
= (modrm
& 7) | REX_B(s
);
3410 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3411 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3414 case 0x212: /* movsldup */
3416 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3417 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3419 rm
= (modrm
& 7) | REX_B(s
);
3420 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3421 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3422 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3423 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3425 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3426 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3427 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3428 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3430 case 0x312: /* movddup */
3432 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3433 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3435 rm
= (modrm
& 7) | REX_B(s
);
3436 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3437 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3439 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3440 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3442 case 0x016: /* movhps */
3443 case 0x116: /* movhpd */
3445 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3446 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3449 rm
= (modrm
& 7) | REX_B(s
);
3450 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3451 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3454 case 0x216: /* movshdup */
3456 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3457 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3459 rm
= (modrm
& 7) | REX_B(s
);
3460 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3461 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3462 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3463 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3465 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3466 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3467 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3468 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3473 int bit_index
, field_length
;
3475 if (b1
== 1 && reg
!= 0)
3477 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3478 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3479 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3480 offsetof(CPUX86State
,xmm_regs
[reg
]));
3482 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3483 tcg_const_i32(bit_index
),
3484 tcg_const_i32(field_length
));
3486 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3487 tcg_const_i32(bit_index
),
3488 tcg_const_i32(field_length
));
3491 case 0x7e: /* movd ea, mm */
3492 #ifdef TARGET_X86_64
3493 if (s
->dflag
== 2) {
3494 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3495 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3496 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3500 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3501 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3502 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3505 case 0x17e: /* movd ea, xmm */
3506 #ifdef TARGET_X86_64
3507 if (s
->dflag
== 2) {
3508 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3509 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3510 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3514 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3515 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3516 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3519 case 0x27e: /* movq xmm, ea */
3521 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3522 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3524 rm
= (modrm
& 7) | REX_B(s
);
3525 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3526 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3528 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3530 case 0x7f: /* movq ea, mm */
3532 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3533 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3536 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3537 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3540 case 0x011: /* movups */
3541 case 0x111: /* movupd */
3542 case 0x029: /* movaps */
3543 case 0x129: /* movapd */
3544 case 0x17f: /* movdqa ea, xmm */
3545 case 0x27f: /* movdqu ea, xmm */
3547 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3548 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3550 rm
= (modrm
& 7) | REX_B(s
);
3551 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3552 offsetof(CPUX86State
,xmm_regs
[reg
]));
3555 case 0x211: /* movss ea, xmm */
3557 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3558 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3559 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3561 rm
= (modrm
& 7) | REX_B(s
);
3562 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3563 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3566 case 0x311: /* movsd ea, xmm */
3568 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3569 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3571 rm
= (modrm
& 7) | REX_B(s
);
3572 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3573 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3576 case 0x013: /* movlps */
3577 case 0x113: /* movlpd */
3579 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3580 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3585 case 0x017: /* movhps */
3586 case 0x117: /* movhpd */
3588 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3589 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3594 case 0x71: /* shift mm, im */
3597 case 0x171: /* shift xmm, im */
3603 val
= cpu_ldub_code(env
, s
->pc
++);
3605 gen_op_movl_T0_im(val
);
3606 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3608 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3609 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3611 gen_op_movl_T0_im(val
);
3612 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3614 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3615 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3617 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3618 (((modrm
>> 3)) & 7)][b1
];
3623 rm
= (modrm
& 7) | REX_B(s
);
3624 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3627 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3629 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3630 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3631 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3633 case 0x050: /* movmskps */
3634 rm
= (modrm
& 7) | REX_B(s
);
3635 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3636 offsetof(CPUX86State
,xmm_regs
[rm
]));
3637 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3638 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3639 gen_op_mov_reg_T0(OT_LONG
, reg
);
3641 case 0x150: /* movmskpd */
3642 rm
= (modrm
& 7) | REX_B(s
);
3643 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3644 offsetof(CPUX86State
,xmm_regs
[rm
]));
3645 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3646 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3647 gen_op_mov_reg_T0(OT_LONG
, reg
);
3649 case 0x02a: /* cvtpi2ps */
3650 case 0x12a: /* cvtpi2pd */
3651 gen_helper_enter_mmx(cpu_env
);
3653 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3654 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3655 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3658 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3660 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3661 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3662 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3665 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3669 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3673 case 0x22a: /* cvtsi2ss */
3674 case 0x32a: /* cvtsi2sd */
3675 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3676 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3677 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3678 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3679 if (ot
== OT_LONG
) {
3680 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3681 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3682 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3684 #ifdef TARGET_X86_64
3685 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3686 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3692 case 0x02c: /* cvttps2pi */
3693 case 0x12c: /* cvttpd2pi */
3694 case 0x02d: /* cvtps2pi */
3695 case 0x12d: /* cvtpd2pi */
3696 gen_helper_enter_mmx(cpu_env
);
3698 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3699 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3700 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3702 rm
= (modrm
& 7) | REX_B(s
);
3703 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3705 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3706 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3707 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3710 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3713 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3716 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3719 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3723 case 0x22c: /* cvttss2si */
3724 case 0x32c: /* cvttsd2si */
3725 case 0x22d: /* cvtss2si */
3726 case 0x32d: /* cvtsd2si */
3727 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3729 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3731 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3733 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3734 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3736 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3738 rm
= (modrm
& 7) | REX_B(s
);
3739 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3741 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3742 if (ot
== OT_LONG
) {
3743 SSEFunc_i_ep sse_fn_i_ep
=
3744 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3745 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3746 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3748 #ifdef TARGET_X86_64
3749 SSEFunc_l_ep sse_fn_l_ep
=
3750 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3751 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3756 gen_op_mov_reg_T0(ot
, reg
);
3758 case 0xc4: /* pinsrw */
3761 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3762 val
= cpu_ldub_code(env
, s
->pc
++);
3765 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3766 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3769 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3770 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3773 case 0xc5: /* pextrw */
3777 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3778 val
= cpu_ldub_code(env
, s
->pc
++);
3781 rm
= (modrm
& 7) | REX_B(s
);
3782 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3783 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3787 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3788 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3790 reg
= ((modrm
>> 3) & 7) | rex_r
;
3791 gen_op_mov_reg_T0(ot
, reg
);
3793 case 0x1d6: /* movq ea, xmm */
3795 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3796 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3798 rm
= (modrm
& 7) | REX_B(s
);
3799 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3800 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3801 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3804 case 0x2d6: /* movq2dq */
3805 gen_helper_enter_mmx(cpu_env
);
3807 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3808 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3809 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3811 case 0x3d6: /* movdq2q */
3812 gen_helper_enter_mmx(cpu_env
);
3813 rm
= (modrm
& 7) | REX_B(s
);
3814 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3815 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3817 case 0xd7: /* pmovmskb */
3822 rm
= (modrm
& 7) | REX_B(s
);
3823 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3824 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3827 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3828 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3830 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3831 reg
= ((modrm
>> 3) & 7) | rex_r
;
3832 gen_op_mov_reg_T0(OT_LONG
, reg
);
3835 if (s
->prefix
& PREFIX_REPNZ
)
3839 modrm
= cpu_ldub_code(env
, s
->pc
++);
3841 reg
= ((modrm
>> 3) & 7) | rex_r
;
3842 mod
= (modrm
>> 6) & 3;
3847 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3851 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3855 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3857 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3859 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3860 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3862 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3863 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3864 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3865 gen_ldq_env_A0(s
->mem_index
, op2_offset
+
3866 offsetof(XMMReg
, XMM_Q(0)));
3868 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3869 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3870 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3871 (s
->mem_index
>> 2) - 1);
3872 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3873 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3874 offsetof(XMMReg
, XMM_L(0)));
3876 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3877 tcg_gen_qemu_ld16u(cpu_tmp0
, cpu_A0
,
3878 (s
->mem_index
>> 2) - 1);
3879 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3880 offsetof(XMMReg
, XMM_W(0)));
3882 case 0x2a: /* movntqda */
3883 gen_ldo_env_A0(s
->mem_index
, op1_offset
);
3886 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3890 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3892 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3894 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3895 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3896 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3899 if (sse_fn_epp
== SSE_SPECIAL
) {
3903 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3904 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3905 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3908 set_cc_op(s
, CC_OP_EFLAGS
);
3911 case 0x338: /* crc32 */
3914 modrm
= cpu_ldub_code(env
, s
->pc
++);
3915 reg
= ((modrm
>> 3) & 7) | rex_r
;
3917 if (b
!= 0xf0 && b
!= 0xf1)
3919 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
))
3924 else if (b
== 0xf1 && s
->dflag
!= 2)
3925 if (s
->prefix
& PREFIX_DATA
)
3932 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
3933 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3934 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3935 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3936 cpu_T
[0], tcg_const_i32(8 << ot
));
3938 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3939 gen_op_mov_reg_T0(ot
, reg
);
3944 modrm
= cpu_ldub_code(env
, s
->pc
++);
3946 reg
= ((modrm
>> 3) & 7) | rex_r
;
3947 mod
= (modrm
>> 6) & 3;
3952 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
3956 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
3959 if (sse_fn_eppi
== SSE_SPECIAL
) {
3960 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3961 rm
= (modrm
& 7) | REX_B(s
);
3963 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3964 reg
= ((modrm
>> 3) & 7) | rex_r
;
3965 val
= cpu_ldub_code(env
, s
->pc
++);
3967 case 0x14: /* pextrb */
3968 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3969 xmm_regs
[reg
].XMM_B(val
& 15)));
3971 gen_op_mov_reg_T0(ot
, rm
);
3973 tcg_gen_qemu_st8(cpu_T
[0], cpu_A0
,
3974 (s
->mem_index
>> 2) - 1);
3976 case 0x15: /* pextrw */
3977 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3978 xmm_regs
[reg
].XMM_W(val
& 7)));
3980 gen_op_mov_reg_T0(ot
, rm
);
3982 tcg_gen_qemu_st16(cpu_T
[0], cpu_A0
,
3983 (s
->mem_index
>> 2) - 1);
3986 if (ot
== OT_LONG
) { /* pextrd */
3987 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
3988 offsetof(CPUX86State
,
3989 xmm_regs
[reg
].XMM_L(val
& 3)));
3990 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3992 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
3994 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
3995 (s
->mem_index
>> 2) - 1);
3996 } else { /* pextrq */
3997 #ifdef TARGET_X86_64
3998 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3999 offsetof(CPUX86State
,
4000 xmm_regs
[reg
].XMM_Q(val
& 1)));
4002 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
4004 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
4005 (s
->mem_index
>> 2) - 1);
4011 case 0x17: /* extractps */
4012 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4013 xmm_regs
[reg
].XMM_L(val
& 3)));
4015 gen_op_mov_reg_T0(ot
, rm
);
4017 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
4018 (s
->mem_index
>> 2) - 1);
4020 case 0x20: /* pinsrb */
4022 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
4024 tcg_gen_qemu_ld8u(cpu_tmp0
, cpu_A0
,
4025 (s
->mem_index
>> 2) - 1);
4026 tcg_gen_st8_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
,
4027 xmm_regs
[reg
].XMM_B(val
& 15)));
4029 case 0x21: /* insertps */
4031 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4032 offsetof(CPUX86State
,xmm_regs
[rm
]
4033 .XMM_L((val
>> 6) & 3)));
4035 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4036 (s
->mem_index
>> 2) - 1);
4037 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4039 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4040 offsetof(CPUX86State
,xmm_regs
[reg
]
4041 .XMM_L((val
>> 4) & 3)));
4043 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4044 cpu_env
, offsetof(CPUX86State
,
4045 xmm_regs
[reg
].XMM_L(0)));
4047 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4048 cpu_env
, offsetof(CPUX86State
,
4049 xmm_regs
[reg
].XMM_L(1)));
4051 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4052 cpu_env
, offsetof(CPUX86State
,
4053 xmm_regs
[reg
].XMM_L(2)));
4055 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4056 cpu_env
, offsetof(CPUX86State
,
4057 xmm_regs
[reg
].XMM_L(3)));
4060 if (ot
== OT_LONG
) { /* pinsrd */
4062 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
4064 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4065 (s
->mem_index
>> 2) - 1);
4066 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4067 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4068 offsetof(CPUX86State
,
4069 xmm_regs
[reg
].XMM_L(val
& 3)));
4070 } else { /* pinsrq */
4071 #ifdef TARGET_X86_64
4073 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4075 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
4076 (s
->mem_index
>> 2) - 1);
4077 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4078 offsetof(CPUX86State
,
4079 xmm_regs
[reg
].XMM_Q(val
& 1)));
4090 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4092 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4094 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4095 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4096 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4099 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4101 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4103 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4104 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4105 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4108 val
= cpu_ldub_code(env
, s
->pc
++);
4110 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4111 set_cc_op(s
, CC_OP_EFLAGS
);
4114 /* The helper must use entire 64-bit gp registers */
4118 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4119 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4120 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4126 /* generic MMX or SSE operation */
4128 case 0x70: /* pshufx insn */
4129 case 0xc6: /* pshufx insn */
4130 case 0xc2: /* compare insns */
4137 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4139 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4140 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4141 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4143 /* specific case for SSE single instructions */
4146 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
4147 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4150 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
4153 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4156 rm
= (modrm
& 7) | REX_B(s
);
4157 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4160 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4162 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4163 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4164 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4167 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4171 case 0x0f: /* 3DNow! data insns */
4172 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4174 val
= cpu_ldub_code(env
, s
->pc
++);
4175 sse_fn_epp
= sse_op_table5
[val
];
4179 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4180 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4181 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4183 case 0x70: /* pshufx insn */
4184 case 0xc6: /* pshufx insn */
4185 val
= cpu_ldub_code(env
, s
->pc
++);
4186 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4187 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4188 /* XXX: introduce a new table? */
4189 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4190 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4194 val
= cpu_ldub_code(env
, s
->pc
++);
4197 sse_fn_epp
= sse_op_table4
[val
][b1
];
4199 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4200 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4201 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4204 /* maskmov : we must prepare A0 */
4207 #ifdef TARGET_X86_64
4208 if (s
->aflag
== 2) {
4209 gen_op_movq_A0_reg(R_EDI
);
4213 gen_op_movl_A0_reg(R_EDI
);
4215 gen_op_andl_A0_ffff();
4217 gen_add_A0_ds_seg(s
);
4219 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4220 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4221 /* XXX: introduce a new table? */
4222 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4223 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4226 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4227 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4228 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4231 if (b
== 0x2e || b
== 0x2f) {
4232 set_cc_op(s
, CC_OP_EFLAGS
);
4237 /* convert one instruction. s->is_jmp is set if the translation must
4238 be stopped. Return the next pc value */
4239 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4240 target_ulong pc_start
)
4242 int b
, prefixes
, aflag
, dflag
;
4244 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
4245 target_ulong next_eip
, tval
;
4248 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4249 tcg_gen_debug_insn_start(pc_start
);
4258 #ifdef TARGET_X86_64
4263 s
->rip_offset
= 0; /* for relative ip address */
4265 b
= cpu_ldub_code(env
, s
->pc
);
4267 /* check prefixes */
4268 #ifdef TARGET_X86_64
4272 prefixes
|= PREFIX_REPZ
;
4275 prefixes
|= PREFIX_REPNZ
;
4278 prefixes
|= PREFIX_LOCK
;
4299 prefixes
|= PREFIX_DATA
;
4302 prefixes
|= PREFIX_ADR
;
4306 rex_w
= (b
>> 3) & 1;
4307 rex_r
= (b
& 0x4) << 1;
4308 s
->rex_x
= (b
& 0x2) << 2;
4309 REX_B(s
) = (b
& 0x1) << 3;
4310 x86_64_hregs
= 1; /* select uniform byte register addressing */
4314 /* 0x66 is ignored if rex.w is set */
4317 if (prefixes
& PREFIX_DATA
)
4320 if (!(prefixes
& PREFIX_ADR
))
4327 prefixes
|= PREFIX_REPZ
;
4330 prefixes
|= PREFIX_REPNZ
;
4333 prefixes
|= PREFIX_LOCK
;
4354 prefixes
|= PREFIX_DATA
;
4357 prefixes
|= PREFIX_ADR
;
4360 if (prefixes
& PREFIX_DATA
)
4362 if (prefixes
& PREFIX_ADR
)
4366 s
->prefix
= prefixes
;
4370 /* lock generation */
4371 if (prefixes
& PREFIX_LOCK
)
4374 /* now check op code */
4378 /**************************/
4379 /* extended op code */
4380 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4383 /**************************/
4401 ot
= dflag
+ OT_WORD
;
4404 case 0: /* OP Ev, Gv */
4405 modrm
= cpu_ldub_code(env
, s
->pc
++);
4406 reg
= ((modrm
>> 3) & 7) | rex_r
;
4407 mod
= (modrm
>> 6) & 3;
4408 rm
= (modrm
& 7) | REX_B(s
);
4410 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4412 } else if (op
== OP_XORL
&& rm
== reg
) {
4414 /* xor reg, reg optimisation */
4416 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4417 gen_op_mov_reg_T0(ot
, reg
);
4418 gen_op_update1_cc();
4423 gen_op_mov_TN_reg(ot
, 1, reg
);
4424 gen_op(s
, op
, ot
, opreg
);
4426 case 1: /* OP Gv, Ev */
4427 modrm
= cpu_ldub_code(env
, s
->pc
++);
4428 mod
= (modrm
>> 6) & 3;
4429 reg
= ((modrm
>> 3) & 7) | rex_r
;
4430 rm
= (modrm
& 7) | REX_B(s
);
4432 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4433 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4434 } else if (op
== OP_XORL
&& rm
== reg
) {
4437 gen_op_mov_TN_reg(ot
, 1, rm
);
4439 gen_op(s
, op
, ot
, reg
);
4441 case 2: /* OP A, Iv */
4442 val
= insn_get(env
, s
, ot
);
4443 gen_op_movl_T1_im(val
);
4444 gen_op(s
, op
, ot
, OR_EAX
);
4453 case 0x80: /* GRP1 */
4462 ot
= dflag
+ OT_WORD
;
4464 modrm
= cpu_ldub_code(env
, s
->pc
++);
4465 mod
= (modrm
>> 6) & 3;
4466 rm
= (modrm
& 7) | REX_B(s
);
4467 op
= (modrm
>> 3) & 7;
4473 s
->rip_offset
= insn_const_size(ot
);
4474 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4485 val
= insn_get(env
, s
, ot
);
4488 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4491 gen_op_movl_T1_im(val
);
4492 gen_op(s
, op
, ot
, opreg
);
4496 /**************************/
4497 /* inc, dec, and other misc arith */
4498 case 0x40 ... 0x47: /* inc Gv */
4499 ot
= dflag
? OT_LONG
: OT_WORD
;
4500 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4502 case 0x48 ... 0x4f: /* dec Gv */
4503 ot
= dflag
? OT_LONG
: OT_WORD
;
4504 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4506 case 0xf6: /* GRP3 */
4511 ot
= dflag
+ OT_WORD
;
4513 modrm
= cpu_ldub_code(env
, s
->pc
++);
4514 mod
= (modrm
>> 6) & 3;
4515 rm
= (modrm
& 7) | REX_B(s
);
4516 op
= (modrm
>> 3) & 7;
4519 s
->rip_offset
= insn_const_size(ot
);
4520 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4521 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4523 gen_op_mov_TN_reg(ot
, 0, rm
);
4528 val
= insn_get(env
, s
, ot
);
4529 gen_op_movl_T1_im(val
);
4530 gen_op_testl_T0_T1_cc();
4531 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4534 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4536 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4538 gen_op_mov_reg_T0(ot
, rm
);
4542 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4544 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4546 gen_op_mov_reg_T0(ot
, rm
);
4548 gen_op_update_neg_cc();
4549 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4554 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4555 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4556 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4557 /* XXX: use 32 bit mul which could be faster */
4558 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4559 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4560 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4561 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4562 set_cc_op(s
, CC_OP_MULB
);
4565 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4566 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4567 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4568 /* XXX: use 32 bit mul which could be faster */
4569 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4570 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4571 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4572 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4573 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4574 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4575 set_cc_op(s
, CC_OP_MULW
);
4579 #ifdef TARGET_X86_64
4580 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4581 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4582 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
4583 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4584 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4585 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4586 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4587 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4588 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4592 t0
= tcg_temp_new_i64();
4593 t1
= tcg_temp_new_i64();
4594 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4595 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
4596 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
4597 tcg_gen_mul_i64(t0
, t0
, t1
);
4598 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4599 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4600 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4601 tcg_gen_shri_i64(t0
, t0
, 32);
4602 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4603 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4604 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4607 set_cc_op(s
, CC_OP_MULL
);
4609 #ifdef TARGET_X86_64
4611 gen_helper_mulq_EAX_T0(cpu_env
, cpu_T
[0]);
4612 set_cc_op(s
, CC_OP_MULQ
);
4620 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4621 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4622 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4623 /* XXX: use 32 bit mul which could be faster */
4624 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4625 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4626 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4627 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4628 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4629 set_cc_op(s
, CC_OP_MULB
);
4632 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4633 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4634 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4635 /* XXX: use 32 bit mul which could be faster */
4636 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4637 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4638 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4639 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4640 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4641 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4642 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4643 set_cc_op(s
, CC_OP_MULW
);
4647 #ifdef TARGET_X86_64
4648 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4649 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4650 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4651 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4652 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4653 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4654 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4655 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4656 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4657 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4661 t0
= tcg_temp_new_i64();
4662 t1
= tcg_temp_new_i64();
4663 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4664 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4665 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4666 tcg_gen_mul_i64(t0
, t0
, t1
);
4667 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4668 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4669 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4670 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4671 tcg_gen_shri_i64(t0
, t0
, 32);
4672 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4673 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4674 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4677 set_cc_op(s
, CC_OP_MULL
);
4679 #ifdef TARGET_X86_64
4681 gen_helper_imulq_EAX_T0(cpu_env
, cpu_T
[0]);
4682 set_cc_op(s
, CC_OP_MULQ
);
4690 gen_jmp_im(pc_start
- s
->cs_base
);
4691 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4694 gen_jmp_im(pc_start
- s
->cs_base
);
4695 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4699 gen_jmp_im(pc_start
- s
->cs_base
);
4700 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4702 #ifdef TARGET_X86_64
4704 gen_jmp_im(pc_start
- s
->cs_base
);
4705 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4713 gen_jmp_im(pc_start
- s
->cs_base
);
4714 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4717 gen_jmp_im(pc_start
- s
->cs_base
);
4718 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4722 gen_jmp_im(pc_start
- s
->cs_base
);
4723 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4725 #ifdef TARGET_X86_64
4727 gen_jmp_im(pc_start
- s
->cs_base
);
4728 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4738 case 0xfe: /* GRP4 */
4739 case 0xff: /* GRP5 */
4743 ot
= dflag
+ OT_WORD
;
4745 modrm
= cpu_ldub_code(env
, s
->pc
++);
4746 mod
= (modrm
>> 6) & 3;
4747 rm
= (modrm
& 7) | REX_B(s
);
4748 op
= (modrm
>> 3) & 7;
4749 if (op
>= 2 && b
== 0xfe) {
4753 if (op
== 2 || op
== 4) {
4754 /* operand size for jumps is 64 bit */
4756 } else if (op
== 3 || op
== 5) {
4757 ot
= dflag
? OT_LONG
+ (rex_w
== 1) : OT_WORD
;
4758 } else if (op
== 6) {
4759 /* default push size is 64 bit */
4760 ot
= dflag
? OT_QUAD
: OT_WORD
;
4764 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4765 if (op
>= 2 && op
!= 3 && op
!= 5)
4766 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4768 gen_op_mov_TN_reg(ot
, 0, rm
);
4772 case 0: /* inc Ev */
4777 gen_inc(s
, ot
, opreg
, 1);
4779 case 1: /* dec Ev */
4784 gen_inc(s
, ot
, opreg
, -1);
4786 case 2: /* call Ev */
4787 /* XXX: optimize if memory (no 'and' is necessary) */
4789 gen_op_andl_T0_ffff();
4790 next_eip
= s
->pc
- s
->cs_base
;
4791 gen_movtl_T1_im(next_eip
);
4796 case 3: /* lcall Ev */
4797 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4798 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4799 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4801 if (s
->pe
&& !s
->vm86
) {
4802 gen_update_cc_op(s
);
4803 gen_jmp_im(pc_start
- s
->cs_base
);
4804 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4805 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4806 tcg_const_i32(dflag
),
4807 tcg_const_i32(s
->pc
- pc_start
));
4809 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4810 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4811 tcg_const_i32(dflag
),
4812 tcg_const_i32(s
->pc
- s
->cs_base
));
4816 case 4: /* jmp Ev */
4818 gen_op_andl_T0_ffff();
4822 case 5: /* ljmp Ev */
4823 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4824 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4825 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4827 if (s
->pe
&& !s
->vm86
) {
4828 gen_update_cc_op(s
);
4829 gen_jmp_im(pc_start
- s
->cs_base
);
4830 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4831 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4832 tcg_const_i32(s
->pc
- pc_start
));
4834 gen_op_movl_seg_T0_vm(R_CS
);
4835 gen_op_movl_T0_T1();
4840 case 6: /* push Ev */
4848 case 0x84: /* test Ev, Gv */
4853 ot
= dflag
+ OT_WORD
;
4855 modrm
= cpu_ldub_code(env
, s
->pc
++);
4856 reg
= ((modrm
>> 3) & 7) | rex_r
;
4858 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4859 gen_op_mov_TN_reg(ot
, 1, reg
);
4860 gen_op_testl_T0_T1_cc();
4861 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4864 case 0xa8: /* test eAX, Iv */
4869 ot
= dflag
+ OT_WORD
;
4870 val
= insn_get(env
, s
, ot
);
4872 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4873 gen_op_movl_T1_im(val
);
4874 gen_op_testl_T0_T1_cc();
4875 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4878 case 0x98: /* CWDE/CBW */
4879 #ifdef TARGET_X86_64
4881 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4882 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4883 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4887 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4888 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4889 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4891 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4892 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4893 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4896 case 0x99: /* CDQ/CWD */
4897 #ifdef TARGET_X86_64
4899 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4900 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4901 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4905 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4906 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4907 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4908 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4910 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4911 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4912 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4913 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4916 case 0x1af: /* imul Gv, Ev */
4917 case 0x69: /* imul Gv, Ev, I */
4919 ot
= dflag
+ OT_WORD
;
4920 modrm
= cpu_ldub_code(env
, s
->pc
++);
4921 reg
= ((modrm
>> 3) & 7) | rex_r
;
4923 s
->rip_offset
= insn_const_size(ot
);
4926 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4928 val
= insn_get(env
, s
, ot
);
4929 gen_op_movl_T1_im(val
);
4930 } else if (b
== 0x6b) {
4931 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4932 gen_op_movl_T1_im(val
);
4934 gen_op_mov_TN_reg(ot
, 1, reg
);
4937 #ifdef TARGET_X86_64
4938 if (ot
== OT_QUAD
) {
4939 gen_helper_imulq_T0_T1(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
4942 if (ot
== OT_LONG
) {
4943 #ifdef TARGET_X86_64
4944 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4945 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4946 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4947 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4948 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4949 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4953 t0
= tcg_temp_new_i64();
4954 t1
= tcg_temp_new_i64();
4955 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4956 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4957 tcg_gen_mul_i64(t0
, t0
, t1
);
4958 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4959 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4960 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4961 tcg_gen_shri_i64(t0
, t0
, 32);
4962 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
4963 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
4967 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4968 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4969 /* XXX: use 32 bit mul which could be faster */
4970 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4971 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4972 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4973 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4975 gen_op_mov_reg_T0(ot
, reg
);
4976 set_cc_op(s
, CC_OP_MULB
+ ot
);
4979 case 0x1c1: /* xadd Ev, Gv */
4983 ot
= dflag
+ OT_WORD
;
4984 modrm
= cpu_ldub_code(env
, s
->pc
++);
4985 reg
= ((modrm
>> 3) & 7) | rex_r
;
4986 mod
= (modrm
>> 6) & 3;
4988 rm
= (modrm
& 7) | REX_B(s
);
4989 gen_op_mov_TN_reg(ot
, 0, reg
);
4990 gen_op_mov_TN_reg(ot
, 1, rm
);
4991 gen_op_addl_T0_T1();
4992 gen_op_mov_reg_T1(ot
, reg
);
4993 gen_op_mov_reg_T0(ot
, rm
);
4995 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4996 gen_op_mov_TN_reg(ot
, 0, reg
);
4997 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4998 gen_op_addl_T0_T1();
4999 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5000 gen_op_mov_reg_T1(ot
, reg
);
5002 gen_op_update2_cc();
5003 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5006 case 0x1b1: /* cmpxchg Ev, Gv */
5009 TCGv t0
, t1
, t2
, a0
;
5014 ot
= dflag
+ OT_WORD
;
5015 modrm
= cpu_ldub_code(env
, s
->pc
++);
5016 reg
= ((modrm
>> 3) & 7) | rex_r
;
5017 mod
= (modrm
>> 6) & 3;
5018 t0
= tcg_temp_local_new();
5019 t1
= tcg_temp_local_new();
5020 t2
= tcg_temp_local_new();
5021 a0
= tcg_temp_local_new();
5022 gen_op_mov_v_reg(ot
, t1
, reg
);
5024 rm
= (modrm
& 7) | REX_B(s
);
5025 gen_op_mov_v_reg(ot
, t0
, rm
);
5027 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5028 tcg_gen_mov_tl(a0
, cpu_A0
);
5029 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
5030 rm
= 0; /* avoid warning */
5032 label1
= gen_new_label();
5033 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5036 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5037 label2
= gen_new_label();
5039 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5041 gen_set_label(label1
);
5042 gen_op_mov_reg_v(ot
, rm
, t1
);
5044 /* perform no-op store cycle like physical cpu; must be
5045 before changing accumulator to ensure idempotency if
5046 the store faults and the instruction is restarted */
5047 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
5048 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5050 gen_set_label(label1
);
5051 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
5053 gen_set_label(label2
);
5054 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5055 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5056 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5057 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5064 case 0x1c7: /* cmpxchg8b */
5065 modrm
= cpu_ldub_code(env
, s
->pc
++);
5066 mod
= (modrm
>> 6) & 3;
5067 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5069 #ifdef TARGET_X86_64
5071 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5073 gen_jmp_im(pc_start
- s
->cs_base
);
5074 gen_update_cc_op(s
);
5075 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5076 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5080 if (!(s
->cpuid_features
& CPUID_CX8
))
5082 gen_jmp_im(pc_start
- s
->cs_base
);
5083 gen_update_cc_op(s
);
5084 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5085 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5087 set_cc_op(s
, CC_OP_EFLAGS
);
5090 /**************************/
5092 case 0x50 ... 0x57: /* push */
5093 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
5096 case 0x58 ... 0x5f: /* pop */
5098 ot
= dflag
? OT_QUAD
: OT_WORD
;
5100 ot
= dflag
+ OT_WORD
;
5103 /* NOTE: order is important for pop %sp */
5105 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
5107 case 0x60: /* pusha */
5112 case 0x61: /* popa */
5117 case 0x68: /* push Iv */
5120 ot
= dflag
? OT_QUAD
: OT_WORD
;
5122 ot
= dflag
+ OT_WORD
;
5125 val
= insn_get(env
, s
, ot
);
5127 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
5128 gen_op_movl_T0_im(val
);
5131 case 0x8f: /* pop Ev */
5133 ot
= dflag
? OT_QUAD
: OT_WORD
;
5135 ot
= dflag
+ OT_WORD
;
5137 modrm
= cpu_ldub_code(env
, s
->pc
++);
5138 mod
= (modrm
>> 6) & 3;
5141 /* NOTE: order is important for pop %sp */
5143 rm
= (modrm
& 7) | REX_B(s
);
5144 gen_op_mov_reg_T0(ot
, rm
);
5146 /* NOTE: order is important too for MMU exceptions */
5147 s
->popl_esp_hack
= 1 << ot
;
5148 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5149 s
->popl_esp_hack
= 0;
5153 case 0xc8: /* enter */
5156 val
= cpu_lduw_code(env
, s
->pc
);
5158 level
= cpu_ldub_code(env
, s
->pc
++);
5159 gen_enter(s
, val
, level
);
5162 case 0xc9: /* leave */
5163 /* XXX: exception not precise (ESP is updated before potential exception) */
5165 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
5166 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
5167 } else if (s
->ss32
) {
5168 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
5169 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
5171 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
5172 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
5176 ot
= dflag
? OT_QUAD
: OT_WORD
;
5178 ot
= dflag
+ OT_WORD
;
5180 gen_op_mov_reg_T0(ot
, R_EBP
);
5183 case 0x06: /* push es */
5184 case 0x0e: /* push cs */
5185 case 0x16: /* push ss */
5186 case 0x1e: /* push ds */
5189 gen_op_movl_T0_seg(b
>> 3);
5192 case 0x1a0: /* push fs */
5193 case 0x1a8: /* push gs */
5194 gen_op_movl_T0_seg((b
>> 3) & 7);
5197 case 0x07: /* pop es */
5198 case 0x17: /* pop ss */
5199 case 0x1f: /* pop ds */
5204 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5207 /* if reg == SS, inhibit interrupts/trace. */
5208 /* If several instructions disable interrupts, only the
5210 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5211 gen_helper_set_inhibit_irq(cpu_env
);
5215 gen_jmp_im(s
->pc
- s
->cs_base
);
5219 case 0x1a1: /* pop fs */
5220 case 0x1a9: /* pop gs */
5222 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5225 gen_jmp_im(s
->pc
- s
->cs_base
);
5230 /**************************/
5233 case 0x89: /* mov Gv, Ev */
5237 ot
= dflag
+ OT_WORD
;
5238 modrm
= cpu_ldub_code(env
, s
->pc
++);
5239 reg
= ((modrm
>> 3) & 7) | rex_r
;
5241 /* generate a generic store */
5242 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5245 case 0xc7: /* mov Ev, Iv */
5249 ot
= dflag
+ OT_WORD
;
5250 modrm
= cpu_ldub_code(env
, s
->pc
++);
5251 mod
= (modrm
>> 6) & 3;
5253 s
->rip_offset
= insn_const_size(ot
);
5254 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5256 val
= insn_get(env
, s
, ot
);
5257 gen_op_movl_T0_im(val
);
5259 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5261 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5264 case 0x8b: /* mov Ev, Gv */
5268 ot
= OT_WORD
+ dflag
;
5269 modrm
= cpu_ldub_code(env
, s
->pc
++);
5270 reg
= ((modrm
>> 3) & 7) | rex_r
;
5272 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5273 gen_op_mov_reg_T0(ot
, reg
);
5275 case 0x8e: /* mov seg, Gv */
5276 modrm
= cpu_ldub_code(env
, s
->pc
++);
5277 reg
= (modrm
>> 3) & 7;
5278 if (reg
>= 6 || reg
== R_CS
)
5280 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
5281 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5283 /* if reg == SS, inhibit interrupts/trace */
5284 /* If several instructions disable interrupts, only the
5286 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5287 gen_helper_set_inhibit_irq(cpu_env
);
5291 gen_jmp_im(s
->pc
- s
->cs_base
);
5295 case 0x8c: /* mov Gv, seg */
5296 modrm
= cpu_ldub_code(env
, s
->pc
++);
5297 reg
= (modrm
>> 3) & 7;
5298 mod
= (modrm
>> 6) & 3;
5301 gen_op_movl_T0_seg(reg
);
5303 ot
= OT_WORD
+ dflag
;
5306 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5309 case 0x1b6: /* movzbS Gv, Eb */
5310 case 0x1b7: /* movzwS Gv, Eb */
5311 case 0x1be: /* movsbS Gv, Eb */
5312 case 0x1bf: /* movswS Gv, Eb */
5315 /* d_ot is the size of destination */
5316 d_ot
= dflag
+ OT_WORD
;
5317 /* ot is the size of source */
5318 ot
= (b
& 1) + OT_BYTE
;
5319 modrm
= cpu_ldub_code(env
, s
->pc
++);
5320 reg
= ((modrm
>> 3) & 7) | rex_r
;
5321 mod
= (modrm
>> 6) & 3;
5322 rm
= (modrm
& 7) | REX_B(s
);
5325 gen_op_mov_TN_reg(ot
, 0, rm
);
5326 switch(ot
| (b
& 8)) {
5328 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5331 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5334 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5338 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5341 gen_op_mov_reg_T0(d_ot
, reg
);
5343 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5345 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
5347 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
5349 gen_op_mov_reg_T0(d_ot
, reg
);
5354 case 0x8d: /* lea */
5355 ot
= dflag
+ OT_WORD
;
5356 modrm
= cpu_ldub_code(env
, s
->pc
++);
5357 mod
= (modrm
>> 6) & 3;
5360 reg
= ((modrm
>> 3) & 7) | rex_r
;
5361 /* we must ensure that no segment is added */
5365 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5367 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
5370 case 0xa0: /* mov EAX, Ov */
5372 case 0xa2: /* mov Ov, EAX */
5375 target_ulong offset_addr
;
5380 ot
= dflag
+ OT_WORD
;
5381 #ifdef TARGET_X86_64
5382 if (s
->aflag
== 2) {
5383 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5385 gen_op_movq_A0_im(offset_addr
);
5390 offset_addr
= insn_get(env
, s
, OT_LONG
);
5392 offset_addr
= insn_get(env
, s
, OT_WORD
);
5394 gen_op_movl_A0_im(offset_addr
);
5396 gen_add_A0_ds_seg(s
);
5398 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
5399 gen_op_mov_reg_T0(ot
, R_EAX
);
5401 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5402 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5406 case 0xd7: /* xlat */
5407 #ifdef TARGET_X86_64
5408 if (s
->aflag
== 2) {
5409 gen_op_movq_A0_reg(R_EBX
);
5410 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
5411 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5412 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5416 gen_op_movl_A0_reg(R_EBX
);
5417 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
5418 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5419 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5421 gen_op_andl_A0_ffff();
5423 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5425 gen_add_A0_ds_seg(s
);
5426 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
5427 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
5429 case 0xb0 ... 0xb7: /* mov R, Ib */
5430 val
= insn_get(env
, s
, OT_BYTE
);
5431 gen_op_movl_T0_im(val
);
5432 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
5434 case 0xb8 ... 0xbf: /* mov R, Iv */
5435 #ifdef TARGET_X86_64
5439 tmp
= cpu_ldq_code(env
, s
->pc
);
5441 reg
= (b
& 7) | REX_B(s
);
5442 gen_movtl_T0_im(tmp
);
5443 gen_op_mov_reg_T0(OT_QUAD
, reg
);
5447 ot
= dflag
? OT_LONG
: OT_WORD
;
5448 val
= insn_get(env
, s
, ot
);
5449 reg
= (b
& 7) | REX_B(s
);
5450 gen_op_movl_T0_im(val
);
5451 gen_op_mov_reg_T0(ot
, reg
);
5455 case 0x91 ... 0x97: /* xchg R, EAX */
5457 ot
= dflag
+ OT_WORD
;
5458 reg
= (b
& 7) | REX_B(s
);
5462 case 0x87: /* xchg Ev, Gv */
5466 ot
= dflag
+ OT_WORD
;
5467 modrm
= cpu_ldub_code(env
, s
->pc
++);
5468 reg
= ((modrm
>> 3) & 7) | rex_r
;
5469 mod
= (modrm
>> 6) & 3;
5471 rm
= (modrm
& 7) | REX_B(s
);
5473 gen_op_mov_TN_reg(ot
, 0, reg
);
5474 gen_op_mov_TN_reg(ot
, 1, rm
);
5475 gen_op_mov_reg_T0(ot
, rm
);
5476 gen_op_mov_reg_T1(ot
, reg
);
5478 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5479 gen_op_mov_TN_reg(ot
, 0, reg
);
5480 /* for xchg, lock is implicit */
5481 if (!(prefixes
& PREFIX_LOCK
))
5483 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5484 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5485 if (!(prefixes
& PREFIX_LOCK
))
5486 gen_helper_unlock();
5487 gen_op_mov_reg_T1(ot
, reg
);
5490 case 0xc4: /* les Gv */
5495 case 0xc5: /* lds Gv */
5500 case 0x1b2: /* lss Gv */
5503 case 0x1b4: /* lfs Gv */
5506 case 0x1b5: /* lgs Gv */
5509 ot
= dflag
? OT_LONG
: OT_WORD
;
5510 modrm
= cpu_ldub_code(env
, s
->pc
++);
5511 reg
= ((modrm
>> 3) & 7) | rex_r
;
5512 mod
= (modrm
>> 6) & 3;
5515 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5516 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5517 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
5518 /* load the segment first to handle exceptions properly */
5519 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
5520 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5521 /* then put the data */
5522 gen_op_mov_reg_T1(ot
, reg
);
5524 gen_jmp_im(s
->pc
- s
->cs_base
);
5529 /************************/
5540 ot
= dflag
+ OT_WORD
;
5542 modrm
= cpu_ldub_code(env
, s
->pc
++);
5543 mod
= (modrm
>> 6) & 3;
5544 op
= (modrm
>> 3) & 7;
5550 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5553 opreg
= (modrm
& 7) | REX_B(s
);
5558 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5561 shift
= cpu_ldub_code(env
, s
->pc
++);
5563 gen_shifti(s
, op
, ot
, opreg
, shift
);
5578 case 0x1a4: /* shld imm */
5582 case 0x1a5: /* shld cl */
5586 case 0x1ac: /* shrd imm */
5590 case 0x1ad: /* shrd cl */
5594 ot
= dflag
+ OT_WORD
;
5595 modrm
= cpu_ldub_code(env
, s
->pc
++);
5596 mod
= (modrm
>> 6) & 3;
5597 rm
= (modrm
& 7) | REX_B(s
);
5598 reg
= ((modrm
>> 3) & 7) | rex_r
;
5600 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5605 gen_op_mov_TN_reg(ot
, 1, reg
);
5608 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5609 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5612 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5616 /************************/
5619 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5620 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5621 /* XXX: what to do if illegal op ? */
5622 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5625 modrm
= cpu_ldub_code(env
, s
->pc
++);
5626 mod
= (modrm
>> 6) & 3;
5628 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5631 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5633 case 0x00 ... 0x07: /* fxxxs */
5634 case 0x10 ... 0x17: /* fixxxl */
5635 case 0x20 ... 0x27: /* fxxxl */
5636 case 0x30 ... 0x37: /* fixxx */
5643 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5644 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5645 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5648 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5649 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5650 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5653 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5654 (s
->mem_index
>> 2) - 1);
5655 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5659 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5660 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5661 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5665 gen_helper_fp_arith_ST0_FT0(op1
);
5667 /* fcomp needs pop */
5668 gen_helper_fpop(cpu_env
);
5672 case 0x08: /* flds */
5673 case 0x0a: /* fsts */
5674 case 0x0b: /* fstps */
5675 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5676 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5677 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5682 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5683 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5684 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5687 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5688 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5689 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5692 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5693 (s
->mem_index
>> 2) - 1);
5694 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5698 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5699 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5700 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5705 /* XXX: the corresponding CPUID bit must be tested ! */
5708 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5709 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5710 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5713 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5714 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5715 (s
->mem_index
>> 2) - 1);
5719 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5720 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5721 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5724 gen_helper_fpop(cpu_env
);
5729 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5730 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5731 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5734 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5735 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5736 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5739 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5740 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5741 (s
->mem_index
>> 2) - 1);
5745 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5746 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5747 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5751 gen_helper_fpop(cpu_env
);
5755 case 0x0c: /* fldenv mem */
5756 gen_update_cc_op(s
);
5757 gen_jmp_im(pc_start
- s
->cs_base
);
5758 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5760 case 0x0d: /* fldcw mem */
5761 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5762 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5763 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5765 case 0x0e: /* fnstenv mem */
5766 gen_update_cc_op(s
);
5767 gen_jmp_im(pc_start
- s
->cs_base
);
5768 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5770 case 0x0f: /* fnstcw mem */
5771 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5772 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5773 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5775 case 0x1d: /* fldt mem */
5776 gen_update_cc_op(s
);
5777 gen_jmp_im(pc_start
- s
->cs_base
);
5778 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5780 case 0x1f: /* fstpt mem */
5781 gen_update_cc_op(s
);
5782 gen_jmp_im(pc_start
- s
->cs_base
);
5783 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5784 gen_helper_fpop(cpu_env
);
5786 case 0x2c: /* frstor mem */
5787 gen_update_cc_op(s
);
5788 gen_jmp_im(pc_start
- s
->cs_base
);
5789 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5791 case 0x2e: /* fnsave mem */
5792 gen_update_cc_op(s
);
5793 gen_jmp_im(pc_start
- s
->cs_base
);
5794 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5796 case 0x2f: /* fnstsw mem */
5797 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5798 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5799 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5801 case 0x3c: /* fbld */
5802 gen_update_cc_op(s
);
5803 gen_jmp_im(pc_start
- s
->cs_base
);
5804 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5806 case 0x3e: /* fbstp */
5807 gen_update_cc_op(s
);
5808 gen_jmp_im(pc_start
- s
->cs_base
);
5809 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5810 gen_helper_fpop(cpu_env
);
5812 case 0x3d: /* fildll */
5813 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5814 (s
->mem_index
>> 2) - 1);
5815 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5817 case 0x3f: /* fistpll */
5818 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5819 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5820 (s
->mem_index
>> 2) - 1);
5821 gen_helper_fpop(cpu_env
);
5827 /* register float ops */
5831 case 0x08: /* fld sti */
5832 gen_helper_fpush(cpu_env
);
5833 gen_helper_fmov_ST0_STN(cpu_env
,
5834 tcg_const_i32((opreg
+ 1) & 7));
5836 case 0x09: /* fxchg sti */
5837 case 0x29: /* fxchg4 sti, undocumented op */
5838 case 0x39: /* fxchg7 sti, undocumented op */
5839 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5841 case 0x0a: /* grp d9/2 */
5844 /* check exceptions (FreeBSD FPU probe) */
5845 gen_update_cc_op(s
);
5846 gen_jmp_im(pc_start
- s
->cs_base
);
5847 gen_helper_fwait(cpu_env
);
5853 case 0x0c: /* grp d9/4 */
5856 gen_helper_fchs_ST0(cpu_env
);
5859 gen_helper_fabs_ST0(cpu_env
);
5862 gen_helper_fldz_FT0(cpu_env
);
5863 gen_helper_fcom_ST0_FT0(cpu_env
);
5866 gen_helper_fxam_ST0(cpu_env
);
5872 case 0x0d: /* grp d9/5 */
5876 gen_helper_fpush(cpu_env
);
5877 gen_helper_fld1_ST0(cpu_env
);
5880 gen_helper_fpush(cpu_env
);
5881 gen_helper_fldl2t_ST0(cpu_env
);
5884 gen_helper_fpush(cpu_env
);
5885 gen_helper_fldl2e_ST0(cpu_env
);
5888 gen_helper_fpush(cpu_env
);
5889 gen_helper_fldpi_ST0(cpu_env
);
5892 gen_helper_fpush(cpu_env
);
5893 gen_helper_fldlg2_ST0(cpu_env
);
5896 gen_helper_fpush(cpu_env
);
5897 gen_helper_fldln2_ST0(cpu_env
);
5900 gen_helper_fpush(cpu_env
);
5901 gen_helper_fldz_ST0(cpu_env
);
5908 case 0x0e: /* grp d9/6 */
5911 gen_helper_f2xm1(cpu_env
);
5914 gen_helper_fyl2x(cpu_env
);
5917 gen_helper_fptan(cpu_env
);
5919 case 3: /* fpatan */
5920 gen_helper_fpatan(cpu_env
);
5922 case 4: /* fxtract */
5923 gen_helper_fxtract(cpu_env
);
5925 case 5: /* fprem1 */
5926 gen_helper_fprem1(cpu_env
);
5928 case 6: /* fdecstp */
5929 gen_helper_fdecstp(cpu_env
);
5932 case 7: /* fincstp */
5933 gen_helper_fincstp(cpu_env
);
5937 case 0x0f: /* grp d9/7 */
5940 gen_helper_fprem(cpu_env
);
5942 case 1: /* fyl2xp1 */
5943 gen_helper_fyl2xp1(cpu_env
);
5946 gen_helper_fsqrt(cpu_env
);
5948 case 3: /* fsincos */
5949 gen_helper_fsincos(cpu_env
);
5951 case 5: /* fscale */
5952 gen_helper_fscale(cpu_env
);
5954 case 4: /* frndint */
5955 gen_helper_frndint(cpu_env
);
5958 gen_helper_fsin(cpu_env
);
5962 gen_helper_fcos(cpu_env
);
5966 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5967 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5968 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5974 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
5976 gen_helper_fpop(cpu_env
);
5978 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
5979 gen_helper_fp_arith_ST0_FT0(op1
);
5983 case 0x02: /* fcom */
5984 case 0x22: /* fcom2, undocumented op */
5985 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
5986 gen_helper_fcom_ST0_FT0(cpu_env
);
5988 case 0x03: /* fcomp */
5989 case 0x23: /* fcomp3, undocumented op */
5990 case 0x32: /* fcomp5, undocumented op */
5991 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
5992 gen_helper_fcom_ST0_FT0(cpu_env
);
5993 gen_helper_fpop(cpu_env
);
5995 case 0x15: /* da/5 */
5997 case 1: /* fucompp */
5998 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
5999 gen_helper_fucom_ST0_FT0(cpu_env
);
6000 gen_helper_fpop(cpu_env
);
6001 gen_helper_fpop(cpu_env
);
6009 case 0: /* feni (287 only, just do nop here) */
6011 case 1: /* fdisi (287 only, just do nop here) */
6014 gen_helper_fclex(cpu_env
);
6016 case 3: /* fninit */
6017 gen_helper_fninit(cpu_env
);
6019 case 4: /* fsetpm (287 only, just do nop here) */
6025 case 0x1d: /* fucomi */
6026 gen_update_cc_op(s
);
6027 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6028 gen_helper_fucomi_ST0_FT0(cpu_env
);
6029 set_cc_op(s
, CC_OP_EFLAGS
);
6031 case 0x1e: /* fcomi */
6032 gen_update_cc_op(s
);
6033 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6034 gen_helper_fcomi_ST0_FT0(cpu_env
);
6035 set_cc_op(s
, CC_OP_EFLAGS
);
6037 case 0x28: /* ffree sti */
6038 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6040 case 0x2a: /* fst sti */
6041 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6043 case 0x2b: /* fstp sti */
6044 case 0x0b: /* fstp1 sti, undocumented op */
6045 case 0x3a: /* fstp8 sti, undocumented op */
6046 case 0x3b: /* fstp9 sti, undocumented op */
6047 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6048 gen_helper_fpop(cpu_env
);
6050 case 0x2c: /* fucom st(i) */
6051 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6052 gen_helper_fucom_ST0_FT0(cpu_env
);
6054 case 0x2d: /* fucomp st(i) */
6055 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6056 gen_helper_fucom_ST0_FT0(cpu_env
);
6057 gen_helper_fpop(cpu_env
);
6059 case 0x33: /* de/3 */
6061 case 1: /* fcompp */
6062 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6063 gen_helper_fcom_ST0_FT0(cpu_env
);
6064 gen_helper_fpop(cpu_env
);
6065 gen_helper_fpop(cpu_env
);
6071 case 0x38: /* ffreep sti, undocumented op */
6072 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6073 gen_helper_fpop(cpu_env
);
6075 case 0x3c: /* df/4 */
6078 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6079 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6080 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
6086 case 0x3d: /* fucomip */
6087 gen_update_cc_op(s
);
6088 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6089 gen_helper_fucomi_ST0_FT0(cpu_env
);
6090 gen_helper_fpop(cpu_env
);
6091 set_cc_op(s
, CC_OP_EFLAGS
);
6093 case 0x3e: /* fcomip */
6094 gen_update_cc_op(s
);
6095 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6096 gen_helper_fcomi_ST0_FT0(cpu_env
);
6097 gen_helper_fpop(cpu_env
);
6098 set_cc_op(s
, CC_OP_EFLAGS
);
6100 case 0x10 ... 0x13: /* fcmovxx */
6104 static const uint8_t fcmov_cc
[8] = {
6110 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6111 l1
= gen_new_label();
6112 gen_jcc1_noeob(s
, op1
, l1
);
6113 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6122 /************************/
6125 case 0xa4: /* movsS */
6130 ot
= dflag
+ OT_WORD
;
6132 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6133 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6139 case 0xaa: /* stosS */
6144 ot
= dflag
+ OT_WORD
;
6146 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6147 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6152 case 0xac: /* lodsS */
6157 ot
= dflag
+ OT_WORD
;
6158 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6159 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6164 case 0xae: /* scasS */
6169 ot
= dflag
+ OT_WORD
;
6170 if (prefixes
& PREFIX_REPNZ
) {
6171 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6172 } else if (prefixes
& PREFIX_REPZ
) {
6173 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6179 case 0xa6: /* cmpsS */
6184 ot
= dflag
+ OT_WORD
;
6185 if (prefixes
& PREFIX_REPNZ
) {
6186 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6187 } else if (prefixes
& PREFIX_REPZ
) {
6188 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6193 case 0x6c: /* insS */
6198 ot
= dflag
? OT_LONG
: OT_WORD
;
6199 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6200 gen_op_andl_T0_ffff();
6201 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6202 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6203 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6204 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6208 gen_jmp(s
, s
->pc
- s
->cs_base
);
6212 case 0x6e: /* outsS */
6217 ot
= dflag
? OT_LONG
: OT_WORD
;
6218 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6219 gen_op_andl_T0_ffff();
6220 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6221 svm_is_rep(prefixes
) | 4);
6222 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6223 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6227 gen_jmp(s
, s
->pc
- s
->cs_base
);
6232 /************************/
6240 ot
= dflag
? OT_LONG
: OT_WORD
;
6241 val
= cpu_ldub_code(env
, s
->pc
++);
6242 gen_op_movl_T0_im(val
);
6243 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6244 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6247 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6248 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6249 gen_op_mov_reg_T1(ot
, R_EAX
);
6252 gen_jmp(s
, s
->pc
- s
->cs_base
);
6260 ot
= dflag
? OT_LONG
: OT_WORD
;
6261 val
= cpu_ldub_code(env
, s
->pc
++);
6262 gen_op_movl_T0_im(val
);
6263 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6264 svm_is_rep(prefixes
));
6265 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6269 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6270 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6271 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6274 gen_jmp(s
, s
->pc
- s
->cs_base
);
6282 ot
= dflag
? OT_LONG
: OT_WORD
;
6283 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6284 gen_op_andl_T0_ffff();
6285 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6286 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6289 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6290 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6291 gen_op_mov_reg_T1(ot
, R_EAX
);
6294 gen_jmp(s
, s
->pc
- s
->cs_base
);
6302 ot
= dflag
? OT_LONG
: OT_WORD
;
6303 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6304 gen_op_andl_T0_ffff();
6305 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6306 svm_is_rep(prefixes
));
6307 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6311 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6312 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6313 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6316 gen_jmp(s
, s
->pc
- s
->cs_base
);
6320 /************************/
6322 case 0xc2: /* ret im */
6323 val
= cpu_ldsw_code(env
, s
->pc
);
6326 if (CODE64(s
) && s
->dflag
)
6328 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6330 gen_op_andl_T0_ffff();
6334 case 0xc3: /* ret */
6338 gen_op_andl_T0_ffff();
6342 case 0xca: /* lret im */
6343 val
= cpu_ldsw_code(env
, s
->pc
);
6346 if (s
->pe
&& !s
->vm86
) {
6347 gen_update_cc_op(s
);
6348 gen_jmp_im(pc_start
- s
->cs_base
);
6349 gen_helper_lret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6350 tcg_const_i32(val
));
6354 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6356 gen_op_andl_T0_ffff();
6357 /* NOTE: keeping EIP updated is not a problem in case of
6361 gen_op_addl_A0_im(2 << s
->dflag
);
6362 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6363 gen_op_movl_seg_T0_vm(R_CS
);
6364 /* add stack offset */
6365 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6369 case 0xcb: /* lret */
6372 case 0xcf: /* iret */
6373 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6376 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6377 set_cc_op(s
, CC_OP_EFLAGS
);
6378 } else if (s
->vm86
) {
6380 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6382 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6383 set_cc_op(s
, CC_OP_EFLAGS
);
6386 gen_update_cc_op(s
);
6387 gen_jmp_im(pc_start
- s
->cs_base
);
6388 gen_helper_iret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6389 tcg_const_i32(s
->pc
- s
->cs_base
));
6390 set_cc_op(s
, CC_OP_EFLAGS
);
6394 case 0xe8: /* call im */
6397 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6399 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6400 next_eip
= s
->pc
- s
->cs_base
;
6406 gen_movtl_T0_im(next_eip
);
6411 case 0x9a: /* lcall im */
6413 unsigned int selector
, offset
;
6417 ot
= dflag
? OT_LONG
: OT_WORD
;
6418 offset
= insn_get(env
, s
, ot
);
6419 selector
= insn_get(env
, s
, OT_WORD
);
6421 gen_op_movl_T0_im(selector
);
6422 gen_op_movl_T1_imu(offset
);
6425 case 0xe9: /* jmp im */
6427 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6429 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6430 tval
+= s
->pc
- s
->cs_base
;
6437 case 0xea: /* ljmp im */
6439 unsigned int selector
, offset
;
6443 ot
= dflag
? OT_LONG
: OT_WORD
;
6444 offset
= insn_get(env
, s
, ot
);
6445 selector
= insn_get(env
, s
, OT_WORD
);
6447 gen_op_movl_T0_im(selector
);
6448 gen_op_movl_T1_imu(offset
);
6451 case 0xeb: /* jmp Jb */
6452 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6453 tval
+= s
->pc
- s
->cs_base
;
6458 case 0x70 ... 0x7f: /* jcc Jb */
6459 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6461 case 0x180 ... 0x18f: /* jcc Jv */
6463 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6465 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6468 next_eip
= s
->pc
- s
->cs_base
;
6472 gen_jcc(s
, b
, tval
, next_eip
);
6475 case 0x190 ... 0x19f: /* setcc Gv */
6476 modrm
= cpu_ldub_code(env
, s
->pc
++);
6477 gen_setcc1(s
, b
, cpu_T
[0]);
6478 gen_ldst_modrm(env
, s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
6480 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6481 ot
= dflag
+ OT_WORD
;
6482 modrm
= cpu_ldub_code(env
, s
->pc
++);
6483 reg
= ((modrm
>> 3) & 7) | rex_r
;
6484 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6487 /************************/
6489 case 0x9c: /* pushf */
6490 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6491 if (s
->vm86
&& s
->iopl
!= 3) {
6492 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6494 gen_update_cc_op(s
);
6495 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6499 case 0x9d: /* popf */
6500 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6501 if (s
->vm86
&& s
->iopl
!= 3) {
6502 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6507 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6508 tcg_const_i32((TF_MASK
| AC_MASK
|
6513 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6514 tcg_const_i32((TF_MASK
| AC_MASK
|
6516 IF_MASK
| IOPL_MASK
)
6520 if (s
->cpl
<= s
->iopl
) {
6522 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6523 tcg_const_i32((TF_MASK
|
6529 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6530 tcg_const_i32((TF_MASK
|
6539 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6540 tcg_const_i32((TF_MASK
| AC_MASK
|
6541 ID_MASK
| NT_MASK
)));
6543 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6544 tcg_const_i32((TF_MASK
| AC_MASK
|
6551 set_cc_op(s
, CC_OP_EFLAGS
);
6552 /* abort translation because TF/AC flag may change */
6553 gen_jmp_im(s
->pc
- s
->cs_base
);
6557 case 0x9e: /* sahf */
6558 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6560 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
6561 gen_compute_eflags(s
);
6562 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6563 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6564 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6566 case 0x9f: /* lahf */
6567 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6569 gen_compute_eflags(s
);
6570 /* Note: gen_compute_eflags() only gives the condition codes */
6571 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6572 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
6574 case 0xf5: /* cmc */
6575 gen_compute_eflags(s
);
6576 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6578 case 0xf8: /* clc */
6579 gen_compute_eflags(s
);
6580 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6582 case 0xf9: /* stc */
6583 gen_compute_eflags(s
);
6584 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6586 case 0xfc: /* cld */
6587 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6588 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6590 case 0xfd: /* std */
6591 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6592 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6595 /************************/
6596 /* bit operations */
6597 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6598 ot
= dflag
+ OT_WORD
;
6599 modrm
= cpu_ldub_code(env
, s
->pc
++);
6600 op
= (modrm
>> 3) & 7;
6601 mod
= (modrm
>> 6) & 3;
6602 rm
= (modrm
& 7) | REX_B(s
);
6605 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6606 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6608 gen_op_mov_TN_reg(ot
, 0, rm
);
6611 val
= cpu_ldub_code(env
, s
->pc
++);
6612 gen_op_movl_T1_im(val
);
6617 case 0x1a3: /* bt Gv, Ev */
6620 case 0x1ab: /* bts */
6623 case 0x1b3: /* btr */
6626 case 0x1bb: /* btc */
6629 ot
= dflag
+ OT_WORD
;
6630 modrm
= cpu_ldub_code(env
, s
->pc
++);
6631 reg
= ((modrm
>> 3) & 7) | rex_r
;
6632 mod
= (modrm
>> 6) & 3;
6633 rm
= (modrm
& 7) | REX_B(s
);
6634 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6636 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6637 /* specific case: we need to add a displacement */
6638 gen_exts(ot
, cpu_T
[1]);
6639 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6640 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6641 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6642 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6644 gen_op_mov_TN_reg(ot
, 0, rm
);
6647 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6650 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6651 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6654 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6655 tcg_gen_movi_tl(cpu_tmp0
, 1);
6656 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6657 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6660 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6661 tcg_gen_movi_tl(cpu_tmp0
, 1);
6662 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6663 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6664 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6668 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6669 tcg_gen_movi_tl(cpu_tmp0
, 1);
6670 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6671 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6674 set_cc_op(s
, CC_OP_SARB
+ ot
);
6677 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6679 gen_op_mov_reg_T0(ot
, rm
);
6680 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6681 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6684 case 0x1bc: /* bsf */
6685 case 0x1bd: /* bsr */
6690 ot
= dflag
+ OT_WORD
;
6691 modrm
= cpu_ldub_code(env
, s
->pc
++);
6692 reg
= ((modrm
>> 3) & 7) | rex_r
;
6693 gen_ldst_modrm(env
, s
,modrm
, ot
, OR_TMP0
, 0);
6694 gen_extu(ot
, cpu_T
[0]);
6695 t0
= tcg_temp_local_new();
6696 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6697 if ((b
& 1) && (prefixes
& PREFIX_REPZ
) &&
6698 (s
->cpuid_ext3_features
& CPUID_EXT3_ABM
)) {
6700 case OT_WORD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6701 tcg_const_i32(16)); break;
6702 case OT_LONG
: gen_helper_lzcnt(cpu_T
[0], t0
,
6703 tcg_const_i32(32)); break;
6704 case OT_QUAD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6705 tcg_const_i32(64)); break;
6707 gen_op_mov_reg_T0(ot
, reg
);
6709 label1
= gen_new_label();
6710 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6711 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6713 gen_helper_bsr(cpu_T
[0], t0
);
6715 gen_helper_bsf(cpu_T
[0], t0
);
6717 gen_op_mov_reg_T0(ot
, reg
);
6718 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6719 gen_set_label(label1
);
6720 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6725 /************************/
6727 case 0x27: /* daa */
6730 gen_update_cc_op(s
);
6731 gen_helper_daa(cpu_env
);
6732 set_cc_op(s
, CC_OP_EFLAGS
);
6734 case 0x2f: /* das */
6737 gen_update_cc_op(s
);
6738 gen_helper_das(cpu_env
);
6739 set_cc_op(s
, CC_OP_EFLAGS
);
6741 case 0x37: /* aaa */
6744 gen_update_cc_op(s
);
6745 gen_helper_aaa(cpu_env
);
6746 set_cc_op(s
, CC_OP_EFLAGS
);
6748 case 0x3f: /* aas */
6751 gen_update_cc_op(s
);
6752 gen_helper_aas(cpu_env
);
6753 set_cc_op(s
, CC_OP_EFLAGS
);
6755 case 0xd4: /* aam */
6758 val
= cpu_ldub_code(env
, s
->pc
++);
6760 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6762 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6763 set_cc_op(s
, CC_OP_LOGICB
);
6766 case 0xd5: /* aad */
6769 val
= cpu_ldub_code(env
, s
->pc
++);
6770 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6771 set_cc_op(s
, CC_OP_LOGICB
);
6773 /************************/
6775 case 0x90: /* nop */
6776 /* XXX: correct lock test for all insn */
6777 if (prefixes
& PREFIX_LOCK
) {
6780 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6782 goto do_xchg_reg_eax
;
6784 if (prefixes
& PREFIX_REPZ
) {
6785 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6788 case 0x9b: /* fwait */
6789 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6790 (HF_MP_MASK
| HF_TS_MASK
)) {
6791 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6793 gen_update_cc_op(s
);
6794 gen_jmp_im(pc_start
- s
->cs_base
);
6795 gen_helper_fwait(cpu_env
);
6798 case 0xcc: /* int3 */
6799 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6801 case 0xcd: /* int N */
6802 val
= cpu_ldub_code(env
, s
->pc
++);
6803 if (s
->vm86
&& s
->iopl
!= 3) {
6804 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6806 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6809 case 0xce: /* into */
6812 gen_update_cc_op(s
);
6813 gen_jmp_im(pc_start
- s
->cs_base
);
6814 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6817 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6818 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6820 gen_debug(s
, pc_start
- s
->cs_base
);
6824 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6828 case 0xfa: /* cli */
6830 if (s
->cpl
<= s
->iopl
) {
6831 gen_helper_cli(cpu_env
);
6833 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6837 gen_helper_cli(cpu_env
);
6839 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6843 case 0xfb: /* sti */
6845 if (s
->cpl
<= s
->iopl
) {
6847 gen_helper_sti(cpu_env
);
6848 /* interruptions are enabled only the first insn after sti */
6849 /* If several instructions disable interrupts, only the
6851 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6852 gen_helper_set_inhibit_irq(cpu_env
);
6853 /* give a chance to handle pending irqs */
6854 gen_jmp_im(s
->pc
- s
->cs_base
);
6857 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6863 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6867 case 0x62: /* bound */
6870 ot
= dflag
? OT_LONG
: OT_WORD
;
6871 modrm
= cpu_ldub_code(env
, s
->pc
++);
6872 reg
= (modrm
>> 3) & 7;
6873 mod
= (modrm
>> 6) & 3;
6876 gen_op_mov_TN_reg(ot
, 0, reg
);
6877 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6878 gen_jmp_im(pc_start
- s
->cs_base
);
6879 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6880 if (ot
== OT_WORD
) {
6881 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6883 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6886 case 0x1c8 ... 0x1cf: /* bswap reg */
6887 reg
= (b
& 7) | REX_B(s
);
6888 #ifdef TARGET_X86_64
6890 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6891 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6892 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6896 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6897 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6898 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6899 gen_op_mov_reg_T0(OT_LONG
, reg
);
6902 case 0xd6: /* salc */
6905 gen_compute_eflags_c(s
, cpu_T
[0]);
6906 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6907 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
6909 case 0xe0: /* loopnz */
6910 case 0xe1: /* loopz */
6911 case 0xe2: /* loop */
6912 case 0xe3: /* jecxz */
6916 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6917 next_eip
= s
->pc
- s
->cs_base
;
6922 l1
= gen_new_label();
6923 l2
= gen_new_label();
6924 l3
= gen_new_label();
6927 case 0: /* loopnz */
6929 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6930 gen_op_jz_ecx(s
->aflag
, l3
);
6931 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
6934 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6935 gen_op_jnz_ecx(s
->aflag
, l1
);
6939 gen_op_jz_ecx(s
->aflag
, l1
);
6944 gen_jmp_im(next_eip
);
6953 case 0x130: /* wrmsr */
6954 case 0x132: /* rdmsr */
6956 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6958 gen_update_cc_op(s
);
6959 gen_jmp_im(pc_start
- s
->cs_base
);
6961 gen_helper_rdmsr(cpu_env
);
6963 gen_helper_wrmsr(cpu_env
);
6967 case 0x131: /* rdtsc */
6968 gen_update_cc_op(s
);
6969 gen_jmp_im(pc_start
- s
->cs_base
);
6972 gen_helper_rdtsc(cpu_env
);
6975 gen_jmp(s
, s
->pc
- s
->cs_base
);
6978 case 0x133: /* rdpmc */
6979 gen_update_cc_op(s
);
6980 gen_jmp_im(pc_start
- s
->cs_base
);
6981 gen_helper_rdpmc(cpu_env
);
6983 case 0x134: /* sysenter */
6984 /* For Intel SYSENTER is valid on 64-bit */
6985 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6988 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6990 gen_update_cc_op(s
);
6991 gen_jmp_im(pc_start
- s
->cs_base
);
6992 gen_helper_sysenter(cpu_env
);
6996 case 0x135: /* sysexit */
6997 /* For Intel SYSEXIT is valid on 64-bit */
6998 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7001 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7003 gen_update_cc_op(s
);
7004 gen_jmp_im(pc_start
- s
->cs_base
);
7005 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
));
7009 #ifdef TARGET_X86_64
7010 case 0x105: /* syscall */
7011 /* XXX: is it usable in real mode ? */
7012 gen_update_cc_op(s
);
7013 gen_jmp_im(pc_start
- s
->cs_base
);
7014 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7017 case 0x107: /* sysret */
7019 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7021 gen_update_cc_op(s
);
7022 gen_jmp_im(pc_start
- s
->cs_base
);
7023 gen_helper_sysret(cpu_env
, tcg_const_i32(s
->dflag
));
7024 /* condition codes are modified only in long mode */
7026 set_cc_op(s
, CC_OP_EFLAGS
);
7032 case 0x1a2: /* cpuid */
7033 gen_update_cc_op(s
);
7034 gen_jmp_im(pc_start
- s
->cs_base
);
7035 gen_helper_cpuid(cpu_env
);
7037 case 0xf4: /* hlt */
7039 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7041 gen_update_cc_op(s
);
7042 gen_jmp_im(pc_start
- s
->cs_base
);
7043 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7044 s
->is_jmp
= DISAS_TB_JUMP
;
7048 modrm
= cpu_ldub_code(env
, s
->pc
++);
7049 mod
= (modrm
>> 6) & 3;
7050 op
= (modrm
>> 3) & 7;
7053 if (!s
->pe
|| s
->vm86
)
7055 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7056 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7060 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7063 if (!s
->pe
|| s
->vm86
)
7066 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7068 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7069 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7070 gen_jmp_im(pc_start
- s
->cs_base
);
7071 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7072 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7076 if (!s
->pe
|| s
->vm86
)
7078 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7079 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7083 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7086 if (!s
->pe
|| s
->vm86
)
7089 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7091 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7092 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7093 gen_jmp_im(pc_start
- s
->cs_base
);
7094 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7095 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7100 if (!s
->pe
|| s
->vm86
)
7102 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7103 gen_update_cc_op(s
);
7105 gen_helper_verr(cpu_env
, cpu_T
[0]);
7107 gen_helper_verw(cpu_env
, cpu_T
[0]);
7109 set_cc_op(s
, CC_OP_EFLAGS
);
7116 modrm
= cpu_ldub_code(env
, s
->pc
++);
7117 mod
= (modrm
>> 6) & 3;
7118 op
= (modrm
>> 3) & 7;
7124 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7125 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7126 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7127 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7128 gen_add_A0_im(s
, 2);
7129 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7131 gen_op_andl_T0_im(0xffffff);
7132 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7137 case 0: /* monitor */
7138 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7141 gen_update_cc_op(s
);
7142 gen_jmp_im(pc_start
- s
->cs_base
);
7143 #ifdef TARGET_X86_64
7144 if (s
->aflag
== 2) {
7145 gen_op_movq_A0_reg(R_EAX
);
7149 gen_op_movl_A0_reg(R_EAX
);
7151 gen_op_andl_A0_ffff();
7153 gen_add_A0_ds_seg(s
);
7154 gen_helper_monitor(cpu_env
, cpu_A0
);
7157 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7160 gen_update_cc_op(s
);
7161 gen_jmp_im(pc_start
- s
->cs_base
);
7162 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7166 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7170 gen_helper_clac(cpu_env
);
7171 gen_jmp_im(s
->pc
- s
->cs_base
);
7175 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7179 gen_helper_stac(cpu_env
);
7180 gen_jmp_im(s
->pc
- s
->cs_base
);
7187 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7188 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7189 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7190 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7191 gen_add_A0_im(s
, 2);
7192 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7194 gen_op_andl_T0_im(0xffffff);
7195 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7201 gen_update_cc_op(s
);
7202 gen_jmp_im(pc_start
- s
->cs_base
);
7205 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7208 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7211 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
),
7212 tcg_const_i32(s
->pc
- pc_start
));
7214 s
->is_jmp
= DISAS_TB_JUMP
;
7217 case 1: /* VMMCALL */
7218 if (!(s
->flags
& HF_SVME_MASK
))
7220 gen_helper_vmmcall(cpu_env
);
7222 case 2: /* VMLOAD */
7223 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7226 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7229 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
));
7232 case 3: /* VMSAVE */
7233 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7236 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7239 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
));
7243 if ((!(s
->flags
& HF_SVME_MASK
) &&
7244 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7248 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7251 gen_helper_stgi(cpu_env
);
7255 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7258 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7261 gen_helper_clgi(cpu_env
);
7264 case 6: /* SKINIT */
7265 if ((!(s
->flags
& HF_SVME_MASK
) &&
7266 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7269 gen_helper_skinit(cpu_env
);
7271 case 7: /* INVLPGA */
7272 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7275 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7278 gen_helper_invlpga(cpu_env
, tcg_const_i32(s
->aflag
));
7284 } else if (s
->cpl
!= 0) {
7285 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7287 gen_svm_check_intercept(s
, pc_start
,
7288 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7289 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7290 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
7291 gen_add_A0_im(s
, 2);
7292 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7294 gen_op_andl_T0_im(0xffffff);
7296 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7297 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7299 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7300 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7305 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7306 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7307 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7309 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7311 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 1);
7315 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7317 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7318 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7319 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7320 gen_jmp_im(s
->pc
- s
->cs_base
);
7325 if (mod
!= 3) { /* invlpg */
7327 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7329 gen_update_cc_op(s
);
7330 gen_jmp_im(pc_start
- s
->cs_base
);
7331 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7332 gen_helper_invlpg(cpu_env
, cpu_A0
);
7333 gen_jmp_im(s
->pc
- s
->cs_base
);
7338 case 0: /* swapgs */
7339 #ifdef TARGET_X86_64
7342 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7344 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7345 offsetof(CPUX86State
,segs
[R_GS
].base
));
7346 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7347 offsetof(CPUX86State
,kernelgsbase
));
7348 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7349 offsetof(CPUX86State
,segs
[R_GS
].base
));
7350 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7351 offsetof(CPUX86State
,kernelgsbase
));
7359 case 1: /* rdtscp */
7360 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7362 gen_update_cc_op(s
);
7363 gen_jmp_im(pc_start
- s
->cs_base
);
7366 gen_helper_rdtscp(cpu_env
);
7369 gen_jmp(s
, s
->pc
- s
->cs_base
);
7381 case 0x108: /* invd */
7382 case 0x109: /* wbinvd */
7384 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7386 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7390 case 0x63: /* arpl or movslS (x86_64) */
7391 #ifdef TARGET_X86_64
7394 /* d_ot is the size of destination */
7395 d_ot
= dflag
+ OT_WORD
;
7397 modrm
= cpu_ldub_code(env
, s
->pc
++);
7398 reg
= ((modrm
>> 3) & 7) | rex_r
;
7399 mod
= (modrm
>> 6) & 3;
7400 rm
= (modrm
& 7) | REX_B(s
);
7403 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
7405 if (d_ot
== OT_QUAD
)
7406 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7407 gen_op_mov_reg_T0(d_ot
, reg
);
7409 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7410 if (d_ot
== OT_QUAD
) {
7411 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
7413 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7415 gen_op_mov_reg_T0(d_ot
, reg
);
7421 TCGv t0
, t1
, t2
, a0
;
7423 if (!s
->pe
|| s
->vm86
)
7425 t0
= tcg_temp_local_new();
7426 t1
= tcg_temp_local_new();
7427 t2
= tcg_temp_local_new();
7429 modrm
= cpu_ldub_code(env
, s
->pc
++);
7430 reg
= (modrm
>> 3) & 7;
7431 mod
= (modrm
>> 6) & 3;
7434 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7435 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7436 a0
= tcg_temp_local_new();
7437 tcg_gen_mov_tl(a0
, cpu_A0
);
7439 gen_op_mov_v_reg(ot
, t0
, rm
);
7442 gen_op_mov_v_reg(ot
, t1
, reg
);
7443 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7444 tcg_gen_andi_tl(t1
, t1
, 3);
7445 tcg_gen_movi_tl(t2
, 0);
7446 label1
= gen_new_label();
7447 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7448 tcg_gen_andi_tl(t0
, t0
, ~3);
7449 tcg_gen_or_tl(t0
, t0
, t1
);
7450 tcg_gen_movi_tl(t2
, CC_Z
);
7451 gen_set_label(label1
);
7453 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
7456 gen_op_mov_reg_v(ot
, rm
, t0
);
7458 gen_compute_eflags(s
);
7459 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7460 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7466 case 0x102: /* lar */
7467 case 0x103: /* lsl */
7471 if (!s
->pe
|| s
->vm86
)
7473 ot
= dflag
? OT_LONG
: OT_WORD
;
7474 modrm
= cpu_ldub_code(env
, s
->pc
++);
7475 reg
= ((modrm
>> 3) & 7) | rex_r
;
7476 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7477 t0
= tcg_temp_local_new();
7478 gen_update_cc_op(s
);
7480 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7482 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7484 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7485 label1
= gen_new_label();
7486 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7487 gen_op_mov_reg_v(ot
, reg
, t0
);
7488 gen_set_label(label1
);
7489 set_cc_op(s
, CC_OP_EFLAGS
);
7494 modrm
= cpu_ldub_code(env
, s
->pc
++);
7495 mod
= (modrm
>> 6) & 3;
7496 op
= (modrm
>> 3) & 7;
7498 case 0: /* prefetchnta */
7499 case 1: /* prefetchnt0 */
7500 case 2: /* prefetchnt0 */
7501 case 3: /* prefetchnt0 */
7504 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7505 /* nothing more to do */
7507 default: /* nop (multi byte) */
7508 gen_nop_modrm(env
, s
, modrm
);
7512 case 0x119 ... 0x11f: /* nop (multi byte) */
7513 modrm
= cpu_ldub_code(env
, s
->pc
++);
7514 gen_nop_modrm(env
, s
, modrm
);
7516 case 0x120: /* mov reg, crN */
7517 case 0x122: /* mov crN, reg */
7519 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7521 modrm
= cpu_ldub_code(env
, s
->pc
++);
7522 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7523 * AMD documentation (24594.pdf) and testing of
7524 * intel 386 and 486 processors all show that the mod bits
7525 * are assumed to be 1's, regardless of actual values.
7527 rm
= (modrm
& 7) | REX_B(s
);
7528 reg
= ((modrm
>> 3) & 7) | rex_r
;
7533 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7534 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7543 gen_update_cc_op(s
);
7544 gen_jmp_im(pc_start
- s
->cs_base
);
7546 gen_op_mov_TN_reg(ot
, 0, rm
);
7547 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7549 gen_jmp_im(s
->pc
- s
->cs_base
);
7552 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7553 gen_op_mov_reg_T0(ot
, rm
);
7561 case 0x121: /* mov reg, drN */
7562 case 0x123: /* mov drN, reg */
7564 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7566 modrm
= cpu_ldub_code(env
, s
->pc
++);
7567 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7568 * AMD documentation (24594.pdf) and testing of
7569 * intel 386 and 486 processors all show that the mod bits
7570 * are assumed to be 1's, regardless of actual values.
7572 rm
= (modrm
& 7) | REX_B(s
);
7573 reg
= ((modrm
>> 3) & 7) | rex_r
;
7578 /* XXX: do it dynamically with CR4.DE bit */
7579 if (reg
== 4 || reg
== 5 || reg
>= 8)
7582 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7583 gen_op_mov_TN_reg(ot
, 0, rm
);
7584 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7585 gen_jmp_im(s
->pc
- s
->cs_base
);
7588 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7589 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7590 gen_op_mov_reg_T0(ot
, rm
);
7594 case 0x106: /* clts */
7596 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7598 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7599 gen_helper_clts(cpu_env
);
7600 /* abort block because static cpu state changed */
7601 gen_jmp_im(s
->pc
- s
->cs_base
);
7605 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7606 case 0x1c3: /* MOVNTI reg, mem */
7607 if (!(s
->cpuid_features
& CPUID_SSE2
))
7609 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
7610 modrm
= cpu_ldub_code(env
, s
->pc
++);
7611 mod
= (modrm
>> 6) & 3;
7614 reg
= ((modrm
>> 3) & 7) | rex_r
;
7615 /* generate a generic store */
7616 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7619 modrm
= cpu_ldub_code(env
, s
->pc
++);
7620 mod
= (modrm
>> 6) & 3;
7621 op
= (modrm
>> 3) & 7;
7623 case 0: /* fxsave */
7624 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7625 (s
->prefix
& PREFIX_LOCK
))
7627 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7628 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7631 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7632 gen_update_cc_op(s
);
7633 gen_jmp_im(pc_start
- s
->cs_base
);
7634 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7636 case 1: /* fxrstor */
7637 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7638 (s
->prefix
& PREFIX_LOCK
))
7640 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7641 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7644 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7645 gen_update_cc_op(s
);
7646 gen_jmp_im(pc_start
- s
->cs_base
);
7647 gen_helper_fxrstor(cpu_env
, cpu_A0
,
7648 tcg_const_i32((s
->dflag
== 2)));
7650 case 2: /* ldmxcsr */
7651 case 3: /* stmxcsr */
7652 if (s
->flags
& HF_TS_MASK
) {
7653 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7656 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7659 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7661 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7662 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7663 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7665 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7666 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7669 case 5: /* lfence */
7670 case 6: /* mfence */
7671 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7674 case 7: /* sfence / clflush */
7675 if ((modrm
& 0xc7) == 0xc0) {
7677 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7678 if (!(s
->cpuid_features
& CPUID_SSE
))
7682 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7684 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7691 case 0x10d: /* 3DNow! prefetch(w) */
7692 modrm
= cpu_ldub_code(env
, s
->pc
++);
7693 mod
= (modrm
>> 6) & 3;
7696 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7697 /* ignore for now */
7699 case 0x1aa: /* rsm */
7700 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7701 if (!(s
->flags
& HF_SMM_MASK
))
7703 gen_update_cc_op(s
);
7704 gen_jmp_im(s
->pc
- s
->cs_base
);
7705 gen_helper_rsm(cpu_env
);
7708 case 0x1b8: /* SSE4.2 popcnt */
7709 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7712 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7715 modrm
= cpu_ldub_code(env
, s
->pc
++);
7716 reg
= ((modrm
>> 3) & 7) | rex_r
;
7718 if (s
->prefix
& PREFIX_DATA
)
7720 else if (s
->dflag
!= 2)
7725 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7726 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7727 gen_op_mov_reg_T0(ot
, reg
);
7729 set_cc_op(s
, CC_OP_EFLAGS
);
7731 case 0x10e ... 0x10f:
7732 /* 3DNow! instructions, ignore prefixes */
7733 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7734 case 0x110 ... 0x117:
7735 case 0x128 ... 0x12f:
7736 case 0x138 ... 0x13a:
7737 case 0x150 ... 0x179:
7738 case 0x17c ... 0x17f:
7740 case 0x1c4 ... 0x1c6:
7741 case 0x1d0 ... 0x1fe:
7742 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7747 /* lock generation */
7748 if (s
->prefix
& PREFIX_LOCK
)
7749 gen_helper_unlock();
7752 if (s
->prefix
& PREFIX_LOCK
)
7753 gen_helper_unlock();
7754 /* XXX: ensure that no lock was generated */
7755 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7759 void optimize_flags_init(void)
7761 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7762 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7763 offsetof(CPUX86State
, cc_op
), "cc_op");
7764 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7766 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7769 #ifdef TARGET_X86_64
7770 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7771 offsetof(CPUX86State
, regs
[R_EAX
]), "rax");
7772 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7773 offsetof(CPUX86State
, regs
[R_ECX
]), "rcx");
7774 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7775 offsetof(CPUX86State
, regs
[R_EDX
]), "rdx");
7776 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7777 offsetof(CPUX86State
, regs
[R_EBX
]), "rbx");
7778 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7779 offsetof(CPUX86State
, regs
[R_ESP
]), "rsp");
7780 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7781 offsetof(CPUX86State
, regs
[R_EBP
]), "rbp");
7782 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7783 offsetof(CPUX86State
, regs
[R_ESI
]), "rsi");
7784 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7785 offsetof(CPUX86State
, regs
[R_EDI
]), "rdi");
7786 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
7787 offsetof(CPUX86State
, regs
[8]), "r8");
7788 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
7789 offsetof(CPUX86State
, regs
[9]), "r9");
7790 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
7791 offsetof(CPUX86State
, regs
[10]), "r10");
7792 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
7793 offsetof(CPUX86State
, regs
[11]), "r11");
7794 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
7795 offsetof(CPUX86State
, regs
[12]), "r12");
7796 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
7797 offsetof(CPUX86State
, regs
[13]), "r13");
7798 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
7799 offsetof(CPUX86State
, regs
[14]), "r14");
7800 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
7801 offsetof(CPUX86State
, regs
[15]), "r15");
7803 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7804 offsetof(CPUX86State
, regs
[R_EAX
]), "eax");
7805 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7806 offsetof(CPUX86State
, regs
[R_ECX
]), "ecx");
7807 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7808 offsetof(CPUX86State
, regs
[R_EDX
]), "edx");
7809 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7810 offsetof(CPUX86State
, regs
[R_EBX
]), "ebx");
7811 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7812 offsetof(CPUX86State
, regs
[R_ESP
]), "esp");
7813 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7814 offsetof(CPUX86State
, regs
[R_EBP
]), "ebp");
7815 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7816 offsetof(CPUX86State
, regs
[R_ESI
]), "esi");
7817 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7818 offsetof(CPUX86State
, regs
[R_EDI
]), "edi");
7821 /* register helpers */
7822 #define GEN_HELPER 2
7826 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7827 basic block 'tb'. If search_pc is TRUE, also generate PC
7828 information for each intermediate instruction. */
7829 static inline void gen_intermediate_code_internal(CPUX86State
*env
,
7830 TranslationBlock
*tb
,
7833 DisasContext dc1
, *dc
= &dc1
;
7834 target_ulong pc_ptr
;
7835 uint16_t *gen_opc_end
;
7839 target_ulong pc_start
;
7840 target_ulong cs_base
;
7844 /* generate intermediate code */
7846 cs_base
= tb
->cs_base
;
7849 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7850 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7851 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7852 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7854 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7855 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7856 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7857 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7858 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7859 dc
->cc_op
= CC_OP_DYNAMIC
;
7860 dc
->cc_op_dirty
= false;
7861 dc
->cs_base
= cs_base
;
7863 dc
->popl_esp_hack
= 0;
7864 /* select memory access functions */
7866 if (flags
& HF_SOFTMMU_MASK
) {
7867 dc
->mem_index
= (cpu_mmu_index(env
) + 1) << 2;
7869 dc
->cpuid_features
= env
->cpuid_features
;
7870 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7871 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7872 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7873 dc
->cpuid_7_0_ebx_features
= env
->cpuid_7_0_ebx_features
;
7874 #ifdef TARGET_X86_64
7875 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7876 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7879 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7880 (flags
& HF_INHIBIT_IRQ_MASK
)
7881 #ifndef CONFIG_SOFTMMU
7882 || (flags
& HF_SOFTMMU_MASK
)
7886 /* check addseg logic */
7887 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7888 printf("ERROR addseg\n");
7891 cpu_T
[0] = tcg_temp_new();
7892 cpu_T
[1] = tcg_temp_new();
7893 cpu_A0
= tcg_temp_new();
7895 cpu_tmp0
= tcg_temp_new();
7896 cpu_tmp1_i64
= tcg_temp_new_i64();
7897 cpu_tmp2_i32
= tcg_temp_new_i32();
7898 cpu_tmp3_i32
= tcg_temp_new_i32();
7899 cpu_tmp4
= tcg_temp_new();
7900 cpu_tmp5
= tcg_temp_new();
7901 cpu_ptr0
= tcg_temp_new_ptr();
7902 cpu_ptr1
= tcg_temp_new_ptr();
7903 cpu_cc_srcT
= tcg_temp_local_new();
7905 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
7907 dc
->is_jmp
= DISAS_NEXT
;
7911 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7913 max_insns
= CF_COUNT_MASK
;
7917 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7918 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7919 if (bp
->pc
== pc_ptr
&&
7920 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7921 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7927 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
7931 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
7933 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
7934 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7935 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
7936 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
7938 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7941 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
7943 /* stop translation if indicated */
7946 /* if single step mode, we generate only one instruction and
7947 generate an exception */
7948 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7949 the flag and abort the translation to give the irqs a
7950 change to be happen */
7951 if (dc
->tf
|| dc
->singlestep_enabled
||
7952 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7953 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7957 /* if too long translation, stop generation too */
7958 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
7959 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
7960 num_insns
>= max_insns
) {
7961 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7966 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7971 if (tb
->cflags
& CF_LAST_IO
)
7973 gen_icount_end(tb
, num_insns
);
7974 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
7975 /* we don't forget to fill the last values */
7977 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
7980 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
7984 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
7986 qemu_log("----------------\n");
7987 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
7988 #ifdef TARGET_X86_64
7993 disas_flags
= !dc
->code32
;
7994 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8000 tb
->size
= pc_ptr
- pc_start
;
8001 tb
->icount
= num_insns
;
8005 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8007 gen_intermediate_code_internal(env
, tb
, 0);
8010 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8012 gen_intermediate_code_internal(env
, tb
, 1);
8015 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8019 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8021 qemu_log("RESTORE:\n");
8022 for(i
= 0;i
<= pc_pos
; i
++) {
8023 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8024 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8025 tcg_ctx
.gen_opc_pc
[i
]);
8028 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8029 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8030 (uint32_t)tb
->cs_base
);
8033 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8034 cc_op
= gen_opc_cc_op
[pc_pos
];
8035 if (cc_op
!= CC_OP_DYNAMIC
)