4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
40 #define PREFIX_VEX 0x20
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
60 //#define MACRO_TEST 1
62 /* global register indexes */
63 static TCGv_ptr cpu_env
;
65 static TCGv cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
, cpu_cc_srcT
;
66 static TCGv_i32 cpu_cc_op
;
67 static TCGv cpu_regs
[CPU_NB_REGS
];
70 /* local register indexes (only used inside old micro ops) */
71 static TCGv cpu_tmp0
, cpu_tmp4
;
72 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
73 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
74 static TCGv_i64 cpu_tmp1_i64
;
76 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
78 #include "exec/gen-icount.h"
81 static int x86_64_hregs
;
84 typedef struct DisasContext
{
85 /* current insn context */
86 int override
; /* -1 if no override */
89 target_ulong pc
; /* pc = eip + cs_base */
90 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
91 static state change (stop translation) */
92 /* current block context */
93 target_ulong cs_base
; /* base of CS segment */
94 int pe
; /* protected mode */
95 int code32
; /* 32 bit code segment */
97 int lma
; /* long mode active */
98 int code64
; /* 64 bit code segment */
101 int vex_l
; /* vex vector length */
102 int vex_v
; /* vex vvvv register, without 1's compliment. */
103 int ss32
; /* 32 bit stack segment */
104 CCOp cc_op
; /* current CC operation */
106 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
107 int f_st
; /* currently unused */
108 int vm86
; /* vm86 mode */
111 int tf
; /* TF cpu flag */
112 int singlestep_enabled
; /* "hardware" single step enabled */
113 int jmp_opt
; /* use direct block chaining for direct jumps */
114 int mem_index
; /* select memory access functions */
115 uint64_t flags
; /* all execution flags */
116 struct TranslationBlock
*tb
;
117 int popl_esp_hack
; /* for correct popl with esp base handling */
118 int rip_offset
; /* only used in x86_64, but left for simplicity */
120 int cpuid_ext_features
;
121 int cpuid_ext2_features
;
122 int cpuid_ext3_features
;
123 int cpuid_7_0_ebx_features
;
126 static void gen_eob(DisasContext
*s
);
127 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
128 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
129 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
);
131 /* i386 arith/logic operations */
151 OP_SHL1
, /* undocumented */
167 /* I386 int registers */
168 OR_EAX
, /* MUST be even numbered */
177 OR_TMP0
= 16, /* temporary operand register */
179 OR_A0
, /* temporary register used when doing address evaluation */
189 /* Bit set if the global variable is live after setting CC_OP to X. */
190 static const uint8_t cc_op_live
[CC_OP_NB
] = {
191 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
192 [CC_OP_EFLAGS
] = USES_CC_SRC
,
193 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
194 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
195 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
196 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
197 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
198 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
199 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
200 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
202 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_BMILGB
... CC_OP_BMILGQ
] = USES_CC_DST
| USES_CC_SRC
,
204 [CC_OP_ADCX
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_ADOX
] = USES_CC_SRC
| USES_CC_SRC2
,
206 [CC_OP_ADCOX
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
210 static void set_cc_op(DisasContext
*s
, CCOp op
)
214 if (s
->cc_op
== op
) {
218 /* Discard CC computation that will no longer be used. */
219 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
220 if (dead
& USES_CC_DST
) {
221 tcg_gen_discard_tl(cpu_cc_dst
);
223 if (dead
& USES_CC_SRC
) {
224 tcg_gen_discard_tl(cpu_cc_src
);
226 if (dead
& USES_CC_SRC2
) {
227 tcg_gen_discard_tl(cpu_cc_src2
);
229 if (dead
& USES_CC_SRCT
) {
230 tcg_gen_discard_tl(cpu_cc_srcT
);
233 if (op
== CC_OP_DYNAMIC
) {
234 /* The DYNAMIC setting is translator only, and should never be
235 stored. Thus we always consider it clean. */
236 s
->cc_op_dirty
= false;
238 /* Discard any computed CC_OP value (see shifts). */
239 if (s
->cc_op
== CC_OP_DYNAMIC
) {
240 tcg_gen_discard_i32(cpu_cc_op
);
242 s
->cc_op_dirty
= true;
247 static void gen_update_cc_op(DisasContext
*s
)
249 if (s
->cc_op_dirty
) {
250 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
251 s
->cc_op_dirty
= false;
255 static inline void gen_movtl_T0_im(target_ulong val
)
257 tcg_gen_movi_tl(cpu_T
[0], val
);
260 static inline void gen_movtl_T1_im(target_ulong val
)
262 tcg_gen_movi_tl(cpu_T
[1], val
);
265 static inline void gen_op_andl_T0_ffff(void)
267 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
270 static inline void gen_op_andl_T0_im(uint32_t val
)
272 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
275 static inline void gen_op_movl_T0_T1(void)
277 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
280 static inline void gen_op_andl_A0_ffff(void)
282 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
287 #define NB_OP_SIZES 4
289 #else /* !TARGET_X86_64 */
291 #define NB_OP_SIZES 3
293 #endif /* !TARGET_X86_64 */
295 #if defined(HOST_WORDS_BIGENDIAN)
296 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
297 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
298 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
299 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
300 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
302 #define REG_B_OFFSET 0
303 #define REG_H_OFFSET 1
304 #define REG_W_OFFSET 0
305 #define REG_L_OFFSET 0
306 #define REG_LH_OFFSET 4
309 /* In instruction encodings for byte register accesses the
310 * register number usually indicates "low 8 bits of register N";
311 * however there are some special cases where N 4..7 indicates
312 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
313 * true for this special case, false otherwise.
315 static inline bool byte_reg_is_xH(int reg
)
321 if (reg
>= 8 || x86_64_hregs
) {
328 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
332 if (!byte_reg_is_xH(reg
)) {
333 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
335 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
339 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
341 default: /* XXX this shouldn't be reached; abort? */
343 /* For x86_64, this sets the higher half of register to zero.
344 For i386, this is equivalent to a mov. */
345 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
349 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
355 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
357 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
360 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
362 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
365 static inline void gen_op_mov_reg_A0(int size
, int reg
)
369 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_A0
, 0, 16);
371 default: /* XXX this shouldn't be reached; abort? */
373 /* For x86_64, this sets the higher half of register to zero.
374 For i386, this is equivalent to a mov. */
375 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
379 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
385 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
387 if (ot
== MO_8
&& byte_reg_is_xH(reg
)) {
388 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
389 tcg_gen_ext8u_tl(t0
, t0
);
391 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
395 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
397 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
400 static inline void gen_op_movl_A0_reg(int reg
)
402 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
405 static inline void gen_op_addl_A0_im(int32_t val
)
407 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
409 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
414 static inline void gen_op_addq_A0_im(int64_t val
)
416 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
420 static void gen_add_A0_im(DisasContext
*s
, int val
)
424 gen_op_addq_A0_im(val
);
427 gen_op_addl_A0_im(val
);
430 static inline void gen_op_addl_T0_T1(void)
432 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
435 static inline void gen_op_jmp_T0(void)
437 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
440 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
444 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
445 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
448 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
449 /* For x86_64, this sets the higher half of register to zero.
450 For i386, this is equivalent to a nop. */
451 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
452 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
456 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
462 static inline void gen_op_add_reg_T0(int size
, int reg
)
466 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
467 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
470 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
471 /* For x86_64, this sets the higher half of register to zero.
472 For i386, this is equivalent to a nop. */
473 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
474 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
478 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
484 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
486 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
488 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
489 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
490 /* For x86_64, this sets the higher half of register to zero.
491 For i386, this is equivalent to a nop. */
492 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
495 static inline void gen_op_movl_A0_seg(int reg
)
497 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
500 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
502 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
505 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
506 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
508 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
509 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
512 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
517 static inline void gen_op_movq_A0_seg(int reg
)
519 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
522 static inline void gen_op_addq_A0_seg(int reg
)
524 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
525 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
528 static inline void gen_op_movq_A0_reg(int reg
)
530 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
533 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
535 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
537 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
538 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
542 static inline void gen_op_ld_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
544 tcg_gen_qemu_ld_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
547 static inline void gen_op_st_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
549 tcg_gen_qemu_st_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
552 static inline void gen_op_st_rm_T0_A0(DisasContext
*s
, int idx
, int d
)
555 gen_op_st_v(s
, idx
, cpu_T
[0], cpu_A0
);
557 gen_op_mov_reg_T0(idx
, d
);
561 static inline void gen_jmp_im(target_ulong pc
)
563 tcg_gen_movi_tl(cpu_tmp0
, pc
);
564 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
567 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
571 override
= s
->override
;
575 gen_op_movq_A0_seg(override
);
576 gen_op_addq_A0_reg_sN(0, R_ESI
);
578 gen_op_movq_A0_reg(R_ESI
);
584 if (s
->addseg
&& override
< 0)
587 gen_op_movl_A0_seg(override
);
588 gen_op_addl_A0_reg_sN(0, R_ESI
);
590 gen_op_movl_A0_reg(R_ESI
);
593 /* 16 address, always override */
596 gen_op_movl_A0_reg(R_ESI
);
597 gen_op_andl_A0_ffff();
598 gen_op_addl_A0_seg(s
, override
);
602 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
606 gen_op_movq_A0_reg(R_EDI
);
611 gen_op_movl_A0_seg(R_ES
);
612 gen_op_addl_A0_reg_sN(0, R_EDI
);
614 gen_op_movl_A0_reg(R_EDI
);
617 gen_op_movl_A0_reg(R_EDI
);
618 gen_op_andl_A0_ffff();
619 gen_op_addl_A0_seg(s
, R_ES
);
623 static inline void gen_op_movl_T0_Dshift(int ot
)
625 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
626 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
629 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, int size
, bool sign
)
634 tcg_gen_ext8s_tl(dst
, src
);
636 tcg_gen_ext8u_tl(dst
, src
);
641 tcg_gen_ext16s_tl(dst
, src
);
643 tcg_gen_ext16u_tl(dst
, src
);
649 tcg_gen_ext32s_tl(dst
, src
);
651 tcg_gen_ext32u_tl(dst
, src
);
660 static void gen_extu(int ot
, TCGv reg
)
662 gen_ext_tl(reg
, reg
, ot
, false);
665 static void gen_exts(int ot
, TCGv reg
)
667 gen_ext_tl(reg
, reg
, ot
, true);
670 static inline void gen_op_jnz_ecx(int size
, int label1
)
672 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
673 gen_extu(size
+ 1, cpu_tmp0
);
674 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
677 static inline void gen_op_jz_ecx(int size
, int label1
)
679 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
680 gen_extu(size
+ 1, cpu_tmp0
);
681 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
684 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
688 gen_helper_inb(v
, n
);
691 gen_helper_inw(v
, n
);
694 gen_helper_inl(v
, n
);
699 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
703 gen_helper_outb(v
, n
);
706 gen_helper_outw(v
, n
);
709 gen_helper_outl(v
, n
);
714 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
718 target_ulong next_eip
;
721 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
725 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
728 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
731 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
734 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
738 if(s
->flags
& HF_SVMI_MASK
) {
743 svm_flags
|= (1 << (4 + ot
));
744 next_eip
= s
->pc
- s
->cs_base
;
745 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
746 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
747 tcg_const_i32(svm_flags
),
748 tcg_const_i32(next_eip
- cur_eip
));
752 static inline void gen_movs(DisasContext
*s
, int ot
)
754 gen_string_movl_A0_ESI(s
);
755 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
756 gen_string_movl_A0_EDI(s
);
757 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
758 gen_op_movl_T0_Dshift(ot
);
759 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
760 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
763 static void gen_op_update1_cc(void)
765 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
768 static void gen_op_update2_cc(void)
770 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
771 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
774 static void gen_op_update3_cc(TCGv reg
)
776 tcg_gen_mov_tl(cpu_cc_src2
, reg
);
777 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
778 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
781 static inline void gen_op_testl_T0_T1_cc(void)
783 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
786 static void gen_op_update_neg_cc(void)
788 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
789 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
790 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
793 /* compute all eflags to cc_src */
794 static void gen_compute_eflags(DisasContext
*s
)
796 TCGv zero
, dst
, src1
, src2
;
799 if (s
->cc_op
== CC_OP_EFLAGS
) {
802 if (s
->cc_op
== CC_OP_CLR
) {
803 tcg_gen_movi_tl(cpu_cc_src
, CC_Z
);
804 set_cc_op(s
, CC_OP_EFLAGS
);
813 /* Take care to not read values that are not live. */
814 live
= cc_op_live
[s
->cc_op
] & ~USES_CC_SRCT
;
815 dead
= live
^ (USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
);
817 zero
= tcg_const_tl(0);
818 if (dead
& USES_CC_DST
) {
821 if (dead
& USES_CC_SRC
) {
824 if (dead
& USES_CC_SRC2
) {
830 gen_helper_cc_compute_all(cpu_cc_src
, dst
, src1
, src2
, cpu_cc_op
);
831 set_cc_op(s
, CC_OP_EFLAGS
);
838 typedef struct CCPrepare
{
848 /* compute eflags.C to reg */
849 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
855 case CC_OP_SUBB
... CC_OP_SUBQ
:
856 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
857 size
= s
->cc_op
- CC_OP_SUBB
;
858 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
859 /* If no temporary was used, be careful not to alias t1 and t0. */
860 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
861 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
865 case CC_OP_ADDB
... CC_OP_ADDQ
:
866 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
867 size
= s
->cc_op
- CC_OP_ADDB
;
868 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
869 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
871 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
872 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
874 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
876 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
878 case CC_OP_INCB
... CC_OP_INCQ
:
879 case CC_OP_DECB
... CC_OP_DECQ
:
880 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
881 .mask
= -1, .no_setcond
= true };
883 case CC_OP_SHLB
... CC_OP_SHLQ
:
884 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
885 size
= s
->cc_op
- CC_OP_SHLB
;
886 shift
= (8 << size
) - 1;
887 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
888 .mask
= (target_ulong
)1 << shift
};
890 case CC_OP_MULB
... CC_OP_MULQ
:
891 return (CCPrepare
) { .cond
= TCG_COND_NE
,
892 .reg
= cpu_cc_src
, .mask
= -1 };
894 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
895 size
= s
->cc_op
- CC_OP_BMILGB
;
896 t0
= gen_ext_tl(reg
, cpu_cc_src
, size
, false);
897 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
901 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_dst
,
902 .mask
= -1, .no_setcond
= true };
905 case CC_OP_SARB
... CC_OP_SARQ
:
907 return (CCPrepare
) { .cond
= TCG_COND_NE
,
908 .reg
= cpu_cc_src
, .mask
= CC_C
};
911 /* The need to compute only C from CC_OP_DYNAMIC is important
912 in efficiently implementing e.g. INC at the start of a TB. */
914 gen_helper_cc_compute_c(reg
, cpu_cc_dst
, cpu_cc_src
,
915 cpu_cc_src2
, cpu_cc_op
);
916 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
917 .mask
= -1, .no_setcond
= true };
921 /* compute eflags.P to reg */
922 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
924 gen_compute_eflags(s
);
925 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
929 /* compute eflags.S to reg */
930 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
934 gen_compute_eflags(s
);
940 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
943 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
946 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
947 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
948 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
953 /* compute eflags.O to reg */
954 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
959 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src2
,
960 .mask
= -1, .no_setcond
= true };
962 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
964 gen_compute_eflags(s
);
965 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
970 /* compute eflags.Z to reg */
971 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
975 gen_compute_eflags(s
);
981 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
984 return (CCPrepare
) { .cond
= TCG_COND_ALWAYS
, .mask
= -1 };
987 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
988 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
989 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
994 /* perform a conditional store into register 'reg' according to jump opcode
995 value 'b'. In the fast case, T0 is guaranted not to be used. */
996 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
998 int inv
, jcc_op
, size
, cond
;
1003 jcc_op
= (b
>> 1) & 7;
1006 case CC_OP_SUBB
... CC_OP_SUBQ
:
1007 /* We optimize relational operators for the cmp/jcc case. */
1008 size
= s
->cc_op
- CC_OP_SUBB
;
1011 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
1012 gen_extu(size
, cpu_tmp4
);
1013 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
1014 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
1015 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1024 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
1025 gen_exts(size
, cpu_tmp4
);
1026 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1027 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
1028 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1038 /* This actually generates good code for JC, JZ and JS. */
1041 cc
= gen_prepare_eflags_o(s
, reg
);
1044 cc
= gen_prepare_eflags_c(s
, reg
);
1047 cc
= gen_prepare_eflags_z(s
, reg
);
1050 gen_compute_eflags(s
);
1051 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1052 .mask
= CC_Z
| CC_C
};
1055 cc
= gen_prepare_eflags_s(s
, reg
);
1058 cc
= gen_prepare_eflags_p(s
, reg
);
1061 gen_compute_eflags(s
);
1062 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1065 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1066 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1067 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1072 gen_compute_eflags(s
);
1073 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1076 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1077 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1078 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1079 .mask
= CC_S
| CC_Z
};
1086 cc
.cond
= tcg_invert_cond(cc
.cond
);
1091 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1093 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1095 if (cc
.no_setcond
) {
1096 if (cc
.cond
== TCG_COND_EQ
) {
1097 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1099 tcg_gen_mov_tl(reg
, cc
.reg
);
1104 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1105 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1106 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1107 tcg_gen_andi_tl(reg
, reg
, 1);
1110 if (cc
.mask
!= -1) {
1111 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1115 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1117 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1121 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1123 gen_setcc1(s
, JCC_B
<< 1, reg
);
1126 /* generate a conditional jump to label 'l1' according to jump opcode
1127 value 'b'. In the fast case, T0 is guaranted not to be used. */
1128 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1130 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1132 if (cc
.mask
!= -1) {
1133 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1137 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1139 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1143 /* Generate a conditional jump to label 'l1' according to jump opcode
1144 value 'b'. In the fast case, T0 is guaranted not to be used.
1145 A translation block must end soon. */
1146 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1148 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1150 gen_update_cc_op(s
);
1151 if (cc
.mask
!= -1) {
1152 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1155 set_cc_op(s
, CC_OP_DYNAMIC
);
1157 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1159 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1163 /* XXX: does not work with gdbstub "ice" single step - not a
1165 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1169 l1
= gen_new_label();
1170 l2
= gen_new_label();
1171 gen_op_jnz_ecx(s
->aflag
, l1
);
1173 gen_jmp_tb(s
, next_eip
, 1);
1178 static inline void gen_stos(DisasContext
*s
, int ot
)
1180 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
1181 gen_string_movl_A0_EDI(s
);
1182 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1183 gen_op_movl_T0_Dshift(ot
);
1184 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1187 static inline void gen_lods(DisasContext
*s
, int ot
)
1189 gen_string_movl_A0_ESI(s
);
1190 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1191 gen_op_mov_reg_T0(ot
, R_EAX
);
1192 gen_op_movl_T0_Dshift(ot
);
1193 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1196 static inline void gen_scas(DisasContext
*s
, int ot
)
1198 gen_string_movl_A0_EDI(s
);
1199 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1200 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1201 gen_op_movl_T0_Dshift(ot
);
1202 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1205 static inline void gen_cmps(DisasContext
*s
, int ot
)
1207 gen_string_movl_A0_EDI(s
);
1208 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1209 gen_string_movl_A0_ESI(s
);
1210 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1211 gen_op_movl_T0_Dshift(ot
);
1212 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1213 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1216 static inline void gen_ins(DisasContext
*s
, int ot
)
1220 gen_string_movl_A0_EDI(s
);
1221 /* Note: we must do this dummy write first to be restartable in
1222 case of page fault. */
1223 tcg_gen_movi_tl(cpu_T
[0], 0);
1224 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1225 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1226 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1227 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1228 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1229 gen_op_movl_T0_Dshift(ot
);
1230 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1235 static inline void gen_outs(DisasContext
*s
, int ot
)
1239 gen_string_movl_A0_ESI(s
);
1240 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1242 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1243 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1244 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1245 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1247 gen_op_movl_T0_Dshift(ot
);
1248 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1253 /* same method as Valgrind : we generate jumps to current or next
1255 #define GEN_REPZ(op) \
1256 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1257 target_ulong cur_eip, target_ulong next_eip) \
1260 gen_update_cc_op(s); \
1261 l2 = gen_jz_ecx_string(s, next_eip); \
1262 gen_ ## op(s, ot); \
1263 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1264 /* a loop would cause two single step exceptions if ECX = 1 \
1265 before rep string_insn */ \
1267 gen_op_jz_ecx(s->aflag, l2); \
1268 gen_jmp(s, cur_eip); \
1271 #define GEN_REPZ2(op) \
1272 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1273 target_ulong cur_eip, \
1274 target_ulong next_eip, \
1278 gen_update_cc_op(s); \
1279 l2 = gen_jz_ecx_string(s, next_eip); \
1280 gen_ ## op(s, ot); \
1281 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1282 gen_update_cc_op(s); \
1283 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1285 gen_op_jz_ecx(s->aflag, l2); \
1286 gen_jmp(s, cur_eip); \
1297 static void gen_helper_fp_arith_ST0_FT0(int op
)
1301 gen_helper_fadd_ST0_FT0(cpu_env
);
1304 gen_helper_fmul_ST0_FT0(cpu_env
);
1307 gen_helper_fcom_ST0_FT0(cpu_env
);
1310 gen_helper_fcom_ST0_FT0(cpu_env
);
1313 gen_helper_fsub_ST0_FT0(cpu_env
);
1316 gen_helper_fsubr_ST0_FT0(cpu_env
);
1319 gen_helper_fdiv_ST0_FT0(cpu_env
);
1322 gen_helper_fdivr_ST0_FT0(cpu_env
);
1327 /* NOTE the exception in "r" op ordering */
1328 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1330 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1333 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1336 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1339 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1342 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1345 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1348 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1353 /* if d == OR_TMP0, it means memory operand (address in A0) */
1354 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1357 gen_op_mov_TN_reg(ot
, 0, d
);
1359 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1363 gen_compute_eflags_c(s1
, cpu_tmp4
);
1364 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1365 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1366 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1367 gen_op_update3_cc(cpu_tmp4
);
1368 set_cc_op(s1
, CC_OP_ADCB
+ ot
);
1371 gen_compute_eflags_c(s1
, cpu_tmp4
);
1372 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1373 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1374 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1375 gen_op_update3_cc(cpu_tmp4
);
1376 set_cc_op(s1
, CC_OP_SBBB
+ ot
);
1379 gen_op_addl_T0_T1();
1380 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1381 gen_op_update2_cc();
1382 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1385 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1386 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1387 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1388 gen_op_update2_cc();
1389 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1393 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1394 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1395 gen_op_update1_cc();
1396 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1399 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1400 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1401 gen_op_update1_cc();
1402 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1405 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1406 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1407 gen_op_update1_cc();
1408 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1411 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1412 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1413 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1414 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1419 /* if d == OR_TMP0, it means memory operand (address in A0) */
1420 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1423 gen_op_mov_TN_reg(ot
, 0, d
);
1425 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1427 gen_compute_eflags_c(s1
, cpu_cc_src
);
1429 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1430 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1432 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1433 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1435 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1436 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1439 static void gen_shift_flags(DisasContext
*s
, int ot
, TCGv result
, TCGv shm1
,
1440 TCGv count
, bool is_right
)
1442 TCGv_i32 z32
, s32
, oldop
;
1445 /* Store the results into the CC variables. If we know that the
1446 variable must be dead, store unconditionally. Otherwise we'll
1447 need to not disrupt the current contents. */
1448 z_tl
= tcg_const_tl(0);
1449 if (cc_op_live
[s
->cc_op
] & USES_CC_DST
) {
1450 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_dst
, count
, z_tl
,
1451 result
, cpu_cc_dst
);
1453 tcg_gen_mov_tl(cpu_cc_dst
, result
);
1455 if (cc_op_live
[s
->cc_op
] & USES_CC_SRC
) {
1456 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_src
, count
, z_tl
,
1459 tcg_gen_mov_tl(cpu_cc_src
, shm1
);
1461 tcg_temp_free(z_tl
);
1463 /* Get the two potential CC_OP values into temporaries. */
1464 tcg_gen_movi_i32(cpu_tmp2_i32
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1465 if (s
->cc_op
== CC_OP_DYNAMIC
) {
1468 tcg_gen_movi_i32(cpu_tmp3_i32
, s
->cc_op
);
1469 oldop
= cpu_tmp3_i32
;
1472 /* Conditionally store the CC_OP value. */
1473 z32
= tcg_const_i32(0);
1474 s32
= tcg_temp_new_i32();
1475 tcg_gen_trunc_tl_i32(s32
, count
);
1476 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, s32
, z32
, cpu_tmp2_i32
, oldop
);
1477 tcg_temp_free_i32(z32
);
1478 tcg_temp_free_i32(s32
);
1480 /* The CC_OP value is no longer predictable. */
1481 set_cc_op(s
, CC_OP_DYNAMIC
);
1484 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1485 int is_right
, int is_arith
)
1487 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1490 if (op1
== OR_TMP0
) {
1491 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1493 gen_op_mov_TN_reg(ot
, 0, op1
);
1496 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1497 tcg_gen_subi_tl(cpu_tmp0
, cpu_T
[1], 1);
1501 gen_exts(ot
, cpu_T
[0]);
1502 tcg_gen_sar_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1503 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1505 gen_extu(ot
, cpu_T
[0]);
1506 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1507 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1510 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1511 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1515 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1517 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, cpu_T
[1], is_right
);
1520 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1521 int is_right
, int is_arith
)
1523 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1527 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1529 gen_op_mov_TN_reg(ot
, 0, op1
);
1535 gen_exts(ot
, cpu_T
[0]);
1536 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1537 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1539 gen_extu(ot
, cpu_T
[0]);
1540 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1541 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1544 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1545 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1550 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1552 /* update eflags if non zero shift */
1554 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1555 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1556 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1560 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1563 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1565 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1568 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
, int is_right
)
1570 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1574 if (op1
== OR_TMP0
) {
1575 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1577 gen_op_mov_TN_reg(ot
, 0, op1
);
1580 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1584 /* Replicate the 8-bit input so that a 32-bit rotate works. */
1585 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
1586 tcg_gen_muli_tl(cpu_T
[0], cpu_T
[0], 0x01010101);
1589 /* Replicate the 16-bit input so that a 32-bit rotate works. */
1590 tcg_gen_deposit_tl(cpu_T
[0], cpu_T
[0], cpu_T
[0], 16, 16);
1593 #ifdef TARGET_X86_64
1595 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1596 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
1598 tcg_gen_rotr_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1600 tcg_gen_rotl_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1602 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1607 tcg_gen_rotr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1609 tcg_gen_rotl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1615 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1617 /* We'll need the flags computed into CC_SRC. */
1618 gen_compute_eflags(s
);
1620 /* The value that was "rotated out" is now present at the other end
1621 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1622 since we've computed the flags into CC_SRC, these variables are
1625 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1626 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1627 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1629 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1630 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1632 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1633 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1635 /* Now conditionally store the new CC_OP value. If the shift count
1636 is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
1637 Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
1638 exactly as we computed above. */
1639 t0
= tcg_const_i32(0);
1640 t1
= tcg_temp_new_i32();
1641 tcg_gen_trunc_tl_i32(t1
, cpu_T
[1]);
1642 tcg_gen_movi_i32(cpu_tmp2_i32
, CC_OP_ADCOX
);
1643 tcg_gen_movi_i32(cpu_tmp3_i32
, CC_OP_EFLAGS
);
1644 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, t1
, t0
,
1645 cpu_tmp2_i32
, cpu_tmp3_i32
);
1646 tcg_temp_free_i32(t0
);
1647 tcg_temp_free_i32(t1
);
1649 /* The CC_OP value is no longer predictable. */
1650 set_cc_op(s
, CC_OP_DYNAMIC
);
1653 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1656 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1660 if (op1
== OR_TMP0
) {
1661 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1663 gen_op_mov_TN_reg(ot
, 0, op1
);
1669 #ifdef TARGET_X86_64
1671 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1673 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1675 tcg_gen_rotli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1677 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1682 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], op2
);
1684 tcg_gen_rotli_tl(cpu_T
[0], cpu_T
[0], op2
);
1695 shift
= mask
+ 1 - shift
;
1697 gen_extu(ot
, cpu_T
[0]);
1698 tcg_gen_shli_tl(cpu_tmp0
, cpu_T
[0], shift
);
1699 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], mask
+ 1 - shift
);
1700 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
1706 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1709 /* Compute the flags into CC_SRC. */
1710 gen_compute_eflags(s
);
1712 /* The value that was "rotated out" is now present at the other end
1713 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1714 since we've computed the flags into CC_SRC, these variables are
1717 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1718 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1719 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1721 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1722 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1724 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1725 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1726 set_cc_op(s
, CC_OP_ADCOX
);
1730 /* XXX: add faster immediate = 1 case */
1731 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1734 gen_compute_eflags(s
);
1735 assert(s
->cc_op
== CC_OP_EFLAGS
);
1739 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1741 gen_op_mov_TN_reg(ot
, 0, op1
);
1746 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1749 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1752 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1754 #ifdef TARGET_X86_64
1756 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1763 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1766 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1769 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1771 #ifdef TARGET_X86_64
1773 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1779 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1782 /* XXX: add faster immediate case */
1783 static void gen_shiftd_rm_T1(DisasContext
*s
, int ot
, int op1
,
1784 bool is_right
, TCGv count_in
)
1786 target_ulong mask
= (ot
== MO_64
? 63 : 31);
1790 if (op1
== OR_TMP0
) {
1791 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1793 gen_op_mov_TN_reg(ot
, 0, op1
);
1796 count
= tcg_temp_new();
1797 tcg_gen_andi_tl(count
, count_in
, mask
);
1801 /* Note: we implement the Intel behaviour for shift count > 16.
1802 This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
1803 portion by constructing it as a 32-bit value. */
1805 tcg_gen_deposit_tl(cpu_tmp0
, cpu_T
[0], cpu_T
[1], 16, 16);
1806 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1807 tcg_gen_mov_tl(cpu_T
[0], cpu_tmp0
);
1809 tcg_gen_deposit_tl(cpu_T
[1], cpu_T
[0], cpu_T
[1], 16, 16);
1812 #ifdef TARGET_X86_64
1814 /* Concatenate the two 32-bit values and use a 64-bit shift. */
1815 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1817 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1818 tcg_gen_shr_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1819 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], count
);
1821 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[1], cpu_T
[0]);
1822 tcg_gen_shl_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1823 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], count
);
1824 tcg_gen_shri_i64(cpu_tmp0
, cpu_tmp0
, 32);
1825 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], 32);
1830 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1832 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1834 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1835 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], count
);
1836 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1838 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1840 /* Only needed if count > 16, for Intel behaviour. */
1841 tcg_gen_subfi_tl(cpu_tmp4
, 33, count
);
1842 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[1], cpu_tmp4
);
1843 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, cpu_tmp4
);
1846 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1847 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], count
);
1848 tcg_gen_shr_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1850 tcg_gen_movi_tl(cpu_tmp4
, 0);
1851 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[1], count
, cpu_tmp4
,
1852 cpu_tmp4
, cpu_T
[1]);
1853 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1858 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1860 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, count
, is_right
);
1861 tcg_temp_free(count
);
1864 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
1867 gen_op_mov_TN_reg(ot
, 1, s
);
1870 gen_rot_rm_T1(s1
, ot
, d
, 0);
1873 gen_rot_rm_T1(s1
, ot
, d
, 1);
1877 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1880 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1883 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1886 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1889 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1894 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
1898 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1901 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1905 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1908 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1911 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1914 /* currently not optimized */
1915 tcg_gen_movi_tl(cpu_T
[1], c
);
1916 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1921 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
1928 int mod
, rm
, code
, override
, must_add_seg
;
1931 override
= s
->override
;
1932 must_add_seg
= s
->addseg
;
1935 mod
= (modrm
>> 6) & 3;
1946 code
= cpu_ldub_code(env
, s
->pc
++);
1947 scale
= (code
>> 6) & 3;
1948 index
= ((code
>> 3) & 7) | REX_X(s
);
1950 index
= -1; /* no index */
1958 if ((base
& 7) == 5) {
1960 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1962 if (CODE64(s
) && !havesib
) {
1963 disp
+= s
->pc
+ s
->rip_offset
;
1970 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
1974 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1979 /* For correct popl handling with esp. */
1980 if (base
== R_ESP
&& s
->popl_esp_hack
) {
1981 disp
+= s
->popl_esp_hack
;
1984 /* Compute the address, with a minimum number of TCG ops. */
1988 sum
= cpu_regs
[index
];
1990 tcg_gen_shli_tl(cpu_A0
, cpu_regs
[index
], scale
);
1994 tcg_gen_add_tl(cpu_A0
, sum
, cpu_regs
[base
]);
1997 } else if (base
>= 0) {
1998 sum
= cpu_regs
[base
];
2000 if (TCGV_IS_UNUSED(sum
)) {
2001 tcg_gen_movi_tl(cpu_A0
, disp
);
2003 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
2008 if (base
== R_EBP
|| base
== R_ESP
) {
2015 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
2016 offsetof(CPUX86State
, segs
[override
].base
));
2018 if (s
->aflag
!= 2) {
2019 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2021 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
2025 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
2028 if (s
->aflag
!= 2) {
2029 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2035 disp
= cpu_lduw_code(env
, s
->pc
);
2037 tcg_gen_movi_tl(cpu_A0
, disp
);
2038 rm
= 0; /* avoid SS override */
2045 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2049 disp
= cpu_lduw_code(env
, s
->pc
);
2055 gen_op_movl_A0_reg(R_EBX
);
2056 gen_op_addl_A0_reg_sN(0, R_ESI
);
2059 gen_op_movl_A0_reg(R_EBX
);
2060 gen_op_addl_A0_reg_sN(0, R_EDI
);
2063 gen_op_movl_A0_reg(R_EBP
);
2064 gen_op_addl_A0_reg_sN(0, R_ESI
);
2067 gen_op_movl_A0_reg(R_EBP
);
2068 gen_op_addl_A0_reg_sN(0, R_EDI
);
2071 gen_op_movl_A0_reg(R_ESI
);
2074 gen_op_movl_A0_reg(R_EDI
);
2077 gen_op_movl_A0_reg(R_EBP
);
2081 gen_op_movl_A0_reg(R_EBX
);
2085 gen_op_addl_A0_im(disp
);
2086 gen_op_andl_A0_ffff();
2090 if (rm
== 2 || rm
== 3 || rm
== 6)
2095 gen_op_addl_A0_seg(s
, override
);
2100 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2102 int mod
, rm
, base
, code
;
2104 mod
= (modrm
>> 6) & 3;
2114 code
= cpu_ldub_code(env
, s
->pc
++);
2150 /* used for LEA and MOV AX, mem */
2151 static void gen_add_A0_ds_seg(DisasContext
*s
)
2153 int override
, must_add_seg
;
2154 must_add_seg
= s
->addseg
;
2156 if (s
->override
>= 0) {
2157 override
= s
->override
;
2161 #ifdef TARGET_X86_64
2163 gen_op_addq_A0_seg(override
);
2167 gen_op_addl_A0_seg(s
, override
);
2172 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2174 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2175 int ot
, int reg
, int is_store
)
2179 mod
= (modrm
>> 6) & 3;
2180 rm
= (modrm
& 7) | REX_B(s
);
2184 gen_op_mov_TN_reg(ot
, 0, reg
);
2185 gen_op_mov_reg_T0(ot
, rm
);
2187 gen_op_mov_TN_reg(ot
, 0, rm
);
2189 gen_op_mov_reg_T0(ot
, reg
);
2192 gen_lea_modrm(env
, s
, modrm
);
2195 gen_op_mov_TN_reg(ot
, 0, reg
);
2196 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2198 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
2200 gen_op_mov_reg_T0(ot
, reg
);
2205 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, int ot
)
2211 ret
= cpu_ldub_code(env
, s
->pc
);
2215 ret
= cpu_lduw_code(env
, s
->pc
);
2220 ret
= cpu_ldl_code(env
, s
->pc
);
2227 static inline int insn_const_size(unsigned int ot
)
2236 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2238 TranslationBlock
*tb
;
2241 pc
= s
->cs_base
+ eip
;
2243 /* NOTE: we handle the case where the TB spans two pages here */
2244 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2245 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2246 /* jump to same page: we can use a direct jump */
2247 tcg_gen_goto_tb(tb_num
);
2249 tcg_gen_exit_tb((uintptr_t)tb
+ tb_num
);
2251 /* jump to another page: currently not optimized */
2257 static inline void gen_jcc(DisasContext
*s
, int b
,
2258 target_ulong val
, target_ulong next_eip
)
2263 l1
= gen_new_label();
2266 gen_goto_tb(s
, 0, next_eip
);
2269 gen_goto_tb(s
, 1, val
);
2270 s
->is_jmp
= DISAS_TB_JUMP
;
2272 l1
= gen_new_label();
2273 l2
= gen_new_label();
2276 gen_jmp_im(next_eip
);
2286 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, int ot
, int b
,
2291 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2293 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2294 if (cc
.mask
!= -1) {
2295 TCGv t0
= tcg_temp_new();
2296 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2300 cc
.reg2
= tcg_const_tl(cc
.imm
);
2303 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2304 cpu_T
[0], cpu_regs
[reg
]);
2305 gen_op_mov_reg_T0(ot
, reg
);
2307 if (cc
.mask
!= -1) {
2308 tcg_temp_free(cc
.reg
);
2311 tcg_temp_free(cc
.reg2
);
2315 static inline void gen_op_movl_T0_seg(int seg_reg
)
2317 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2318 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2321 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2323 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2324 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2325 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2326 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2327 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2328 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2331 /* move T0 to seg_reg and compute if the CPU state may change. Never
2332 call this function with seg_reg == R_CS */
2333 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2335 if (s
->pe
&& !s
->vm86
) {
2336 /* XXX: optimize by finding processor state dynamically */
2337 gen_update_cc_op(s
);
2338 gen_jmp_im(cur_eip
);
2339 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2340 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2341 /* abort translation because the addseg value may change or
2342 because ss32 may change. For R_SS, translation must always
2343 stop as a special handling must be done to disable hardware
2344 interrupts for the next instruction */
2345 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2346 s
->is_jmp
= DISAS_TB_JUMP
;
2348 gen_op_movl_seg_T0_vm(seg_reg
);
2349 if (seg_reg
== R_SS
)
2350 s
->is_jmp
= DISAS_TB_JUMP
;
2354 static inline int svm_is_rep(int prefixes
)
2356 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2360 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2361 uint32_t type
, uint64_t param
)
2363 /* no SVM activated; fast case */
2364 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2366 gen_update_cc_op(s
);
2367 gen_jmp_im(pc_start
- s
->cs_base
);
2368 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2369 tcg_const_i64(param
));
2373 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2375 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2378 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2380 #ifdef TARGET_X86_64
2382 gen_op_add_reg_im(2, R_ESP
, addend
);
2386 gen_op_add_reg_im(1, R_ESP
, addend
);
2388 gen_op_add_reg_im(0, R_ESP
, addend
);
2392 /* generate a push. It depends on ss32, addseg and dflag */
2393 static void gen_push_T0(DisasContext
*s
)
2395 #ifdef TARGET_X86_64
2397 gen_op_movq_A0_reg(R_ESP
);
2399 gen_op_addq_A0_im(-8);
2400 gen_op_st_v(s
, MO_64
, cpu_T
[0], cpu_A0
);
2402 gen_op_addq_A0_im(-2);
2403 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
2405 gen_op_mov_reg_A0(2, R_ESP
);
2409 gen_op_movl_A0_reg(R_ESP
);
2411 gen_op_addl_A0_im(-2);
2413 gen_op_addl_A0_im(-4);
2416 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2417 gen_op_addl_A0_seg(s
, R_SS
);
2420 gen_op_andl_A0_ffff();
2421 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2422 gen_op_addl_A0_seg(s
, R_SS
);
2424 gen_op_st_v(s
, s
->dflag
+ 1, cpu_T
[0], cpu_A0
);
2425 if (s
->ss32
&& !s
->addseg
)
2426 gen_op_mov_reg_A0(1, R_ESP
);
2428 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2432 /* generate a push. It depends on ss32, addseg and dflag */
2433 /* slower version for T1, only used for call Ev */
2434 static void gen_push_T1(DisasContext
*s
)
2436 #ifdef TARGET_X86_64
2438 gen_op_movq_A0_reg(R_ESP
);
2440 gen_op_addq_A0_im(-8);
2441 gen_op_st_v(s
, MO_64
, cpu_T
[1], cpu_A0
);
2443 gen_op_addq_A0_im(-2);
2444 gen_op_st_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
2446 gen_op_mov_reg_A0(2, R_ESP
);
2450 gen_op_movl_A0_reg(R_ESP
);
2452 gen_op_addl_A0_im(-2);
2454 gen_op_addl_A0_im(-4);
2457 gen_op_addl_A0_seg(s
, R_SS
);
2460 gen_op_andl_A0_ffff();
2461 gen_op_addl_A0_seg(s
, R_SS
);
2463 gen_op_st_v(s
, s
->dflag
+ 1, cpu_T
[1], cpu_A0
);
2465 if (s
->ss32
&& !s
->addseg
)
2466 gen_op_mov_reg_A0(1, R_ESP
);
2468 gen_stack_update(s
, (-2) << s
->dflag
);
2472 /* two step pop is necessary for precise exceptions */
2473 static void gen_pop_T0(DisasContext
*s
)
2475 #ifdef TARGET_X86_64
2477 gen_op_movq_A0_reg(R_ESP
);
2478 gen_op_ld_v(s
, s
->dflag
? MO_64
: MO_16
, cpu_T
[0], cpu_A0
);
2482 gen_op_movl_A0_reg(R_ESP
);
2485 gen_op_addl_A0_seg(s
, R_SS
);
2487 gen_op_andl_A0_ffff();
2488 gen_op_addl_A0_seg(s
, R_SS
);
2490 gen_op_ld_v(s
, s
->dflag
+ 1, cpu_T
[0], cpu_A0
);
2494 static void gen_pop_update(DisasContext
*s
)
2496 #ifdef TARGET_X86_64
2497 if (CODE64(s
) && s
->dflag
) {
2498 gen_stack_update(s
, 8);
2502 gen_stack_update(s
, 2 << s
->dflag
);
2506 static void gen_stack_A0(DisasContext
*s
)
2508 gen_op_movl_A0_reg(R_ESP
);
2510 gen_op_andl_A0_ffff();
2511 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2513 gen_op_addl_A0_seg(s
, R_SS
);
2516 /* NOTE: wrap around in 16 bit not fully handled */
2517 static void gen_pusha(DisasContext
*s
)
2520 gen_op_movl_A0_reg(R_ESP
);
2521 gen_op_addl_A0_im(-16 << s
->dflag
);
2523 gen_op_andl_A0_ffff();
2524 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2526 gen_op_addl_A0_seg(s
, R_SS
);
2527 for(i
= 0;i
< 8; i
++) {
2528 gen_op_mov_TN_reg(MO_32
, 0, 7 - i
);
2529 gen_op_st_v(s
, MO_16
+ s
->dflag
, cpu_T
[0], cpu_A0
);
2530 gen_op_addl_A0_im(2 << s
->dflag
);
2532 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2535 /* NOTE: wrap around in 16 bit not fully handled */
2536 static void gen_popa(DisasContext
*s
)
2539 gen_op_movl_A0_reg(R_ESP
);
2541 gen_op_andl_A0_ffff();
2542 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2543 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2545 gen_op_addl_A0_seg(s
, R_SS
);
2546 for(i
= 0;i
< 8; i
++) {
2547 /* ESP is not reloaded */
2549 gen_op_ld_v(s
, MO_16
+ s
->dflag
, cpu_T
[0], cpu_A0
);
2550 gen_op_mov_reg_T0(MO_16
+ s
->dflag
, 7 - i
);
2552 gen_op_addl_A0_im(2 << s
->dflag
);
2554 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2557 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2562 #ifdef TARGET_X86_64
2564 ot
= s
->dflag
? MO_64
: MO_16
;
2567 gen_op_movl_A0_reg(R_ESP
);
2568 gen_op_addq_A0_im(-opsize
);
2569 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2572 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2573 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2575 /* XXX: must save state */
2576 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2577 tcg_const_i32((ot
== MO_64
)),
2580 gen_op_mov_reg_T1(ot
, R_EBP
);
2581 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2582 gen_op_mov_reg_T1(MO_64
, R_ESP
);
2586 ot
= s
->dflag
+ MO_16
;
2587 opsize
= 2 << s
->dflag
;
2589 gen_op_movl_A0_reg(R_ESP
);
2590 gen_op_addl_A0_im(-opsize
);
2592 gen_op_andl_A0_ffff();
2593 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2595 gen_op_addl_A0_seg(s
, R_SS
);
2597 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2598 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2600 /* XXX: must save state */
2601 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2602 tcg_const_i32(s
->dflag
),
2605 gen_op_mov_reg_T1(ot
, R_EBP
);
2606 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2607 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2611 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2613 gen_update_cc_op(s
);
2614 gen_jmp_im(cur_eip
);
2615 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2616 s
->is_jmp
= DISAS_TB_JUMP
;
2619 /* an interrupt is different from an exception because of the
2621 static void gen_interrupt(DisasContext
*s
, int intno
,
2622 target_ulong cur_eip
, target_ulong next_eip
)
2624 gen_update_cc_op(s
);
2625 gen_jmp_im(cur_eip
);
2626 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2627 tcg_const_i32(next_eip
- cur_eip
));
2628 s
->is_jmp
= DISAS_TB_JUMP
;
2631 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2633 gen_update_cc_op(s
);
2634 gen_jmp_im(cur_eip
);
2635 gen_helper_debug(cpu_env
);
2636 s
->is_jmp
= DISAS_TB_JUMP
;
2639 /* generate a generic end of block. Trace exception is also generated
2641 static void gen_eob(DisasContext
*s
)
2643 gen_update_cc_op(s
);
2644 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2645 gen_helper_reset_inhibit_irq(cpu_env
);
2647 if (s
->tb
->flags
& HF_RF_MASK
) {
2648 gen_helper_reset_rf(cpu_env
);
2650 if (s
->singlestep_enabled
) {
2651 gen_helper_debug(cpu_env
);
2653 gen_helper_single_step(cpu_env
);
2657 s
->is_jmp
= DISAS_TB_JUMP
;
2660 /* generate a jump to eip. No segment change must happen before as a
2661 direct call to the next block may occur */
2662 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2664 gen_update_cc_op(s
);
2665 set_cc_op(s
, CC_OP_DYNAMIC
);
2667 gen_goto_tb(s
, tb_num
, eip
);
2668 s
->is_jmp
= DISAS_TB_JUMP
;
2675 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2677 gen_jmp_tb(s
, eip
, 0);
2680 static inline void gen_ldq_env_A0(DisasContext
*s
, int offset
)
2682 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2683 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2686 static inline void gen_stq_env_A0(DisasContext
*s
, int offset
)
2688 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2689 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2692 static inline void gen_ldo_env_A0(DisasContext
*s
, int offset
)
2694 int mem_index
= s
->mem_index
;
2695 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2696 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2697 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2698 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2699 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2702 static inline void gen_sto_env_A0(DisasContext
*s
, int offset
)
2704 int mem_index
= s
->mem_index
;
2705 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2706 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2707 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2708 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2709 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2712 static inline void gen_op_movo(int d_offset
, int s_offset
)
2714 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2715 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2716 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2717 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2720 static inline void gen_op_movq(int d_offset
, int s_offset
)
2722 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2723 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2726 static inline void gen_op_movl(int d_offset
, int s_offset
)
2728 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2729 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2732 static inline void gen_op_movq_env_0(int d_offset
)
2734 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2735 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2738 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2739 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2740 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2741 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2742 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2743 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2745 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2746 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2749 #define SSE_SPECIAL ((void *)1)
2750 #define SSE_DUMMY ((void *)2)
2752 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2753 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2754 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2756 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2757 /* 3DNow! extensions */
2758 [0x0e] = { SSE_DUMMY
}, /* femms */
2759 [0x0f] = { SSE_DUMMY
}, /* pf... */
2760 /* pure SSE operations */
2761 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2762 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2763 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2764 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2765 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2766 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2767 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2768 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2770 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2771 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2772 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2773 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2774 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2775 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2776 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2777 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2778 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2779 [0x51] = SSE_FOP(sqrt
),
2780 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2781 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2782 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2783 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2784 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2785 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2786 [0x58] = SSE_FOP(add
),
2787 [0x59] = SSE_FOP(mul
),
2788 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2789 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2790 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2791 [0x5c] = SSE_FOP(sub
),
2792 [0x5d] = SSE_FOP(min
),
2793 [0x5e] = SSE_FOP(div
),
2794 [0x5f] = SSE_FOP(max
),
2796 [0xc2] = SSE_FOP(cmpeq
),
2797 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2798 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2800 /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
2801 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2802 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2804 /* MMX ops and their SSE extensions */
2805 [0x60] = MMX_OP2(punpcklbw
),
2806 [0x61] = MMX_OP2(punpcklwd
),
2807 [0x62] = MMX_OP2(punpckldq
),
2808 [0x63] = MMX_OP2(packsswb
),
2809 [0x64] = MMX_OP2(pcmpgtb
),
2810 [0x65] = MMX_OP2(pcmpgtw
),
2811 [0x66] = MMX_OP2(pcmpgtl
),
2812 [0x67] = MMX_OP2(packuswb
),
2813 [0x68] = MMX_OP2(punpckhbw
),
2814 [0x69] = MMX_OP2(punpckhwd
),
2815 [0x6a] = MMX_OP2(punpckhdq
),
2816 [0x6b] = MMX_OP2(packssdw
),
2817 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2818 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2819 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2820 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2821 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2822 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2823 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2824 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2825 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2826 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2827 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2828 [0x74] = MMX_OP2(pcmpeqb
),
2829 [0x75] = MMX_OP2(pcmpeqw
),
2830 [0x76] = MMX_OP2(pcmpeql
),
2831 [0x77] = { SSE_DUMMY
}, /* emms */
2832 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2833 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2834 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2835 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2836 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2837 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2838 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2839 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2840 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2841 [0xd1] = MMX_OP2(psrlw
),
2842 [0xd2] = MMX_OP2(psrld
),
2843 [0xd3] = MMX_OP2(psrlq
),
2844 [0xd4] = MMX_OP2(paddq
),
2845 [0xd5] = MMX_OP2(pmullw
),
2846 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2847 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2848 [0xd8] = MMX_OP2(psubusb
),
2849 [0xd9] = MMX_OP2(psubusw
),
2850 [0xda] = MMX_OP2(pminub
),
2851 [0xdb] = MMX_OP2(pand
),
2852 [0xdc] = MMX_OP2(paddusb
),
2853 [0xdd] = MMX_OP2(paddusw
),
2854 [0xde] = MMX_OP2(pmaxub
),
2855 [0xdf] = MMX_OP2(pandn
),
2856 [0xe0] = MMX_OP2(pavgb
),
2857 [0xe1] = MMX_OP2(psraw
),
2858 [0xe2] = MMX_OP2(psrad
),
2859 [0xe3] = MMX_OP2(pavgw
),
2860 [0xe4] = MMX_OP2(pmulhuw
),
2861 [0xe5] = MMX_OP2(pmulhw
),
2862 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2863 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2864 [0xe8] = MMX_OP2(psubsb
),
2865 [0xe9] = MMX_OP2(psubsw
),
2866 [0xea] = MMX_OP2(pminsw
),
2867 [0xeb] = MMX_OP2(por
),
2868 [0xec] = MMX_OP2(paddsb
),
2869 [0xed] = MMX_OP2(paddsw
),
2870 [0xee] = MMX_OP2(pmaxsw
),
2871 [0xef] = MMX_OP2(pxor
),
2872 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2873 [0xf1] = MMX_OP2(psllw
),
2874 [0xf2] = MMX_OP2(pslld
),
2875 [0xf3] = MMX_OP2(psllq
),
2876 [0xf4] = MMX_OP2(pmuludq
),
2877 [0xf5] = MMX_OP2(pmaddwd
),
2878 [0xf6] = MMX_OP2(psadbw
),
2879 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
2880 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
2881 [0xf8] = MMX_OP2(psubb
),
2882 [0xf9] = MMX_OP2(psubw
),
2883 [0xfa] = MMX_OP2(psubl
),
2884 [0xfb] = MMX_OP2(psubq
),
2885 [0xfc] = MMX_OP2(paddb
),
2886 [0xfd] = MMX_OP2(paddw
),
2887 [0xfe] = MMX_OP2(paddl
),
2890 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
2891 [0 + 2] = MMX_OP2(psrlw
),
2892 [0 + 4] = MMX_OP2(psraw
),
2893 [0 + 6] = MMX_OP2(psllw
),
2894 [8 + 2] = MMX_OP2(psrld
),
2895 [8 + 4] = MMX_OP2(psrad
),
2896 [8 + 6] = MMX_OP2(pslld
),
2897 [16 + 2] = MMX_OP2(psrlq
),
2898 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2899 [16 + 6] = MMX_OP2(psllq
),
2900 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2903 static const SSEFunc_0_epi sse_op_table3ai
[] = {
2904 gen_helper_cvtsi2ss
,
2908 #ifdef TARGET_X86_64
2909 static const SSEFunc_0_epl sse_op_table3aq
[] = {
2910 gen_helper_cvtsq2ss
,
2915 static const SSEFunc_i_ep sse_op_table3bi
[] = {
2916 gen_helper_cvttss2si
,
2917 gen_helper_cvtss2si
,
2918 gen_helper_cvttsd2si
,
2922 #ifdef TARGET_X86_64
2923 static const SSEFunc_l_ep sse_op_table3bq
[] = {
2924 gen_helper_cvttss2sq
,
2925 gen_helper_cvtss2sq
,
2926 gen_helper_cvttsd2sq
,
2931 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
2942 static const SSEFunc_0_epp sse_op_table5
[256] = {
2943 [0x0c] = gen_helper_pi2fw
,
2944 [0x0d] = gen_helper_pi2fd
,
2945 [0x1c] = gen_helper_pf2iw
,
2946 [0x1d] = gen_helper_pf2id
,
2947 [0x8a] = gen_helper_pfnacc
,
2948 [0x8e] = gen_helper_pfpnacc
,
2949 [0x90] = gen_helper_pfcmpge
,
2950 [0x94] = gen_helper_pfmin
,
2951 [0x96] = gen_helper_pfrcp
,
2952 [0x97] = gen_helper_pfrsqrt
,
2953 [0x9a] = gen_helper_pfsub
,
2954 [0x9e] = gen_helper_pfadd
,
2955 [0xa0] = gen_helper_pfcmpgt
,
2956 [0xa4] = gen_helper_pfmax
,
2957 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2958 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2959 [0xaa] = gen_helper_pfsubr
,
2960 [0xae] = gen_helper_pfacc
,
2961 [0xb0] = gen_helper_pfcmpeq
,
2962 [0xb4] = gen_helper_pfmul
,
2963 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
2964 [0xb7] = gen_helper_pmulhrw_mmx
,
2965 [0xbb] = gen_helper_pswapd
,
2966 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
2969 struct SSEOpHelper_epp
{
2970 SSEFunc_0_epp op
[2];
2974 struct SSEOpHelper_eppi
{
2975 SSEFunc_0_eppi op
[2];
2979 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2980 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
2981 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
2982 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
2983 #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
2984 CPUID_EXT_PCLMULQDQ }
2985 #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
2987 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
2988 [0x00] = SSSE3_OP(pshufb
),
2989 [0x01] = SSSE3_OP(phaddw
),
2990 [0x02] = SSSE3_OP(phaddd
),
2991 [0x03] = SSSE3_OP(phaddsw
),
2992 [0x04] = SSSE3_OP(pmaddubsw
),
2993 [0x05] = SSSE3_OP(phsubw
),
2994 [0x06] = SSSE3_OP(phsubd
),
2995 [0x07] = SSSE3_OP(phsubsw
),
2996 [0x08] = SSSE3_OP(psignb
),
2997 [0x09] = SSSE3_OP(psignw
),
2998 [0x0a] = SSSE3_OP(psignd
),
2999 [0x0b] = SSSE3_OP(pmulhrsw
),
3000 [0x10] = SSE41_OP(pblendvb
),
3001 [0x14] = SSE41_OP(blendvps
),
3002 [0x15] = SSE41_OP(blendvpd
),
3003 [0x17] = SSE41_OP(ptest
),
3004 [0x1c] = SSSE3_OP(pabsb
),
3005 [0x1d] = SSSE3_OP(pabsw
),
3006 [0x1e] = SSSE3_OP(pabsd
),
3007 [0x20] = SSE41_OP(pmovsxbw
),
3008 [0x21] = SSE41_OP(pmovsxbd
),
3009 [0x22] = SSE41_OP(pmovsxbq
),
3010 [0x23] = SSE41_OP(pmovsxwd
),
3011 [0x24] = SSE41_OP(pmovsxwq
),
3012 [0x25] = SSE41_OP(pmovsxdq
),
3013 [0x28] = SSE41_OP(pmuldq
),
3014 [0x29] = SSE41_OP(pcmpeqq
),
3015 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3016 [0x2b] = SSE41_OP(packusdw
),
3017 [0x30] = SSE41_OP(pmovzxbw
),
3018 [0x31] = SSE41_OP(pmovzxbd
),
3019 [0x32] = SSE41_OP(pmovzxbq
),
3020 [0x33] = SSE41_OP(pmovzxwd
),
3021 [0x34] = SSE41_OP(pmovzxwq
),
3022 [0x35] = SSE41_OP(pmovzxdq
),
3023 [0x37] = SSE42_OP(pcmpgtq
),
3024 [0x38] = SSE41_OP(pminsb
),
3025 [0x39] = SSE41_OP(pminsd
),
3026 [0x3a] = SSE41_OP(pminuw
),
3027 [0x3b] = SSE41_OP(pminud
),
3028 [0x3c] = SSE41_OP(pmaxsb
),
3029 [0x3d] = SSE41_OP(pmaxsd
),
3030 [0x3e] = SSE41_OP(pmaxuw
),
3031 [0x3f] = SSE41_OP(pmaxud
),
3032 [0x40] = SSE41_OP(pmulld
),
3033 [0x41] = SSE41_OP(phminposuw
),
3034 [0xdb] = AESNI_OP(aesimc
),
3035 [0xdc] = AESNI_OP(aesenc
),
3036 [0xdd] = AESNI_OP(aesenclast
),
3037 [0xde] = AESNI_OP(aesdec
),
3038 [0xdf] = AESNI_OP(aesdeclast
),
3041 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
3042 [0x08] = SSE41_OP(roundps
),
3043 [0x09] = SSE41_OP(roundpd
),
3044 [0x0a] = SSE41_OP(roundss
),
3045 [0x0b] = SSE41_OP(roundsd
),
3046 [0x0c] = SSE41_OP(blendps
),
3047 [0x0d] = SSE41_OP(blendpd
),
3048 [0x0e] = SSE41_OP(pblendw
),
3049 [0x0f] = SSSE3_OP(palignr
),
3050 [0x14] = SSE41_SPECIAL
, /* pextrb */
3051 [0x15] = SSE41_SPECIAL
, /* pextrw */
3052 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3053 [0x17] = SSE41_SPECIAL
, /* extractps */
3054 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3055 [0x21] = SSE41_SPECIAL
, /* insertps */
3056 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3057 [0x40] = SSE41_OP(dpps
),
3058 [0x41] = SSE41_OP(dppd
),
3059 [0x42] = SSE41_OP(mpsadbw
),
3060 [0x44] = PCLMULQDQ_OP(pclmulqdq
),
3061 [0x60] = SSE42_OP(pcmpestrm
),
3062 [0x61] = SSE42_OP(pcmpestri
),
3063 [0x62] = SSE42_OP(pcmpistrm
),
3064 [0x63] = SSE42_OP(pcmpistri
),
3065 [0xdf] = AESNI_OP(aeskeygenassist
),
3068 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
3069 target_ulong pc_start
, int rex_r
)
3071 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3072 int modrm
, mod
, rm
, reg
;
3073 SSEFunc_0_epp sse_fn_epp
;
3074 SSEFunc_0_eppi sse_fn_eppi
;
3075 SSEFunc_0_ppi sse_fn_ppi
;
3076 SSEFunc_0_eppt sse_fn_eppt
;
3079 if (s
->prefix
& PREFIX_DATA
)
3081 else if (s
->prefix
& PREFIX_REPZ
)
3083 else if (s
->prefix
& PREFIX_REPNZ
)
3087 sse_fn_epp
= sse_op_table1
[b
][b1
];
3091 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3101 /* simple MMX/SSE operation */
3102 if (s
->flags
& HF_TS_MASK
) {
3103 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3106 if (s
->flags
& HF_EM_MASK
) {
3108 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3111 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3112 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3115 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3118 gen_helper_emms(cpu_env
);
3123 gen_helper_emms(cpu_env
);
3126 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3127 the static cpu state) */
3129 gen_helper_enter_mmx(cpu_env
);
3132 modrm
= cpu_ldub_code(env
, s
->pc
++);
3133 reg
= ((modrm
>> 3) & 7);
3136 mod
= (modrm
>> 6) & 3;
3137 if (sse_fn_epp
== SSE_SPECIAL
) {
3140 case 0x0e7: /* movntq */
3143 gen_lea_modrm(env
, s
, modrm
);
3144 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3146 case 0x1e7: /* movntdq */
3147 case 0x02b: /* movntps */
3148 case 0x12b: /* movntps */
3151 gen_lea_modrm(env
, s
, modrm
);
3152 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3154 case 0x3f0: /* lddqu */
3157 gen_lea_modrm(env
, s
, modrm
);
3158 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3160 case 0x22b: /* movntss */
3161 case 0x32b: /* movntsd */
3164 gen_lea_modrm(env
, s
, modrm
);
3166 gen_stq_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3168 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3169 xmm_regs
[reg
].XMM_L(0)));
3170 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3173 case 0x6e: /* movd mm, ea */
3174 #ifdef TARGET_X86_64
3175 if (s
->dflag
== 2) {
3176 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3177 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3181 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3182 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3183 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3184 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3185 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3188 case 0x16e: /* movd xmm, ea */
3189 #ifdef TARGET_X86_64
3190 if (s
->dflag
== 2) {
3191 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3192 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3193 offsetof(CPUX86State
,xmm_regs
[reg
]));
3194 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3198 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3199 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3200 offsetof(CPUX86State
,xmm_regs
[reg
]));
3201 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3202 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3205 case 0x6f: /* movq mm, ea */
3207 gen_lea_modrm(env
, s
, modrm
);
3208 gen_ldq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3211 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3212 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3213 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3214 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3217 case 0x010: /* movups */
3218 case 0x110: /* movupd */
3219 case 0x028: /* movaps */
3220 case 0x128: /* movapd */
3221 case 0x16f: /* movdqa xmm, ea */
3222 case 0x26f: /* movdqu xmm, ea */
3224 gen_lea_modrm(env
, s
, modrm
);
3225 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3227 rm
= (modrm
& 7) | REX_B(s
);
3228 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3229 offsetof(CPUX86State
,xmm_regs
[rm
]));
3232 case 0x210: /* movss xmm, ea */
3234 gen_lea_modrm(env
, s
, modrm
);
3235 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3236 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3237 tcg_gen_movi_tl(cpu_T
[0], 0);
3238 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3239 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3240 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3242 rm
= (modrm
& 7) | REX_B(s
);
3243 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3244 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3247 case 0x310: /* movsd xmm, ea */
3249 gen_lea_modrm(env
, s
, modrm
);
3250 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3251 xmm_regs
[reg
].XMM_Q(0)));
3252 tcg_gen_movi_tl(cpu_T
[0], 0);
3253 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3254 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3256 rm
= (modrm
& 7) | REX_B(s
);
3257 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3258 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3261 case 0x012: /* movlps */
3262 case 0x112: /* movlpd */
3264 gen_lea_modrm(env
, s
, modrm
);
3265 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3266 xmm_regs
[reg
].XMM_Q(0)));
3269 rm
= (modrm
& 7) | REX_B(s
);
3270 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3271 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3274 case 0x212: /* movsldup */
3276 gen_lea_modrm(env
, s
, modrm
);
3277 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3279 rm
= (modrm
& 7) | REX_B(s
);
3280 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3281 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3282 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3283 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3285 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3286 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3287 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3288 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3290 case 0x312: /* movddup */
3292 gen_lea_modrm(env
, s
, modrm
);
3293 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3294 xmm_regs
[reg
].XMM_Q(0)));
3296 rm
= (modrm
& 7) | REX_B(s
);
3297 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3298 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3300 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3301 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3303 case 0x016: /* movhps */
3304 case 0x116: /* movhpd */
3306 gen_lea_modrm(env
, s
, modrm
);
3307 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3308 xmm_regs
[reg
].XMM_Q(1)));
3311 rm
= (modrm
& 7) | REX_B(s
);
3312 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3313 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3316 case 0x216: /* movshdup */
3318 gen_lea_modrm(env
, s
, modrm
);
3319 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3321 rm
= (modrm
& 7) | REX_B(s
);
3322 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3323 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3324 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3325 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3327 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3328 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3329 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3330 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3335 int bit_index
, field_length
;
3337 if (b1
== 1 && reg
!= 0)
3339 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3340 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3341 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3342 offsetof(CPUX86State
,xmm_regs
[reg
]));
3344 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3345 tcg_const_i32(bit_index
),
3346 tcg_const_i32(field_length
));
3348 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3349 tcg_const_i32(bit_index
),
3350 tcg_const_i32(field_length
));
3353 case 0x7e: /* movd ea, mm */
3354 #ifdef TARGET_X86_64
3355 if (s
->dflag
== 2) {
3356 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3357 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3358 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3362 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3363 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3364 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3367 case 0x17e: /* movd ea, xmm */
3368 #ifdef TARGET_X86_64
3369 if (s
->dflag
== 2) {
3370 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3371 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3372 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3376 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3377 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3378 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3381 case 0x27e: /* movq xmm, ea */
3383 gen_lea_modrm(env
, s
, modrm
);
3384 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3385 xmm_regs
[reg
].XMM_Q(0)));
3387 rm
= (modrm
& 7) | REX_B(s
);
3388 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3389 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3391 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3393 case 0x7f: /* movq ea, mm */
3395 gen_lea_modrm(env
, s
, modrm
);
3396 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3399 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3400 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3403 case 0x011: /* movups */
3404 case 0x111: /* movupd */
3405 case 0x029: /* movaps */
3406 case 0x129: /* movapd */
3407 case 0x17f: /* movdqa ea, xmm */
3408 case 0x27f: /* movdqu ea, xmm */
3410 gen_lea_modrm(env
, s
, modrm
);
3411 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3413 rm
= (modrm
& 7) | REX_B(s
);
3414 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3415 offsetof(CPUX86State
,xmm_regs
[reg
]));
3418 case 0x211: /* movss ea, xmm */
3420 gen_lea_modrm(env
, s
, modrm
);
3421 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3422 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3424 rm
= (modrm
& 7) | REX_B(s
);
3425 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3426 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3429 case 0x311: /* movsd ea, xmm */
3431 gen_lea_modrm(env
, s
, modrm
);
3432 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3433 xmm_regs
[reg
].XMM_Q(0)));
3435 rm
= (modrm
& 7) | REX_B(s
);
3436 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3437 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3440 case 0x013: /* movlps */
3441 case 0x113: /* movlpd */
3443 gen_lea_modrm(env
, s
, modrm
);
3444 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3445 xmm_regs
[reg
].XMM_Q(0)));
3450 case 0x017: /* movhps */
3451 case 0x117: /* movhpd */
3453 gen_lea_modrm(env
, s
, modrm
);
3454 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3455 xmm_regs
[reg
].XMM_Q(1)));
3460 case 0x71: /* shift mm, im */
3463 case 0x171: /* shift xmm, im */
3469 val
= cpu_ldub_code(env
, s
->pc
++);
3471 tcg_gen_movi_tl(cpu_T
[0], val
);
3472 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3473 tcg_gen_movi_tl(cpu_T
[0], 0);
3474 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3475 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3477 tcg_gen_movi_tl(cpu_T
[0], val
);
3478 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3479 tcg_gen_movi_tl(cpu_T
[0], 0);
3480 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3481 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3483 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3484 (((modrm
>> 3)) & 7)][b1
];
3489 rm
= (modrm
& 7) | REX_B(s
);
3490 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3493 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3495 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3496 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3497 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3499 case 0x050: /* movmskps */
3500 rm
= (modrm
& 7) | REX_B(s
);
3501 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3502 offsetof(CPUX86State
,xmm_regs
[rm
]));
3503 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3504 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3506 case 0x150: /* movmskpd */
3507 rm
= (modrm
& 7) | REX_B(s
);
3508 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3509 offsetof(CPUX86State
,xmm_regs
[rm
]));
3510 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3511 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3513 case 0x02a: /* cvtpi2ps */
3514 case 0x12a: /* cvtpi2pd */
3515 gen_helper_enter_mmx(cpu_env
);
3517 gen_lea_modrm(env
, s
, modrm
);
3518 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3519 gen_ldq_env_A0(s
, op2_offset
);
3522 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3524 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3525 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3526 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3529 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3533 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3537 case 0x22a: /* cvtsi2ss */
3538 case 0x32a: /* cvtsi2sd */
3539 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
3540 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3541 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3542 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3544 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3545 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3546 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3548 #ifdef TARGET_X86_64
3549 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3550 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3556 case 0x02c: /* cvttps2pi */
3557 case 0x12c: /* cvttpd2pi */
3558 case 0x02d: /* cvtps2pi */
3559 case 0x12d: /* cvtpd2pi */
3560 gen_helper_enter_mmx(cpu_env
);
3562 gen_lea_modrm(env
, s
, modrm
);
3563 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3564 gen_ldo_env_A0(s
, op2_offset
);
3566 rm
= (modrm
& 7) | REX_B(s
);
3567 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3569 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3570 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3571 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3574 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3577 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3580 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3583 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3587 case 0x22c: /* cvttss2si */
3588 case 0x32c: /* cvttsd2si */
3589 case 0x22d: /* cvtss2si */
3590 case 0x32d: /* cvtsd2si */
3591 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
3593 gen_lea_modrm(env
, s
, modrm
);
3595 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_Q(0)));
3597 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3598 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3600 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3602 rm
= (modrm
& 7) | REX_B(s
);
3603 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3605 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3607 SSEFunc_i_ep sse_fn_i_ep
=
3608 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3609 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3610 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3612 #ifdef TARGET_X86_64
3613 SSEFunc_l_ep sse_fn_l_ep
=
3614 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3615 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3620 gen_op_mov_reg_T0(ot
, reg
);
3622 case 0xc4: /* pinsrw */
3625 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
3626 val
= cpu_ldub_code(env
, s
->pc
++);
3629 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3630 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3633 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3634 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3637 case 0xc5: /* pextrw */
3641 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
3642 val
= cpu_ldub_code(env
, s
->pc
++);
3645 rm
= (modrm
& 7) | REX_B(s
);
3646 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3647 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3651 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3652 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3654 reg
= ((modrm
>> 3) & 7) | rex_r
;
3655 gen_op_mov_reg_T0(ot
, reg
);
3657 case 0x1d6: /* movq ea, xmm */
3659 gen_lea_modrm(env
, s
, modrm
);
3660 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3661 xmm_regs
[reg
].XMM_Q(0)));
3663 rm
= (modrm
& 7) | REX_B(s
);
3664 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3665 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3666 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3669 case 0x2d6: /* movq2dq */
3670 gen_helper_enter_mmx(cpu_env
);
3672 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3673 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3674 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3676 case 0x3d6: /* movdq2q */
3677 gen_helper_enter_mmx(cpu_env
);
3678 rm
= (modrm
& 7) | REX_B(s
);
3679 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3680 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3682 case 0xd7: /* pmovmskb */
3687 rm
= (modrm
& 7) | REX_B(s
);
3688 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3689 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3692 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3693 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3695 reg
= ((modrm
>> 3) & 7) | rex_r
;
3696 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3702 if ((b
& 0xf0) == 0xf0) {
3705 modrm
= cpu_ldub_code(env
, s
->pc
++);
3707 reg
= ((modrm
>> 3) & 7) | rex_r
;
3708 mod
= (modrm
>> 6) & 3;
3713 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3717 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3721 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3723 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3725 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3726 gen_lea_modrm(env
, s
, modrm
);
3728 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3729 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3730 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3731 gen_ldq_env_A0(s
, op2_offset
+
3732 offsetof(XMMReg
, XMM_Q(0)));
3734 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3735 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3736 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
3737 s
->mem_index
, MO_LEUL
);
3738 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3739 offsetof(XMMReg
, XMM_L(0)));
3741 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3742 tcg_gen_qemu_ld_tl(cpu_tmp0
, cpu_A0
,
3743 s
->mem_index
, MO_LEUW
);
3744 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3745 offsetof(XMMReg
, XMM_W(0)));
3747 case 0x2a: /* movntqda */
3748 gen_ldo_env_A0(s
, op1_offset
);
3751 gen_ldo_env_A0(s
, op2_offset
);
3755 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3757 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3759 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3760 gen_lea_modrm(env
, s
, modrm
);
3761 gen_ldq_env_A0(s
, op2_offset
);
3764 if (sse_fn_epp
== SSE_SPECIAL
) {
3768 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3769 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3770 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3773 set_cc_op(s
, CC_OP_EFLAGS
);
3780 /* Various integer extensions at 0f 38 f[0-f]. */
3781 b
= modrm
| (b1
<< 8);
3782 modrm
= cpu_ldub_code(env
, s
->pc
++);
3783 reg
= ((modrm
>> 3) & 7) | rex_r
;
3786 case 0x3f0: /* crc32 Gd,Eb */
3787 case 0x3f1: /* crc32 Gd,Ey */
3789 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
)) {
3792 if ((b
& 0xff) == 0xf0) {
3794 } else if (s
->dflag
!= 2) {
3795 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3800 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[reg
]);
3801 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3802 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3803 cpu_T
[0], tcg_const_i32(8 << ot
));
3805 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
3806 gen_op_mov_reg_T0(ot
, reg
);
3809 case 0x1f0: /* crc32 or movbe */
3811 /* For these insns, the f3 prefix is supposed to have priority
3812 over the 66 prefix, but that's not what we implement above
3814 if (s
->prefix
& PREFIX_REPNZ
) {
3818 case 0x0f0: /* movbe Gy,My */
3819 case 0x0f1: /* movbe My,Gy */
3820 if (!(s
->cpuid_ext_features
& CPUID_EXT_MOVBE
)) {
3823 if (s
->dflag
!= 2) {
3824 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3829 gen_lea_modrm(env
, s
, modrm
);
3831 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
3832 s
->mem_index
, ot
| MO_BE
);
3833 gen_op_mov_reg_T0(ot
, reg
);
3835 tcg_gen_qemu_st_tl(cpu_regs
[reg
], cpu_A0
,
3836 s
->mem_index
, ot
| MO_BE
);
3840 case 0x0f2: /* andn Gy, By, Ey */
3841 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3842 || !(s
->prefix
& PREFIX_VEX
)
3846 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3847 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3848 tcg_gen_andc_tl(cpu_T
[0], cpu_regs
[s
->vex_v
], cpu_T
[0]);
3849 gen_op_mov_reg_T0(ot
, reg
);
3850 gen_op_update1_cc();
3851 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3854 case 0x0f7: /* bextr Gy, Ey, By */
3855 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3856 || !(s
->prefix
& PREFIX_VEX
)
3860 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3864 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3865 /* Extract START, and shift the operand.
3866 Shifts larger than operand size get zeros. */
3867 tcg_gen_ext8u_tl(cpu_A0
, cpu_regs
[s
->vex_v
]);
3868 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3870 bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3871 zero
= tcg_const_tl(0);
3872 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_T
[0], cpu_A0
, bound
,
3874 tcg_temp_free(zero
);
3876 /* Extract the LEN into a mask. Lengths larger than
3877 operand size get all ones. */
3878 tcg_gen_shri_tl(cpu_A0
, cpu_regs
[s
->vex_v
], 8);
3879 tcg_gen_ext8u_tl(cpu_A0
, cpu_A0
);
3880 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_A0
, cpu_A0
, bound
,
3882 tcg_temp_free(bound
);
3883 tcg_gen_movi_tl(cpu_T
[1], 1);
3884 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_A0
);
3885 tcg_gen_subi_tl(cpu_T
[1], cpu_T
[1], 1);
3886 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3888 gen_op_mov_reg_T0(ot
, reg
);
3889 gen_op_update1_cc();
3890 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3894 case 0x0f5: /* bzhi Gy, Ey, By */
3895 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3896 || !(s
->prefix
& PREFIX_VEX
)
3900 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3901 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3902 tcg_gen_ext8u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3904 TCGv bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3905 /* Note that since we're using BMILG (in order to get O
3906 cleared) we need to store the inverse into C. */
3907 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_cc_src
,
3909 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_T
[1], cpu_T
[1],
3910 bound
, bound
, cpu_T
[1]);
3911 tcg_temp_free(bound
);
3913 tcg_gen_movi_tl(cpu_A0
, -1);
3914 tcg_gen_shl_tl(cpu_A0
, cpu_A0
, cpu_T
[1]);
3915 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3916 gen_op_mov_reg_T0(ot
, reg
);
3917 gen_op_update1_cc();
3918 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
3921 case 0x3f6: /* mulx By, Gy, rdx, Ey */
3922 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3923 || !(s
->prefix
& PREFIX_VEX
)
3927 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3928 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3931 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3932 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EDX
]);
3933 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
3934 cpu_tmp2_i32
, cpu_tmp3_i32
);
3935 tcg_gen_extu_i32_tl(cpu_regs
[s
->vex_v
], cpu_tmp2_i32
);
3936 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp3_i32
);
3938 #ifdef TARGET_X86_64
3940 tcg_gen_mulu2_i64(cpu_regs
[s
->vex_v
], cpu_regs
[reg
],
3941 cpu_T
[0], cpu_regs
[R_EDX
]);
3947 case 0x3f5: /* pdep Gy, By, Ey */
3948 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3949 || !(s
->prefix
& PREFIX_VEX
)
3953 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3954 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3955 /* Note that by zero-extending the mask operand, we
3956 automatically handle zero-extending the result. */
3957 if (s
->dflag
== 2) {
3958 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3960 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3962 gen_helper_pdep(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3965 case 0x2f5: /* pext Gy, By, Ey */
3966 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3967 || !(s
->prefix
& PREFIX_VEX
)
3971 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3972 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3973 /* Note that by zero-extending the mask operand, we
3974 automatically handle zero-extending the result. */
3975 if (s
->dflag
== 2) {
3976 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3978 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3980 gen_helper_pext(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3983 case 0x1f6: /* adcx Gy, Ey */
3984 case 0x2f6: /* adox Gy, Ey */
3985 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_ADX
)) {
3988 TCGv carry_in
, carry_out
, zero
;
3991 ot
= (s
->dflag
== 2 ? MO_64
: MO_32
);
3992 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3994 /* Re-use the carry-out from a previous round. */
3995 TCGV_UNUSED(carry_in
);
3996 carry_out
= (b
== 0x1f6 ? cpu_cc_dst
: cpu_cc_src2
);
4000 carry_in
= cpu_cc_dst
;
4001 end_op
= CC_OP_ADCX
;
4003 end_op
= CC_OP_ADCOX
;
4008 end_op
= CC_OP_ADCOX
;
4010 carry_in
= cpu_cc_src2
;
4011 end_op
= CC_OP_ADOX
;
4015 end_op
= CC_OP_ADCOX
;
4016 carry_in
= carry_out
;
4019 end_op
= (b
== 0x1f6 ? CC_OP_ADCX
: CC_OP_ADOX
);
4022 /* If we can't reuse carry-out, get it out of EFLAGS. */
4023 if (TCGV_IS_UNUSED(carry_in
)) {
4024 if (s
->cc_op
!= CC_OP_ADCX
&& s
->cc_op
!= CC_OP_ADOX
) {
4025 gen_compute_eflags(s
);
4027 carry_in
= cpu_tmp0
;
4028 tcg_gen_shri_tl(carry_in
, cpu_cc_src
,
4029 ctz32(b
== 0x1f6 ? CC_C
: CC_O
));
4030 tcg_gen_andi_tl(carry_in
, carry_in
, 1);
4034 #ifdef TARGET_X86_64
4036 /* If we know TL is 64-bit, and we want a 32-bit
4037 result, just do everything in 64-bit arithmetic. */
4038 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_regs
[reg
]);
4039 tcg_gen_ext32u_i64(cpu_T
[0], cpu_T
[0]);
4040 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_regs
[reg
]);
4041 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], carry_in
);
4042 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_T
[0]);
4043 tcg_gen_shri_i64(carry_out
, cpu_T
[0], 32);
4047 /* Otherwise compute the carry-out in two steps. */
4048 zero
= tcg_const_tl(0);
4049 tcg_gen_add2_tl(cpu_T
[0], carry_out
,
4052 tcg_gen_add2_tl(cpu_regs
[reg
], carry_out
,
4053 cpu_regs
[reg
], carry_out
,
4055 tcg_temp_free(zero
);
4058 set_cc_op(s
, end_op
);
4062 case 0x1f7: /* shlx Gy, Ey, By */
4063 case 0x2f7: /* sarx Gy, Ey, By */
4064 case 0x3f7: /* shrx Gy, Ey, By */
4065 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4066 || !(s
->prefix
& PREFIX_VEX
)
4070 ot
= (s
->dflag
== 2 ? MO_64
: MO_32
);
4071 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4073 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 63);
4075 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 31);
4078 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4079 } else if (b
== 0x2f7) {
4081 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4083 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4086 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4088 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4090 gen_op_mov_reg_T0(ot
, reg
);
4096 case 0x3f3: /* Group 17 */
4097 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
4098 || !(s
->prefix
& PREFIX_VEX
)
4102 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
4103 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4106 case 1: /* blsr By,Ey */
4107 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[0]);
4108 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4109 gen_op_mov_reg_T0(ot
, s
->vex_v
);
4110 gen_op_update2_cc();
4111 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4114 case 2: /* blsmsk By,Ey */
4115 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4116 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4117 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4118 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4119 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4122 case 3: /* blsi By, Ey */
4123 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4124 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4125 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4126 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4127 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4143 modrm
= cpu_ldub_code(env
, s
->pc
++);
4145 reg
= ((modrm
>> 3) & 7) | rex_r
;
4146 mod
= (modrm
>> 6) & 3;
4151 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4155 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4158 if (sse_fn_eppi
== SSE_SPECIAL
) {
4159 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
4160 rm
= (modrm
& 7) | REX_B(s
);
4162 gen_lea_modrm(env
, s
, modrm
);
4163 reg
= ((modrm
>> 3) & 7) | rex_r
;
4164 val
= cpu_ldub_code(env
, s
->pc
++);
4166 case 0x14: /* pextrb */
4167 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4168 xmm_regs
[reg
].XMM_B(val
& 15)));
4170 gen_op_mov_reg_T0(ot
, rm
);
4172 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4173 s
->mem_index
, MO_UB
);
4176 case 0x15: /* pextrw */
4177 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4178 xmm_regs
[reg
].XMM_W(val
& 7)));
4180 gen_op_mov_reg_T0(ot
, rm
);
4182 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4183 s
->mem_index
, MO_LEUW
);
4187 if (ot
== MO_32
) { /* pextrd */
4188 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4189 offsetof(CPUX86State
,
4190 xmm_regs
[reg
].XMM_L(val
& 3)));
4192 tcg_gen_extu_i32_tl(cpu_regs
[rm
], cpu_tmp2_i32
);
4194 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
4195 s
->mem_index
, MO_LEUL
);
4197 } else { /* pextrq */
4198 #ifdef TARGET_X86_64
4199 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4200 offsetof(CPUX86State
,
4201 xmm_regs
[reg
].XMM_Q(val
& 1)));
4203 tcg_gen_mov_i64(cpu_regs
[rm
], cpu_tmp1_i64
);
4205 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
4206 s
->mem_index
, MO_LEQ
);
4213 case 0x17: /* extractps */
4214 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4215 xmm_regs
[reg
].XMM_L(val
& 3)));
4217 gen_op_mov_reg_T0(ot
, rm
);
4219 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4220 s
->mem_index
, MO_LEUL
);
4223 case 0x20: /* pinsrb */
4225 gen_op_mov_TN_reg(MO_32
, 0, rm
);
4227 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
4228 s
->mem_index
, MO_UB
);
4230 tcg_gen_st8_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4231 xmm_regs
[reg
].XMM_B(val
& 15)));
4233 case 0x21: /* insertps */
4235 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4236 offsetof(CPUX86State
,xmm_regs
[rm
]
4237 .XMM_L((val
>> 6) & 3)));
4239 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4240 s
->mem_index
, MO_LEUL
);
4242 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4243 offsetof(CPUX86State
,xmm_regs
[reg
]
4244 .XMM_L((val
>> 4) & 3)));
4246 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4247 cpu_env
, offsetof(CPUX86State
,
4248 xmm_regs
[reg
].XMM_L(0)));
4250 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4251 cpu_env
, offsetof(CPUX86State
,
4252 xmm_regs
[reg
].XMM_L(1)));
4254 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4255 cpu_env
, offsetof(CPUX86State
,
4256 xmm_regs
[reg
].XMM_L(2)));
4258 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4259 cpu_env
, offsetof(CPUX86State
,
4260 xmm_regs
[reg
].XMM_L(3)));
4263 if (ot
== MO_32
) { /* pinsrd */
4265 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[rm
]);
4267 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4268 s
->mem_index
, MO_LEUL
);
4270 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4271 offsetof(CPUX86State
,
4272 xmm_regs
[reg
].XMM_L(val
& 3)));
4273 } else { /* pinsrq */
4274 #ifdef TARGET_X86_64
4276 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4278 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
4279 s
->mem_index
, MO_LEQ
);
4281 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4282 offsetof(CPUX86State
,
4283 xmm_regs
[reg
].XMM_Q(val
& 1)));
4294 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4296 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4298 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4299 gen_lea_modrm(env
, s
, modrm
);
4300 gen_ldo_env_A0(s
, op2_offset
);
4303 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4305 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4307 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4308 gen_lea_modrm(env
, s
, modrm
);
4309 gen_ldq_env_A0(s
, op2_offset
);
4312 val
= cpu_ldub_code(env
, s
->pc
++);
4314 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4315 set_cc_op(s
, CC_OP_EFLAGS
);
4318 /* The helper must use entire 64-bit gp registers */
4322 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4323 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4324 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4328 /* Various integer extensions at 0f 3a f[0-f]. */
4329 b
= modrm
| (b1
<< 8);
4330 modrm
= cpu_ldub_code(env
, s
->pc
++);
4331 reg
= ((modrm
>> 3) & 7) | rex_r
;
4334 case 0x3f0: /* rorx Gy,Ey, Ib */
4335 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4336 || !(s
->prefix
& PREFIX_VEX
)
4340 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
4341 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4342 b
= cpu_ldub_code(env
, s
->pc
++);
4344 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], b
& 63);
4346 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4347 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, b
& 31);
4348 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4350 gen_op_mov_reg_T0(ot
, reg
);
4362 /* generic MMX or SSE operation */
4364 case 0x70: /* pshufx insn */
4365 case 0xc6: /* pshufx insn */
4366 case 0xc2: /* compare insns */
4373 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4375 gen_lea_modrm(env
, s
, modrm
);
4376 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4377 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4379 /* specific case for SSE single instructions */
4382 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
4383 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4386 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
4390 gen_ldo_env_A0(s
, op2_offset
);
4393 rm
= (modrm
& 7) | REX_B(s
);
4394 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4397 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4399 gen_lea_modrm(env
, s
, modrm
);
4400 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4401 gen_ldq_env_A0(s
, op2_offset
);
4404 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4408 case 0x0f: /* 3DNow! data insns */
4409 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4411 val
= cpu_ldub_code(env
, s
->pc
++);
4412 sse_fn_epp
= sse_op_table5
[val
];
4416 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4417 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4418 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4420 case 0x70: /* pshufx insn */
4421 case 0xc6: /* pshufx insn */
4422 val
= cpu_ldub_code(env
, s
->pc
++);
4423 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4424 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4425 /* XXX: introduce a new table? */
4426 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4427 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4431 val
= cpu_ldub_code(env
, s
->pc
++);
4434 sse_fn_epp
= sse_op_table4
[val
][b1
];
4436 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4437 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4438 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4441 /* maskmov : we must prepare A0 */
4444 #ifdef TARGET_X86_64
4445 if (s
->aflag
== 2) {
4446 gen_op_movq_A0_reg(R_EDI
);
4450 gen_op_movl_A0_reg(R_EDI
);
4452 gen_op_andl_A0_ffff();
4454 gen_add_A0_ds_seg(s
);
4456 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4457 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4458 /* XXX: introduce a new table? */
4459 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4460 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4463 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4464 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4465 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4468 if (b
== 0x2e || b
== 0x2f) {
4469 set_cc_op(s
, CC_OP_EFLAGS
);
4474 /* convert one instruction. s->is_jmp is set if the translation must
4475 be stopped. Return the next pc value */
4476 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4477 target_ulong pc_start
)
4479 int b
, prefixes
, aflag
, dflag
;
4481 int modrm
, reg
, rm
, mod
, op
, opreg
, val
;
4482 target_ulong next_eip
, tval
;
4485 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4486 tcg_gen_debug_insn_start(pc_start
);
4493 #ifdef TARGET_X86_64
4498 s
->rip_offset
= 0; /* for relative ip address */
4502 b
= cpu_ldub_code(env
, s
->pc
);
4504 /* Collect prefixes. */
4507 prefixes
|= PREFIX_REPZ
;
4510 prefixes
|= PREFIX_REPNZ
;
4513 prefixes
|= PREFIX_LOCK
;
4534 prefixes
|= PREFIX_DATA
;
4537 prefixes
|= PREFIX_ADR
;
4539 #ifdef TARGET_X86_64
4543 rex_w
= (b
>> 3) & 1;
4544 rex_r
= (b
& 0x4) << 1;
4545 s
->rex_x
= (b
& 0x2) << 2;
4546 REX_B(s
) = (b
& 0x1) << 3;
4547 x86_64_hregs
= 1; /* select uniform byte register addressing */
4552 case 0xc5: /* 2-byte VEX */
4553 case 0xc4: /* 3-byte VEX */
4554 /* VEX prefixes cannot be used except in 32-bit mode.
4555 Otherwise the instruction is LES or LDS. */
4556 if (s
->code32
&& !s
->vm86
) {
4557 static const int pp_prefix
[4] = {
4558 0, PREFIX_DATA
, PREFIX_REPZ
, PREFIX_REPNZ
4560 int vex3
, vex2
= cpu_ldub_code(env
, s
->pc
);
4562 if (!CODE64(s
) && (vex2
& 0xc0) != 0xc0) {
4563 /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
4564 otherwise the instruction is LES or LDS. */
4569 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
4570 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
4571 | PREFIX_LOCK
| PREFIX_DATA
)) {
4574 #ifdef TARGET_X86_64
4579 rex_r
= (~vex2
>> 4) & 8;
4582 b
= cpu_ldub_code(env
, s
->pc
++);
4584 #ifdef TARGET_X86_64
4585 s
->rex_x
= (~vex2
>> 3) & 8;
4586 s
->rex_b
= (~vex2
>> 2) & 8;
4588 vex3
= cpu_ldub_code(env
, s
->pc
++);
4589 rex_w
= (vex3
>> 7) & 1;
4590 switch (vex2
& 0x1f) {
4591 case 0x01: /* Implied 0f leading opcode bytes. */
4592 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4594 case 0x02: /* Implied 0f 38 leading opcode bytes. */
4597 case 0x03: /* Implied 0f 3a leading opcode bytes. */
4600 default: /* Reserved for future use. */
4604 s
->vex_v
= (~vex3
>> 3) & 0xf;
4605 s
->vex_l
= (vex3
>> 2) & 1;
4606 prefixes
|= pp_prefix
[vex3
& 3] | PREFIX_VEX
;
4611 /* Post-process prefixes. */
4613 /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
4614 data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
4615 over 0x66 if both are present. */
4616 dflag
= (rex_w
> 0 ? 2 : prefixes
& PREFIX_DATA
? 0 : 1);
4617 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
4618 aflag
= (prefixes
& PREFIX_ADR
? 1 : 2);
4620 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
4622 if (prefixes
& PREFIX_DATA
) {
4625 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
4627 if (prefixes
& PREFIX_ADR
) {
4632 s
->prefix
= prefixes
;
4636 /* lock generation */
4637 if (prefixes
& PREFIX_LOCK
)
4640 /* now check op code */
4644 /**************************/
4645 /* extended op code */
4646 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4649 /**************************/
4670 case 0: /* OP Ev, Gv */
4671 modrm
= cpu_ldub_code(env
, s
->pc
++);
4672 reg
= ((modrm
>> 3) & 7) | rex_r
;
4673 mod
= (modrm
>> 6) & 3;
4674 rm
= (modrm
& 7) | REX_B(s
);
4676 gen_lea_modrm(env
, s
, modrm
);
4678 } else if (op
== OP_XORL
&& rm
== reg
) {
4680 /* xor reg, reg optimisation */
4681 set_cc_op(s
, CC_OP_CLR
);
4682 tcg_gen_movi_tl(cpu_T
[0], 0);
4683 gen_op_mov_reg_T0(ot
, reg
);
4688 gen_op_mov_TN_reg(ot
, 1, reg
);
4689 gen_op(s
, op
, ot
, opreg
);
4691 case 1: /* OP Gv, Ev */
4692 modrm
= cpu_ldub_code(env
, s
->pc
++);
4693 mod
= (modrm
>> 6) & 3;
4694 reg
= ((modrm
>> 3) & 7) | rex_r
;
4695 rm
= (modrm
& 7) | REX_B(s
);
4697 gen_lea_modrm(env
, s
, modrm
);
4698 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4699 } else if (op
== OP_XORL
&& rm
== reg
) {
4702 gen_op_mov_TN_reg(ot
, 1, rm
);
4704 gen_op(s
, op
, ot
, reg
);
4706 case 2: /* OP A, Iv */
4707 val
= insn_get(env
, s
, ot
);
4708 tcg_gen_movi_tl(cpu_T
[1], val
);
4709 gen_op(s
, op
, ot
, OR_EAX
);
4718 case 0x80: /* GRP1 */
4729 modrm
= cpu_ldub_code(env
, s
->pc
++);
4730 mod
= (modrm
>> 6) & 3;
4731 rm
= (modrm
& 7) | REX_B(s
);
4732 op
= (modrm
>> 3) & 7;
4738 s
->rip_offset
= insn_const_size(ot
);
4739 gen_lea_modrm(env
, s
, modrm
);
4750 val
= insn_get(env
, s
, ot
);
4753 val
= (int8_t)insn_get(env
, s
, MO_8
);
4756 tcg_gen_movi_tl(cpu_T
[1], val
);
4757 gen_op(s
, op
, ot
, opreg
);
4761 /**************************/
4762 /* inc, dec, and other misc arith */
4763 case 0x40 ... 0x47: /* inc Gv */
4764 ot
= dflag
? MO_32
: MO_16
;
4765 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4767 case 0x48 ... 0x4f: /* dec Gv */
4768 ot
= dflag
? MO_32
: MO_16
;
4769 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4771 case 0xf6: /* GRP3 */
4778 modrm
= cpu_ldub_code(env
, s
->pc
++);
4779 mod
= (modrm
>> 6) & 3;
4780 rm
= (modrm
& 7) | REX_B(s
);
4781 op
= (modrm
>> 3) & 7;
4784 s
->rip_offset
= insn_const_size(ot
);
4785 gen_lea_modrm(env
, s
, modrm
);
4786 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4788 gen_op_mov_TN_reg(ot
, 0, rm
);
4793 val
= insn_get(env
, s
, ot
);
4794 tcg_gen_movi_tl(cpu_T
[1], val
);
4795 gen_op_testl_T0_T1_cc();
4796 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4799 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4801 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4803 gen_op_mov_reg_T0(ot
, rm
);
4807 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4809 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4811 gen_op_mov_reg_T0(ot
, rm
);
4813 gen_op_update_neg_cc();
4814 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4819 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4820 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4821 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4822 /* XXX: use 32 bit mul which could be faster */
4823 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4824 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4825 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4826 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4827 set_cc_op(s
, CC_OP_MULB
);
4830 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4831 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4832 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4833 /* XXX: use 32 bit mul which could be faster */
4834 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4835 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4836 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4837 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4838 gen_op_mov_reg_T0(MO_16
, R_EDX
);
4839 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4840 set_cc_op(s
, CC_OP_MULW
);
4844 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4845 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4846 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4847 cpu_tmp2_i32
, cpu_tmp3_i32
);
4848 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4849 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4850 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4851 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4852 set_cc_op(s
, CC_OP_MULL
);
4854 #ifdef TARGET_X86_64
4856 tcg_gen_mulu2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4857 cpu_T
[0], cpu_regs
[R_EAX
]);
4858 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4859 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4860 set_cc_op(s
, CC_OP_MULQ
);
4868 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4869 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4870 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4871 /* XXX: use 32 bit mul which could be faster */
4872 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4873 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4874 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4875 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4876 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4877 set_cc_op(s
, CC_OP_MULB
);
4880 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4881 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4882 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4883 /* XXX: use 32 bit mul which could be faster */
4884 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4885 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4886 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4887 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4888 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4889 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4890 gen_op_mov_reg_T0(MO_16
, R_EDX
);
4891 set_cc_op(s
, CC_OP_MULW
);
4895 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4896 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4897 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4898 cpu_tmp2_i32
, cpu_tmp3_i32
);
4899 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4900 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4901 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
4902 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4903 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
4904 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
4905 set_cc_op(s
, CC_OP_MULL
);
4907 #ifdef TARGET_X86_64
4909 tcg_gen_muls2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4910 cpu_T
[0], cpu_regs
[R_EAX
]);
4911 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4912 tcg_gen_sari_tl(cpu_cc_src
, cpu_regs
[R_EAX
], 63);
4913 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_regs
[R_EDX
]);
4914 set_cc_op(s
, CC_OP_MULQ
);
4922 gen_jmp_im(pc_start
- s
->cs_base
);
4923 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4926 gen_jmp_im(pc_start
- s
->cs_base
);
4927 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4931 gen_jmp_im(pc_start
- s
->cs_base
);
4932 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4934 #ifdef TARGET_X86_64
4936 gen_jmp_im(pc_start
- s
->cs_base
);
4937 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4945 gen_jmp_im(pc_start
- s
->cs_base
);
4946 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4949 gen_jmp_im(pc_start
- s
->cs_base
);
4950 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4954 gen_jmp_im(pc_start
- s
->cs_base
);
4955 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4957 #ifdef TARGET_X86_64
4959 gen_jmp_im(pc_start
- s
->cs_base
);
4960 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4970 case 0xfe: /* GRP4 */
4971 case 0xff: /* GRP5 */
4977 modrm
= cpu_ldub_code(env
, s
->pc
++);
4978 mod
= (modrm
>> 6) & 3;
4979 rm
= (modrm
& 7) | REX_B(s
);
4980 op
= (modrm
>> 3) & 7;
4981 if (op
>= 2 && b
== 0xfe) {
4985 if (op
== 2 || op
== 4) {
4986 /* operand size for jumps is 64 bit */
4988 } else if (op
== 3 || op
== 5) {
4989 ot
= dflag
? MO_32
+ (rex_w
== 1) : MO_16
;
4990 } else if (op
== 6) {
4991 /* default push size is 64 bit */
4992 ot
= dflag
? MO_64
: MO_16
;
4996 gen_lea_modrm(env
, s
, modrm
);
4997 if (op
>= 2 && op
!= 3 && op
!= 5)
4998 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5000 gen_op_mov_TN_reg(ot
, 0, rm
);
5004 case 0: /* inc Ev */
5009 gen_inc(s
, ot
, opreg
, 1);
5011 case 1: /* dec Ev */
5016 gen_inc(s
, ot
, opreg
, -1);
5018 case 2: /* call Ev */
5019 /* XXX: optimize if memory (no 'and' is necessary) */
5021 gen_op_andl_T0_ffff();
5022 next_eip
= s
->pc
- s
->cs_base
;
5023 gen_movtl_T1_im(next_eip
);
5028 case 3: /* lcall Ev */
5029 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5030 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5031 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5033 if (s
->pe
&& !s
->vm86
) {
5034 gen_update_cc_op(s
);
5035 gen_jmp_im(pc_start
- s
->cs_base
);
5036 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5037 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5038 tcg_const_i32(dflag
),
5039 tcg_const_i32(s
->pc
- pc_start
));
5041 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5042 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5043 tcg_const_i32(dflag
),
5044 tcg_const_i32(s
->pc
- s
->cs_base
));
5048 case 4: /* jmp Ev */
5050 gen_op_andl_T0_ffff();
5054 case 5: /* ljmp Ev */
5055 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5056 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5057 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5059 if (s
->pe
&& !s
->vm86
) {
5060 gen_update_cc_op(s
);
5061 gen_jmp_im(pc_start
- s
->cs_base
);
5062 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5063 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5064 tcg_const_i32(s
->pc
- pc_start
));
5066 gen_op_movl_seg_T0_vm(R_CS
);
5067 gen_op_movl_T0_T1();
5072 case 6: /* push Ev */
5080 case 0x84: /* test Ev, Gv */
5087 modrm
= cpu_ldub_code(env
, s
->pc
++);
5088 reg
= ((modrm
>> 3) & 7) | rex_r
;
5090 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5091 gen_op_mov_TN_reg(ot
, 1, reg
);
5092 gen_op_testl_T0_T1_cc();
5093 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5096 case 0xa8: /* test eAX, Iv */
5102 val
= insn_get(env
, s
, ot
);
5104 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
5105 tcg_gen_movi_tl(cpu_T
[1], val
);
5106 gen_op_testl_T0_T1_cc();
5107 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5110 case 0x98: /* CWDE/CBW */
5111 #ifdef TARGET_X86_64
5113 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5114 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5115 gen_op_mov_reg_T0(MO_64
, R_EAX
);
5119 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5120 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5121 gen_op_mov_reg_T0(MO_32
, R_EAX
);
5123 gen_op_mov_TN_reg(MO_8
, 0, R_EAX
);
5124 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5125 gen_op_mov_reg_T0(MO_16
, R_EAX
);
5128 case 0x99: /* CDQ/CWD */
5129 #ifdef TARGET_X86_64
5131 gen_op_mov_TN_reg(MO_64
, 0, R_EAX
);
5132 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
5133 gen_op_mov_reg_T0(MO_64
, R_EDX
);
5137 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5138 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5139 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
5140 gen_op_mov_reg_T0(MO_32
, R_EDX
);
5142 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5143 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5144 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
5145 gen_op_mov_reg_T0(MO_16
, R_EDX
);
5148 case 0x1af: /* imul Gv, Ev */
5149 case 0x69: /* imul Gv, Ev, I */
5152 modrm
= cpu_ldub_code(env
, s
->pc
++);
5153 reg
= ((modrm
>> 3) & 7) | rex_r
;
5155 s
->rip_offset
= insn_const_size(ot
);
5158 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5160 val
= insn_get(env
, s
, ot
);
5161 tcg_gen_movi_tl(cpu_T
[1], val
);
5162 } else if (b
== 0x6b) {
5163 val
= (int8_t)insn_get(env
, s
, MO_8
);
5164 tcg_gen_movi_tl(cpu_T
[1], val
);
5166 gen_op_mov_TN_reg(ot
, 1, reg
);
5169 #ifdef TARGET_X86_64
5171 tcg_gen_muls2_i64(cpu_regs
[reg
], cpu_T
[1], cpu_T
[0], cpu_T
[1]);
5172 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5173 tcg_gen_sari_tl(cpu_cc_src
, cpu_cc_dst
, 63);
5174 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[1]);
5178 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5179 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5180 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
5181 cpu_tmp2_i32
, cpu_tmp3_i32
);
5182 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
5183 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
5184 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5185 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
5186 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
5189 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5190 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5191 /* XXX: use 32 bit mul which could be faster */
5192 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5193 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5194 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5195 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5196 gen_op_mov_reg_T0(ot
, reg
);
5199 set_cc_op(s
, CC_OP_MULB
+ ot
);
5202 case 0x1c1: /* xadd Ev, Gv */
5207 modrm
= cpu_ldub_code(env
, s
->pc
++);
5208 reg
= ((modrm
>> 3) & 7) | rex_r
;
5209 mod
= (modrm
>> 6) & 3;
5211 rm
= (modrm
& 7) | REX_B(s
);
5212 gen_op_mov_TN_reg(ot
, 0, reg
);
5213 gen_op_mov_TN_reg(ot
, 1, rm
);
5214 gen_op_addl_T0_T1();
5215 gen_op_mov_reg_T1(ot
, reg
);
5216 gen_op_mov_reg_T0(ot
, rm
);
5218 gen_lea_modrm(env
, s
, modrm
);
5219 gen_op_mov_TN_reg(ot
, 0, reg
);
5220 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5221 gen_op_addl_T0_T1();
5222 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5223 gen_op_mov_reg_T1(ot
, reg
);
5225 gen_op_update2_cc();
5226 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5229 case 0x1b1: /* cmpxchg Ev, Gv */
5232 TCGv t0
, t1
, t2
, a0
;
5238 modrm
= cpu_ldub_code(env
, s
->pc
++);
5239 reg
= ((modrm
>> 3) & 7) | rex_r
;
5240 mod
= (modrm
>> 6) & 3;
5241 t0
= tcg_temp_local_new();
5242 t1
= tcg_temp_local_new();
5243 t2
= tcg_temp_local_new();
5244 a0
= tcg_temp_local_new();
5245 gen_op_mov_v_reg(ot
, t1
, reg
);
5247 rm
= (modrm
& 7) | REX_B(s
);
5248 gen_op_mov_v_reg(ot
, t0
, rm
);
5250 gen_lea_modrm(env
, s
, modrm
);
5251 tcg_gen_mov_tl(a0
, cpu_A0
);
5252 gen_op_ld_v(s
, ot
, t0
, a0
);
5253 rm
= 0; /* avoid warning */
5255 label1
= gen_new_label();
5256 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5259 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5260 label2
= gen_new_label();
5262 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5264 gen_set_label(label1
);
5265 gen_op_mov_reg_v(ot
, rm
, t1
);
5267 /* perform no-op store cycle like physical cpu; must be
5268 before changing accumulator to ensure idempotency if
5269 the store faults and the instruction is restarted */
5270 gen_op_st_v(s
, ot
, t0
, a0
);
5271 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5273 gen_set_label(label1
);
5274 gen_op_st_v(s
, ot
, t1
, a0
);
5276 gen_set_label(label2
);
5277 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5278 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5279 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5280 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5287 case 0x1c7: /* cmpxchg8b */
5288 modrm
= cpu_ldub_code(env
, s
->pc
++);
5289 mod
= (modrm
>> 6) & 3;
5290 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5292 #ifdef TARGET_X86_64
5294 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5296 gen_jmp_im(pc_start
- s
->cs_base
);
5297 gen_update_cc_op(s
);
5298 gen_lea_modrm(env
, s
, modrm
);
5299 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5303 if (!(s
->cpuid_features
& CPUID_CX8
))
5305 gen_jmp_im(pc_start
- s
->cs_base
);
5306 gen_update_cc_op(s
);
5307 gen_lea_modrm(env
, s
, modrm
);
5308 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5310 set_cc_op(s
, CC_OP_EFLAGS
);
5313 /**************************/
5315 case 0x50 ... 0x57: /* push */
5316 gen_op_mov_TN_reg(MO_32
, 0, (b
& 7) | REX_B(s
));
5319 case 0x58 ... 0x5f: /* pop */
5321 ot
= dflag
? MO_64
: MO_16
;
5326 /* NOTE: order is important for pop %sp */
5328 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
5330 case 0x60: /* pusha */
5335 case 0x61: /* popa */
5340 case 0x68: /* push Iv */
5343 ot
= dflag
? MO_64
: MO_16
;
5348 val
= insn_get(env
, s
, ot
);
5350 val
= (int8_t)insn_get(env
, s
, MO_8
);
5351 tcg_gen_movi_tl(cpu_T
[0], val
);
5354 case 0x8f: /* pop Ev */
5356 ot
= dflag
? MO_64
: MO_16
;
5360 modrm
= cpu_ldub_code(env
, s
->pc
++);
5361 mod
= (modrm
>> 6) & 3;
5364 /* NOTE: order is important for pop %sp */
5366 rm
= (modrm
& 7) | REX_B(s
);
5367 gen_op_mov_reg_T0(ot
, rm
);
5369 /* NOTE: order is important too for MMU exceptions */
5370 s
->popl_esp_hack
= 1 << ot
;
5371 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5372 s
->popl_esp_hack
= 0;
5376 case 0xc8: /* enter */
5379 val
= cpu_lduw_code(env
, s
->pc
);
5381 level
= cpu_ldub_code(env
, s
->pc
++);
5382 gen_enter(s
, val
, level
);
5385 case 0xc9: /* leave */
5386 /* XXX: exception not precise (ESP is updated before potential exception) */
5388 gen_op_mov_TN_reg(MO_64
, 0, R_EBP
);
5389 gen_op_mov_reg_T0(MO_64
, R_ESP
);
5390 } else if (s
->ss32
) {
5391 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
5392 gen_op_mov_reg_T0(MO_32
, R_ESP
);
5394 gen_op_mov_TN_reg(MO_16
, 0, R_EBP
);
5395 gen_op_mov_reg_T0(MO_16
, R_ESP
);
5399 ot
= dflag
? MO_64
: MO_16
;
5403 gen_op_mov_reg_T0(ot
, R_EBP
);
5406 case 0x06: /* push es */
5407 case 0x0e: /* push cs */
5408 case 0x16: /* push ss */
5409 case 0x1e: /* push ds */
5412 gen_op_movl_T0_seg(b
>> 3);
5415 case 0x1a0: /* push fs */
5416 case 0x1a8: /* push gs */
5417 gen_op_movl_T0_seg((b
>> 3) & 7);
5420 case 0x07: /* pop es */
5421 case 0x17: /* pop ss */
5422 case 0x1f: /* pop ds */
5427 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5430 /* if reg == SS, inhibit interrupts/trace. */
5431 /* If several instructions disable interrupts, only the
5433 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5434 gen_helper_set_inhibit_irq(cpu_env
);
5438 gen_jmp_im(s
->pc
- s
->cs_base
);
5442 case 0x1a1: /* pop fs */
5443 case 0x1a9: /* pop gs */
5445 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5448 gen_jmp_im(s
->pc
- s
->cs_base
);
5453 /**************************/
5456 case 0x89: /* mov Gv, Ev */
5461 modrm
= cpu_ldub_code(env
, s
->pc
++);
5462 reg
= ((modrm
>> 3) & 7) | rex_r
;
5464 /* generate a generic store */
5465 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5468 case 0xc7: /* mov Ev, Iv */
5473 modrm
= cpu_ldub_code(env
, s
->pc
++);
5474 mod
= (modrm
>> 6) & 3;
5476 s
->rip_offset
= insn_const_size(ot
);
5477 gen_lea_modrm(env
, s
, modrm
);
5479 val
= insn_get(env
, s
, ot
);
5480 tcg_gen_movi_tl(cpu_T
[0], val
);
5482 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5484 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5488 case 0x8b: /* mov Ev, Gv */
5493 modrm
= cpu_ldub_code(env
, s
->pc
++);
5494 reg
= ((modrm
>> 3) & 7) | rex_r
;
5496 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5497 gen_op_mov_reg_T0(ot
, reg
);
5499 case 0x8e: /* mov seg, Gv */
5500 modrm
= cpu_ldub_code(env
, s
->pc
++);
5501 reg
= (modrm
>> 3) & 7;
5502 if (reg
>= 6 || reg
== R_CS
)
5504 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
5505 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5507 /* if reg == SS, inhibit interrupts/trace */
5508 /* If several instructions disable interrupts, only the
5510 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5511 gen_helper_set_inhibit_irq(cpu_env
);
5515 gen_jmp_im(s
->pc
- s
->cs_base
);
5519 case 0x8c: /* mov Gv, seg */
5520 modrm
= cpu_ldub_code(env
, s
->pc
++);
5521 reg
= (modrm
>> 3) & 7;
5522 mod
= (modrm
>> 6) & 3;
5525 gen_op_movl_T0_seg(reg
);
5530 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5533 case 0x1b6: /* movzbS Gv, Eb */
5534 case 0x1b7: /* movzwS Gv, Eb */
5535 case 0x1be: /* movsbS Gv, Eb */
5536 case 0x1bf: /* movswS Gv, Eb */
5541 /* d_ot is the size of destination */
5542 d_ot
= dflag
+ MO_16
;
5543 /* ot is the size of source */
5544 ot
= (b
& 1) + MO_8
;
5545 /* s_ot is the sign+size of source */
5546 s_ot
= b
& 8 ? MO_SIGN
| ot
: ot
;
5548 modrm
= cpu_ldub_code(env
, s
->pc
++);
5549 reg
= ((modrm
>> 3) & 7) | rex_r
;
5550 mod
= (modrm
>> 6) & 3;
5551 rm
= (modrm
& 7) | REX_B(s
);
5554 gen_op_mov_TN_reg(ot
, 0, rm
);
5557 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5560 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5563 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5567 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5570 gen_op_mov_reg_T0(d_ot
, reg
);
5572 gen_lea_modrm(env
, s
, modrm
);
5573 gen_op_ld_v(s
, s_ot
, cpu_T
[0], cpu_A0
);
5574 gen_op_mov_reg_T0(d_ot
, reg
);
5579 case 0x8d: /* lea */
5581 modrm
= cpu_ldub_code(env
, s
->pc
++);
5582 mod
= (modrm
>> 6) & 3;
5585 reg
= ((modrm
>> 3) & 7) | rex_r
;
5586 /* we must ensure that no segment is added */
5590 gen_lea_modrm(env
, s
, modrm
);
5592 gen_op_mov_reg_A0(ot
- MO_16
, reg
);
5595 case 0xa0: /* mov EAX, Ov */
5597 case 0xa2: /* mov Ov, EAX */
5600 target_ulong offset_addr
;
5606 #ifdef TARGET_X86_64
5607 if (s
->aflag
== 2) {
5608 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5614 offset_addr
= insn_get(env
, s
, MO_32
);
5616 offset_addr
= insn_get(env
, s
, MO_16
);
5619 tcg_gen_movi_tl(cpu_A0
, offset_addr
);
5620 gen_add_A0_ds_seg(s
);
5622 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5623 gen_op_mov_reg_T0(ot
, R_EAX
);
5625 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5626 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5630 case 0xd7: /* xlat */
5631 #ifdef TARGET_X86_64
5632 if (s
->aflag
== 2) {
5633 gen_op_movq_A0_reg(R_EBX
);
5634 gen_op_mov_TN_reg(MO_64
, 0, R_EAX
);
5635 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5636 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5640 gen_op_movl_A0_reg(R_EBX
);
5641 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5642 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5643 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5645 gen_op_andl_A0_ffff();
5647 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5649 gen_add_A0_ds_seg(s
);
5650 gen_op_ld_v(s
, MO_8
, cpu_T
[0], cpu_A0
);
5651 gen_op_mov_reg_T0(MO_8
, R_EAX
);
5653 case 0xb0 ... 0xb7: /* mov R, Ib */
5654 val
= insn_get(env
, s
, MO_8
);
5655 tcg_gen_movi_tl(cpu_T
[0], val
);
5656 gen_op_mov_reg_T0(MO_8
, (b
& 7) | REX_B(s
));
5658 case 0xb8 ... 0xbf: /* mov R, Iv */
5659 #ifdef TARGET_X86_64
5663 tmp
= cpu_ldq_code(env
, s
->pc
);
5665 reg
= (b
& 7) | REX_B(s
);
5666 gen_movtl_T0_im(tmp
);
5667 gen_op_mov_reg_T0(MO_64
, reg
);
5671 ot
= dflag
? MO_32
: MO_16
;
5672 val
= insn_get(env
, s
, ot
);
5673 reg
= (b
& 7) | REX_B(s
);
5674 tcg_gen_movi_tl(cpu_T
[0], val
);
5675 gen_op_mov_reg_T0(ot
, reg
);
5679 case 0x91 ... 0x97: /* xchg R, EAX */
5682 reg
= (b
& 7) | REX_B(s
);
5686 case 0x87: /* xchg Ev, Gv */
5691 modrm
= cpu_ldub_code(env
, s
->pc
++);
5692 reg
= ((modrm
>> 3) & 7) | rex_r
;
5693 mod
= (modrm
>> 6) & 3;
5695 rm
= (modrm
& 7) | REX_B(s
);
5697 gen_op_mov_TN_reg(ot
, 0, reg
);
5698 gen_op_mov_TN_reg(ot
, 1, rm
);
5699 gen_op_mov_reg_T0(ot
, rm
);
5700 gen_op_mov_reg_T1(ot
, reg
);
5702 gen_lea_modrm(env
, s
, modrm
);
5703 gen_op_mov_TN_reg(ot
, 0, reg
);
5704 /* for xchg, lock is implicit */
5705 if (!(prefixes
& PREFIX_LOCK
))
5707 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5708 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5709 if (!(prefixes
& PREFIX_LOCK
))
5710 gen_helper_unlock();
5711 gen_op_mov_reg_T1(ot
, reg
);
5714 case 0xc4: /* les Gv */
5715 /* In CODE64 this is VEX3; see above. */
5718 case 0xc5: /* lds Gv */
5719 /* In CODE64 this is VEX2; see above. */
5722 case 0x1b2: /* lss Gv */
5725 case 0x1b4: /* lfs Gv */
5728 case 0x1b5: /* lgs Gv */
5731 ot
= dflag
? MO_32
: MO_16
;
5732 modrm
= cpu_ldub_code(env
, s
->pc
++);
5733 reg
= ((modrm
>> 3) & 7) | rex_r
;
5734 mod
= (modrm
>> 6) & 3;
5737 gen_lea_modrm(env
, s
, modrm
);
5738 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5739 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5740 /* load the segment first to handle exceptions properly */
5741 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5742 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5743 /* then put the data */
5744 gen_op_mov_reg_T1(ot
, reg
);
5746 gen_jmp_im(s
->pc
- s
->cs_base
);
5751 /************************/
5764 modrm
= cpu_ldub_code(env
, s
->pc
++);
5765 mod
= (modrm
>> 6) & 3;
5766 op
= (modrm
>> 3) & 7;
5772 gen_lea_modrm(env
, s
, modrm
);
5775 opreg
= (modrm
& 7) | REX_B(s
);
5780 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5783 shift
= cpu_ldub_code(env
, s
->pc
++);
5785 gen_shifti(s
, op
, ot
, opreg
, shift
);
5800 case 0x1a4: /* shld imm */
5804 case 0x1a5: /* shld cl */
5808 case 0x1ac: /* shrd imm */
5812 case 0x1ad: /* shrd cl */
5817 modrm
= cpu_ldub_code(env
, s
->pc
++);
5818 mod
= (modrm
>> 6) & 3;
5819 rm
= (modrm
& 7) | REX_B(s
);
5820 reg
= ((modrm
>> 3) & 7) | rex_r
;
5822 gen_lea_modrm(env
, s
, modrm
);
5827 gen_op_mov_TN_reg(ot
, 1, reg
);
5830 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5831 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5834 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5838 /************************/
5841 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5842 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5843 /* XXX: what to do if illegal op ? */
5844 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5847 modrm
= cpu_ldub_code(env
, s
->pc
++);
5848 mod
= (modrm
>> 6) & 3;
5850 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5853 gen_lea_modrm(env
, s
, modrm
);
5855 case 0x00 ... 0x07: /* fxxxs */
5856 case 0x10 ... 0x17: /* fixxxl */
5857 case 0x20 ... 0x27: /* fxxxl */
5858 case 0x30 ... 0x37: /* fixxx */
5865 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5866 s
->mem_index
, MO_LEUL
);
5867 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5870 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5871 s
->mem_index
, MO_LEUL
);
5872 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5875 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5876 s
->mem_index
, MO_LEQ
);
5877 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5881 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5882 s
->mem_index
, MO_LESW
);
5883 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5887 gen_helper_fp_arith_ST0_FT0(op1
);
5889 /* fcomp needs pop */
5890 gen_helper_fpop(cpu_env
);
5894 case 0x08: /* flds */
5895 case 0x0a: /* fsts */
5896 case 0x0b: /* fstps */
5897 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5898 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5899 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5904 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5905 s
->mem_index
, MO_LEUL
);
5906 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5909 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5910 s
->mem_index
, MO_LEUL
);
5911 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5914 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5915 s
->mem_index
, MO_LEQ
);
5916 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5920 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5921 s
->mem_index
, MO_LESW
);
5922 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5927 /* XXX: the corresponding CPUID bit must be tested ! */
5930 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5931 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5932 s
->mem_index
, MO_LEUL
);
5935 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5936 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5937 s
->mem_index
, MO_LEQ
);
5941 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5942 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5943 s
->mem_index
, MO_LEUW
);
5946 gen_helper_fpop(cpu_env
);
5951 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5952 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5953 s
->mem_index
, MO_LEUL
);
5956 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5957 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5958 s
->mem_index
, MO_LEUL
);
5961 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5962 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5963 s
->mem_index
, MO_LEQ
);
5967 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5968 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5969 s
->mem_index
, MO_LEUW
);
5973 gen_helper_fpop(cpu_env
);
5977 case 0x0c: /* fldenv mem */
5978 gen_update_cc_op(s
);
5979 gen_jmp_im(pc_start
- s
->cs_base
);
5980 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5982 case 0x0d: /* fldcw mem */
5983 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5984 s
->mem_index
, MO_LEUW
);
5985 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5987 case 0x0e: /* fnstenv mem */
5988 gen_update_cc_op(s
);
5989 gen_jmp_im(pc_start
- s
->cs_base
);
5990 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5992 case 0x0f: /* fnstcw mem */
5993 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5994 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5995 s
->mem_index
, MO_LEUW
);
5997 case 0x1d: /* fldt mem */
5998 gen_update_cc_op(s
);
5999 gen_jmp_im(pc_start
- s
->cs_base
);
6000 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
6002 case 0x1f: /* fstpt mem */
6003 gen_update_cc_op(s
);
6004 gen_jmp_im(pc_start
- s
->cs_base
);
6005 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
6006 gen_helper_fpop(cpu_env
);
6008 case 0x2c: /* frstor mem */
6009 gen_update_cc_op(s
);
6010 gen_jmp_im(pc_start
- s
->cs_base
);
6011 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
6013 case 0x2e: /* fnsave mem */
6014 gen_update_cc_op(s
);
6015 gen_jmp_im(pc_start
- s
->cs_base
);
6016 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
6018 case 0x2f: /* fnstsw mem */
6019 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6020 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
6021 s
->mem_index
, MO_LEUW
);
6023 case 0x3c: /* fbld */
6024 gen_update_cc_op(s
);
6025 gen_jmp_im(pc_start
- s
->cs_base
);
6026 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
6028 case 0x3e: /* fbstp */
6029 gen_update_cc_op(s
);
6030 gen_jmp_im(pc_start
- s
->cs_base
);
6031 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
6032 gen_helper_fpop(cpu_env
);
6034 case 0x3d: /* fildll */
6035 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
6036 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
6038 case 0x3f: /* fistpll */
6039 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
6040 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
6041 gen_helper_fpop(cpu_env
);
6047 /* register float ops */
6051 case 0x08: /* fld sti */
6052 gen_helper_fpush(cpu_env
);
6053 gen_helper_fmov_ST0_STN(cpu_env
,
6054 tcg_const_i32((opreg
+ 1) & 7));
6056 case 0x09: /* fxchg sti */
6057 case 0x29: /* fxchg4 sti, undocumented op */
6058 case 0x39: /* fxchg7 sti, undocumented op */
6059 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6061 case 0x0a: /* grp d9/2 */
6064 /* check exceptions (FreeBSD FPU probe) */
6065 gen_update_cc_op(s
);
6066 gen_jmp_im(pc_start
- s
->cs_base
);
6067 gen_helper_fwait(cpu_env
);
6073 case 0x0c: /* grp d9/4 */
6076 gen_helper_fchs_ST0(cpu_env
);
6079 gen_helper_fabs_ST0(cpu_env
);
6082 gen_helper_fldz_FT0(cpu_env
);
6083 gen_helper_fcom_ST0_FT0(cpu_env
);
6086 gen_helper_fxam_ST0(cpu_env
);
6092 case 0x0d: /* grp d9/5 */
6096 gen_helper_fpush(cpu_env
);
6097 gen_helper_fld1_ST0(cpu_env
);
6100 gen_helper_fpush(cpu_env
);
6101 gen_helper_fldl2t_ST0(cpu_env
);
6104 gen_helper_fpush(cpu_env
);
6105 gen_helper_fldl2e_ST0(cpu_env
);
6108 gen_helper_fpush(cpu_env
);
6109 gen_helper_fldpi_ST0(cpu_env
);
6112 gen_helper_fpush(cpu_env
);
6113 gen_helper_fldlg2_ST0(cpu_env
);
6116 gen_helper_fpush(cpu_env
);
6117 gen_helper_fldln2_ST0(cpu_env
);
6120 gen_helper_fpush(cpu_env
);
6121 gen_helper_fldz_ST0(cpu_env
);
6128 case 0x0e: /* grp d9/6 */
6131 gen_helper_f2xm1(cpu_env
);
6134 gen_helper_fyl2x(cpu_env
);
6137 gen_helper_fptan(cpu_env
);
6139 case 3: /* fpatan */
6140 gen_helper_fpatan(cpu_env
);
6142 case 4: /* fxtract */
6143 gen_helper_fxtract(cpu_env
);
6145 case 5: /* fprem1 */
6146 gen_helper_fprem1(cpu_env
);
6148 case 6: /* fdecstp */
6149 gen_helper_fdecstp(cpu_env
);
6152 case 7: /* fincstp */
6153 gen_helper_fincstp(cpu_env
);
6157 case 0x0f: /* grp d9/7 */
6160 gen_helper_fprem(cpu_env
);
6162 case 1: /* fyl2xp1 */
6163 gen_helper_fyl2xp1(cpu_env
);
6166 gen_helper_fsqrt(cpu_env
);
6168 case 3: /* fsincos */
6169 gen_helper_fsincos(cpu_env
);
6171 case 5: /* fscale */
6172 gen_helper_fscale(cpu_env
);
6174 case 4: /* frndint */
6175 gen_helper_frndint(cpu_env
);
6178 gen_helper_fsin(cpu_env
);
6182 gen_helper_fcos(cpu_env
);
6186 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6187 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6188 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6194 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6196 gen_helper_fpop(cpu_env
);
6198 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6199 gen_helper_fp_arith_ST0_FT0(op1
);
6203 case 0x02: /* fcom */
6204 case 0x22: /* fcom2, undocumented op */
6205 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6206 gen_helper_fcom_ST0_FT0(cpu_env
);
6208 case 0x03: /* fcomp */
6209 case 0x23: /* fcomp3, undocumented op */
6210 case 0x32: /* fcomp5, undocumented op */
6211 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6212 gen_helper_fcom_ST0_FT0(cpu_env
);
6213 gen_helper_fpop(cpu_env
);
6215 case 0x15: /* da/5 */
6217 case 1: /* fucompp */
6218 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6219 gen_helper_fucom_ST0_FT0(cpu_env
);
6220 gen_helper_fpop(cpu_env
);
6221 gen_helper_fpop(cpu_env
);
6229 case 0: /* feni (287 only, just do nop here) */
6231 case 1: /* fdisi (287 only, just do nop here) */
6234 gen_helper_fclex(cpu_env
);
6236 case 3: /* fninit */
6237 gen_helper_fninit(cpu_env
);
6239 case 4: /* fsetpm (287 only, just do nop here) */
6245 case 0x1d: /* fucomi */
6246 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6249 gen_update_cc_op(s
);
6250 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6251 gen_helper_fucomi_ST0_FT0(cpu_env
);
6252 set_cc_op(s
, CC_OP_EFLAGS
);
6254 case 0x1e: /* fcomi */
6255 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6258 gen_update_cc_op(s
);
6259 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6260 gen_helper_fcomi_ST0_FT0(cpu_env
);
6261 set_cc_op(s
, CC_OP_EFLAGS
);
6263 case 0x28: /* ffree sti */
6264 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6266 case 0x2a: /* fst sti */
6267 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6269 case 0x2b: /* fstp sti */
6270 case 0x0b: /* fstp1 sti, undocumented op */
6271 case 0x3a: /* fstp8 sti, undocumented op */
6272 case 0x3b: /* fstp9 sti, undocumented op */
6273 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6274 gen_helper_fpop(cpu_env
);
6276 case 0x2c: /* fucom st(i) */
6277 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6278 gen_helper_fucom_ST0_FT0(cpu_env
);
6280 case 0x2d: /* fucomp st(i) */
6281 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6282 gen_helper_fucom_ST0_FT0(cpu_env
);
6283 gen_helper_fpop(cpu_env
);
6285 case 0x33: /* de/3 */
6287 case 1: /* fcompp */
6288 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6289 gen_helper_fcom_ST0_FT0(cpu_env
);
6290 gen_helper_fpop(cpu_env
);
6291 gen_helper_fpop(cpu_env
);
6297 case 0x38: /* ffreep sti, undocumented op */
6298 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6299 gen_helper_fpop(cpu_env
);
6301 case 0x3c: /* df/4 */
6304 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6305 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6306 gen_op_mov_reg_T0(MO_16
, R_EAX
);
6312 case 0x3d: /* fucomip */
6313 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6316 gen_update_cc_op(s
);
6317 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6318 gen_helper_fucomi_ST0_FT0(cpu_env
);
6319 gen_helper_fpop(cpu_env
);
6320 set_cc_op(s
, CC_OP_EFLAGS
);
6322 case 0x3e: /* fcomip */
6323 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6326 gen_update_cc_op(s
);
6327 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6328 gen_helper_fcomi_ST0_FT0(cpu_env
);
6329 gen_helper_fpop(cpu_env
);
6330 set_cc_op(s
, CC_OP_EFLAGS
);
6332 case 0x10 ... 0x13: /* fcmovxx */
6336 static const uint8_t fcmov_cc
[8] = {
6343 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6346 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6347 l1
= gen_new_label();
6348 gen_jcc1_noeob(s
, op1
, l1
);
6349 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6358 /************************/
6361 case 0xa4: /* movsS */
6368 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6369 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6375 case 0xaa: /* stosS */
6382 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6383 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6388 case 0xac: /* lodsS */
6394 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6395 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6400 case 0xae: /* scasS */
6406 if (prefixes
& PREFIX_REPNZ
) {
6407 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6408 } else if (prefixes
& PREFIX_REPZ
) {
6409 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6415 case 0xa6: /* cmpsS */
6421 if (prefixes
& PREFIX_REPNZ
) {
6422 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6423 } else if (prefixes
& PREFIX_REPZ
) {
6424 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6429 case 0x6c: /* insS */
6434 ot
= dflag
? MO_32
: MO_16
;
6435 gen_op_mov_TN_reg(MO_16
, 0, R_EDX
);
6436 gen_op_andl_T0_ffff();
6437 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6438 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6439 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6440 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6444 gen_jmp(s
, s
->pc
- s
->cs_base
);
6448 case 0x6e: /* outsS */
6453 ot
= dflag
? MO_32
: MO_16
;
6454 gen_op_mov_TN_reg(MO_16
, 0, R_EDX
);
6455 gen_op_andl_T0_ffff();
6456 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6457 svm_is_rep(prefixes
) | 4);
6458 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6459 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6463 gen_jmp(s
, s
->pc
- s
->cs_base
);
6468 /************************/
6476 ot
= dflag
? MO_32
: MO_16
;
6477 val
= cpu_ldub_code(env
, s
->pc
++);
6478 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6479 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6482 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6483 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6484 gen_op_mov_reg_T1(ot
, R_EAX
);
6487 gen_jmp(s
, s
->pc
- s
->cs_base
);
6495 ot
= dflag
? MO_32
: MO_16
;
6496 val
= cpu_ldub_code(env
, s
->pc
++);
6497 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6498 svm_is_rep(prefixes
));
6499 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6503 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6504 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6505 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6508 gen_jmp(s
, s
->pc
- s
->cs_base
);
6516 ot
= dflag
? MO_32
: MO_16
;
6517 gen_op_mov_TN_reg(MO_16
, 0, R_EDX
);
6518 gen_op_andl_T0_ffff();
6519 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6520 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6523 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6524 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6525 gen_op_mov_reg_T1(ot
, R_EAX
);
6528 gen_jmp(s
, s
->pc
- s
->cs_base
);
6536 ot
= dflag
? MO_32
: MO_16
;
6537 gen_op_mov_TN_reg(MO_16
, 0, R_EDX
);
6538 gen_op_andl_T0_ffff();
6539 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6540 svm_is_rep(prefixes
));
6541 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6545 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6546 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6547 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6550 gen_jmp(s
, s
->pc
- s
->cs_base
);
6554 /************************/
6556 case 0xc2: /* ret im */
6557 val
= cpu_ldsw_code(env
, s
->pc
);
6560 if (CODE64(s
) && s
->dflag
)
6562 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6564 gen_op_andl_T0_ffff();
6568 case 0xc3: /* ret */
6572 gen_op_andl_T0_ffff();
6576 case 0xca: /* lret im */
6577 val
= cpu_ldsw_code(env
, s
->pc
);
6580 if (s
->pe
&& !s
->vm86
) {
6581 gen_update_cc_op(s
);
6582 gen_jmp_im(pc_start
- s
->cs_base
);
6583 gen_helper_lret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6584 tcg_const_i32(val
));
6588 gen_op_ld_v(s
, 1 + s
->dflag
, cpu_T
[0], cpu_A0
);
6590 gen_op_andl_T0_ffff();
6591 /* NOTE: keeping EIP updated is not a problem in case of
6595 gen_op_addl_A0_im(2 << s
->dflag
);
6596 gen_op_ld_v(s
, 1 + s
->dflag
, cpu_T
[0], cpu_A0
);
6597 gen_op_movl_seg_T0_vm(R_CS
);
6598 /* add stack offset */
6599 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6603 case 0xcb: /* lret */
6606 case 0xcf: /* iret */
6607 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6610 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6611 set_cc_op(s
, CC_OP_EFLAGS
);
6612 } else if (s
->vm86
) {
6614 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6616 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6617 set_cc_op(s
, CC_OP_EFLAGS
);
6620 gen_update_cc_op(s
);
6621 gen_jmp_im(pc_start
- s
->cs_base
);
6622 gen_helper_iret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6623 tcg_const_i32(s
->pc
- s
->cs_base
));
6624 set_cc_op(s
, CC_OP_EFLAGS
);
6628 case 0xe8: /* call im */
6631 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6633 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6634 next_eip
= s
->pc
- s
->cs_base
;
6640 gen_movtl_T0_im(next_eip
);
6645 case 0x9a: /* lcall im */
6647 unsigned int selector
, offset
;
6651 ot
= dflag
? MO_32
: MO_16
;
6652 offset
= insn_get(env
, s
, ot
);
6653 selector
= insn_get(env
, s
, MO_16
);
6655 tcg_gen_movi_tl(cpu_T
[0], selector
);
6656 tcg_gen_movi_tl(cpu_T
[1], offset
);
6659 case 0xe9: /* jmp im */
6661 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6663 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6664 tval
+= s
->pc
- s
->cs_base
;
6671 case 0xea: /* ljmp im */
6673 unsigned int selector
, offset
;
6677 ot
= dflag
? MO_32
: MO_16
;
6678 offset
= insn_get(env
, s
, ot
);
6679 selector
= insn_get(env
, s
, MO_16
);
6681 tcg_gen_movi_tl(cpu_T
[0], selector
);
6682 tcg_gen_movi_tl(cpu_T
[1], offset
);
6685 case 0xeb: /* jmp Jb */
6686 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6687 tval
+= s
->pc
- s
->cs_base
;
6692 case 0x70 ... 0x7f: /* jcc Jb */
6693 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6695 case 0x180 ... 0x18f: /* jcc Jv */
6697 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6699 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6702 next_eip
= s
->pc
- s
->cs_base
;
6706 gen_jcc(s
, b
, tval
, next_eip
);
6709 case 0x190 ... 0x19f: /* setcc Gv */
6710 modrm
= cpu_ldub_code(env
, s
->pc
++);
6711 gen_setcc1(s
, b
, cpu_T
[0]);
6712 gen_ldst_modrm(env
, s
, modrm
, MO_8
, OR_TMP0
, 1);
6714 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6715 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6719 modrm
= cpu_ldub_code(env
, s
->pc
++);
6720 reg
= ((modrm
>> 3) & 7) | rex_r
;
6721 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6724 /************************/
6726 case 0x9c: /* pushf */
6727 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6728 if (s
->vm86
&& s
->iopl
!= 3) {
6729 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6731 gen_update_cc_op(s
);
6732 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6736 case 0x9d: /* popf */
6737 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6738 if (s
->vm86
&& s
->iopl
!= 3) {
6739 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6744 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6745 tcg_const_i32((TF_MASK
| AC_MASK
|
6750 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6751 tcg_const_i32((TF_MASK
| AC_MASK
|
6753 IF_MASK
| IOPL_MASK
)
6757 if (s
->cpl
<= s
->iopl
) {
6759 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6760 tcg_const_i32((TF_MASK
|
6766 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6767 tcg_const_i32((TF_MASK
|
6776 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6777 tcg_const_i32((TF_MASK
| AC_MASK
|
6778 ID_MASK
| NT_MASK
)));
6780 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6781 tcg_const_i32((TF_MASK
| AC_MASK
|
6788 set_cc_op(s
, CC_OP_EFLAGS
);
6789 /* abort translation because TF/AC flag may change */
6790 gen_jmp_im(s
->pc
- s
->cs_base
);
6794 case 0x9e: /* sahf */
6795 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6797 gen_op_mov_TN_reg(MO_8
, 0, R_AH
);
6798 gen_compute_eflags(s
);
6799 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6800 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6801 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6803 case 0x9f: /* lahf */
6804 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6806 gen_compute_eflags(s
);
6807 /* Note: gen_compute_eflags() only gives the condition codes */
6808 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6809 gen_op_mov_reg_T0(MO_8
, R_AH
);
6811 case 0xf5: /* cmc */
6812 gen_compute_eflags(s
);
6813 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6815 case 0xf8: /* clc */
6816 gen_compute_eflags(s
);
6817 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6819 case 0xf9: /* stc */
6820 gen_compute_eflags(s
);
6821 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6823 case 0xfc: /* cld */
6824 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6825 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6827 case 0xfd: /* std */
6828 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6829 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6832 /************************/
6833 /* bit operations */
6834 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6836 modrm
= cpu_ldub_code(env
, s
->pc
++);
6837 op
= (modrm
>> 3) & 7;
6838 mod
= (modrm
>> 6) & 3;
6839 rm
= (modrm
& 7) | REX_B(s
);
6842 gen_lea_modrm(env
, s
, modrm
);
6843 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6845 gen_op_mov_TN_reg(ot
, 0, rm
);
6848 val
= cpu_ldub_code(env
, s
->pc
++);
6849 tcg_gen_movi_tl(cpu_T
[1], val
);
6854 case 0x1a3: /* bt Gv, Ev */
6857 case 0x1ab: /* bts */
6860 case 0x1b3: /* btr */
6863 case 0x1bb: /* btc */
6867 modrm
= cpu_ldub_code(env
, s
->pc
++);
6868 reg
= ((modrm
>> 3) & 7) | rex_r
;
6869 mod
= (modrm
>> 6) & 3;
6870 rm
= (modrm
& 7) | REX_B(s
);
6871 gen_op_mov_TN_reg(MO_32
, 1, reg
);
6873 gen_lea_modrm(env
, s
, modrm
);
6874 /* specific case: we need to add a displacement */
6875 gen_exts(ot
, cpu_T
[1]);
6876 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6877 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6878 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6879 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6881 gen_op_mov_TN_reg(ot
, 0, rm
);
6884 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6887 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6888 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6891 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6892 tcg_gen_movi_tl(cpu_tmp0
, 1);
6893 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6894 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6897 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6898 tcg_gen_movi_tl(cpu_tmp0
, 1);
6899 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6900 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6901 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6905 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6906 tcg_gen_movi_tl(cpu_tmp0
, 1);
6907 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6908 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6911 set_cc_op(s
, CC_OP_SARB
+ ot
);
6914 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
6916 gen_op_mov_reg_T0(ot
, rm
);
6918 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6919 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6922 case 0x1bc: /* bsf / tzcnt */
6923 case 0x1bd: /* bsr / lzcnt */
6925 modrm
= cpu_ldub_code(env
, s
->pc
++);
6926 reg
= ((modrm
>> 3) & 7) | rex_r
;
6927 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
6928 gen_extu(ot
, cpu_T
[0]);
6930 /* Note that lzcnt and tzcnt are in different extensions. */
6931 if ((prefixes
& PREFIX_REPZ
)
6933 ? s
->cpuid_ext3_features
& CPUID_EXT3_ABM
6934 : s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)) {
6936 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
6938 /* For lzcnt, reduce the target_ulong result by the
6939 number of zeros that we expect to find at the top. */
6940 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6941 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- size
);
6943 /* For tzcnt, a zero input must return the operand size:
6944 force all bits outside the operand size to 1. */
6945 target_ulong mask
= (target_ulong
)-2 << (size
- 1);
6946 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], mask
);
6947 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6949 /* For lzcnt/tzcnt, C and Z bits are defined and are
6950 related to the result. */
6951 gen_op_update1_cc();
6952 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
6954 /* For bsr/bsf, only the Z bit is defined and it is related
6955 to the input and not the result. */
6956 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
6957 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6959 /* For bsr, return the bit index of the first 1 bit,
6960 not the count of leading zeros. */
6961 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6962 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- 1);
6964 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6966 /* ??? The manual says that the output is undefined when the
6967 input is zero, but real hardware leaves it unchanged, and
6968 real programs appear to depend on that. */
6969 tcg_gen_movi_tl(cpu_tmp0
, 0);
6970 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[0], cpu_cc_dst
, cpu_tmp0
,
6971 cpu_regs
[reg
], cpu_T
[0]);
6973 gen_op_mov_reg_T0(ot
, reg
);
6975 /************************/
6977 case 0x27: /* daa */
6980 gen_update_cc_op(s
);
6981 gen_helper_daa(cpu_env
);
6982 set_cc_op(s
, CC_OP_EFLAGS
);
6984 case 0x2f: /* das */
6987 gen_update_cc_op(s
);
6988 gen_helper_das(cpu_env
);
6989 set_cc_op(s
, CC_OP_EFLAGS
);
6991 case 0x37: /* aaa */
6994 gen_update_cc_op(s
);
6995 gen_helper_aaa(cpu_env
);
6996 set_cc_op(s
, CC_OP_EFLAGS
);
6998 case 0x3f: /* aas */
7001 gen_update_cc_op(s
);
7002 gen_helper_aas(cpu_env
);
7003 set_cc_op(s
, CC_OP_EFLAGS
);
7005 case 0xd4: /* aam */
7008 val
= cpu_ldub_code(env
, s
->pc
++);
7010 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
7012 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
7013 set_cc_op(s
, CC_OP_LOGICB
);
7016 case 0xd5: /* aad */
7019 val
= cpu_ldub_code(env
, s
->pc
++);
7020 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
7021 set_cc_op(s
, CC_OP_LOGICB
);
7023 /************************/
7025 case 0x90: /* nop */
7026 /* XXX: correct lock test for all insn */
7027 if (prefixes
& PREFIX_LOCK
) {
7030 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
7032 goto do_xchg_reg_eax
;
7034 if (prefixes
& PREFIX_REPZ
) {
7035 gen_update_cc_op(s
);
7036 gen_jmp_im(pc_start
- s
->cs_base
);
7037 gen_helper_pause(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7038 s
->is_jmp
= DISAS_TB_JUMP
;
7041 case 0x9b: /* fwait */
7042 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
7043 (HF_MP_MASK
| HF_TS_MASK
)) {
7044 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7046 gen_update_cc_op(s
);
7047 gen_jmp_im(pc_start
- s
->cs_base
);
7048 gen_helper_fwait(cpu_env
);
7051 case 0xcc: /* int3 */
7052 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
7054 case 0xcd: /* int N */
7055 val
= cpu_ldub_code(env
, s
->pc
++);
7056 if (s
->vm86
&& s
->iopl
!= 3) {
7057 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7059 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
7062 case 0xce: /* into */
7065 gen_update_cc_op(s
);
7066 gen_jmp_im(pc_start
- s
->cs_base
);
7067 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7070 case 0xf1: /* icebp (undocumented, exits to external debugger) */
7071 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
7073 gen_debug(s
, pc_start
- s
->cs_base
);
7077 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
7081 case 0xfa: /* cli */
7083 if (s
->cpl
<= s
->iopl
) {
7084 gen_helper_cli(cpu_env
);
7086 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7090 gen_helper_cli(cpu_env
);
7092 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7096 case 0xfb: /* sti */
7098 if (s
->cpl
<= s
->iopl
) {
7100 gen_helper_sti(cpu_env
);
7101 /* interruptions are enabled only the first insn after sti */
7102 /* If several instructions disable interrupts, only the
7104 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
7105 gen_helper_set_inhibit_irq(cpu_env
);
7106 /* give a chance to handle pending irqs */
7107 gen_jmp_im(s
->pc
- s
->cs_base
);
7110 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7116 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7120 case 0x62: /* bound */
7123 ot
= dflag
? MO_32
: MO_16
;
7124 modrm
= cpu_ldub_code(env
, s
->pc
++);
7125 reg
= (modrm
>> 3) & 7;
7126 mod
= (modrm
>> 6) & 3;
7129 gen_op_mov_TN_reg(ot
, 0, reg
);
7130 gen_lea_modrm(env
, s
, modrm
);
7131 gen_jmp_im(pc_start
- s
->cs_base
);
7132 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7134 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
7136 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
7139 case 0x1c8 ... 0x1cf: /* bswap reg */
7140 reg
= (b
& 7) | REX_B(s
);
7141 #ifdef TARGET_X86_64
7143 gen_op_mov_TN_reg(MO_64
, 0, reg
);
7144 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
7145 gen_op_mov_reg_T0(MO_64
, reg
);
7149 gen_op_mov_TN_reg(MO_32
, 0, reg
);
7150 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
7151 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
7152 gen_op_mov_reg_T0(MO_32
, reg
);
7155 case 0xd6: /* salc */
7158 gen_compute_eflags_c(s
, cpu_T
[0]);
7159 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
7160 gen_op_mov_reg_T0(MO_8
, R_EAX
);
7162 case 0xe0: /* loopnz */
7163 case 0xe1: /* loopz */
7164 case 0xe2: /* loop */
7165 case 0xe3: /* jecxz */
7169 tval
= (int8_t)insn_get(env
, s
, MO_8
);
7170 next_eip
= s
->pc
- s
->cs_base
;
7175 l1
= gen_new_label();
7176 l2
= gen_new_label();
7177 l3
= gen_new_label();
7180 case 0: /* loopnz */
7182 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7183 gen_op_jz_ecx(s
->aflag
, l3
);
7184 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7187 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7188 gen_op_jnz_ecx(s
->aflag
, l1
);
7192 gen_op_jz_ecx(s
->aflag
, l1
);
7197 gen_jmp_im(next_eip
);
7206 case 0x130: /* wrmsr */
7207 case 0x132: /* rdmsr */
7209 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7211 gen_update_cc_op(s
);
7212 gen_jmp_im(pc_start
- s
->cs_base
);
7214 gen_helper_rdmsr(cpu_env
);
7216 gen_helper_wrmsr(cpu_env
);
7220 case 0x131: /* rdtsc */
7221 gen_update_cc_op(s
);
7222 gen_jmp_im(pc_start
- s
->cs_base
);
7225 gen_helper_rdtsc(cpu_env
);
7228 gen_jmp(s
, s
->pc
- s
->cs_base
);
7231 case 0x133: /* rdpmc */
7232 gen_update_cc_op(s
);
7233 gen_jmp_im(pc_start
- s
->cs_base
);
7234 gen_helper_rdpmc(cpu_env
);
7236 case 0x134: /* sysenter */
7237 /* For Intel SYSENTER is valid on 64-bit */
7238 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7241 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7243 gen_update_cc_op(s
);
7244 gen_jmp_im(pc_start
- s
->cs_base
);
7245 gen_helper_sysenter(cpu_env
);
7249 case 0x135: /* sysexit */
7250 /* For Intel SYSEXIT is valid on 64-bit */
7251 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7254 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7256 gen_update_cc_op(s
);
7257 gen_jmp_im(pc_start
- s
->cs_base
);
7258 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
));
7262 #ifdef TARGET_X86_64
7263 case 0x105: /* syscall */
7264 /* XXX: is it usable in real mode ? */
7265 gen_update_cc_op(s
);
7266 gen_jmp_im(pc_start
- s
->cs_base
);
7267 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7270 case 0x107: /* sysret */
7272 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7274 gen_update_cc_op(s
);
7275 gen_jmp_im(pc_start
- s
->cs_base
);
7276 gen_helper_sysret(cpu_env
, tcg_const_i32(s
->dflag
));
7277 /* condition codes are modified only in long mode */
7279 set_cc_op(s
, CC_OP_EFLAGS
);
7285 case 0x1a2: /* cpuid */
7286 gen_update_cc_op(s
);
7287 gen_jmp_im(pc_start
- s
->cs_base
);
7288 gen_helper_cpuid(cpu_env
);
7290 case 0xf4: /* hlt */
7292 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7294 gen_update_cc_op(s
);
7295 gen_jmp_im(pc_start
- s
->cs_base
);
7296 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7297 s
->is_jmp
= DISAS_TB_JUMP
;
7301 modrm
= cpu_ldub_code(env
, s
->pc
++);
7302 mod
= (modrm
>> 6) & 3;
7303 op
= (modrm
>> 3) & 7;
7306 if (!s
->pe
|| s
->vm86
)
7308 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7309 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7313 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7316 if (!s
->pe
|| s
->vm86
)
7319 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7321 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7322 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7323 gen_jmp_im(pc_start
- s
->cs_base
);
7324 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7325 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7329 if (!s
->pe
|| s
->vm86
)
7331 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7332 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7336 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7339 if (!s
->pe
|| s
->vm86
)
7342 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7344 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7345 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7346 gen_jmp_im(pc_start
- s
->cs_base
);
7347 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7348 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7353 if (!s
->pe
|| s
->vm86
)
7355 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7356 gen_update_cc_op(s
);
7358 gen_helper_verr(cpu_env
, cpu_T
[0]);
7360 gen_helper_verw(cpu_env
, cpu_T
[0]);
7362 set_cc_op(s
, CC_OP_EFLAGS
);
7369 modrm
= cpu_ldub_code(env
, s
->pc
++);
7370 mod
= (modrm
>> 6) & 3;
7371 op
= (modrm
>> 3) & 7;
7377 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7378 gen_lea_modrm(env
, s
, modrm
);
7379 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7380 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7381 gen_add_A0_im(s
, 2);
7382 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7384 gen_op_andl_T0_im(0xffffff);
7385 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7390 case 0: /* monitor */
7391 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7394 gen_update_cc_op(s
);
7395 gen_jmp_im(pc_start
- s
->cs_base
);
7396 #ifdef TARGET_X86_64
7397 if (s
->aflag
== 2) {
7398 gen_op_movq_A0_reg(R_EAX
);
7402 gen_op_movl_A0_reg(R_EAX
);
7404 gen_op_andl_A0_ffff();
7406 gen_add_A0_ds_seg(s
);
7407 gen_helper_monitor(cpu_env
, cpu_A0
);
7410 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7413 gen_update_cc_op(s
);
7414 gen_jmp_im(pc_start
- s
->cs_base
);
7415 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7419 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7423 gen_helper_clac(cpu_env
);
7424 gen_jmp_im(s
->pc
- s
->cs_base
);
7428 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7432 gen_helper_stac(cpu_env
);
7433 gen_jmp_im(s
->pc
- s
->cs_base
);
7440 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7441 gen_lea_modrm(env
, s
, modrm
);
7442 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7443 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7444 gen_add_A0_im(s
, 2);
7445 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7447 gen_op_andl_T0_im(0xffffff);
7448 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7454 gen_update_cc_op(s
);
7455 gen_jmp_im(pc_start
- s
->cs_base
);
7458 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7461 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7464 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
),
7465 tcg_const_i32(s
->pc
- pc_start
));
7467 s
->is_jmp
= DISAS_TB_JUMP
;
7470 case 1: /* VMMCALL */
7471 if (!(s
->flags
& HF_SVME_MASK
))
7473 gen_helper_vmmcall(cpu_env
);
7475 case 2: /* VMLOAD */
7476 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7479 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7482 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
));
7485 case 3: /* VMSAVE */
7486 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7489 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7492 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
));
7496 if ((!(s
->flags
& HF_SVME_MASK
) &&
7497 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7501 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7504 gen_helper_stgi(cpu_env
);
7508 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7511 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7514 gen_helper_clgi(cpu_env
);
7517 case 6: /* SKINIT */
7518 if ((!(s
->flags
& HF_SVME_MASK
) &&
7519 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7522 gen_helper_skinit(cpu_env
);
7524 case 7: /* INVLPGA */
7525 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7528 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7531 gen_helper_invlpga(cpu_env
, tcg_const_i32(s
->aflag
));
7537 } else if (s
->cpl
!= 0) {
7538 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7540 gen_svm_check_intercept(s
, pc_start
,
7541 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7542 gen_lea_modrm(env
, s
, modrm
);
7543 gen_op_ld_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
7544 gen_add_A0_im(s
, 2);
7545 gen_op_ld_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7547 gen_op_andl_T0_im(0xffffff);
7549 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7550 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7552 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7553 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7558 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7559 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7560 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7562 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7564 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 1);
7568 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7570 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7571 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7572 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7573 gen_jmp_im(s
->pc
- s
->cs_base
);
7578 if (mod
!= 3) { /* invlpg */
7580 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7582 gen_update_cc_op(s
);
7583 gen_jmp_im(pc_start
- s
->cs_base
);
7584 gen_lea_modrm(env
, s
, modrm
);
7585 gen_helper_invlpg(cpu_env
, cpu_A0
);
7586 gen_jmp_im(s
->pc
- s
->cs_base
);
7591 case 0: /* swapgs */
7592 #ifdef TARGET_X86_64
7595 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7597 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7598 offsetof(CPUX86State
,segs
[R_GS
].base
));
7599 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7600 offsetof(CPUX86State
,kernelgsbase
));
7601 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7602 offsetof(CPUX86State
,segs
[R_GS
].base
));
7603 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7604 offsetof(CPUX86State
,kernelgsbase
));
7612 case 1: /* rdtscp */
7613 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7615 gen_update_cc_op(s
);
7616 gen_jmp_im(pc_start
- s
->cs_base
);
7619 gen_helper_rdtscp(cpu_env
);
7622 gen_jmp(s
, s
->pc
- s
->cs_base
);
7634 case 0x108: /* invd */
7635 case 0x109: /* wbinvd */
7637 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7639 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7643 case 0x63: /* arpl or movslS (x86_64) */
7644 #ifdef TARGET_X86_64
7647 /* d_ot is the size of destination */
7648 d_ot
= dflag
+ MO_16
;
7650 modrm
= cpu_ldub_code(env
, s
->pc
++);
7651 reg
= ((modrm
>> 3) & 7) | rex_r
;
7652 mod
= (modrm
>> 6) & 3;
7653 rm
= (modrm
& 7) | REX_B(s
);
7656 gen_op_mov_TN_reg(MO_32
, 0, rm
);
7658 if (d_ot
== MO_64
) {
7659 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7661 gen_op_mov_reg_T0(d_ot
, reg
);
7663 gen_lea_modrm(env
, s
, modrm
);
7664 gen_op_ld_v(s
, MO_32
| MO_SIGN
, cpu_T
[0], cpu_A0
);
7665 gen_op_mov_reg_T0(d_ot
, reg
);
7671 TCGv t0
, t1
, t2
, a0
;
7673 if (!s
->pe
|| s
->vm86
)
7675 t0
= tcg_temp_local_new();
7676 t1
= tcg_temp_local_new();
7677 t2
= tcg_temp_local_new();
7679 modrm
= cpu_ldub_code(env
, s
->pc
++);
7680 reg
= (modrm
>> 3) & 7;
7681 mod
= (modrm
>> 6) & 3;
7684 gen_lea_modrm(env
, s
, modrm
);
7685 gen_op_ld_v(s
, ot
, t0
, cpu_A0
);
7686 a0
= tcg_temp_local_new();
7687 tcg_gen_mov_tl(a0
, cpu_A0
);
7689 gen_op_mov_v_reg(ot
, t0
, rm
);
7692 gen_op_mov_v_reg(ot
, t1
, reg
);
7693 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7694 tcg_gen_andi_tl(t1
, t1
, 3);
7695 tcg_gen_movi_tl(t2
, 0);
7696 label1
= gen_new_label();
7697 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7698 tcg_gen_andi_tl(t0
, t0
, ~3);
7699 tcg_gen_or_tl(t0
, t0
, t1
);
7700 tcg_gen_movi_tl(t2
, CC_Z
);
7701 gen_set_label(label1
);
7703 gen_op_st_v(s
, ot
, t0
, a0
);
7706 gen_op_mov_reg_v(ot
, rm
, t0
);
7708 gen_compute_eflags(s
);
7709 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7710 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7716 case 0x102: /* lar */
7717 case 0x103: /* lsl */
7721 if (!s
->pe
|| s
->vm86
)
7723 ot
= dflag
? MO_32
: MO_16
;
7724 modrm
= cpu_ldub_code(env
, s
->pc
++);
7725 reg
= ((modrm
>> 3) & 7) | rex_r
;
7726 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7727 t0
= tcg_temp_local_new();
7728 gen_update_cc_op(s
);
7730 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7732 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7734 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7735 label1
= gen_new_label();
7736 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7737 gen_op_mov_reg_v(ot
, reg
, t0
);
7738 gen_set_label(label1
);
7739 set_cc_op(s
, CC_OP_EFLAGS
);
7744 modrm
= cpu_ldub_code(env
, s
->pc
++);
7745 mod
= (modrm
>> 6) & 3;
7746 op
= (modrm
>> 3) & 7;
7748 case 0: /* prefetchnta */
7749 case 1: /* prefetchnt0 */
7750 case 2: /* prefetchnt0 */
7751 case 3: /* prefetchnt0 */
7754 gen_lea_modrm(env
, s
, modrm
);
7755 /* nothing more to do */
7757 default: /* nop (multi byte) */
7758 gen_nop_modrm(env
, s
, modrm
);
7762 case 0x119 ... 0x11f: /* nop (multi byte) */
7763 modrm
= cpu_ldub_code(env
, s
->pc
++);
7764 gen_nop_modrm(env
, s
, modrm
);
7766 case 0x120: /* mov reg, crN */
7767 case 0x122: /* mov crN, reg */
7769 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7771 modrm
= cpu_ldub_code(env
, s
->pc
++);
7772 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7773 * AMD documentation (24594.pdf) and testing of
7774 * intel 386 and 486 processors all show that the mod bits
7775 * are assumed to be 1's, regardless of actual values.
7777 rm
= (modrm
& 7) | REX_B(s
);
7778 reg
= ((modrm
>> 3) & 7) | rex_r
;
7783 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7784 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7793 gen_update_cc_op(s
);
7794 gen_jmp_im(pc_start
- s
->cs_base
);
7796 gen_op_mov_TN_reg(ot
, 0, rm
);
7797 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7799 gen_jmp_im(s
->pc
- s
->cs_base
);
7802 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7803 gen_op_mov_reg_T0(ot
, rm
);
7811 case 0x121: /* mov reg, drN */
7812 case 0x123: /* mov drN, reg */
7814 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7816 modrm
= cpu_ldub_code(env
, s
->pc
++);
7817 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7818 * AMD documentation (24594.pdf) and testing of
7819 * intel 386 and 486 processors all show that the mod bits
7820 * are assumed to be 1's, regardless of actual values.
7822 rm
= (modrm
& 7) | REX_B(s
);
7823 reg
= ((modrm
>> 3) & 7) | rex_r
;
7828 /* XXX: do it dynamically with CR4.DE bit */
7829 if (reg
== 4 || reg
== 5 || reg
>= 8)
7832 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7833 gen_op_mov_TN_reg(ot
, 0, rm
);
7834 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7835 gen_jmp_im(s
->pc
- s
->cs_base
);
7838 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7839 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7840 gen_op_mov_reg_T0(ot
, rm
);
7844 case 0x106: /* clts */
7846 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7848 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7849 gen_helper_clts(cpu_env
);
7850 /* abort block because static cpu state changed */
7851 gen_jmp_im(s
->pc
- s
->cs_base
);
7855 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7856 case 0x1c3: /* MOVNTI reg, mem */
7857 if (!(s
->cpuid_features
& CPUID_SSE2
))
7859 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
7860 modrm
= cpu_ldub_code(env
, s
->pc
++);
7861 mod
= (modrm
>> 6) & 3;
7864 reg
= ((modrm
>> 3) & 7) | rex_r
;
7865 /* generate a generic store */
7866 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7869 modrm
= cpu_ldub_code(env
, s
->pc
++);
7870 mod
= (modrm
>> 6) & 3;
7871 op
= (modrm
>> 3) & 7;
7873 case 0: /* fxsave */
7874 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7875 (s
->prefix
& PREFIX_LOCK
))
7877 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7878 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7881 gen_lea_modrm(env
, s
, modrm
);
7882 gen_update_cc_op(s
);
7883 gen_jmp_im(pc_start
- s
->cs_base
);
7884 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7886 case 1: /* fxrstor */
7887 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7888 (s
->prefix
& PREFIX_LOCK
))
7890 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7891 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7894 gen_lea_modrm(env
, s
, modrm
);
7895 gen_update_cc_op(s
);
7896 gen_jmp_im(pc_start
- s
->cs_base
);
7897 gen_helper_fxrstor(cpu_env
, cpu_A0
,
7898 tcg_const_i32((s
->dflag
== 2)));
7900 case 2: /* ldmxcsr */
7901 case 3: /* stmxcsr */
7902 if (s
->flags
& HF_TS_MASK
) {
7903 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7906 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7909 gen_lea_modrm(env
, s
, modrm
);
7911 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
7912 s
->mem_index
, MO_LEUL
);
7913 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7915 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7916 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
7919 case 5: /* lfence */
7920 case 6: /* mfence */
7921 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7924 case 7: /* sfence / clflush */
7925 if ((modrm
& 0xc7) == 0xc0) {
7927 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7928 if (!(s
->cpuid_features
& CPUID_SSE
))
7932 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7934 gen_lea_modrm(env
, s
, modrm
);
7941 case 0x10d: /* 3DNow! prefetch(w) */
7942 modrm
= cpu_ldub_code(env
, s
->pc
++);
7943 mod
= (modrm
>> 6) & 3;
7946 gen_lea_modrm(env
, s
, modrm
);
7947 /* ignore for now */
7949 case 0x1aa: /* rsm */
7950 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7951 if (!(s
->flags
& HF_SMM_MASK
))
7953 gen_update_cc_op(s
);
7954 gen_jmp_im(s
->pc
- s
->cs_base
);
7955 gen_helper_rsm(cpu_env
);
7958 case 0x1b8: /* SSE4.2 popcnt */
7959 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7962 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7965 modrm
= cpu_ldub_code(env
, s
->pc
++);
7966 reg
= ((modrm
>> 3) & 7) | rex_r
;
7968 if (s
->prefix
& PREFIX_DATA
)
7970 else if (s
->dflag
!= 2)
7975 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7976 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7977 gen_op_mov_reg_T0(ot
, reg
);
7979 set_cc_op(s
, CC_OP_EFLAGS
);
7981 case 0x10e ... 0x10f:
7982 /* 3DNow! instructions, ignore prefixes */
7983 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7984 case 0x110 ... 0x117:
7985 case 0x128 ... 0x12f:
7986 case 0x138 ... 0x13a:
7987 case 0x150 ... 0x179:
7988 case 0x17c ... 0x17f:
7990 case 0x1c4 ... 0x1c6:
7991 case 0x1d0 ... 0x1fe:
7992 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7997 /* lock generation */
7998 if (s
->prefix
& PREFIX_LOCK
)
7999 gen_helper_unlock();
8002 if (s
->prefix
& PREFIX_LOCK
)
8003 gen_helper_unlock();
8004 /* XXX: ensure that no lock was generated */
8005 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
8009 void optimize_flags_init(void)
8011 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
8012 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
8013 offsetof(CPUX86State
, cc_op
), "cc_op");
8014 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
8016 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
8018 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src2
),
8021 #ifdef TARGET_X86_64
8022 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
8023 offsetof(CPUX86State
, regs
[R_EAX
]), "rax");
8024 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
8025 offsetof(CPUX86State
, regs
[R_ECX
]), "rcx");
8026 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
8027 offsetof(CPUX86State
, regs
[R_EDX
]), "rdx");
8028 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
8029 offsetof(CPUX86State
, regs
[R_EBX
]), "rbx");
8030 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
8031 offsetof(CPUX86State
, regs
[R_ESP
]), "rsp");
8032 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
8033 offsetof(CPUX86State
, regs
[R_EBP
]), "rbp");
8034 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
8035 offsetof(CPUX86State
, regs
[R_ESI
]), "rsi");
8036 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
8037 offsetof(CPUX86State
, regs
[R_EDI
]), "rdi");
8038 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
8039 offsetof(CPUX86State
, regs
[8]), "r8");
8040 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
8041 offsetof(CPUX86State
, regs
[9]), "r9");
8042 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
8043 offsetof(CPUX86State
, regs
[10]), "r10");
8044 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
8045 offsetof(CPUX86State
, regs
[11]), "r11");
8046 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
8047 offsetof(CPUX86State
, regs
[12]), "r12");
8048 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
8049 offsetof(CPUX86State
, regs
[13]), "r13");
8050 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
8051 offsetof(CPUX86State
, regs
[14]), "r14");
8052 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
8053 offsetof(CPUX86State
, regs
[15]), "r15");
8055 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
8056 offsetof(CPUX86State
, regs
[R_EAX
]), "eax");
8057 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
8058 offsetof(CPUX86State
, regs
[R_ECX
]), "ecx");
8059 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
8060 offsetof(CPUX86State
, regs
[R_EDX
]), "edx");
8061 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
8062 offsetof(CPUX86State
, regs
[R_EBX
]), "ebx");
8063 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
8064 offsetof(CPUX86State
, regs
[R_ESP
]), "esp");
8065 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
8066 offsetof(CPUX86State
, regs
[R_EBP
]), "ebp");
8067 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
8068 offsetof(CPUX86State
, regs
[R_ESI
]), "esi");
8069 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
8070 offsetof(CPUX86State
, regs
[R_EDI
]), "edi");
8074 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
8075 basic block 'tb'. If search_pc is TRUE, also generate PC
8076 information for each intermediate instruction. */
8077 static inline void gen_intermediate_code_internal(X86CPU
*cpu
,
8078 TranslationBlock
*tb
,
8081 CPUState
*cs
= CPU(cpu
);
8082 CPUX86State
*env
= &cpu
->env
;
8083 DisasContext dc1
, *dc
= &dc1
;
8084 target_ulong pc_ptr
;
8085 uint16_t *gen_opc_end
;
8089 target_ulong pc_start
;
8090 target_ulong cs_base
;
8094 /* generate intermediate code */
8096 cs_base
= tb
->cs_base
;
8099 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
8100 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
8101 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
8102 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
8104 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
8105 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
8106 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
8107 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
8108 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
8109 dc
->cc_op
= CC_OP_DYNAMIC
;
8110 dc
->cc_op_dirty
= false;
8111 dc
->cs_base
= cs_base
;
8113 dc
->popl_esp_hack
= 0;
8114 /* select memory access functions */
8116 if (flags
& HF_SOFTMMU_MASK
) {
8117 dc
->mem_index
= cpu_mmu_index(env
);
8119 dc
->cpuid_features
= env
->features
[FEAT_1_EDX
];
8120 dc
->cpuid_ext_features
= env
->features
[FEAT_1_ECX
];
8121 dc
->cpuid_ext2_features
= env
->features
[FEAT_8000_0001_EDX
];
8122 dc
->cpuid_ext3_features
= env
->features
[FEAT_8000_0001_ECX
];
8123 dc
->cpuid_7_0_ebx_features
= env
->features
[FEAT_7_0_EBX
];
8124 #ifdef TARGET_X86_64
8125 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
8126 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
8129 dc
->jmp_opt
= !(dc
->tf
|| cs
->singlestep_enabled
||
8130 (flags
& HF_INHIBIT_IRQ_MASK
)
8131 #ifndef CONFIG_SOFTMMU
8132 || (flags
& HF_SOFTMMU_MASK
)
8136 /* check addseg logic */
8137 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
8138 printf("ERROR addseg\n");
8141 cpu_T
[0] = tcg_temp_new();
8142 cpu_T
[1] = tcg_temp_new();
8143 cpu_A0
= tcg_temp_new();
8145 cpu_tmp0
= tcg_temp_new();
8146 cpu_tmp1_i64
= tcg_temp_new_i64();
8147 cpu_tmp2_i32
= tcg_temp_new_i32();
8148 cpu_tmp3_i32
= tcg_temp_new_i32();
8149 cpu_tmp4
= tcg_temp_new();
8150 cpu_ptr0
= tcg_temp_new_ptr();
8151 cpu_ptr1
= tcg_temp_new_ptr();
8152 cpu_cc_srcT
= tcg_temp_local_new();
8154 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
8156 dc
->is_jmp
= DISAS_NEXT
;
8160 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8162 max_insns
= CF_COUNT_MASK
;
8166 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
8167 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8168 if (bp
->pc
== pc_ptr
&&
8169 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
8170 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
8176 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8180 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8182 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
8183 gen_opc_cc_op
[lj
] = dc
->cc_op
;
8184 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
8185 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
8187 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8190 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
8192 /* stop translation if indicated */
8195 /* if single step mode, we generate only one instruction and
8196 generate an exception */
8197 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8198 the flag and abort the translation to give the irqs a
8199 change to be happen */
8200 if (dc
->tf
|| dc
->singlestep_enabled
||
8201 (flags
& HF_INHIBIT_IRQ_MASK
)) {
8202 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8206 /* if too long translation, stop generation too */
8207 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
8208 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
8209 num_insns
>= max_insns
) {
8210 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8215 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8220 if (tb
->cflags
& CF_LAST_IO
)
8222 gen_tb_end(tb
, num_insns
);
8223 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
8224 /* we don't forget to fill the last values */
8226 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8229 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8233 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8235 qemu_log("----------------\n");
8236 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8237 #ifdef TARGET_X86_64
8242 disas_flags
= !dc
->code32
;
8243 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8249 tb
->size
= pc_ptr
- pc_start
;
8250 tb
->icount
= num_insns
;
8254 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8256 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, false);
8259 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8261 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, true);
8264 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8268 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8270 qemu_log("RESTORE:\n");
8271 for(i
= 0;i
<= pc_pos
; i
++) {
8272 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8273 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8274 tcg_ctx
.gen_opc_pc
[i
]);
8277 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8278 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8279 (uint32_t)tb
->cs_base
);
8282 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8283 cc_op
= gen_opc_cc_op
[pc_pos
];
8284 if (cc_op
!= CC_OP_DYNAMIC
)