4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
40 #define PREFIX_VEX 0x20
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
60 //#define MACRO_TEST 1
62 /* global register indexes */
63 static TCGv_ptr cpu_env
;
65 static TCGv cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
, cpu_cc_srcT
;
66 static TCGv_i32 cpu_cc_op
;
67 static TCGv cpu_regs
[CPU_NB_REGS
];
70 /* local register indexes (only used inside old micro ops) */
71 static TCGv cpu_tmp0
, cpu_tmp4
;
72 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
73 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
74 static TCGv_i64 cpu_tmp1_i64
;
76 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
78 #include "exec/gen-icount.h"
81 static int x86_64_hregs
;
84 typedef struct DisasContext
{
85 /* current insn context */
86 int override
; /* -1 if no override */
90 target_ulong pc
; /* pc = eip + cs_base */
91 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
92 static state change (stop translation) */
93 /* current block context */
94 target_ulong cs_base
; /* base of CS segment */
95 int pe
; /* protected mode */
96 int code32
; /* 32 bit code segment */
98 int lma
; /* long mode active */
99 int code64
; /* 64 bit code segment */
102 int vex_l
; /* vex vector length */
103 int vex_v
; /* vex vvvv register, without 1's compliment. */
104 int ss32
; /* 32 bit stack segment */
105 CCOp cc_op
; /* current CC operation */
107 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
108 int f_st
; /* currently unused */
109 int vm86
; /* vm86 mode */
112 int tf
; /* TF cpu flag */
113 int singlestep_enabled
; /* "hardware" single step enabled */
114 int jmp_opt
; /* use direct block chaining for direct jumps */
115 int mem_index
; /* select memory access functions */
116 uint64_t flags
; /* all execution flags */
117 struct TranslationBlock
*tb
;
118 int popl_esp_hack
; /* for correct popl with esp base handling */
119 int rip_offset
; /* only used in x86_64, but left for simplicity */
121 int cpuid_ext_features
;
122 int cpuid_ext2_features
;
123 int cpuid_ext3_features
;
124 int cpuid_7_0_ebx_features
;
127 static void gen_eob(DisasContext
*s
);
128 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
129 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
130 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
);
132 /* i386 arith/logic operations */
152 OP_SHL1
, /* undocumented */
168 /* I386 int registers */
169 OR_EAX
, /* MUST be even numbered */
178 OR_TMP0
= 16, /* temporary operand register */
180 OR_A0
, /* temporary register used when doing address evaluation */
190 /* Bit set if the global variable is live after setting CC_OP to X. */
191 static const uint8_t cc_op_live
[CC_OP_NB
] = {
192 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
193 [CC_OP_EFLAGS
] = USES_CC_SRC
,
194 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
195 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
196 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
197 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
198 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
199 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
200 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
202 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
204 [CC_OP_BMILGB
... CC_OP_BMILGQ
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_ADCX
] = USES_CC_DST
| USES_CC_SRC
,
206 [CC_OP_ADOX
] = USES_CC_SRC
| USES_CC_SRC2
,
207 [CC_OP_ADCOX
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
211 static void set_cc_op(DisasContext
*s
, CCOp op
)
215 if (s
->cc_op
== op
) {
219 /* Discard CC computation that will no longer be used. */
220 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
221 if (dead
& USES_CC_DST
) {
222 tcg_gen_discard_tl(cpu_cc_dst
);
224 if (dead
& USES_CC_SRC
) {
225 tcg_gen_discard_tl(cpu_cc_src
);
227 if (dead
& USES_CC_SRC2
) {
228 tcg_gen_discard_tl(cpu_cc_src2
);
230 if (dead
& USES_CC_SRCT
) {
231 tcg_gen_discard_tl(cpu_cc_srcT
);
234 if (op
== CC_OP_DYNAMIC
) {
235 /* The DYNAMIC setting is translator only, and should never be
236 stored. Thus we always consider it clean. */
237 s
->cc_op_dirty
= false;
239 /* Discard any computed CC_OP value (see shifts). */
240 if (s
->cc_op
== CC_OP_DYNAMIC
) {
241 tcg_gen_discard_i32(cpu_cc_op
);
243 s
->cc_op_dirty
= true;
248 static void gen_update_cc_op(DisasContext
*s
)
250 if (s
->cc_op_dirty
) {
251 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
252 s
->cc_op_dirty
= false;
258 #define NB_OP_SIZES 4
260 #else /* !TARGET_X86_64 */
262 #define NB_OP_SIZES 3
264 #endif /* !TARGET_X86_64 */
266 #if defined(HOST_WORDS_BIGENDIAN)
267 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
268 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
269 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
270 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
271 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
273 #define REG_B_OFFSET 0
274 #define REG_H_OFFSET 1
275 #define REG_W_OFFSET 0
276 #define REG_L_OFFSET 0
277 #define REG_LH_OFFSET 4
280 /* In instruction encodings for byte register accesses the
281 * register number usually indicates "low 8 bits of register N";
282 * however there are some special cases where N 4..7 indicates
283 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
284 * true for this special case, false otherwise.
286 static inline bool byte_reg_is_xH(int reg
)
292 if (reg
>= 8 || x86_64_hregs
) {
299 /* Select the size of a push/pop operation. */
300 static inline TCGMemOp
mo_pushpop(DisasContext
*s
, TCGMemOp ot
)
303 return ot
== MO_16
? MO_16
: MO_64
;
309 /* Select only size 64 else 32. Used for SSE operand sizes. */
310 static inline TCGMemOp
mo_64_32(TCGMemOp ot
)
313 return ot
== MO_64
? MO_64
: MO_32
;
319 /* Select size 8 if lsb of B is clear, else OT. Used for decoding
320 byte vs word opcodes. */
321 static inline TCGMemOp
mo_b_d(int b
, TCGMemOp ot
)
323 return b
& 1 ? ot
: MO_8
;
326 /* Select size 8 if lsb of B is clear, else OT capped at 32.
327 Used for decoding operand size of port opcodes. */
328 static inline TCGMemOp
mo_b_d32(int b
, TCGMemOp ot
)
330 return b
& 1 ? (ot
== MO_16
? MO_16
: MO_32
) : MO_8
;
333 static void gen_op_mov_reg_v(TCGMemOp ot
, int reg
, TCGv t0
)
337 if (!byte_reg_is_xH(reg
)) {
338 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
340 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
344 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
347 /* For x86_64, this sets the higher half of register to zero.
348 For i386, this is equivalent to a mov. */
349 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
353 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
361 static inline void gen_op_mov_reg_T1(TCGMemOp ot
, int reg
)
363 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
366 static inline void gen_op_mov_reg_A0(TCGMemOp size
, int reg
)
368 gen_op_mov_reg_v(size
, reg
, cpu_A0
);
371 static inline void gen_op_mov_v_reg(TCGMemOp ot
, TCGv t0
, int reg
)
373 if (ot
== MO_8
&& byte_reg_is_xH(reg
)) {
374 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
375 tcg_gen_ext8u_tl(t0
, t0
);
377 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
381 static inline void gen_op_mov_TN_reg(TCGMemOp ot
, int t_index
, int reg
)
383 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
386 static inline void gen_op_movl_A0_reg(int reg
)
388 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
391 static inline void gen_op_addl_A0_im(int32_t val
)
393 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
395 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
400 static inline void gen_op_addq_A0_im(int64_t val
)
402 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
406 static void gen_add_A0_im(DisasContext
*s
, int val
)
410 gen_op_addq_A0_im(val
);
413 gen_op_addl_A0_im(val
);
416 static inline void gen_op_addl_T0_T1(void)
418 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
421 static inline void gen_op_jmp_T0(void)
423 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
426 static inline void gen_op_add_reg_im(TCGMemOp size
, int reg
, int32_t val
)
428 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
429 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
432 static inline void gen_op_add_reg_T0(TCGMemOp size
, int reg
)
434 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
435 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
438 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
440 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
442 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
443 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
444 /* For x86_64, this sets the higher half of register to zero.
445 For i386, this is equivalent to a nop. */
446 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
449 static inline void gen_op_movl_A0_seg(int reg
)
451 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
454 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
456 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
459 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
460 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
462 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
463 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
466 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
471 static inline void gen_op_movq_A0_seg(int reg
)
473 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
476 static inline void gen_op_addq_A0_seg(int reg
)
478 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
479 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
482 static inline void gen_op_movq_A0_reg(int reg
)
484 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
487 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
489 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
491 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
492 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
496 static inline void gen_op_ld_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
498 tcg_gen_qemu_ld_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
501 static inline void gen_op_st_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
503 tcg_gen_qemu_st_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
506 static inline void gen_op_st_rm_T0_A0(DisasContext
*s
, int idx
, int d
)
509 gen_op_st_v(s
, idx
, cpu_T
[0], cpu_A0
);
511 gen_op_mov_reg_v(idx
, d
, cpu_T
[0]);
515 static inline void gen_jmp_im(target_ulong pc
)
517 tcg_gen_movi_tl(cpu_tmp0
, pc
);
518 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
521 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
525 override
= s
->override
;
530 gen_op_movq_A0_seg(override
);
531 gen_op_addq_A0_reg_sN(0, R_ESI
);
533 gen_op_movq_A0_reg(R_ESI
);
539 if (s
->addseg
&& override
< 0)
542 gen_op_movl_A0_seg(override
);
543 gen_op_addl_A0_reg_sN(0, R_ESI
);
545 gen_op_movl_A0_reg(R_ESI
);
549 /* 16 address, always override */
552 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESI
]);
553 gen_op_addl_A0_seg(s
, override
);
560 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
565 gen_op_movq_A0_reg(R_EDI
);
570 gen_op_movl_A0_seg(R_ES
);
571 gen_op_addl_A0_reg_sN(0, R_EDI
);
573 gen_op_movl_A0_reg(R_EDI
);
577 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_EDI
]);
578 gen_op_addl_A0_seg(s
, R_ES
);
585 static inline void gen_op_movl_T0_Dshift(TCGMemOp ot
)
587 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
588 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
591 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, TCGMemOp size
, bool sign
)
596 tcg_gen_ext8s_tl(dst
, src
);
598 tcg_gen_ext8u_tl(dst
, src
);
603 tcg_gen_ext16s_tl(dst
, src
);
605 tcg_gen_ext16u_tl(dst
, src
);
611 tcg_gen_ext32s_tl(dst
, src
);
613 tcg_gen_ext32u_tl(dst
, src
);
622 static void gen_extu(TCGMemOp ot
, TCGv reg
)
624 gen_ext_tl(reg
, reg
, ot
, false);
627 static void gen_exts(TCGMemOp ot
, TCGv reg
)
629 gen_ext_tl(reg
, reg
, ot
, true);
632 static inline void gen_op_jnz_ecx(TCGMemOp size
, int label1
)
634 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
635 gen_extu(size
, cpu_tmp0
);
636 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
639 static inline void gen_op_jz_ecx(TCGMemOp size
, int label1
)
641 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
642 gen_extu(size
, cpu_tmp0
);
643 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
646 static void gen_helper_in_func(TCGMemOp ot
, TCGv v
, TCGv_i32 n
)
650 gen_helper_inb(v
, n
);
653 gen_helper_inw(v
, n
);
656 gen_helper_inl(v
, n
);
663 static void gen_helper_out_func(TCGMemOp ot
, TCGv_i32 v
, TCGv_i32 n
)
667 gen_helper_outb(v
, n
);
670 gen_helper_outw(v
, n
);
673 gen_helper_outl(v
, n
);
680 static void gen_check_io(DisasContext
*s
, TCGMemOp ot
, target_ulong cur_eip
,
684 target_ulong next_eip
;
687 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
691 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
694 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
697 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
700 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
706 if(s
->flags
& HF_SVMI_MASK
) {
711 svm_flags
|= (1 << (4 + ot
));
712 next_eip
= s
->pc
- s
->cs_base
;
713 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
714 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
715 tcg_const_i32(svm_flags
),
716 tcg_const_i32(next_eip
- cur_eip
));
720 static inline void gen_movs(DisasContext
*s
, TCGMemOp ot
)
722 gen_string_movl_A0_ESI(s
);
723 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
724 gen_string_movl_A0_EDI(s
);
725 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
726 gen_op_movl_T0_Dshift(ot
);
727 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
728 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
731 static void gen_op_update1_cc(void)
733 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
736 static void gen_op_update2_cc(void)
738 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
739 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
742 static void gen_op_update3_cc(TCGv reg
)
744 tcg_gen_mov_tl(cpu_cc_src2
, reg
);
745 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
746 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
749 static inline void gen_op_testl_T0_T1_cc(void)
751 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
754 static void gen_op_update_neg_cc(void)
756 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
757 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
758 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
761 /* compute all eflags to cc_src */
762 static void gen_compute_eflags(DisasContext
*s
)
764 TCGv zero
, dst
, src1
, src2
;
767 if (s
->cc_op
== CC_OP_EFLAGS
) {
770 if (s
->cc_op
== CC_OP_CLR
) {
771 tcg_gen_movi_tl(cpu_cc_src
, CC_Z
);
772 set_cc_op(s
, CC_OP_EFLAGS
);
781 /* Take care to not read values that are not live. */
782 live
= cc_op_live
[s
->cc_op
] & ~USES_CC_SRCT
;
783 dead
= live
^ (USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
);
785 zero
= tcg_const_tl(0);
786 if (dead
& USES_CC_DST
) {
789 if (dead
& USES_CC_SRC
) {
792 if (dead
& USES_CC_SRC2
) {
798 gen_helper_cc_compute_all(cpu_cc_src
, dst
, src1
, src2
, cpu_cc_op
);
799 set_cc_op(s
, CC_OP_EFLAGS
);
806 typedef struct CCPrepare
{
816 /* compute eflags.C to reg */
817 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
823 case CC_OP_SUBB
... CC_OP_SUBQ
:
824 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
825 size
= s
->cc_op
- CC_OP_SUBB
;
826 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
827 /* If no temporary was used, be careful not to alias t1 and t0. */
828 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
829 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
833 case CC_OP_ADDB
... CC_OP_ADDQ
:
834 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
835 size
= s
->cc_op
- CC_OP_ADDB
;
836 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
837 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
839 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
840 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
842 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
844 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
846 case CC_OP_INCB
... CC_OP_INCQ
:
847 case CC_OP_DECB
... CC_OP_DECQ
:
848 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
849 .mask
= -1, .no_setcond
= true };
851 case CC_OP_SHLB
... CC_OP_SHLQ
:
852 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
853 size
= s
->cc_op
- CC_OP_SHLB
;
854 shift
= (8 << size
) - 1;
855 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
856 .mask
= (target_ulong
)1 << shift
};
858 case CC_OP_MULB
... CC_OP_MULQ
:
859 return (CCPrepare
) { .cond
= TCG_COND_NE
,
860 .reg
= cpu_cc_src
, .mask
= -1 };
862 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
863 size
= s
->cc_op
- CC_OP_BMILGB
;
864 t0
= gen_ext_tl(reg
, cpu_cc_src
, size
, false);
865 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
869 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_dst
,
870 .mask
= -1, .no_setcond
= true };
873 case CC_OP_SARB
... CC_OP_SARQ
:
875 return (CCPrepare
) { .cond
= TCG_COND_NE
,
876 .reg
= cpu_cc_src
, .mask
= CC_C
};
879 /* The need to compute only C from CC_OP_DYNAMIC is important
880 in efficiently implementing e.g. INC at the start of a TB. */
882 gen_helper_cc_compute_c(reg
, cpu_cc_dst
, cpu_cc_src
,
883 cpu_cc_src2
, cpu_cc_op
);
884 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
885 .mask
= -1, .no_setcond
= true };
889 /* compute eflags.P to reg */
890 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
892 gen_compute_eflags(s
);
893 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
897 /* compute eflags.S to reg */
898 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
902 gen_compute_eflags(s
);
908 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
911 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
914 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
915 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
916 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
921 /* compute eflags.O to reg */
922 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
927 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src2
,
928 .mask
= -1, .no_setcond
= true };
930 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
932 gen_compute_eflags(s
);
933 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
938 /* compute eflags.Z to reg */
939 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
943 gen_compute_eflags(s
);
949 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
952 return (CCPrepare
) { .cond
= TCG_COND_ALWAYS
, .mask
= -1 };
955 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
956 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
957 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
962 /* perform a conditional store into register 'reg' according to jump opcode
963 value 'b'. In the fast case, T0 is guaranted not to be used. */
964 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
966 int inv
, jcc_op
, cond
;
972 jcc_op
= (b
>> 1) & 7;
975 case CC_OP_SUBB
... CC_OP_SUBQ
:
976 /* We optimize relational operators for the cmp/jcc case. */
977 size
= s
->cc_op
- CC_OP_SUBB
;
980 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
981 gen_extu(size
, cpu_tmp4
);
982 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
983 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
984 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
993 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
994 gen_exts(size
, cpu_tmp4
);
995 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
996 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
997 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1007 /* This actually generates good code for JC, JZ and JS. */
1010 cc
= gen_prepare_eflags_o(s
, reg
);
1013 cc
= gen_prepare_eflags_c(s
, reg
);
1016 cc
= gen_prepare_eflags_z(s
, reg
);
1019 gen_compute_eflags(s
);
1020 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1021 .mask
= CC_Z
| CC_C
};
1024 cc
= gen_prepare_eflags_s(s
, reg
);
1027 cc
= gen_prepare_eflags_p(s
, reg
);
1030 gen_compute_eflags(s
);
1031 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1034 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1035 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1036 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1041 gen_compute_eflags(s
);
1042 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1045 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1046 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1047 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1048 .mask
= CC_S
| CC_Z
};
1055 cc
.cond
= tcg_invert_cond(cc
.cond
);
1060 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1062 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1064 if (cc
.no_setcond
) {
1065 if (cc
.cond
== TCG_COND_EQ
) {
1066 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1068 tcg_gen_mov_tl(reg
, cc
.reg
);
1073 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1074 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1075 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1076 tcg_gen_andi_tl(reg
, reg
, 1);
1079 if (cc
.mask
!= -1) {
1080 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1084 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1086 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1090 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1092 gen_setcc1(s
, JCC_B
<< 1, reg
);
1095 /* generate a conditional jump to label 'l1' according to jump opcode
1096 value 'b'. In the fast case, T0 is guaranted not to be used. */
1097 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1099 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1101 if (cc
.mask
!= -1) {
1102 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1106 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1108 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1112 /* Generate a conditional jump to label 'l1' according to jump opcode
1113 value 'b'. In the fast case, T0 is guaranted not to be used.
1114 A translation block must end soon. */
1115 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1117 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1119 gen_update_cc_op(s
);
1120 if (cc
.mask
!= -1) {
1121 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1124 set_cc_op(s
, CC_OP_DYNAMIC
);
1126 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1128 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1132 /* XXX: does not work with gdbstub "ice" single step - not a
1134 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1138 l1
= gen_new_label();
1139 l2
= gen_new_label();
1140 gen_op_jnz_ecx(s
->aflag
, l1
);
1142 gen_jmp_tb(s
, next_eip
, 1);
1147 static inline void gen_stos(DisasContext
*s
, TCGMemOp ot
)
1149 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
1150 gen_string_movl_A0_EDI(s
);
1151 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1152 gen_op_movl_T0_Dshift(ot
);
1153 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1156 static inline void gen_lods(DisasContext
*s
, TCGMemOp ot
)
1158 gen_string_movl_A0_ESI(s
);
1159 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1160 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[0]);
1161 gen_op_movl_T0_Dshift(ot
);
1162 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1165 static inline void gen_scas(DisasContext
*s
, TCGMemOp ot
)
1167 gen_string_movl_A0_EDI(s
);
1168 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1169 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1170 gen_op_movl_T0_Dshift(ot
);
1171 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1174 static inline void gen_cmps(DisasContext
*s
, TCGMemOp ot
)
1176 gen_string_movl_A0_EDI(s
);
1177 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1178 gen_string_movl_A0_ESI(s
);
1179 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1180 gen_op_movl_T0_Dshift(ot
);
1181 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1182 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1185 static inline void gen_ins(DisasContext
*s
, TCGMemOp ot
)
1189 gen_string_movl_A0_EDI(s
);
1190 /* Note: we must do this dummy write first to be restartable in
1191 case of page fault. */
1192 tcg_gen_movi_tl(cpu_T
[0], 0);
1193 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1194 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1195 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1196 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1197 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1198 gen_op_movl_T0_Dshift(ot
);
1199 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1204 static inline void gen_outs(DisasContext
*s
, TCGMemOp ot
)
1208 gen_string_movl_A0_ESI(s
);
1209 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1211 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1212 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1213 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1214 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1216 gen_op_movl_T0_Dshift(ot
);
1217 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1222 /* same method as Valgrind : we generate jumps to current or next
1224 #define GEN_REPZ(op) \
1225 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1226 target_ulong cur_eip, target_ulong next_eip) \
1229 gen_update_cc_op(s); \
1230 l2 = gen_jz_ecx_string(s, next_eip); \
1231 gen_ ## op(s, ot); \
1232 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1233 /* a loop would cause two single step exceptions if ECX = 1 \
1234 before rep string_insn */ \
1236 gen_op_jz_ecx(s->aflag, l2); \
1237 gen_jmp(s, cur_eip); \
1240 #define GEN_REPZ2(op) \
1241 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1242 target_ulong cur_eip, \
1243 target_ulong next_eip, \
1247 gen_update_cc_op(s); \
1248 l2 = gen_jz_ecx_string(s, next_eip); \
1249 gen_ ## op(s, ot); \
1250 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1251 gen_update_cc_op(s); \
1252 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1254 gen_op_jz_ecx(s->aflag, l2); \
1255 gen_jmp(s, cur_eip); \
1266 static void gen_helper_fp_arith_ST0_FT0(int op
)
1270 gen_helper_fadd_ST0_FT0(cpu_env
);
1273 gen_helper_fmul_ST0_FT0(cpu_env
);
1276 gen_helper_fcom_ST0_FT0(cpu_env
);
1279 gen_helper_fcom_ST0_FT0(cpu_env
);
1282 gen_helper_fsub_ST0_FT0(cpu_env
);
1285 gen_helper_fsubr_ST0_FT0(cpu_env
);
1288 gen_helper_fdiv_ST0_FT0(cpu_env
);
1291 gen_helper_fdivr_ST0_FT0(cpu_env
);
1296 /* NOTE the exception in "r" op ordering */
1297 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1299 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1302 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1305 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1308 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1311 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1314 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1317 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1322 /* if d == OR_TMP0, it means memory operand (address in A0) */
1323 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
)
1326 gen_op_mov_TN_reg(ot
, 0, d
);
1328 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1332 gen_compute_eflags_c(s1
, cpu_tmp4
);
1333 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1334 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1335 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1336 gen_op_update3_cc(cpu_tmp4
);
1337 set_cc_op(s1
, CC_OP_ADCB
+ ot
);
1340 gen_compute_eflags_c(s1
, cpu_tmp4
);
1341 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1342 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1343 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1344 gen_op_update3_cc(cpu_tmp4
);
1345 set_cc_op(s1
, CC_OP_SBBB
+ ot
);
1348 gen_op_addl_T0_T1();
1349 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1350 gen_op_update2_cc();
1351 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1354 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1355 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1356 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1357 gen_op_update2_cc();
1358 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1362 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1363 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1364 gen_op_update1_cc();
1365 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1368 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1369 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1370 gen_op_update1_cc();
1371 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1374 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1375 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1376 gen_op_update1_cc();
1377 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1380 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1381 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1382 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1383 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1388 /* if d == OR_TMP0, it means memory operand (address in A0) */
1389 static void gen_inc(DisasContext
*s1
, TCGMemOp ot
, int d
, int c
)
1392 gen_op_mov_TN_reg(ot
, 0, d
);
1394 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1396 gen_compute_eflags_c(s1
, cpu_cc_src
);
1398 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1399 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1401 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1402 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1404 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1405 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1408 static void gen_shift_flags(DisasContext
*s
, TCGMemOp ot
, TCGv result
,
1409 TCGv shm1
, TCGv count
, bool is_right
)
1411 TCGv_i32 z32
, s32
, oldop
;
1414 /* Store the results into the CC variables. If we know that the
1415 variable must be dead, store unconditionally. Otherwise we'll
1416 need to not disrupt the current contents. */
1417 z_tl
= tcg_const_tl(0);
1418 if (cc_op_live
[s
->cc_op
] & USES_CC_DST
) {
1419 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_dst
, count
, z_tl
,
1420 result
, cpu_cc_dst
);
1422 tcg_gen_mov_tl(cpu_cc_dst
, result
);
1424 if (cc_op_live
[s
->cc_op
] & USES_CC_SRC
) {
1425 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_src
, count
, z_tl
,
1428 tcg_gen_mov_tl(cpu_cc_src
, shm1
);
1430 tcg_temp_free(z_tl
);
1432 /* Get the two potential CC_OP values into temporaries. */
1433 tcg_gen_movi_i32(cpu_tmp2_i32
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1434 if (s
->cc_op
== CC_OP_DYNAMIC
) {
1437 tcg_gen_movi_i32(cpu_tmp3_i32
, s
->cc_op
);
1438 oldop
= cpu_tmp3_i32
;
1441 /* Conditionally store the CC_OP value. */
1442 z32
= tcg_const_i32(0);
1443 s32
= tcg_temp_new_i32();
1444 tcg_gen_trunc_tl_i32(s32
, count
);
1445 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, s32
, z32
, cpu_tmp2_i32
, oldop
);
1446 tcg_temp_free_i32(z32
);
1447 tcg_temp_free_i32(s32
);
1449 /* The CC_OP value is no longer predictable. */
1450 set_cc_op(s
, CC_OP_DYNAMIC
);
1453 static void gen_shift_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1454 int is_right
, int is_arith
)
1456 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1459 if (op1
== OR_TMP0
) {
1460 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1462 gen_op_mov_TN_reg(ot
, 0, op1
);
1465 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1466 tcg_gen_subi_tl(cpu_tmp0
, cpu_T
[1], 1);
1470 gen_exts(ot
, cpu_T
[0]);
1471 tcg_gen_sar_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1472 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1474 gen_extu(ot
, cpu_T
[0]);
1475 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1476 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1479 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1480 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1484 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1486 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, cpu_T
[1], is_right
);
1489 static void gen_shift_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1490 int is_right
, int is_arith
)
1492 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1496 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1498 gen_op_mov_TN_reg(ot
, 0, op1
);
1504 gen_exts(ot
, cpu_T
[0]);
1505 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1506 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1508 gen_extu(ot
, cpu_T
[0]);
1509 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1510 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1513 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1514 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1519 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1521 /* update eflags if non zero shift */
1523 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1524 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1525 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1529 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1532 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1534 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1537 static void gen_rot_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
, int is_right
)
1539 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1543 if (op1
== OR_TMP0
) {
1544 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1546 gen_op_mov_TN_reg(ot
, 0, op1
);
1549 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1553 /* Replicate the 8-bit input so that a 32-bit rotate works. */
1554 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
1555 tcg_gen_muli_tl(cpu_T
[0], cpu_T
[0], 0x01010101);
1558 /* Replicate the 16-bit input so that a 32-bit rotate works. */
1559 tcg_gen_deposit_tl(cpu_T
[0], cpu_T
[0], cpu_T
[0], 16, 16);
1562 #ifdef TARGET_X86_64
1564 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1565 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
1567 tcg_gen_rotr_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1569 tcg_gen_rotl_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1571 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1576 tcg_gen_rotr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1578 tcg_gen_rotl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1584 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1586 /* We'll need the flags computed into CC_SRC. */
1587 gen_compute_eflags(s
);
1589 /* The value that was "rotated out" is now present at the other end
1590 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1591 since we've computed the flags into CC_SRC, these variables are
1594 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1595 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1596 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1598 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1599 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1601 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1602 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1604 /* Now conditionally store the new CC_OP value. If the shift count
1605 is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
1606 Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
1607 exactly as we computed above. */
1608 t0
= tcg_const_i32(0);
1609 t1
= tcg_temp_new_i32();
1610 tcg_gen_trunc_tl_i32(t1
, cpu_T
[1]);
1611 tcg_gen_movi_i32(cpu_tmp2_i32
, CC_OP_ADCOX
);
1612 tcg_gen_movi_i32(cpu_tmp3_i32
, CC_OP_EFLAGS
);
1613 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, t1
, t0
,
1614 cpu_tmp2_i32
, cpu_tmp3_i32
);
1615 tcg_temp_free_i32(t0
);
1616 tcg_temp_free_i32(t1
);
1618 /* The CC_OP value is no longer predictable. */
1619 set_cc_op(s
, CC_OP_DYNAMIC
);
1622 static void gen_rot_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1625 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1629 if (op1
== OR_TMP0
) {
1630 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1632 gen_op_mov_TN_reg(ot
, 0, op1
);
1638 #ifdef TARGET_X86_64
1640 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1642 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1644 tcg_gen_rotli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1646 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1651 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], op2
);
1653 tcg_gen_rotli_tl(cpu_T
[0], cpu_T
[0], op2
);
1664 shift
= mask
+ 1 - shift
;
1666 gen_extu(ot
, cpu_T
[0]);
1667 tcg_gen_shli_tl(cpu_tmp0
, cpu_T
[0], shift
);
1668 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], mask
+ 1 - shift
);
1669 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
1675 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1678 /* Compute the flags into CC_SRC. */
1679 gen_compute_eflags(s
);
1681 /* The value that was "rotated out" is now present at the other end
1682 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1683 since we've computed the flags into CC_SRC, these variables are
1686 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1687 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1688 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1690 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1691 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1693 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1694 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1695 set_cc_op(s
, CC_OP_ADCOX
);
1699 /* XXX: add faster immediate = 1 case */
1700 static void gen_rotc_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1703 gen_compute_eflags(s
);
1704 assert(s
->cc_op
== CC_OP_EFLAGS
);
1708 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1710 gen_op_mov_TN_reg(ot
, 0, op1
);
1715 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1718 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1721 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1723 #ifdef TARGET_X86_64
1725 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1734 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1737 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1740 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1742 #ifdef TARGET_X86_64
1744 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1752 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1755 /* XXX: add faster immediate case */
1756 static void gen_shiftd_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1757 bool is_right
, TCGv count_in
)
1759 target_ulong mask
= (ot
== MO_64
? 63 : 31);
1763 if (op1
== OR_TMP0
) {
1764 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1766 gen_op_mov_TN_reg(ot
, 0, op1
);
1769 count
= tcg_temp_new();
1770 tcg_gen_andi_tl(count
, count_in
, mask
);
1774 /* Note: we implement the Intel behaviour for shift count > 16.
1775 This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
1776 portion by constructing it as a 32-bit value. */
1778 tcg_gen_deposit_tl(cpu_tmp0
, cpu_T
[0], cpu_T
[1], 16, 16);
1779 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1780 tcg_gen_mov_tl(cpu_T
[0], cpu_tmp0
);
1782 tcg_gen_deposit_tl(cpu_T
[1], cpu_T
[0], cpu_T
[1], 16, 16);
1785 #ifdef TARGET_X86_64
1787 /* Concatenate the two 32-bit values and use a 64-bit shift. */
1788 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1790 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1791 tcg_gen_shr_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1792 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], count
);
1794 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[1], cpu_T
[0]);
1795 tcg_gen_shl_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1796 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], count
);
1797 tcg_gen_shri_i64(cpu_tmp0
, cpu_tmp0
, 32);
1798 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], 32);
1803 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1805 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1807 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1808 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], count
);
1809 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1811 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1813 /* Only needed if count > 16, for Intel behaviour. */
1814 tcg_gen_subfi_tl(cpu_tmp4
, 33, count
);
1815 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[1], cpu_tmp4
);
1816 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, cpu_tmp4
);
1819 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1820 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], count
);
1821 tcg_gen_shr_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1823 tcg_gen_movi_tl(cpu_tmp4
, 0);
1824 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[1], count
, cpu_tmp4
,
1825 cpu_tmp4
, cpu_T
[1]);
1826 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1831 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1833 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, count
, is_right
);
1834 tcg_temp_free(count
);
1837 static void gen_shift(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int s
)
1840 gen_op_mov_TN_reg(ot
, 1, s
);
1843 gen_rot_rm_T1(s1
, ot
, d
, 0);
1846 gen_rot_rm_T1(s1
, ot
, d
, 1);
1850 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1853 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1856 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1859 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1862 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1867 static void gen_shifti(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int c
)
1871 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1874 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1878 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1881 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1884 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1887 /* currently not optimized */
1888 tcg_gen_movi_tl(cpu_T
[1], c
);
1889 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1894 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
1901 int mod
, rm
, code
, override
, must_add_seg
;
1904 override
= s
->override
;
1905 must_add_seg
= s
->addseg
;
1908 mod
= (modrm
>> 6) & 3;
1921 code
= cpu_ldub_code(env
, s
->pc
++);
1922 scale
= (code
>> 6) & 3;
1923 index
= ((code
>> 3) & 7) | REX_X(s
);
1925 index
= -1; /* no index */
1933 if ((base
& 7) == 5) {
1935 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1937 if (CODE64(s
) && !havesib
) {
1938 disp
+= s
->pc
+ s
->rip_offset
;
1945 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
1949 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1954 /* For correct popl handling with esp. */
1955 if (base
== R_ESP
&& s
->popl_esp_hack
) {
1956 disp
+= s
->popl_esp_hack
;
1959 /* Compute the address, with a minimum number of TCG ops. */
1963 sum
= cpu_regs
[index
];
1965 tcg_gen_shli_tl(cpu_A0
, cpu_regs
[index
], scale
);
1969 tcg_gen_add_tl(cpu_A0
, sum
, cpu_regs
[base
]);
1972 } else if (base
>= 0) {
1973 sum
= cpu_regs
[base
];
1975 if (TCGV_IS_UNUSED(sum
)) {
1976 tcg_gen_movi_tl(cpu_A0
, disp
);
1978 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
1983 if (base
== R_EBP
|| base
== R_ESP
) {
1990 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
1991 offsetof(CPUX86State
, segs
[override
].base
));
1993 if (s
->aflag
== MO_32
) {
1994 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
1996 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
2000 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
2003 if (s
->aflag
== MO_32
) {
2004 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2012 disp
= cpu_lduw_code(env
, s
->pc
);
2014 tcg_gen_movi_tl(cpu_A0
, disp
);
2015 rm
= 0; /* avoid SS override */
2022 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2026 disp
= (int16_t)cpu_lduw_code(env
, s
->pc
);
2034 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_ESI
]);
2037 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_EDI
]);
2040 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_ESI
]);
2043 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_EDI
]);
2046 sum
= cpu_regs
[R_ESI
];
2049 sum
= cpu_regs
[R_EDI
];
2052 sum
= cpu_regs
[R_EBP
];
2056 sum
= cpu_regs
[R_EBX
];
2059 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
2060 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2064 if (rm
== 2 || rm
== 3 || rm
== 6) {
2070 gen_op_addl_A0_seg(s
, override
);
2079 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2081 int mod
, rm
, base
, code
;
2083 mod
= (modrm
>> 6) & 3;
2094 code
= cpu_ldub_code(env
, s
->pc
++);
2136 /* used for LEA and MOV AX, mem */
2137 static void gen_add_A0_ds_seg(DisasContext
*s
)
2139 int override
, must_add_seg
;
2140 must_add_seg
= s
->addseg
;
2142 if (s
->override
>= 0) {
2143 override
= s
->override
;
2147 #ifdef TARGET_X86_64
2149 gen_op_addq_A0_seg(override
);
2153 gen_op_addl_A0_seg(s
, override
);
2158 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2160 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2161 TCGMemOp ot
, int reg
, int is_store
)
2165 mod
= (modrm
>> 6) & 3;
2166 rm
= (modrm
& 7) | REX_B(s
);
2170 gen_op_mov_TN_reg(ot
, 0, reg
);
2171 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
2173 gen_op_mov_TN_reg(ot
, 0, rm
);
2175 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2178 gen_lea_modrm(env
, s
, modrm
);
2181 gen_op_mov_TN_reg(ot
, 0, reg
);
2182 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2184 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
2186 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2191 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
)
2197 ret
= cpu_ldub_code(env
, s
->pc
);
2201 ret
= cpu_lduw_code(env
, s
->pc
);
2205 #ifdef TARGET_X86_64
2208 ret
= cpu_ldl_code(env
, s
->pc
);
2217 static inline int insn_const_size(TCGMemOp ot
)
2226 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2228 TranslationBlock
*tb
;
2231 pc
= s
->cs_base
+ eip
;
2233 /* NOTE: we handle the case where the TB spans two pages here */
2234 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2235 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2236 /* jump to same page: we can use a direct jump */
2237 tcg_gen_goto_tb(tb_num
);
2239 tcg_gen_exit_tb((uintptr_t)tb
+ tb_num
);
2241 /* jump to another page: currently not optimized */
2247 static inline void gen_jcc(DisasContext
*s
, int b
,
2248 target_ulong val
, target_ulong next_eip
)
2253 l1
= gen_new_label();
2256 gen_goto_tb(s
, 0, next_eip
);
2259 gen_goto_tb(s
, 1, val
);
2260 s
->is_jmp
= DISAS_TB_JUMP
;
2262 l1
= gen_new_label();
2263 l2
= gen_new_label();
2266 gen_jmp_im(next_eip
);
2276 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
, int b
,
2281 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2283 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2284 if (cc
.mask
!= -1) {
2285 TCGv t0
= tcg_temp_new();
2286 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2290 cc
.reg2
= tcg_const_tl(cc
.imm
);
2293 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2294 cpu_T
[0], cpu_regs
[reg
]);
2295 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2297 if (cc
.mask
!= -1) {
2298 tcg_temp_free(cc
.reg
);
2301 tcg_temp_free(cc
.reg2
);
2305 static inline void gen_op_movl_T0_seg(int seg_reg
)
2307 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2308 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2311 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2313 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2314 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2315 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2316 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2317 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2318 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2321 /* move T0 to seg_reg and compute if the CPU state may change. Never
2322 call this function with seg_reg == R_CS */
2323 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2325 if (s
->pe
&& !s
->vm86
) {
2326 /* XXX: optimize by finding processor state dynamically */
2327 gen_update_cc_op(s
);
2328 gen_jmp_im(cur_eip
);
2329 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2330 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2331 /* abort translation because the addseg value may change or
2332 because ss32 may change. For R_SS, translation must always
2333 stop as a special handling must be done to disable hardware
2334 interrupts for the next instruction */
2335 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2336 s
->is_jmp
= DISAS_TB_JUMP
;
2338 gen_op_movl_seg_T0_vm(seg_reg
);
2339 if (seg_reg
== R_SS
)
2340 s
->is_jmp
= DISAS_TB_JUMP
;
2344 static inline int svm_is_rep(int prefixes
)
2346 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2350 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2351 uint32_t type
, uint64_t param
)
2353 /* no SVM activated; fast case */
2354 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2356 gen_update_cc_op(s
);
2357 gen_jmp_im(pc_start
- s
->cs_base
);
2358 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2359 tcg_const_i64(param
));
2363 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2365 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2368 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2370 #ifdef TARGET_X86_64
2372 gen_op_add_reg_im(MO_64
, R_ESP
, addend
);
2376 gen_op_add_reg_im(MO_32
, R_ESP
, addend
);
2378 gen_op_add_reg_im(MO_16
, R_ESP
, addend
);
2382 /* Generate a push. It depends on ss32, addseg and dflag. */
2383 static void gen_push_v(DisasContext
*s
, TCGv val
)
2385 TCGMemOp a_ot
, d_ot
= mo_pushpop(s
, s
->dflag
);
2386 int size
= 1 << d_ot
;
2387 TCGv new_esp
= cpu_A0
;
2389 tcg_gen_subi_tl(cpu_A0
, cpu_regs
[R_ESP
], size
);
2393 } else if (s
->ss32
) {
2397 tcg_gen_mov_tl(new_esp
, cpu_A0
);
2398 gen_op_addl_A0_seg(s
, R_SS
);
2400 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2405 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2406 tcg_gen_mov_tl(new_esp
, cpu_A0
);
2407 gen_op_addl_A0_seg(s
, R_SS
);
2410 gen_op_st_v(s
, d_ot
, val
, cpu_A0
);
2411 gen_op_mov_reg_v(a_ot
, R_ESP
, new_esp
);
2414 /* two step pop is necessary for precise exceptions */
2415 static TCGMemOp
gen_pop_T0(DisasContext
*s
)
2417 TCGMemOp d_ot
= mo_pushpop(s
, s
->dflag
);
2421 addr
= cpu_regs
[R_ESP
];
2422 } else if (!s
->ss32
) {
2423 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2424 gen_op_addl_A0_seg(s
, R_SS
);
2425 } else if (s
->addseg
) {
2426 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2427 gen_op_addl_A0_seg(s
, R_SS
);
2429 tcg_gen_ext32u_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2432 gen_op_ld_v(s
, d_ot
, cpu_T
[0], addr
);
2436 static void gen_pop_update(DisasContext
*s
, TCGMemOp ot
)
2438 gen_stack_update(s
, 1 << ot
);
2441 static void gen_stack_A0(DisasContext
*s
)
2443 gen_op_movl_A0_reg(R_ESP
);
2445 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2446 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2448 gen_op_addl_A0_seg(s
, R_SS
);
2451 /* NOTE: wrap around in 16 bit not fully handled */
2452 static void gen_pusha(DisasContext
*s
)
2455 gen_op_movl_A0_reg(R_ESP
);
2456 gen_op_addl_A0_im(-8 << s
->dflag
);
2458 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2459 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2461 gen_op_addl_A0_seg(s
, R_SS
);
2462 for(i
= 0;i
< 8; i
++) {
2463 gen_op_mov_TN_reg(MO_32
, 0, 7 - i
);
2464 gen_op_st_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2465 gen_op_addl_A0_im(1 << s
->dflag
);
2467 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2470 /* NOTE: wrap around in 16 bit not fully handled */
2471 static void gen_popa(DisasContext
*s
)
2474 gen_op_movl_A0_reg(R_ESP
);
2476 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2477 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2478 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 8 << s
->dflag
);
2480 gen_op_addl_A0_seg(s
, R_SS
);
2481 for(i
= 0;i
< 8; i
++) {
2482 /* ESP is not reloaded */
2484 gen_op_ld_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2485 gen_op_mov_reg_v(s
->dflag
, 7 - i
, cpu_T
[0]);
2487 gen_op_addl_A0_im(1 << s
->dflag
);
2489 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2492 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2494 TCGMemOp ot
= mo_pushpop(s
, s
->dflag
);
2495 int opsize
= 1 << ot
;
2498 #ifdef TARGET_X86_64
2500 gen_op_movl_A0_reg(R_ESP
);
2501 gen_op_addq_A0_im(-opsize
);
2502 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2505 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2506 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2508 /* XXX: must save state */
2509 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2510 tcg_const_i32((ot
== MO_64
)),
2513 gen_op_mov_reg_T1(ot
, R_EBP
);
2514 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2515 gen_op_mov_reg_T1(MO_64
, R_ESP
);
2519 gen_op_movl_A0_reg(R_ESP
);
2520 gen_op_addl_A0_im(-opsize
);
2522 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2523 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2525 gen_op_addl_A0_seg(s
, R_SS
);
2527 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2528 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2530 /* XXX: must save state */
2531 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2532 tcg_const_i32(s
->dflag
- 1),
2535 gen_op_mov_reg_T1(ot
, R_EBP
);
2536 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2537 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2541 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2543 gen_update_cc_op(s
);
2544 gen_jmp_im(cur_eip
);
2545 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2546 s
->is_jmp
= DISAS_TB_JUMP
;
2549 /* an interrupt is different from an exception because of the
2551 static void gen_interrupt(DisasContext
*s
, int intno
,
2552 target_ulong cur_eip
, target_ulong next_eip
)
2554 gen_update_cc_op(s
);
2555 gen_jmp_im(cur_eip
);
2556 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2557 tcg_const_i32(next_eip
- cur_eip
));
2558 s
->is_jmp
= DISAS_TB_JUMP
;
2561 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2563 gen_update_cc_op(s
);
2564 gen_jmp_im(cur_eip
);
2565 gen_helper_debug(cpu_env
);
2566 s
->is_jmp
= DISAS_TB_JUMP
;
2569 /* generate a generic end of block. Trace exception is also generated
2571 static void gen_eob(DisasContext
*s
)
2573 gen_update_cc_op(s
);
2574 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2575 gen_helper_reset_inhibit_irq(cpu_env
);
2577 if (s
->tb
->flags
& HF_RF_MASK
) {
2578 gen_helper_reset_rf(cpu_env
);
2580 if (s
->singlestep_enabled
) {
2581 gen_helper_debug(cpu_env
);
2583 gen_helper_single_step(cpu_env
);
2587 s
->is_jmp
= DISAS_TB_JUMP
;
2590 /* generate a jump to eip. No segment change must happen before as a
2591 direct call to the next block may occur */
2592 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2594 gen_update_cc_op(s
);
2595 set_cc_op(s
, CC_OP_DYNAMIC
);
2597 gen_goto_tb(s
, tb_num
, eip
);
2598 s
->is_jmp
= DISAS_TB_JUMP
;
2605 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2607 gen_jmp_tb(s
, eip
, 0);
2610 static inline void gen_ldq_env_A0(DisasContext
*s
, int offset
)
2612 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2613 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2616 static inline void gen_stq_env_A0(DisasContext
*s
, int offset
)
2618 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2619 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2622 static inline void gen_ldo_env_A0(DisasContext
*s
, int offset
)
2624 int mem_index
= s
->mem_index
;
2625 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2626 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2627 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2628 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2629 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2632 static inline void gen_sto_env_A0(DisasContext
*s
, int offset
)
2634 int mem_index
= s
->mem_index
;
2635 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2636 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2637 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2638 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2639 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2642 static inline void gen_op_movo(int d_offset
, int s_offset
)
2644 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2645 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2646 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2647 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2650 static inline void gen_op_movq(int d_offset
, int s_offset
)
2652 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2653 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2656 static inline void gen_op_movl(int d_offset
, int s_offset
)
2658 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2659 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2662 static inline void gen_op_movq_env_0(int d_offset
)
2664 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2665 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2668 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2669 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2670 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2671 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2672 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2673 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2675 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2676 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2679 #define SSE_SPECIAL ((void *)1)
2680 #define SSE_DUMMY ((void *)2)
2682 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2683 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2684 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2686 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2687 /* 3DNow! extensions */
2688 [0x0e] = { SSE_DUMMY
}, /* femms */
2689 [0x0f] = { SSE_DUMMY
}, /* pf... */
2690 /* pure SSE operations */
2691 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2692 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2693 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2694 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2695 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2696 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2697 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2698 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2700 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2701 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2702 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2703 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2704 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2705 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2706 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2707 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2708 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2709 [0x51] = SSE_FOP(sqrt
),
2710 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2711 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2712 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2713 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2714 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2715 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2716 [0x58] = SSE_FOP(add
),
2717 [0x59] = SSE_FOP(mul
),
2718 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2719 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2720 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2721 [0x5c] = SSE_FOP(sub
),
2722 [0x5d] = SSE_FOP(min
),
2723 [0x5e] = SSE_FOP(div
),
2724 [0x5f] = SSE_FOP(max
),
2726 [0xc2] = SSE_FOP(cmpeq
),
2727 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2728 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2730 /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
2731 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2732 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2734 /* MMX ops and their SSE extensions */
2735 [0x60] = MMX_OP2(punpcklbw
),
2736 [0x61] = MMX_OP2(punpcklwd
),
2737 [0x62] = MMX_OP2(punpckldq
),
2738 [0x63] = MMX_OP2(packsswb
),
2739 [0x64] = MMX_OP2(pcmpgtb
),
2740 [0x65] = MMX_OP2(pcmpgtw
),
2741 [0x66] = MMX_OP2(pcmpgtl
),
2742 [0x67] = MMX_OP2(packuswb
),
2743 [0x68] = MMX_OP2(punpckhbw
),
2744 [0x69] = MMX_OP2(punpckhwd
),
2745 [0x6a] = MMX_OP2(punpckhdq
),
2746 [0x6b] = MMX_OP2(packssdw
),
2747 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2748 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2749 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2750 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2751 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2752 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2753 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2754 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2755 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2756 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2757 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2758 [0x74] = MMX_OP2(pcmpeqb
),
2759 [0x75] = MMX_OP2(pcmpeqw
),
2760 [0x76] = MMX_OP2(pcmpeql
),
2761 [0x77] = { SSE_DUMMY
}, /* emms */
2762 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2763 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2764 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2765 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2766 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2767 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2768 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2769 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2770 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2771 [0xd1] = MMX_OP2(psrlw
),
2772 [0xd2] = MMX_OP2(psrld
),
2773 [0xd3] = MMX_OP2(psrlq
),
2774 [0xd4] = MMX_OP2(paddq
),
2775 [0xd5] = MMX_OP2(pmullw
),
2776 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2777 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2778 [0xd8] = MMX_OP2(psubusb
),
2779 [0xd9] = MMX_OP2(psubusw
),
2780 [0xda] = MMX_OP2(pminub
),
2781 [0xdb] = MMX_OP2(pand
),
2782 [0xdc] = MMX_OP2(paddusb
),
2783 [0xdd] = MMX_OP2(paddusw
),
2784 [0xde] = MMX_OP2(pmaxub
),
2785 [0xdf] = MMX_OP2(pandn
),
2786 [0xe0] = MMX_OP2(pavgb
),
2787 [0xe1] = MMX_OP2(psraw
),
2788 [0xe2] = MMX_OP2(psrad
),
2789 [0xe3] = MMX_OP2(pavgw
),
2790 [0xe4] = MMX_OP2(pmulhuw
),
2791 [0xe5] = MMX_OP2(pmulhw
),
2792 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2793 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2794 [0xe8] = MMX_OP2(psubsb
),
2795 [0xe9] = MMX_OP2(psubsw
),
2796 [0xea] = MMX_OP2(pminsw
),
2797 [0xeb] = MMX_OP2(por
),
2798 [0xec] = MMX_OP2(paddsb
),
2799 [0xed] = MMX_OP2(paddsw
),
2800 [0xee] = MMX_OP2(pmaxsw
),
2801 [0xef] = MMX_OP2(pxor
),
2802 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2803 [0xf1] = MMX_OP2(psllw
),
2804 [0xf2] = MMX_OP2(pslld
),
2805 [0xf3] = MMX_OP2(psllq
),
2806 [0xf4] = MMX_OP2(pmuludq
),
2807 [0xf5] = MMX_OP2(pmaddwd
),
2808 [0xf6] = MMX_OP2(psadbw
),
2809 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
2810 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
2811 [0xf8] = MMX_OP2(psubb
),
2812 [0xf9] = MMX_OP2(psubw
),
2813 [0xfa] = MMX_OP2(psubl
),
2814 [0xfb] = MMX_OP2(psubq
),
2815 [0xfc] = MMX_OP2(paddb
),
2816 [0xfd] = MMX_OP2(paddw
),
2817 [0xfe] = MMX_OP2(paddl
),
2820 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
2821 [0 + 2] = MMX_OP2(psrlw
),
2822 [0 + 4] = MMX_OP2(psraw
),
2823 [0 + 6] = MMX_OP2(psllw
),
2824 [8 + 2] = MMX_OP2(psrld
),
2825 [8 + 4] = MMX_OP2(psrad
),
2826 [8 + 6] = MMX_OP2(pslld
),
2827 [16 + 2] = MMX_OP2(psrlq
),
2828 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2829 [16 + 6] = MMX_OP2(psllq
),
2830 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2833 static const SSEFunc_0_epi sse_op_table3ai
[] = {
2834 gen_helper_cvtsi2ss
,
2838 #ifdef TARGET_X86_64
2839 static const SSEFunc_0_epl sse_op_table3aq
[] = {
2840 gen_helper_cvtsq2ss
,
2845 static const SSEFunc_i_ep sse_op_table3bi
[] = {
2846 gen_helper_cvttss2si
,
2847 gen_helper_cvtss2si
,
2848 gen_helper_cvttsd2si
,
2852 #ifdef TARGET_X86_64
2853 static const SSEFunc_l_ep sse_op_table3bq
[] = {
2854 gen_helper_cvttss2sq
,
2855 gen_helper_cvtss2sq
,
2856 gen_helper_cvttsd2sq
,
2861 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
2872 static const SSEFunc_0_epp sse_op_table5
[256] = {
2873 [0x0c] = gen_helper_pi2fw
,
2874 [0x0d] = gen_helper_pi2fd
,
2875 [0x1c] = gen_helper_pf2iw
,
2876 [0x1d] = gen_helper_pf2id
,
2877 [0x8a] = gen_helper_pfnacc
,
2878 [0x8e] = gen_helper_pfpnacc
,
2879 [0x90] = gen_helper_pfcmpge
,
2880 [0x94] = gen_helper_pfmin
,
2881 [0x96] = gen_helper_pfrcp
,
2882 [0x97] = gen_helper_pfrsqrt
,
2883 [0x9a] = gen_helper_pfsub
,
2884 [0x9e] = gen_helper_pfadd
,
2885 [0xa0] = gen_helper_pfcmpgt
,
2886 [0xa4] = gen_helper_pfmax
,
2887 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2888 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2889 [0xaa] = gen_helper_pfsubr
,
2890 [0xae] = gen_helper_pfacc
,
2891 [0xb0] = gen_helper_pfcmpeq
,
2892 [0xb4] = gen_helper_pfmul
,
2893 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
2894 [0xb7] = gen_helper_pmulhrw_mmx
,
2895 [0xbb] = gen_helper_pswapd
,
2896 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
2899 struct SSEOpHelper_epp
{
2900 SSEFunc_0_epp op
[2];
2904 struct SSEOpHelper_eppi
{
2905 SSEFunc_0_eppi op
[2];
2909 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2910 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
2911 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
2912 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
2913 #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
2914 CPUID_EXT_PCLMULQDQ }
2915 #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
2917 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
2918 [0x00] = SSSE3_OP(pshufb
),
2919 [0x01] = SSSE3_OP(phaddw
),
2920 [0x02] = SSSE3_OP(phaddd
),
2921 [0x03] = SSSE3_OP(phaddsw
),
2922 [0x04] = SSSE3_OP(pmaddubsw
),
2923 [0x05] = SSSE3_OP(phsubw
),
2924 [0x06] = SSSE3_OP(phsubd
),
2925 [0x07] = SSSE3_OP(phsubsw
),
2926 [0x08] = SSSE3_OP(psignb
),
2927 [0x09] = SSSE3_OP(psignw
),
2928 [0x0a] = SSSE3_OP(psignd
),
2929 [0x0b] = SSSE3_OP(pmulhrsw
),
2930 [0x10] = SSE41_OP(pblendvb
),
2931 [0x14] = SSE41_OP(blendvps
),
2932 [0x15] = SSE41_OP(blendvpd
),
2933 [0x17] = SSE41_OP(ptest
),
2934 [0x1c] = SSSE3_OP(pabsb
),
2935 [0x1d] = SSSE3_OP(pabsw
),
2936 [0x1e] = SSSE3_OP(pabsd
),
2937 [0x20] = SSE41_OP(pmovsxbw
),
2938 [0x21] = SSE41_OP(pmovsxbd
),
2939 [0x22] = SSE41_OP(pmovsxbq
),
2940 [0x23] = SSE41_OP(pmovsxwd
),
2941 [0x24] = SSE41_OP(pmovsxwq
),
2942 [0x25] = SSE41_OP(pmovsxdq
),
2943 [0x28] = SSE41_OP(pmuldq
),
2944 [0x29] = SSE41_OP(pcmpeqq
),
2945 [0x2a] = SSE41_SPECIAL
, /* movntqda */
2946 [0x2b] = SSE41_OP(packusdw
),
2947 [0x30] = SSE41_OP(pmovzxbw
),
2948 [0x31] = SSE41_OP(pmovzxbd
),
2949 [0x32] = SSE41_OP(pmovzxbq
),
2950 [0x33] = SSE41_OP(pmovzxwd
),
2951 [0x34] = SSE41_OP(pmovzxwq
),
2952 [0x35] = SSE41_OP(pmovzxdq
),
2953 [0x37] = SSE42_OP(pcmpgtq
),
2954 [0x38] = SSE41_OP(pminsb
),
2955 [0x39] = SSE41_OP(pminsd
),
2956 [0x3a] = SSE41_OP(pminuw
),
2957 [0x3b] = SSE41_OP(pminud
),
2958 [0x3c] = SSE41_OP(pmaxsb
),
2959 [0x3d] = SSE41_OP(pmaxsd
),
2960 [0x3e] = SSE41_OP(pmaxuw
),
2961 [0x3f] = SSE41_OP(pmaxud
),
2962 [0x40] = SSE41_OP(pmulld
),
2963 [0x41] = SSE41_OP(phminposuw
),
2964 [0xdb] = AESNI_OP(aesimc
),
2965 [0xdc] = AESNI_OP(aesenc
),
2966 [0xdd] = AESNI_OP(aesenclast
),
2967 [0xde] = AESNI_OP(aesdec
),
2968 [0xdf] = AESNI_OP(aesdeclast
),
2971 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
2972 [0x08] = SSE41_OP(roundps
),
2973 [0x09] = SSE41_OP(roundpd
),
2974 [0x0a] = SSE41_OP(roundss
),
2975 [0x0b] = SSE41_OP(roundsd
),
2976 [0x0c] = SSE41_OP(blendps
),
2977 [0x0d] = SSE41_OP(blendpd
),
2978 [0x0e] = SSE41_OP(pblendw
),
2979 [0x0f] = SSSE3_OP(palignr
),
2980 [0x14] = SSE41_SPECIAL
, /* pextrb */
2981 [0x15] = SSE41_SPECIAL
, /* pextrw */
2982 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
2983 [0x17] = SSE41_SPECIAL
, /* extractps */
2984 [0x20] = SSE41_SPECIAL
, /* pinsrb */
2985 [0x21] = SSE41_SPECIAL
, /* insertps */
2986 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
2987 [0x40] = SSE41_OP(dpps
),
2988 [0x41] = SSE41_OP(dppd
),
2989 [0x42] = SSE41_OP(mpsadbw
),
2990 [0x44] = PCLMULQDQ_OP(pclmulqdq
),
2991 [0x60] = SSE42_OP(pcmpestrm
),
2992 [0x61] = SSE42_OP(pcmpestri
),
2993 [0x62] = SSE42_OP(pcmpistrm
),
2994 [0x63] = SSE42_OP(pcmpistri
),
2995 [0xdf] = AESNI_OP(aeskeygenassist
),
2998 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
2999 target_ulong pc_start
, int rex_r
)
3001 int b1
, op1_offset
, op2_offset
, is_xmm
, val
;
3002 int modrm
, mod
, rm
, reg
;
3003 SSEFunc_0_epp sse_fn_epp
;
3004 SSEFunc_0_eppi sse_fn_eppi
;
3005 SSEFunc_0_ppi sse_fn_ppi
;
3006 SSEFunc_0_eppt sse_fn_eppt
;
3010 if (s
->prefix
& PREFIX_DATA
)
3012 else if (s
->prefix
& PREFIX_REPZ
)
3014 else if (s
->prefix
& PREFIX_REPNZ
)
3018 sse_fn_epp
= sse_op_table1
[b
][b1
];
3022 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3032 /* simple MMX/SSE operation */
3033 if (s
->flags
& HF_TS_MASK
) {
3034 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3037 if (s
->flags
& HF_EM_MASK
) {
3039 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3042 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3043 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3046 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3049 gen_helper_emms(cpu_env
);
3054 gen_helper_emms(cpu_env
);
3057 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3058 the static cpu state) */
3060 gen_helper_enter_mmx(cpu_env
);
3063 modrm
= cpu_ldub_code(env
, s
->pc
++);
3064 reg
= ((modrm
>> 3) & 7);
3067 mod
= (modrm
>> 6) & 3;
3068 if (sse_fn_epp
== SSE_SPECIAL
) {
3071 case 0x0e7: /* movntq */
3074 gen_lea_modrm(env
, s
, modrm
);
3075 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3077 case 0x1e7: /* movntdq */
3078 case 0x02b: /* movntps */
3079 case 0x12b: /* movntps */
3082 gen_lea_modrm(env
, s
, modrm
);
3083 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3085 case 0x3f0: /* lddqu */
3088 gen_lea_modrm(env
, s
, modrm
);
3089 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3091 case 0x22b: /* movntss */
3092 case 0x32b: /* movntsd */
3095 gen_lea_modrm(env
, s
, modrm
);
3097 gen_stq_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3099 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3100 xmm_regs
[reg
].XMM_L(0)));
3101 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3104 case 0x6e: /* movd mm, ea */
3105 #ifdef TARGET_X86_64
3106 if (s
->dflag
== MO_64
) {
3107 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3108 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3112 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3113 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3114 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3115 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3116 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3119 case 0x16e: /* movd xmm, ea */
3120 #ifdef TARGET_X86_64
3121 if (s
->dflag
== MO_64
) {
3122 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3123 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3124 offsetof(CPUX86State
,xmm_regs
[reg
]));
3125 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3129 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3130 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3131 offsetof(CPUX86State
,xmm_regs
[reg
]));
3132 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3133 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3136 case 0x6f: /* movq mm, ea */
3138 gen_lea_modrm(env
, s
, modrm
);
3139 gen_ldq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3142 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3143 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3144 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3145 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3148 case 0x010: /* movups */
3149 case 0x110: /* movupd */
3150 case 0x028: /* movaps */
3151 case 0x128: /* movapd */
3152 case 0x16f: /* movdqa xmm, ea */
3153 case 0x26f: /* movdqu xmm, ea */
3155 gen_lea_modrm(env
, s
, modrm
);
3156 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3158 rm
= (modrm
& 7) | REX_B(s
);
3159 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3160 offsetof(CPUX86State
,xmm_regs
[rm
]));
3163 case 0x210: /* movss xmm, ea */
3165 gen_lea_modrm(env
, s
, modrm
);
3166 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3167 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3168 tcg_gen_movi_tl(cpu_T
[0], 0);
3169 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3170 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3171 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3173 rm
= (modrm
& 7) | REX_B(s
);
3174 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3175 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3178 case 0x310: /* movsd xmm, ea */
3180 gen_lea_modrm(env
, s
, modrm
);
3181 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3182 xmm_regs
[reg
].XMM_Q(0)));
3183 tcg_gen_movi_tl(cpu_T
[0], 0);
3184 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3185 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3187 rm
= (modrm
& 7) | REX_B(s
);
3188 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3189 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3192 case 0x012: /* movlps */
3193 case 0x112: /* movlpd */
3195 gen_lea_modrm(env
, s
, modrm
);
3196 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3197 xmm_regs
[reg
].XMM_Q(0)));
3200 rm
= (modrm
& 7) | REX_B(s
);
3201 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3202 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3205 case 0x212: /* movsldup */
3207 gen_lea_modrm(env
, s
, modrm
);
3208 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3210 rm
= (modrm
& 7) | REX_B(s
);
3211 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3212 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3213 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3214 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3216 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3217 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3218 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3219 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3221 case 0x312: /* movddup */
3223 gen_lea_modrm(env
, s
, modrm
);
3224 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3225 xmm_regs
[reg
].XMM_Q(0)));
3227 rm
= (modrm
& 7) | REX_B(s
);
3228 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3229 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3231 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3232 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3234 case 0x016: /* movhps */
3235 case 0x116: /* movhpd */
3237 gen_lea_modrm(env
, s
, modrm
);
3238 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3239 xmm_regs
[reg
].XMM_Q(1)));
3242 rm
= (modrm
& 7) | REX_B(s
);
3243 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3244 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3247 case 0x216: /* movshdup */
3249 gen_lea_modrm(env
, s
, modrm
);
3250 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3252 rm
= (modrm
& 7) | REX_B(s
);
3253 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3254 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3255 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3256 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3258 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3259 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3260 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3261 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3266 int bit_index
, field_length
;
3268 if (b1
== 1 && reg
!= 0)
3270 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3271 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3272 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3273 offsetof(CPUX86State
,xmm_regs
[reg
]));
3275 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3276 tcg_const_i32(bit_index
),
3277 tcg_const_i32(field_length
));
3279 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3280 tcg_const_i32(bit_index
),
3281 tcg_const_i32(field_length
));
3284 case 0x7e: /* movd ea, mm */
3285 #ifdef TARGET_X86_64
3286 if (s
->dflag
== MO_64
) {
3287 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3288 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3289 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3293 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3294 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3295 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3298 case 0x17e: /* movd ea, xmm */
3299 #ifdef TARGET_X86_64
3300 if (s
->dflag
== MO_64
) {
3301 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3302 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3303 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3307 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3308 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3309 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3312 case 0x27e: /* movq xmm, ea */
3314 gen_lea_modrm(env
, s
, modrm
);
3315 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3316 xmm_regs
[reg
].XMM_Q(0)));
3318 rm
= (modrm
& 7) | REX_B(s
);
3319 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3320 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3322 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3324 case 0x7f: /* movq ea, mm */
3326 gen_lea_modrm(env
, s
, modrm
);
3327 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3330 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3331 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3334 case 0x011: /* movups */
3335 case 0x111: /* movupd */
3336 case 0x029: /* movaps */
3337 case 0x129: /* movapd */
3338 case 0x17f: /* movdqa ea, xmm */
3339 case 0x27f: /* movdqu ea, xmm */
3341 gen_lea_modrm(env
, s
, modrm
);
3342 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3344 rm
= (modrm
& 7) | REX_B(s
);
3345 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3346 offsetof(CPUX86State
,xmm_regs
[reg
]));
3349 case 0x211: /* movss ea, xmm */
3351 gen_lea_modrm(env
, s
, modrm
);
3352 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3353 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3355 rm
= (modrm
& 7) | REX_B(s
);
3356 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3357 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3360 case 0x311: /* movsd ea, xmm */
3362 gen_lea_modrm(env
, s
, modrm
);
3363 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3364 xmm_regs
[reg
].XMM_Q(0)));
3366 rm
= (modrm
& 7) | REX_B(s
);
3367 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3368 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3371 case 0x013: /* movlps */
3372 case 0x113: /* movlpd */
3374 gen_lea_modrm(env
, s
, modrm
);
3375 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3376 xmm_regs
[reg
].XMM_Q(0)));
3381 case 0x017: /* movhps */
3382 case 0x117: /* movhpd */
3384 gen_lea_modrm(env
, s
, modrm
);
3385 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3386 xmm_regs
[reg
].XMM_Q(1)));
3391 case 0x71: /* shift mm, im */
3394 case 0x171: /* shift xmm, im */
3400 val
= cpu_ldub_code(env
, s
->pc
++);
3402 tcg_gen_movi_tl(cpu_T
[0], val
);
3403 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3404 tcg_gen_movi_tl(cpu_T
[0], 0);
3405 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3406 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3408 tcg_gen_movi_tl(cpu_T
[0], val
);
3409 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3410 tcg_gen_movi_tl(cpu_T
[0], 0);
3411 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3412 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3414 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3415 (((modrm
>> 3)) & 7)][b1
];
3420 rm
= (modrm
& 7) | REX_B(s
);
3421 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3424 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3426 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3427 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3428 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3430 case 0x050: /* movmskps */
3431 rm
= (modrm
& 7) | REX_B(s
);
3432 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3433 offsetof(CPUX86State
,xmm_regs
[rm
]));
3434 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3435 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3437 case 0x150: /* movmskpd */
3438 rm
= (modrm
& 7) | REX_B(s
);
3439 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3440 offsetof(CPUX86State
,xmm_regs
[rm
]));
3441 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3442 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3444 case 0x02a: /* cvtpi2ps */
3445 case 0x12a: /* cvtpi2pd */
3446 gen_helper_enter_mmx(cpu_env
);
3448 gen_lea_modrm(env
, s
, modrm
);
3449 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3450 gen_ldq_env_A0(s
, op2_offset
);
3453 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3455 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3456 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3457 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3460 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3464 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3468 case 0x22a: /* cvtsi2ss */
3469 case 0x32a: /* cvtsi2sd */
3470 ot
= mo_64_32(s
->dflag
);
3471 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3472 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3473 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3475 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3476 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3477 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3479 #ifdef TARGET_X86_64
3480 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3481 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3487 case 0x02c: /* cvttps2pi */
3488 case 0x12c: /* cvttpd2pi */
3489 case 0x02d: /* cvtps2pi */
3490 case 0x12d: /* cvtpd2pi */
3491 gen_helper_enter_mmx(cpu_env
);
3493 gen_lea_modrm(env
, s
, modrm
);
3494 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3495 gen_ldo_env_A0(s
, op2_offset
);
3497 rm
= (modrm
& 7) | REX_B(s
);
3498 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3500 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3501 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3502 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3505 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3508 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3511 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3514 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3518 case 0x22c: /* cvttss2si */
3519 case 0x32c: /* cvttsd2si */
3520 case 0x22d: /* cvtss2si */
3521 case 0x32d: /* cvtsd2si */
3522 ot
= mo_64_32(s
->dflag
);
3524 gen_lea_modrm(env
, s
, modrm
);
3526 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_Q(0)));
3528 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3529 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3531 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3533 rm
= (modrm
& 7) | REX_B(s
);
3534 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3536 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3538 SSEFunc_i_ep sse_fn_i_ep
=
3539 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3540 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3541 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3543 #ifdef TARGET_X86_64
3544 SSEFunc_l_ep sse_fn_l_ep
=
3545 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3546 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3551 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3553 case 0xc4: /* pinsrw */
3556 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
3557 val
= cpu_ldub_code(env
, s
->pc
++);
3560 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3561 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3564 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3565 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3568 case 0xc5: /* pextrw */
3572 ot
= mo_64_32(s
->dflag
);
3573 val
= cpu_ldub_code(env
, s
->pc
++);
3576 rm
= (modrm
& 7) | REX_B(s
);
3577 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3578 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3582 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3583 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3585 reg
= ((modrm
>> 3) & 7) | rex_r
;
3586 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3588 case 0x1d6: /* movq ea, xmm */
3590 gen_lea_modrm(env
, s
, modrm
);
3591 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3592 xmm_regs
[reg
].XMM_Q(0)));
3594 rm
= (modrm
& 7) | REX_B(s
);
3595 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3596 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3597 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3600 case 0x2d6: /* movq2dq */
3601 gen_helper_enter_mmx(cpu_env
);
3603 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3604 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3605 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3607 case 0x3d6: /* movdq2q */
3608 gen_helper_enter_mmx(cpu_env
);
3609 rm
= (modrm
& 7) | REX_B(s
);
3610 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3611 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3613 case 0xd7: /* pmovmskb */
3618 rm
= (modrm
& 7) | REX_B(s
);
3619 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3620 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3623 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3624 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3626 reg
= ((modrm
>> 3) & 7) | rex_r
;
3627 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3633 if ((b
& 0xf0) == 0xf0) {
3636 modrm
= cpu_ldub_code(env
, s
->pc
++);
3638 reg
= ((modrm
>> 3) & 7) | rex_r
;
3639 mod
= (modrm
>> 6) & 3;
3644 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3648 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3652 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3654 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3656 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3657 gen_lea_modrm(env
, s
, modrm
);
3659 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3660 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3661 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3662 gen_ldq_env_A0(s
, op2_offset
+
3663 offsetof(XMMReg
, XMM_Q(0)));
3665 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3666 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3667 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
3668 s
->mem_index
, MO_LEUL
);
3669 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3670 offsetof(XMMReg
, XMM_L(0)));
3672 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3673 tcg_gen_qemu_ld_tl(cpu_tmp0
, cpu_A0
,
3674 s
->mem_index
, MO_LEUW
);
3675 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3676 offsetof(XMMReg
, XMM_W(0)));
3678 case 0x2a: /* movntqda */
3679 gen_ldo_env_A0(s
, op1_offset
);
3682 gen_ldo_env_A0(s
, op2_offset
);
3686 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3688 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3690 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3691 gen_lea_modrm(env
, s
, modrm
);
3692 gen_ldq_env_A0(s
, op2_offset
);
3695 if (sse_fn_epp
== SSE_SPECIAL
) {
3699 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3700 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3701 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3704 set_cc_op(s
, CC_OP_EFLAGS
);
3711 /* Various integer extensions at 0f 38 f[0-f]. */
3712 b
= modrm
| (b1
<< 8);
3713 modrm
= cpu_ldub_code(env
, s
->pc
++);
3714 reg
= ((modrm
>> 3) & 7) | rex_r
;
3717 case 0x3f0: /* crc32 Gd,Eb */
3718 case 0x3f1: /* crc32 Gd,Ey */
3720 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
)) {
3723 if ((b
& 0xff) == 0xf0) {
3725 } else if (s
->dflag
!= MO_64
) {
3726 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3731 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[reg
]);
3732 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3733 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3734 cpu_T
[0], tcg_const_i32(8 << ot
));
3736 ot
= mo_64_32(s
->dflag
);
3737 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3740 case 0x1f0: /* crc32 or movbe */
3742 /* For these insns, the f3 prefix is supposed to have priority
3743 over the 66 prefix, but that's not what we implement above
3745 if (s
->prefix
& PREFIX_REPNZ
) {
3749 case 0x0f0: /* movbe Gy,My */
3750 case 0x0f1: /* movbe My,Gy */
3751 if (!(s
->cpuid_ext_features
& CPUID_EXT_MOVBE
)) {
3754 if (s
->dflag
!= MO_64
) {
3755 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3760 gen_lea_modrm(env
, s
, modrm
);
3762 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
3763 s
->mem_index
, ot
| MO_BE
);
3764 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3766 tcg_gen_qemu_st_tl(cpu_regs
[reg
], cpu_A0
,
3767 s
->mem_index
, ot
| MO_BE
);
3771 case 0x0f2: /* andn Gy, By, Ey */
3772 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3773 || !(s
->prefix
& PREFIX_VEX
)
3777 ot
= mo_64_32(s
->dflag
);
3778 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3779 tcg_gen_andc_tl(cpu_T
[0], cpu_regs
[s
->vex_v
], cpu_T
[0]);
3780 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3781 gen_op_update1_cc();
3782 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3785 case 0x0f7: /* bextr Gy, Ey, By */
3786 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3787 || !(s
->prefix
& PREFIX_VEX
)
3791 ot
= mo_64_32(s
->dflag
);
3795 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3796 /* Extract START, and shift the operand.
3797 Shifts larger than operand size get zeros. */
3798 tcg_gen_ext8u_tl(cpu_A0
, cpu_regs
[s
->vex_v
]);
3799 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3801 bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3802 zero
= tcg_const_tl(0);
3803 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_T
[0], cpu_A0
, bound
,
3805 tcg_temp_free(zero
);
3807 /* Extract the LEN into a mask. Lengths larger than
3808 operand size get all ones. */
3809 tcg_gen_shri_tl(cpu_A0
, cpu_regs
[s
->vex_v
], 8);
3810 tcg_gen_ext8u_tl(cpu_A0
, cpu_A0
);
3811 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_A0
, cpu_A0
, bound
,
3813 tcg_temp_free(bound
);
3814 tcg_gen_movi_tl(cpu_T
[1], 1);
3815 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_A0
);
3816 tcg_gen_subi_tl(cpu_T
[1], cpu_T
[1], 1);
3817 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3819 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3820 gen_op_update1_cc();
3821 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3825 case 0x0f5: /* bzhi Gy, Ey, By */
3826 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3827 || !(s
->prefix
& PREFIX_VEX
)
3831 ot
= mo_64_32(s
->dflag
);
3832 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3833 tcg_gen_ext8u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3835 TCGv bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3836 /* Note that since we're using BMILG (in order to get O
3837 cleared) we need to store the inverse into C. */
3838 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_cc_src
,
3840 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_T
[1], cpu_T
[1],
3841 bound
, bound
, cpu_T
[1]);
3842 tcg_temp_free(bound
);
3844 tcg_gen_movi_tl(cpu_A0
, -1);
3845 tcg_gen_shl_tl(cpu_A0
, cpu_A0
, cpu_T
[1]);
3846 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3847 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3848 gen_op_update1_cc();
3849 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
3852 case 0x3f6: /* mulx By, Gy, rdx, Ey */
3853 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3854 || !(s
->prefix
& PREFIX_VEX
)
3858 ot
= mo_64_32(s
->dflag
);
3859 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3862 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3863 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EDX
]);
3864 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
3865 cpu_tmp2_i32
, cpu_tmp3_i32
);
3866 tcg_gen_extu_i32_tl(cpu_regs
[s
->vex_v
], cpu_tmp2_i32
);
3867 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp3_i32
);
3869 #ifdef TARGET_X86_64
3871 tcg_gen_mulu2_i64(cpu_regs
[s
->vex_v
], cpu_regs
[reg
],
3872 cpu_T
[0], cpu_regs
[R_EDX
]);
3878 case 0x3f5: /* pdep Gy, By, Ey */
3879 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3880 || !(s
->prefix
& PREFIX_VEX
)
3884 ot
= mo_64_32(s
->dflag
);
3885 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3886 /* Note that by zero-extending the mask operand, we
3887 automatically handle zero-extending the result. */
3889 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3891 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3893 gen_helper_pdep(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3896 case 0x2f5: /* pext Gy, By, Ey */
3897 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3898 || !(s
->prefix
& PREFIX_VEX
)
3902 ot
= mo_64_32(s
->dflag
);
3903 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3904 /* Note that by zero-extending the mask operand, we
3905 automatically handle zero-extending the result. */
3907 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3909 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3911 gen_helper_pext(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3914 case 0x1f6: /* adcx Gy, Ey */
3915 case 0x2f6: /* adox Gy, Ey */
3916 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_ADX
)) {
3919 TCGv carry_in
, carry_out
, zero
;
3922 ot
= mo_64_32(s
->dflag
);
3923 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3925 /* Re-use the carry-out from a previous round. */
3926 TCGV_UNUSED(carry_in
);
3927 carry_out
= (b
== 0x1f6 ? cpu_cc_dst
: cpu_cc_src2
);
3931 carry_in
= cpu_cc_dst
;
3932 end_op
= CC_OP_ADCX
;
3934 end_op
= CC_OP_ADCOX
;
3939 end_op
= CC_OP_ADCOX
;
3941 carry_in
= cpu_cc_src2
;
3942 end_op
= CC_OP_ADOX
;
3946 end_op
= CC_OP_ADCOX
;
3947 carry_in
= carry_out
;
3950 end_op
= (b
== 0x1f6 ? CC_OP_ADCX
: CC_OP_ADOX
);
3953 /* If we can't reuse carry-out, get it out of EFLAGS. */
3954 if (TCGV_IS_UNUSED(carry_in
)) {
3955 if (s
->cc_op
!= CC_OP_ADCX
&& s
->cc_op
!= CC_OP_ADOX
) {
3956 gen_compute_eflags(s
);
3958 carry_in
= cpu_tmp0
;
3959 tcg_gen_shri_tl(carry_in
, cpu_cc_src
,
3960 ctz32(b
== 0x1f6 ? CC_C
: CC_O
));
3961 tcg_gen_andi_tl(carry_in
, carry_in
, 1);
3965 #ifdef TARGET_X86_64
3967 /* If we know TL is 64-bit, and we want a 32-bit
3968 result, just do everything in 64-bit arithmetic. */
3969 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_regs
[reg
]);
3970 tcg_gen_ext32u_i64(cpu_T
[0], cpu_T
[0]);
3971 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_regs
[reg
]);
3972 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], carry_in
);
3973 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_T
[0]);
3974 tcg_gen_shri_i64(carry_out
, cpu_T
[0], 32);
3978 /* Otherwise compute the carry-out in two steps. */
3979 zero
= tcg_const_tl(0);
3980 tcg_gen_add2_tl(cpu_T
[0], carry_out
,
3983 tcg_gen_add2_tl(cpu_regs
[reg
], carry_out
,
3984 cpu_regs
[reg
], carry_out
,
3986 tcg_temp_free(zero
);
3989 set_cc_op(s
, end_op
);
3993 case 0x1f7: /* shlx Gy, Ey, By */
3994 case 0x2f7: /* sarx Gy, Ey, By */
3995 case 0x3f7: /* shrx Gy, Ey, By */
3996 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3997 || !(s
->prefix
& PREFIX_VEX
)
4001 ot
= mo_64_32(s
->dflag
);
4002 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4004 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 63);
4006 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 31);
4009 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4010 } else if (b
== 0x2f7) {
4012 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4014 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4017 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4019 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4021 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4027 case 0x3f3: /* Group 17 */
4028 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
4029 || !(s
->prefix
& PREFIX_VEX
)
4033 ot
= mo_64_32(s
->dflag
);
4034 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4037 case 1: /* blsr By,Ey */
4038 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[0]);
4039 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4040 gen_op_mov_reg_v(ot
, s
->vex_v
, cpu_T
[0]);
4041 gen_op_update2_cc();
4042 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4045 case 2: /* blsmsk By,Ey */
4046 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4047 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4048 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4049 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4050 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4053 case 3: /* blsi By, Ey */
4054 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4055 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4056 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4057 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4058 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4074 modrm
= cpu_ldub_code(env
, s
->pc
++);
4076 reg
= ((modrm
>> 3) & 7) | rex_r
;
4077 mod
= (modrm
>> 6) & 3;
4082 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4086 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4089 if (sse_fn_eppi
== SSE_SPECIAL
) {
4090 ot
= mo_64_32(s
->dflag
);
4091 rm
= (modrm
& 7) | REX_B(s
);
4093 gen_lea_modrm(env
, s
, modrm
);
4094 reg
= ((modrm
>> 3) & 7) | rex_r
;
4095 val
= cpu_ldub_code(env
, s
->pc
++);
4097 case 0x14: /* pextrb */
4098 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4099 xmm_regs
[reg
].XMM_B(val
& 15)));
4101 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4103 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4104 s
->mem_index
, MO_UB
);
4107 case 0x15: /* pextrw */
4108 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4109 xmm_regs
[reg
].XMM_W(val
& 7)));
4111 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4113 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4114 s
->mem_index
, MO_LEUW
);
4118 if (ot
== MO_32
) { /* pextrd */
4119 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4120 offsetof(CPUX86State
,
4121 xmm_regs
[reg
].XMM_L(val
& 3)));
4123 tcg_gen_extu_i32_tl(cpu_regs
[rm
], cpu_tmp2_i32
);
4125 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
4126 s
->mem_index
, MO_LEUL
);
4128 } else { /* pextrq */
4129 #ifdef TARGET_X86_64
4130 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4131 offsetof(CPUX86State
,
4132 xmm_regs
[reg
].XMM_Q(val
& 1)));
4134 tcg_gen_mov_i64(cpu_regs
[rm
], cpu_tmp1_i64
);
4136 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
4137 s
->mem_index
, MO_LEQ
);
4144 case 0x17: /* extractps */
4145 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4146 xmm_regs
[reg
].XMM_L(val
& 3)));
4148 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4150 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4151 s
->mem_index
, MO_LEUL
);
4154 case 0x20: /* pinsrb */
4156 gen_op_mov_TN_reg(MO_32
, 0, rm
);
4158 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
4159 s
->mem_index
, MO_UB
);
4161 tcg_gen_st8_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4162 xmm_regs
[reg
].XMM_B(val
& 15)));
4164 case 0x21: /* insertps */
4166 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4167 offsetof(CPUX86State
,xmm_regs
[rm
]
4168 .XMM_L((val
>> 6) & 3)));
4170 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4171 s
->mem_index
, MO_LEUL
);
4173 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4174 offsetof(CPUX86State
,xmm_regs
[reg
]
4175 .XMM_L((val
>> 4) & 3)));
4177 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4178 cpu_env
, offsetof(CPUX86State
,
4179 xmm_regs
[reg
].XMM_L(0)));
4181 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4182 cpu_env
, offsetof(CPUX86State
,
4183 xmm_regs
[reg
].XMM_L(1)));
4185 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4186 cpu_env
, offsetof(CPUX86State
,
4187 xmm_regs
[reg
].XMM_L(2)));
4189 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4190 cpu_env
, offsetof(CPUX86State
,
4191 xmm_regs
[reg
].XMM_L(3)));
4194 if (ot
== MO_32
) { /* pinsrd */
4196 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[rm
]);
4198 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4199 s
->mem_index
, MO_LEUL
);
4201 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4202 offsetof(CPUX86State
,
4203 xmm_regs
[reg
].XMM_L(val
& 3)));
4204 } else { /* pinsrq */
4205 #ifdef TARGET_X86_64
4207 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4209 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
4210 s
->mem_index
, MO_LEQ
);
4212 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4213 offsetof(CPUX86State
,
4214 xmm_regs
[reg
].XMM_Q(val
& 1)));
4225 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4227 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4229 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4230 gen_lea_modrm(env
, s
, modrm
);
4231 gen_ldo_env_A0(s
, op2_offset
);
4234 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4236 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4238 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4239 gen_lea_modrm(env
, s
, modrm
);
4240 gen_ldq_env_A0(s
, op2_offset
);
4243 val
= cpu_ldub_code(env
, s
->pc
++);
4245 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4246 set_cc_op(s
, CC_OP_EFLAGS
);
4248 if (s
->dflag
== MO_64
) {
4249 /* The helper must use entire 64-bit gp registers */
4254 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4255 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4256 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4260 /* Various integer extensions at 0f 3a f[0-f]. */
4261 b
= modrm
| (b1
<< 8);
4262 modrm
= cpu_ldub_code(env
, s
->pc
++);
4263 reg
= ((modrm
>> 3) & 7) | rex_r
;
4266 case 0x3f0: /* rorx Gy,Ey, Ib */
4267 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4268 || !(s
->prefix
& PREFIX_VEX
)
4272 ot
= mo_64_32(s
->dflag
);
4273 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4274 b
= cpu_ldub_code(env
, s
->pc
++);
4276 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], b
& 63);
4278 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4279 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, b
& 31);
4280 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4282 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4294 /* generic MMX or SSE operation */
4296 case 0x70: /* pshufx insn */
4297 case 0xc6: /* pshufx insn */
4298 case 0xc2: /* compare insns */
4305 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4307 gen_lea_modrm(env
, s
, modrm
);
4308 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4309 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4311 /* specific case for SSE single instructions */
4314 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
4315 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4318 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
4322 gen_ldo_env_A0(s
, op2_offset
);
4325 rm
= (modrm
& 7) | REX_B(s
);
4326 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4329 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4331 gen_lea_modrm(env
, s
, modrm
);
4332 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4333 gen_ldq_env_A0(s
, op2_offset
);
4336 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4340 case 0x0f: /* 3DNow! data insns */
4341 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4343 val
= cpu_ldub_code(env
, s
->pc
++);
4344 sse_fn_epp
= sse_op_table5
[val
];
4348 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4349 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4350 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4352 case 0x70: /* pshufx insn */
4353 case 0xc6: /* pshufx insn */
4354 val
= cpu_ldub_code(env
, s
->pc
++);
4355 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4356 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4357 /* XXX: introduce a new table? */
4358 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4359 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4363 val
= cpu_ldub_code(env
, s
->pc
++);
4366 sse_fn_epp
= sse_op_table4
[val
][b1
];
4368 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4369 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4370 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4373 /* maskmov : we must prepare A0 */
4376 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EDI
]);
4377 gen_extu(s
->aflag
, cpu_A0
);
4378 gen_add_A0_ds_seg(s
);
4380 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4381 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4382 /* XXX: introduce a new table? */
4383 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4384 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4387 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4388 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4389 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4392 if (b
== 0x2e || b
== 0x2f) {
4393 set_cc_op(s
, CC_OP_EFLAGS
);
4398 /* convert one instruction. s->is_jmp is set if the translation must
4399 be stopped. Return the next pc value */
4400 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4401 target_ulong pc_start
)
4405 TCGMemOp ot
, aflag
, dflag
;
4406 int modrm
, reg
, rm
, mod
, op
, opreg
, val
;
4407 target_ulong next_eip
, tval
;
4410 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4411 tcg_gen_debug_insn_start(pc_start
);
4418 #ifdef TARGET_X86_64
4423 s
->rip_offset
= 0; /* for relative ip address */
4427 b
= cpu_ldub_code(env
, s
->pc
);
4429 /* Collect prefixes. */
4432 prefixes
|= PREFIX_REPZ
;
4435 prefixes
|= PREFIX_REPNZ
;
4438 prefixes
|= PREFIX_LOCK
;
4459 prefixes
|= PREFIX_DATA
;
4462 prefixes
|= PREFIX_ADR
;
4464 #ifdef TARGET_X86_64
4468 rex_w
= (b
>> 3) & 1;
4469 rex_r
= (b
& 0x4) << 1;
4470 s
->rex_x
= (b
& 0x2) << 2;
4471 REX_B(s
) = (b
& 0x1) << 3;
4472 x86_64_hregs
= 1; /* select uniform byte register addressing */
4477 case 0xc5: /* 2-byte VEX */
4478 case 0xc4: /* 3-byte VEX */
4479 /* VEX prefixes cannot be used except in 32-bit mode.
4480 Otherwise the instruction is LES or LDS. */
4481 if (s
->code32
&& !s
->vm86
) {
4482 static const int pp_prefix
[4] = {
4483 0, PREFIX_DATA
, PREFIX_REPZ
, PREFIX_REPNZ
4485 int vex3
, vex2
= cpu_ldub_code(env
, s
->pc
);
4487 if (!CODE64(s
) && (vex2
& 0xc0) != 0xc0) {
4488 /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
4489 otherwise the instruction is LES or LDS. */
4494 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
4495 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
4496 | PREFIX_LOCK
| PREFIX_DATA
)) {
4499 #ifdef TARGET_X86_64
4504 rex_r
= (~vex2
>> 4) & 8;
4507 b
= cpu_ldub_code(env
, s
->pc
++);
4509 #ifdef TARGET_X86_64
4510 s
->rex_x
= (~vex2
>> 3) & 8;
4511 s
->rex_b
= (~vex2
>> 2) & 8;
4513 vex3
= cpu_ldub_code(env
, s
->pc
++);
4514 rex_w
= (vex3
>> 7) & 1;
4515 switch (vex2
& 0x1f) {
4516 case 0x01: /* Implied 0f leading opcode bytes. */
4517 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4519 case 0x02: /* Implied 0f 38 leading opcode bytes. */
4522 case 0x03: /* Implied 0f 3a leading opcode bytes. */
4525 default: /* Reserved for future use. */
4529 s
->vex_v
= (~vex3
>> 3) & 0xf;
4530 s
->vex_l
= (vex3
>> 2) & 1;
4531 prefixes
|= pp_prefix
[vex3
& 3] | PREFIX_VEX
;
4536 /* Post-process prefixes. */
4538 /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
4539 data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
4540 over 0x66 if both are present. */
4541 dflag
= (rex_w
> 0 ? MO_64
: prefixes
& PREFIX_DATA
? MO_16
: MO_32
);
4542 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
4543 aflag
= (prefixes
& PREFIX_ADR
? MO_32
: MO_64
);
4545 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
4546 if (s
->code32
^ ((prefixes
& PREFIX_DATA
) != 0)) {
4551 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
4552 if (s
->code32
^ ((prefixes
& PREFIX_ADR
) != 0)) {
4559 s
->prefix
= prefixes
;
4563 /* lock generation */
4564 if (prefixes
& PREFIX_LOCK
)
4567 /* now check op code */
4571 /**************************/
4572 /* extended op code */
4573 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4576 /**************************/
4591 ot
= mo_b_d(b
, dflag
);
4594 case 0: /* OP Ev, Gv */
4595 modrm
= cpu_ldub_code(env
, s
->pc
++);
4596 reg
= ((modrm
>> 3) & 7) | rex_r
;
4597 mod
= (modrm
>> 6) & 3;
4598 rm
= (modrm
& 7) | REX_B(s
);
4600 gen_lea_modrm(env
, s
, modrm
);
4602 } else if (op
== OP_XORL
&& rm
== reg
) {
4604 /* xor reg, reg optimisation */
4605 set_cc_op(s
, CC_OP_CLR
);
4606 tcg_gen_movi_tl(cpu_T
[0], 0);
4607 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4612 gen_op_mov_TN_reg(ot
, 1, reg
);
4613 gen_op(s
, op
, ot
, opreg
);
4615 case 1: /* OP Gv, Ev */
4616 modrm
= cpu_ldub_code(env
, s
->pc
++);
4617 mod
= (modrm
>> 6) & 3;
4618 reg
= ((modrm
>> 3) & 7) | rex_r
;
4619 rm
= (modrm
& 7) | REX_B(s
);
4621 gen_lea_modrm(env
, s
, modrm
);
4622 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4623 } else if (op
== OP_XORL
&& rm
== reg
) {
4626 gen_op_mov_TN_reg(ot
, 1, rm
);
4628 gen_op(s
, op
, ot
, reg
);
4630 case 2: /* OP A, Iv */
4631 val
= insn_get(env
, s
, ot
);
4632 tcg_gen_movi_tl(cpu_T
[1], val
);
4633 gen_op(s
, op
, ot
, OR_EAX
);
4642 case 0x80: /* GRP1 */
4648 ot
= mo_b_d(b
, dflag
);
4650 modrm
= cpu_ldub_code(env
, s
->pc
++);
4651 mod
= (modrm
>> 6) & 3;
4652 rm
= (modrm
& 7) | REX_B(s
);
4653 op
= (modrm
>> 3) & 7;
4659 s
->rip_offset
= insn_const_size(ot
);
4660 gen_lea_modrm(env
, s
, modrm
);
4671 val
= insn_get(env
, s
, ot
);
4674 val
= (int8_t)insn_get(env
, s
, MO_8
);
4677 tcg_gen_movi_tl(cpu_T
[1], val
);
4678 gen_op(s
, op
, ot
, opreg
);
4682 /**************************/
4683 /* inc, dec, and other misc arith */
4684 case 0x40 ... 0x47: /* inc Gv */
4686 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4688 case 0x48 ... 0x4f: /* dec Gv */
4690 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4692 case 0xf6: /* GRP3 */
4694 ot
= mo_b_d(b
, dflag
);
4696 modrm
= cpu_ldub_code(env
, s
->pc
++);
4697 mod
= (modrm
>> 6) & 3;
4698 rm
= (modrm
& 7) | REX_B(s
);
4699 op
= (modrm
>> 3) & 7;
4702 s
->rip_offset
= insn_const_size(ot
);
4703 gen_lea_modrm(env
, s
, modrm
);
4704 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4706 gen_op_mov_TN_reg(ot
, 0, rm
);
4711 val
= insn_get(env
, s
, ot
);
4712 tcg_gen_movi_tl(cpu_T
[1], val
);
4713 gen_op_testl_T0_T1_cc();
4714 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4717 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4719 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4721 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4725 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4727 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4729 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4731 gen_op_update_neg_cc();
4732 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4737 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4738 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4739 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4740 /* XXX: use 32 bit mul which could be faster */
4741 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4742 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4743 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4744 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4745 set_cc_op(s
, CC_OP_MULB
);
4748 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4749 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4750 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4751 /* XXX: use 32 bit mul which could be faster */
4752 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4753 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4754 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4755 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4756 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
4757 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4758 set_cc_op(s
, CC_OP_MULW
);
4762 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4763 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4764 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4765 cpu_tmp2_i32
, cpu_tmp3_i32
);
4766 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4767 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4768 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4769 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4770 set_cc_op(s
, CC_OP_MULL
);
4772 #ifdef TARGET_X86_64
4774 tcg_gen_mulu2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4775 cpu_T
[0], cpu_regs
[R_EAX
]);
4776 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4777 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4778 set_cc_op(s
, CC_OP_MULQ
);
4786 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4787 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4788 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4789 /* XXX: use 32 bit mul which could be faster */
4790 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4791 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4792 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4793 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4794 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4795 set_cc_op(s
, CC_OP_MULB
);
4798 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4799 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4800 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4801 /* XXX: use 32 bit mul which could be faster */
4802 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4803 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4804 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4805 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4806 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4807 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4808 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
4809 set_cc_op(s
, CC_OP_MULW
);
4813 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4814 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4815 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4816 cpu_tmp2_i32
, cpu_tmp3_i32
);
4817 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4818 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4819 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
4820 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4821 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
4822 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
4823 set_cc_op(s
, CC_OP_MULL
);
4825 #ifdef TARGET_X86_64
4827 tcg_gen_muls2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4828 cpu_T
[0], cpu_regs
[R_EAX
]);
4829 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4830 tcg_gen_sari_tl(cpu_cc_src
, cpu_regs
[R_EAX
], 63);
4831 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_regs
[R_EDX
]);
4832 set_cc_op(s
, CC_OP_MULQ
);
4840 gen_jmp_im(pc_start
- s
->cs_base
);
4841 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4844 gen_jmp_im(pc_start
- s
->cs_base
);
4845 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4849 gen_jmp_im(pc_start
- s
->cs_base
);
4850 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4852 #ifdef TARGET_X86_64
4854 gen_jmp_im(pc_start
- s
->cs_base
);
4855 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4863 gen_jmp_im(pc_start
- s
->cs_base
);
4864 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4867 gen_jmp_im(pc_start
- s
->cs_base
);
4868 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4872 gen_jmp_im(pc_start
- s
->cs_base
);
4873 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4875 #ifdef TARGET_X86_64
4877 gen_jmp_im(pc_start
- s
->cs_base
);
4878 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4888 case 0xfe: /* GRP4 */
4889 case 0xff: /* GRP5 */
4890 ot
= mo_b_d(b
, dflag
);
4892 modrm
= cpu_ldub_code(env
, s
->pc
++);
4893 mod
= (modrm
>> 6) & 3;
4894 rm
= (modrm
& 7) | REX_B(s
);
4895 op
= (modrm
>> 3) & 7;
4896 if (op
>= 2 && b
== 0xfe) {
4900 if (op
== 2 || op
== 4) {
4901 /* operand size for jumps is 64 bit */
4903 } else if (op
== 3 || op
== 5) {
4904 ot
= dflag
!= MO_16
? MO_32
+ (rex_w
== 1) : MO_16
;
4905 } else if (op
== 6) {
4906 /* default push size is 64 bit */
4907 ot
= mo_pushpop(s
, dflag
);
4911 gen_lea_modrm(env
, s
, modrm
);
4912 if (op
>= 2 && op
!= 3 && op
!= 5)
4913 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4915 gen_op_mov_TN_reg(ot
, 0, rm
);
4919 case 0: /* inc Ev */
4924 gen_inc(s
, ot
, opreg
, 1);
4926 case 1: /* dec Ev */
4931 gen_inc(s
, ot
, opreg
, -1);
4933 case 2: /* call Ev */
4934 /* XXX: optimize if memory (no 'and' is necessary) */
4935 if (dflag
== MO_16
) {
4936 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4938 next_eip
= s
->pc
- s
->cs_base
;
4939 tcg_gen_movi_tl(cpu_T
[1], next_eip
);
4940 gen_push_v(s
, cpu_T
[1]);
4944 case 3: /* lcall Ev */
4945 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4946 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
4947 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4949 if (s
->pe
&& !s
->vm86
) {
4950 gen_update_cc_op(s
);
4951 gen_jmp_im(pc_start
- s
->cs_base
);
4952 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4953 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4954 tcg_const_i32(dflag
- 1),
4955 tcg_const_i32(s
->pc
- pc_start
));
4957 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4958 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4959 tcg_const_i32(dflag
- 1),
4960 tcg_const_i32(s
->pc
- s
->cs_base
));
4964 case 4: /* jmp Ev */
4965 if (dflag
== MO_16
) {
4966 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4971 case 5: /* ljmp Ev */
4972 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4973 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
4974 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4976 if (s
->pe
&& !s
->vm86
) {
4977 gen_update_cc_op(s
);
4978 gen_jmp_im(pc_start
- s
->cs_base
);
4979 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4980 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4981 tcg_const_i32(s
->pc
- pc_start
));
4983 gen_op_movl_seg_T0_vm(R_CS
);
4984 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
4989 case 6: /* push Ev */
4990 gen_push_v(s
, cpu_T
[0]);
4997 case 0x84: /* test Ev, Gv */
4999 ot
= mo_b_d(b
, dflag
);
5001 modrm
= cpu_ldub_code(env
, s
->pc
++);
5002 reg
= ((modrm
>> 3) & 7) | rex_r
;
5004 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5005 gen_op_mov_TN_reg(ot
, 1, reg
);
5006 gen_op_testl_T0_T1_cc();
5007 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5010 case 0xa8: /* test eAX, Iv */
5012 ot
= mo_b_d(b
, dflag
);
5013 val
= insn_get(env
, s
, ot
);
5015 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
5016 tcg_gen_movi_tl(cpu_T
[1], val
);
5017 gen_op_testl_T0_T1_cc();
5018 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5021 case 0x98: /* CWDE/CBW */
5023 #ifdef TARGET_X86_64
5025 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5026 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5027 gen_op_mov_reg_v(MO_64
, R_EAX
, cpu_T
[0]);
5031 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5032 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5033 gen_op_mov_reg_v(MO_32
, R_EAX
, cpu_T
[0]);
5036 gen_op_mov_TN_reg(MO_8
, 0, R_EAX
);
5037 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5038 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
5044 case 0x99: /* CDQ/CWD */
5046 #ifdef TARGET_X86_64
5048 gen_op_mov_TN_reg(MO_64
, 0, R_EAX
);
5049 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
5050 gen_op_mov_reg_v(MO_64
, R_EDX
, cpu_T
[0]);
5054 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5055 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5056 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
5057 gen_op_mov_reg_v(MO_32
, R_EDX
, cpu_T
[0]);
5060 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5061 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5062 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
5063 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
5069 case 0x1af: /* imul Gv, Ev */
5070 case 0x69: /* imul Gv, Ev, I */
5073 modrm
= cpu_ldub_code(env
, s
->pc
++);
5074 reg
= ((modrm
>> 3) & 7) | rex_r
;
5076 s
->rip_offset
= insn_const_size(ot
);
5079 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5081 val
= insn_get(env
, s
, ot
);
5082 tcg_gen_movi_tl(cpu_T
[1], val
);
5083 } else if (b
== 0x6b) {
5084 val
= (int8_t)insn_get(env
, s
, MO_8
);
5085 tcg_gen_movi_tl(cpu_T
[1], val
);
5087 gen_op_mov_TN_reg(ot
, 1, reg
);
5090 #ifdef TARGET_X86_64
5092 tcg_gen_muls2_i64(cpu_regs
[reg
], cpu_T
[1], cpu_T
[0], cpu_T
[1]);
5093 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5094 tcg_gen_sari_tl(cpu_cc_src
, cpu_cc_dst
, 63);
5095 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[1]);
5099 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5100 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5101 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
5102 cpu_tmp2_i32
, cpu_tmp3_i32
);
5103 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
5104 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
5105 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5106 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
5107 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
5110 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5111 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5112 /* XXX: use 32 bit mul which could be faster */
5113 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5114 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5115 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5116 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5117 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5120 set_cc_op(s
, CC_OP_MULB
+ ot
);
5123 case 0x1c1: /* xadd Ev, Gv */
5124 ot
= mo_b_d(b
, dflag
);
5125 modrm
= cpu_ldub_code(env
, s
->pc
++);
5126 reg
= ((modrm
>> 3) & 7) | rex_r
;
5127 mod
= (modrm
>> 6) & 3;
5129 rm
= (modrm
& 7) | REX_B(s
);
5130 gen_op_mov_TN_reg(ot
, 0, reg
);
5131 gen_op_mov_TN_reg(ot
, 1, rm
);
5132 gen_op_addl_T0_T1();
5133 gen_op_mov_reg_T1(ot
, reg
);
5134 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5136 gen_lea_modrm(env
, s
, modrm
);
5137 gen_op_mov_TN_reg(ot
, 0, reg
);
5138 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5139 gen_op_addl_T0_T1();
5140 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5141 gen_op_mov_reg_T1(ot
, reg
);
5143 gen_op_update2_cc();
5144 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5147 case 0x1b1: /* cmpxchg Ev, Gv */
5150 TCGv t0
, t1
, t2
, a0
;
5152 ot
= mo_b_d(b
, dflag
);
5153 modrm
= cpu_ldub_code(env
, s
->pc
++);
5154 reg
= ((modrm
>> 3) & 7) | rex_r
;
5155 mod
= (modrm
>> 6) & 3;
5156 t0
= tcg_temp_local_new();
5157 t1
= tcg_temp_local_new();
5158 t2
= tcg_temp_local_new();
5159 a0
= tcg_temp_local_new();
5160 gen_op_mov_v_reg(ot
, t1
, reg
);
5162 rm
= (modrm
& 7) | REX_B(s
);
5163 gen_op_mov_v_reg(ot
, t0
, rm
);
5165 gen_lea_modrm(env
, s
, modrm
);
5166 tcg_gen_mov_tl(a0
, cpu_A0
);
5167 gen_op_ld_v(s
, ot
, t0
, a0
);
5168 rm
= 0; /* avoid warning */
5170 label1
= gen_new_label();
5171 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5174 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5175 label2
= gen_new_label();
5177 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5179 gen_set_label(label1
);
5180 gen_op_mov_reg_v(ot
, rm
, t1
);
5182 /* perform no-op store cycle like physical cpu; must be
5183 before changing accumulator to ensure idempotency if
5184 the store faults and the instruction is restarted */
5185 gen_op_st_v(s
, ot
, t0
, a0
);
5186 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5188 gen_set_label(label1
);
5189 gen_op_st_v(s
, ot
, t1
, a0
);
5191 gen_set_label(label2
);
5192 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5193 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5194 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5195 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5202 case 0x1c7: /* cmpxchg8b */
5203 modrm
= cpu_ldub_code(env
, s
->pc
++);
5204 mod
= (modrm
>> 6) & 3;
5205 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5207 #ifdef TARGET_X86_64
5208 if (dflag
== MO_64
) {
5209 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5211 gen_jmp_im(pc_start
- s
->cs_base
);
5212 gen_update_cc_op(s
);
5213 gen_lea_modrm(env
, s
, modrm
);
5214 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5218 if (!(s
->cpuid_features
& CPUID_CX8
))
5220 gen_jmp_im(pc_start
- s
->cs_base
);
5221 gen_update_cc_op(s
);
5222 gen_lea_modrm(env
, s
, modrm
);
5223 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5225 set_cc_op(s
, CC_OP_EFLAGS
);
5228 /**************************/
5230 case 0x50 ... 0x57: /* push */
5231 gen_op_mov_TN_reg(MO_32
, 0, (b
& 7) | REX_B(s
));
5232 gen_push_v(s
, cpu_T
[0]);
5234 case 0x58 ... 0x5f: /* pop */
5236 /* NOTE: order is important for pop %sp */
5237 gen_pop_update(s
, ot
);
5238 gen_op_mov_reg_v(ot
, (b
& 7) | REX_B(s
), cpu_T
[0]);
5240 case 0x60: /* pusha */
5245 case 0x61: /* popa */
5250 case 0x68: /* push Iv */
5252 ot
= mo_pushpop(s
, dflag
);
5254 val
= insn_get(env
, s
, ot
);
5256 val
= (int8_t)insn_get(env
, s
, MO_8
);
5257 tcg_gen_movi_tl(cpu_T
[0], val
);
5258 gen_push_v(s
, cpu_T
[0]);
5260 case 0x8f: /* pop Ev */
5261 modrm
= cpu_ldub_code(env
, s
->pc
++);
5262 mod
= (modrm
>> 6) & 3;
5265 /* NOTE: order is important for pop %sp */
5266 gen_pop_update(s
, ot
);
5267 rm
= (modrm
& 7) | REX_B(s
);
5268 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5270 /* NOTE: order is important too for MMU exceptions */
5271 s
->popl_esp_hack
= 1 << ot
;
5272 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5273 s
->popl_esp_hack
= 0;
5274 gen_pop_update(s
, ot
);
5277 case 0xc8: /* enter */
5280 val
= cpu_lduw_code(env
, s
->pc
);
5282 level
= cpu_ldub_code(env
, s
->pc
++);
5283 gen_enter(s
, val
, level
);
5286 case 0xc9: /* leave */
5287 /* XXX: exception not precise (ESP is updated before potential exception) */
5289 gen_op_mov_TN_reg(MO_64
, 0, R_EBP
);
5290 gen_op_mov_reg_v(MO_64
, R_ESP
, cpu_T
[0]);
5291 } else if (s
->ss32
) {
5292 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
5293 gen_op_mov_reg_v(MO_32
, R_ESP
, cpu_T
[0]);
5295 gen_op_mov_TN_reg(MO_16
, 0, R_EBP
);
5296 gen_op_mov_reg_v(MO_16
, R_ESP
, cpu_T
[0]);
5299 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[0]);
5300 gen_pop_update(s
, ot
);
5302 case 0x06: /* push es */
5303 case 0x0e: /* push cs */
5304 case 0x16: /* push ss */
5305 case 0x1e: /* push ds */
5308 gen_op_movl_T0_seg(b
>> 3);
5309 gen_push_v(s
, cpu_T
[0]);
5311 case 0x1a0: /* push fs */
5312 case 0x1a8: /* push gs */
5313 gen_op_movl_T0_seg((b
>> 3) & 7);
5314 gen_push_v(s
, cpu_T
[0]);
5316 case 0x07: /* pop es */
5317 case 0x17: /* pop ss */
5318 case 0x1f: /* pop ds */
5323 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5324 gen_pop_update(s
, ot
);
5326 /* if reg == SS, inhibit interrupts/trace. */
5327 /* If several instructions disable interrupts, only the
5329 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5330 gen_helper_set_inhibit_irq(cpu_env
);
5334 gen_jmp_im(s
->pc
- s
->cs_base
);
5338 case 0x1a1: /* pop fs */
5339 case 0x1a9: /* pop gs */
5341 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5342 gen_pop_update(s
, ot
);
5344 gen_jmp_im(s
->pc
- s
->cs_base
);
5349 /**************************/
5352 case 0x89: /* mov Gv, Ev */
5353 ot
= mo_b_d(b
, dflag
);
5354 modrm
= cpu_ldub_code(env
, s
->pc
++);
5355 reg
= ((modrm
>> 3) & 7) | rex_r
;
5357 /* generate a generic store */
5358 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5361 case 0xc7: /* mov Ev, Iv */
5362 ot
= mo_b_d(b
, dflag
);
5363 modrm
= cpu_ldub_code(env
, s
->pc
++);
5364 mod
= (modrm
>> 6) & 3;
5366 s
->rip_offset
= insn_const_size(ot
);
5367 gen_lea_modrm(env
, s
, modrm
);
5369 val
= insn_get(env
, s
, ot
);
5370 tcg_gen_movi_tl(cpu_T
[0], val
);
5372 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5374 gen_op_mov_reg_v(ot
, (modrm
& 7) | REX_B(s
), cpu_T
[0]);
5378 case 0x8b: /* mov Ev, Gv */
5379 ot
= mo_b_d(b
, dflag
);
5380 modrm
= cpu_ldub_code(env
, s
->pc
++);
5381 reg
= ((modrm
>> 3) & 7) | rex_r
;
5383 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5384 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5386 case 0x8e: /* mov seg, Gv */
5387 modrm
= cpu_ldub_code(env
, s
->pc
++);
5388 reg
= (modrm
>> 3) & 7;
5389 if (reg
>= 6 || reg
== R_CS
)
5391 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
5392 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5394 /* if reg == SS, inhibit interrupts/trace */
5395 /* If several instructions disable interrupts, only the
5397 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5398 gen_helper_set_inhibit_irq(cpu_env
);
5402 gen_jmp_im(s
->pc
- s
->cs_base
);
5406 case 0x8c: /* mov Gv, seg */
5407 modrm
= cpu_ldub_code(env
, s
->pc
++);
5408 reg
= (modrm
>> 3) & 7;
5409 mod
= (modrm
>> 6) & 3;
5412 gen_op_movl_T0_seg(reg
);
5413 ot
= mod
== 3 ? dflag
: MO_16
;
5414 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5417 case 0x1b6: /* movzbS Gv, Eb */
5418 case 0x1b7: /* movzwS Gv, Eb */
5419 case 0x1be: /* movsbS Gv, Eb */
5420 case 0x1bf: /* movswS Gv, Eb */
5425 /* d_ot is the size of destination */
5427 /* ot is the size of source */
5428 ot
= (b
& 1) + MO_8
;
5429 /* s_ot is the sign+size of source */
5430 s_ot
= b
& 8 ? MO_SIGN
| ot
: ot
;
5432 modrm
= cpu_ldub_code(env
, s
->pc
++);
5433 reg
= ((modrm
>> 3) & 7) | rex_r
;
5434 mod
= (modrm
>> 6) & 3;
5435 rm
= (modrm
& 7) | REX_B(s
);
5438 gen_op_mov_TN_reg(ot
, 0, rm
);
5441 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5444 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5447 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5451 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5454 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
5456 gen_lea_modrm(env
, s
, modrm
);
5457 gen_op_ld_v(s
, s_ot
, cpu_T
[0], cpu_A0
);
5458 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
5463 case 0x8d: /* lea */
5465 modrm
= cpu_ldub_code(env
, s
->pc
++);
5466 mod
= (modrm
>> 6) & 3;
5469 reg
= ((modrm
>> 3) & 7) | rex_r
;
5470 /* we must ensure that no segment is added */
5474 gen_lea_modrm(env
, s
, modrm
);
5476 gen_op_mov_reg_A0(ot
, reg
);
5479 case 0xa0: /* mov EAX, Ov */
5481 case 0xa2: /* mov Ov, EAX */
5484 target_ulong offset_addr
;
5486 ot
= mo_b_d(b
, dflag
);
5488 #ifdef TARGET_X86_64
5490 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5495 offset_addr
= insn_get(env
, s
, s
->aflag
);
5498 tcg_gen_movi_tl(cpu_A0
, offset_addr
);
5499 gen_add_A0_ds_seg(s
);
5501 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5502 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[0]);
5504 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5505 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5509 case 0xd7: /* xlat */
5510 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EBX
]);
5511 tcg_gen_ext8u_tl(cpu_T
[0], cpu_regs
[R_EAX
]);
5512 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5513 gen_extu(s
->aflag
, cpu_A0
);
5514 gen_add_A0_ds_seg(s
);
5515 gen_op_ld_v(s
, MO_8
, cpu_T
[0], cpu_A0
);
5516 gen_op_mov_reg_v(MO_8
, R_EAX
, cpu_T
[0]);
5518 case 0xb0 ... 0xb7: /* mov R, Ib */
5519 val
= insn_get(env
, s
, MO_8
);
5520 tcg_gen_movi_tl(cpu_T
[0], val
);
5521 gen_op_mov_reg_v(MO_8
, (b
& 7) | REX_B(s
), cpu_T
[0]);
5523 case 0xb8 ... 0xbf: /* mov R, Iv */
5524 #ifdef TARGET_X86_64
5525 if (dflag
== MO_64
) {
5528 tmp
= cpu_ldq_code(env
, s
->pc
);
5530 reg
= (b
& 7) | REX_B(s
);
5531 tcg_gen_movi_tl(cpu_T
[0], tmp
);
5532 gen_op_mov_reg_v(MO_64
, reg
, cpu_T
[0]);
5537 val
= insn_get(env
, s
, ot
);
5538 reg
= (b
& 7) | REX_B(s
);
5539 tcg_gen_movi_tl(cpu_T
[0], val
);
5540 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5544 case 0x91 ... 0x97: /* xchg R, EAX */
5547 reg
= (b
& 7) | REX_B(s
);
5551 case 0x87: /* xchg Ev, Gv */
5552 ot
= mo_b_d(b
, dflag
);
5553 modrm
= cpu_ldub_code(env
, s
->pc
++);
5554 reg
= ((modrm
>> 3) & 7) | rex_r
;
5555 mod
= (modrm
>> 6) & 3;
5557 rm
= (modrm
& 7) | REX_B(s
);
5559 gen_op_mov_TN_reg(ot
, 0, reg
);
5560 gen_op_mov_TN_reg(ot
, 1, rm
);
5561 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5562 gen_op_mov_reg_T1(ot
, reg
);
5564 gen_lea_modrm(env
, s
, modrm
);
5565 gen_op_mov_TN_reg(ot
, 0, reg
);
5566 /* for xchg, lock is implicit */
5567 if (!(prefixes
& PREFIX_LOCK
))
5569 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5570 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5571 if (!(prefixes
& PREFIX_LOCK
))
5572 gen_helper_unlock();
5573 gen_op_mov_reg_T1(ot
, reg
);
5576 case 0xc4: /* les Gv */
5577 /* In CODE64 this is VEX3; see above. */
5580 case 0xc5: /* lds Gv */
5581 /* In CODE64 this is VEX2; see above. */
5584 case 0x1b2: /* lss Gv */
5587 case 0x1b4: /* lfs Gv */
5590 case 0x1b5: /* lgs Gv */
5593 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
5594 modrm
= cpu_ldub_code(env
, s
->pc
++);
5595 reg
= ((modrm
>> 3) & 7) | rex_r
;
5596 mod
= (modrm
>> 6) & 3;
5599 gen_lea_modrm(env
, s
, modrm
);
5600 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5601 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5602 /* load the segment first to handle exceptions properly */
5603 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5604 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5605 /* then put the data */
5606 gen_op_mov_reg_T1(ot
, reg
);
5608 gen_jmp_im(s
->pc
- s
->cs_base
);
5613 /************************/
5621 ot
= mo_b_d(b
, dflag
);
5622 modrm
= cpu_ldub_code(env
, s
->pc
++);
5623 mod
= (modrm
>> 6) & 3;
5624 op
= (modrm
>> 3) & 7;
5630 gen_lea_modrm(env
, s
, modrm
);
5633 opreg
= (modrm
& 7) | REX_B(s
);
5638 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5641 shift
= cpu_ldub_code(env
, s
->pc
++);
5643 gen_shifti(s
, op
, ot
, opreg
, shift
);
5658 case 0x1a4: /* shld imm */
5662 case 0x1a5: /* shld cl */
5666 case 0x1ac: /* shrd imm */
5670 case 0x1ad: /* shrd cl */
5675 modrm
= cpu_ldub_code(env
, s
->pc
++);
5676 mod
= (modrm
>> 6) & 3;
5677 rm
= (modrm
& 7) | REX_B(s
);
5678 reg
= ((modrm
>> 3) & 7) | rex_r
;
5680 gen_lea_modrm(env
, s
, modrm
);
5685 gen_op_mov_TN_reg(ot
, 1, reg
);
5688 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5689 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5692 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5696 /************************/
5699 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5700 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5701 /* XXX: what to do if illegal op ? */
5702 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5705 modrm
= cpu_ldub_code(env
, s
->pc
++);
5706 mod
= (modrm
>> 6) & 3;
5708 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5711 gen_lea_modrm(env
, s
, modrm
);
5713 case 0x00 ... 0x07: /* fxxxs */
5714 case 0x10 ... 0x17: /* fixxxl */
5715 case 0x20 ... 0x27: /* fxxxl */
5716 case 0x30 ... 0x37: /* fixxx */
5723 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5724 s
->mem_index
, MO_LEUL
);
5725 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5728 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5729 s
->mem_index
, MO_LEUL
);
5730 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5733 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5734 s
->mem_index
, MO_LEQ
);
5735 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5739 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5740 s
->mem_index
, MO_LESW
);
5741 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5745 gen_helper_fp_arith_ST0_FT0(op1
);
5747 /* fcomp needs pop */
5748 gen_helper_fpop(cpu_env
);
5752 case 0x08: /* flds */
5753 case 0x0a: /* fsts */
5754 case 0x0b: /* fstps */
5755 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5756 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5757 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5762 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5763 s
->mem_index
, MO_LEUL
);
5764 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5767 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5768 s
->mem_index
, MO_LEUL
);
5769 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5772 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5773 s
->mem_index
, MO_LEQ
);
5774 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5778 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5779 s
->mem_index
, MO_LESW
);
5780 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5785 /* XXX: the corresponding CPUID bit must be tested ! */
5788 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5789 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5790 s
->mem_index
, MO_LEUL
);
5793 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5794 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5795 s
->mem_index
, MO_LEQ
);
5799 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5800 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5801 s
->mem_index
, MO_LEUW
);
5804 gen_helper_fpop(cpu_env
);
5809 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5810 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5811 s
->mem_index
, MO_LEUL
);
5814 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5815 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5816 s
->mem_index
, MO_LEUL
);
5819 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5820 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5821 s
->mem_index
, MO_LEQ
);
5825 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5826 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5827 s
->mem_index
, MO_LEUW
);
5831 gen_helper_fpop(cpu_env
);
5835 case 0x0c: /* fldenv mem */
5836 gen_update_cc_op(s
);
5837 gen_jmp_im(pc_start
- s
->cs_base
);
5838 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5840 case 0x0d: /* fldcw mem */
5841 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5842 s
->mem_index
, MO_LEUW
);
5843 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5845 case 0x0e: /* fnstenv mem */
5846 gen_update_cc_op(s
);
5847 gen_jmp_im(pc_start
- s
->cs_base
);
5848 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5850 case 0x0f: /* fnstcw mem */
5851 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5852 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5853 s
->mem_index
, MO_LEUW
);
5855 case 0x1d: /* fldt mem */
5856 gen_update_cc_op(s
);
5857 gen_jmp_im(pc_start
- s
->cs_base
);
5858 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5860 case 0x1f: /* fstpt mem */
5861 gen_update_cc_op(s
);
5862 gen_jmp_im(pc_start
- s
->cs_base
);
5863 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5864 gen_helper_fpop(cpu_env
);
5866 case 0x2c: /* frstor mem */
5867 gen_update_cc_op(s
);
5868 gen_jmp_im(pc_start
- s
->cs_base
);
5869 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5871 case 0x2e: /* fnsave mem */
5872 gen_update_cc_op(s
);
5873 gen_jmp_im(pc_start
- s
->cs_base
);
5874 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5876 case 0x2f: /* fnstsw mem */
5877 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5878 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5879 s
->mem_index
, MO_LEUW
);
5881 case 0x3c: /* fbld */
5882 gen_update_cc_op(s
);
5883 gen_jmp_im(pc_start
- s
->cs_base
);
5884 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5886 case 0x3e: /* fbstp */
5887 gen_update_cc_op(s
);
5888 gen_jmp_im(pc_start
- s
->cs_base
);
5889 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5890 gen_helper_fpop(cpu_env
);
5892 case 0x3d: /* fildll */
5893 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5894 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5896 case 0x3f: /* fistpll */
5897 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5898 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5899 gen_helper_fpop(cpu_env
);
5905 /* register float ops */
5909 case 0x08: /* fld sti */
5910 gen_helper_fpush(cpu_env
);
5911 gen_helper_fmov_ST0_STN(cpu_env
,
5912 tcg_const_i32((opreg
+ 1) & 7));
5914 case 0x09: /* fxchg sti */
5915 case 0x29: /* fxchg4 sti, undocumented op */
5916 case 0x39: /* fxchg7 sti, undocumented op */
5917 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5919 case 0x0a: /* grp d9/2 */
5922 /* check exceptions (FreeBSD FPU probe) */
5923 gen_update_cc_op(s
);
5924 gen_jmp_im(pc_start
- s
->cs_base
);
5925 gen_helper_fwait(cpu_env
);
5931 case 0x0c: /* grp d9/4 */
5934 gen_helper_fchs_ST0(cpu_env
);
5937 gen_helper_fabs_ST0(cpu_env
);
5940 gen_helper_fldz_FT0(cpu_env
);
5941 gen_helper_fcom_ST0_FT0(cpu_env
);
5944 gen_helper_fxam_ST0(cpu_env
);
5950 case 0x0d: /* grp d9/5 */
5954 gen_helper_fpush(cpu_env
);
5955 gen_helper_fld1_ST0(cpu_env
);
5958 gen_helper_fpush(cpu_env
);
5959 gen_helper_fldl2t_ST0(cpu_env
);
5962 gen_helper_fpush(cpu_env
);
5963 gen_helper_fldl2e_ST0(cpu_env
);
5966 gen_helper_fpush(cpu_env
);
5967 gen_helper_fldpi_ST0(cpu_env
);
5970 gen_helper_fpush(cpu_env
);
5971 gen_helper_fldlg2_ST0(cpu_env
);
5974 gen_helper_fpush(cpu_env
);
5975 gen_helper_fldln2_ST0(cpu_env
);
5978 gen_helper_fpush(cpu_env
);
5979 gen_helper_fldz_ST0(cpu_env
);
5986 case 0x0e: /* grp d9/6 */
5989 gen_helper_f2xm1(cpu_env
);
5992 gen_helper_fyl2x(cpu_env
);
5995 gen_helper_fptan(cpu_env
);
5997 case 3: /* fpatan */
5998 gen_helper_fpatan(cpu_env
);
6000 case 4: /* fxtract */
6001 gen_helper_fxtract(cpu_env
);
6003 case 5: /* fprem1 */
6004 gen_helper_fprem1(cpu_env
);
6006 case 6: /* fdecstp */
6007 gen_helper_fdecstp(cpu_env
);
6010 case 7: /* fincstp */
6011 gen_helper_fincstp(cpu_env
);
6015 case 0x0f: /* grp d9/7 */
6018 gen_helper_fprem(cpu_env
);
6020 case 1: /* fyl2xp1 */
6021 gen_helper_fyl2xp1(cpu_env
);
6024 gen_helper_fsqrt(cpu_env
);
6026 case 3: /* fsincos */
6027 gen_helper_fsincos(cpu_env
);
6029 case 5: /* fscale */
6030 gen_helper_fscale(cpu_env
);
6032 case 4: /* frndint */
6033 gen_helper_frndint(cpu_env
);
6036 gen_helper_fsin(cpu_env
);
6040 gen_helper_fcos(cpu_env
);
6044 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6045 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6046 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6052 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6054 gen_helper_fpop(cpu_env
);
6056 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6057 gen_helper_fp_arith_ST0_FT0(op1
);
6061 case 0x02: /* fcom */
6062 case 0x22: /* fcom2, undocumented op */
6063 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6064 gen_helper_fcom_ST0_FT0(cpu_env
);
6066 case 0x03: /* fcomp */
6067 case 0x23: /* fcomp3, undocumented op */
6068 case 0x32: /* fcomp5, undocumented op */
6069 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6070 gen_helper_fcom_ST0_FT0(cpu_env
);
6071 gen_helper_fpop(cpu_env
);
6073 case 0x15: /* da/5 */
6075 case 1: /* fucompp */
6076 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6077 gen_helper_fucom_ST0_FT0(cpu_env
);
6078 gen_helper_fpop(cpu_env
);
6079 gen_helper_fpop(cpu_env
);
6087 case 0: /* feni (287 only, just do nop here) */
6089 case 1: /* fdisi (287 only, just do nop here) */
6092 gen_helper_fclex(cpu_env
);
6094 case 3: /* fninit */
6095 gen_helper_fninit(cpu_env
);
6097 case 4: /* fsetpm (287 only, just do nop here) */
6103 case 0x1d: /* fucomi */
6104 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6107 gen_update_cc_op(s
);
6108 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6109 gen_helper_fucomi_ST0_FT0(cpu_env
);
6110 set_cc_op(s
, CC_OP_EFLAGS
);
6112 case 0x1e: /* fcomi */
6113 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6116 gen_update_cc_op(s
);
6117 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6118 gen_helper_fcomi_ST0_FT0(cpu_env
);
6119 set_cc_op(s
, CC_OP_EFLAGS
);
6121 case 0x28: /* ffree sti */
6122 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6124 case 0x2a: /* fst sti */
6125 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6127 case 0x2b: /* fstp sti */
6128 case 0x0b: /* fstp1 sti, undocumented op */
6129 case 0x3a: /* fstp8 sti, undocumented op */
6130 case 0x3b: /* fstp9 sti, undocumented op */
6131 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6132 gen_helper_fpop(cpu_env
);
6134 case 0x2c: /* fucom st(i) */
6135 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6136 gen_helper_fucom_ST0_FT0(cpu_env
);
6138 case 0x2d: /* fucomp st(i) */
6139 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6140 gen_helper_fucom_ST0_FT0(cpu_env
);
6141 gen_helper_fpop(cpu_env
);
6143 case 0x33: /* de/3 */
6145 case 1: /* fcompp */
6146 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6147 gen_helper_fcom_ST0_FT0(cpu_env
);
6148 gen_helper_fpop(cpu_env
);
6149 gen_helper_fpop(cpu_env
);
6155 case 0x38: /* ffreep sti, undocumented op */
6156 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6157 gen_helper_fpop(cpu_env
);
6159 case 0x3c: /* df/4 */
6162 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6163 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6164 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
6170 case 0x3d: /* fucomip */
6171 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6174 gen_update_cc_op(s
);
6175 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6176 gen_helper_fucomi_ST0_FT0(cpu_env
);
6177 gen_helper_fpop(cpu_env
);
6178 set_cc_op(s
, CC_OP_EFLAGS
);
6180 case 0x3e: /* fcomip */
6181 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6184 gen_update_cc_op(s
);
6185 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6186 gen_helper_fcomi_ST0_FT0(cpu_env
);
6187 gen_helper_fpop(cpu_env
);
6188 set_cc_op(s
, CC_OP_EFLAGS
);
6190 case 0x10 ... 0x13: /* fcmovxx */
6194 static const uint8_t fcmov_cc
[8] = {
6201 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6204 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6205 l1
= gen_new_label();
6206 gen_jcc1_noeob(s
, op1
, l1
);
6207 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6216 /************************/
6219 case 0xa4: /* movsS */
6221 ot
= mo_b_d(b
, dflag
);
6222 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6223 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6229 case 0xaa: /* stosS */
6231 ot
= mo_b_d(b
, dflag
);
6232 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6233 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6238 case 0xac: /* lodsS */
6240 ot
= mo_b_d(b
, dflag
);
6241 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6242 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6247 case 0xae: /* scasS */
6249 ot
= mo_b_d(b
, dflag
);
6250 if (prefixes
& PREFIX_REPNZ
) {
6251 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6252 } else if (prefixes
& PREFIX_REPZ
) {
6253 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6259 case 0xa6: /* cmpsS */
6261 ot
= mo_b_d(b
, dflag
);
6262 if (prefixes
& PREFIX_REPNZ
) {
6263 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6264 } else if (prefixes
& PREFIX_REPZ
) {
6265 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6270 case 0x6c: /* insS */
6272 ot
= mo_b_d32(b
, dflag
);
6273 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6274 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6275 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6276 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6277 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6281 gen_jmp(s
, s
->pc
- s
->cs_base
);
6285 case 0x6e: /* outsS */
6287 ot
= mo_b_d32(b
, dflag
);
6288 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6289 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6290 svm_is_rep(prefixes
) | 4);
6291 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6292 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6296 gen_jmp(s
, s
->pc
- s
->cs_base
);
6301 /************************/
6306 ot
= mo_b_d32(b
, dflag
);
6307 val
= cpu_ldub_code(env
, s
->pc
++);
6308 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6309 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6312 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6313 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6314 gen_op_mov_reg_T1(ot
, R_EAX
);
6317 gen_jmp(s
, s
->pc
- s
->cs_base
);
6322 ot
= mo_b_d32(b
, dflag
);
6323 val
= cpu_ldub_code(env
, s
->pc
++);
6324 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6325 svm_is_rep(prefixes
));
6326 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6330 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6331 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6332 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6335 gen_jmp(s
, s
->pc
- s
->cs_base
);
6340 ot
= mo_b_d32(b
, dflag
);
6341 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6342 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6343 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6346 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6347 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6348 gen_op_mov_reg_T1(ot
, R_EAX
);
6351 gen_jmp(s
, s
->pc
- s
->cs_base
);
6356 ot
= mo_b_d32(b
, dflag
);
6357 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6358 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6359 svm_is_rep(prefixes
));
6360 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6364 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6365 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6366 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6369 gen_jmp(s
, s
->pc
- s
->cs_base
);
6373 /************************/
6375 case 0xc2: /* ret im */
6376 val
= cpu_ldsw_code(env
, s
->pc
);
6379 gen_stack_update(s
, val
+ (1 << ot
));
6380 /* Note that gen_pop_T0 uses a zero-extending load. */
6384 case 0xc3: /* ret */
6386 gen_pop_update(s
, ot
);
6387 /* Note that gen_pop_T0 uses a zero-extending load. */
6391 case 0xca: /* lret im */
6392 val
= cpu_ldsw_code(env
, s
->pc
);
6395 if (s
->pe
&& !s
->vm86
) {
6396 gen_update_cc_op(s
);
6397 gen_jmp_im(pc_start
- s
->cs_base
);
6398 gen_helper_lret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6399 tcg_const_i32(val
));
6403 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6404 /* NOTE: keeping EIP updated is not a problem in case of
6408 gen_op_addl_A0_im(1 << dflag
);
6409 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6410 gen_op_movl_seg_T0_vm(R_CS
);
6411 /* add stack offset */
6412 gen_stack_update(s
, val
+ (2 << dflag
));
6416 case 0xcb: /* lret */
6419 case 0xcf: /* iret */
6420 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6423 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6424 set_cc_op(s
, CC_OP_EFLAGS
);
6425 } else if (s
->vm86
) {
6427 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6429 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6430 set_cc_op(s
, CC_OP_EFLAGS
);
6433 gen_update_cc_op(s
);
6434 gen_jmp_im(pc_start
- s
->cs_base
);
6435 gen_helper_iret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6436 tcg_const_i32(s
->pc
- s
->cs_base
));
6437 set_cc_op(s
, CC_OP_EFLAGS
);
6441 case 0xe8: /* call im */
6443 if (dflag
!= MO_16
) {
6444 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6446 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6448 next_eip
= s
->pc
- s
->cs_base
;
6450 if (dflag
== MO_16
) {
6452 } else if (!CODE64(s
)) {
6455 tcg_gen_movi_tl(cpu_T
[0], next_eip
);
6456 gen_push_v(s
, cpu_T
[0]);
6460 case 0x9a: /* lcall im */
6462 unsigned int selector
, offset
;
6467 offset
= insn_get(env
, s
, ot
);
6468 selector
= insn_get(env
, s
, MO_16
);
6470 tcg_gen_movi_tl(cpu_T
[0], selector
);
6471 tcg_gen_movi_tl(cpu_T
[1], offset
);
6474 case 0xe9: /* jmp im */
6475 if (dflag
!= MO_16
) {
6476 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6478 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6480 tval
+= s
->pc
- s
->cs_base
;
6481 if (dflag
== MO_16
) {
6483 } else if (!CODE64(s
)) {
6488 case 0xea: /* ljmp im */
6490 unsigned int selector
, offset
;
6495 offset
= insn_get(env
, s
, ot
);
6496 selector
= insn_get(env
, s
, MO_16
);
6498 tcg_gen_movi_tl(cpu_T
[0], selector
);
6499 tcg_gen_movi_tl(cpu_T
[1], offset
);
6502 case 0xeb: /* jmp Jb */
6503 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6504 tval
+= s
->pc
- s
->cs_base
;
6505 if (dflag
== MO_16
) {
6510 case 0x70 ... 0x7f: /* jcc Jb */
6511 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6513 case 0x180 ... 0x18f: /* jcc Jv */
6514 if (dflag
!= MO_16
) {
6515 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6517 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6520 next_eip
= s
->pc
- s
->cs_base
;
6522 if (dflag
== MO_16
) {
6525 gen_jcc(s
, b
, tval
, next_eip
);
6528 case 0x190 ... 0x19f: /* setcc Gv */
6529 modrm
= cpu_ldub_code(env
, s
->pc
++);
6530 gen_setcc1(s
, b
, cpu_T
[0]);
6531 gen_ldst_modrm(env
, s
, modrm
, MO_8
, OR_TMP0
, 1);
6533 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6534 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6538 modrm
= cpu_ldub_code(env
, s
->pc
++);
6539 reg
= ((modrm
>> 3) & 7) | rex_r
;
6540 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6543 /************************/
6545 case 0x9c: /* pushf */
6546 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6547 if (s
->vm86
&& s
->iopl
!= 3) {
6548 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6550 gen_update_cc_op(s
);
6551 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6552 gen_push_v(s
, cpu_T
[0]);
6555 case 0x9d: /* popf */
6556 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6557 if (s
->vm86
&& s
->iopl
!= 3) {
6558 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6562 if (dflag
!= MO_16
) {
6563 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6564 tcg_const_i32((TF_MASK
| AC_MASK
|
6569 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6570 tcg_const_i32((TF_MASK
| AC_MASK
|
6572 IF_MASK
| IOPL_MASK
)
6576 if (s
->cpl
<= s
->iopl
) {
6577 if (dflag
!= MO_16
) {
6578 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6579 tcg_const_i32((TF_MASK
|
6585 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6586 tcg_const_i32((TF_MASK
|
6594 if (dflag
!= MO_16
) {
6595 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6596 tcg_const_i32((TF_MASK
| AC_MASK
|
6597 ID_MASK
| NT_MASK
)));
6599 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6600 tcg_const_i32((TF_MASK
| AC_MASK
|
6606 gen_pop_update(s
, ot
);
6607 set_cc_op(s
, CC_OP_EFLAGS
);
6608 /* abort translation because TF/AC flag may change */
6609 gen_jmp_im(s
->pc
- s
->cs_base
);
6613 case 0x9e: /* sahf */
6614 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6616 gen_op_mov_TN_reg(MO_8
, 0, R_AH
);
6617 gen_compute_eflags(s
);
6618 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6619 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6620 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6622 case 0x9f: /* lahf */
6623 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6625 gen_compute_eflags(s
);
6626 /* Note: gen_compute_eflags() only gives the condition codes */
6627 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6628 gen_op_mov_reg_v(MO_8
, R_AH
, cpu_T
[0]);
6630 case 0xf5: /* cmc */
6631 gen_compute_eflags(s
);
6632 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6634 case 0xf8: /* clc */
6635 gen_compute_eflags(s
);
6636 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6638 case 0xf9: /* stc */
6639 gen_compute_eflags(s
);
6640 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6642 case 0xfc: /* cld */
6643 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6644 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6646 case 0xfd: /* std */
6647 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6648 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6651 /************************/
6652 /* bit operations */
6653 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6655 modrm
= cpu_ldub_code(env
, s
->pc
++);
6656 op
= (modrm
>> 3) & 7;
6657 mod
= (modrm
>> 6) & 3;
6658 rm
= (modrm
& 7) | REX_B(s
);
6661 gen_lea_modrm(env
, s
, modrm
);
6662 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6664 gen_op_mov_TN_reg(ot
, 0, rm
);
6667 val
= cpu_ldub_code(env
, s
->pc
++);
6668 tcg_gen_movi_tl(cpu_T
[1], val
);
6673 case 0x1a3: /* bt Gv, Ev */
6676 case 0x1ab: /* bts */
6679 case 0x1b3: /* btr */
6682 case 0x1bb: /* btc */
6686 modrm
= cpu_ldub_code(env
, s
->pc
++);
6687 reg
= ((modrm
>> 3) & 7) | rex_r
;
6688 mod
= (modrm
>> 6) & 3;
6689 rm
= (modrm
& 7) | REX_B(s
);
6690 gen_op_mov_TN_reg(MO_32
, 1, reg
);
6692 gen_lea_modrm(env
, s
, modrm
);
6693 /* specific case: we need to add a displacement */
6694 gen_exts(ot
, cpu_T
[1]);
6695 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6696 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6697 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6698 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6700 gen_op_mov_TN_reg(ot
, 0, rm
);
6703 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6706 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6707 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6710 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6711 tcg_gen_movi_tl(cpu_tmp0
, 1);
6712 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6713 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6716 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6717 tcg_gen_movi_tl(cpu_tmp0
, 1);
6718 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6719 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6720 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6724 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6725 tcg_gen_movi_tl(cpu_tmp0
, 1);
6726 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6727 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6730 set_cc_op(s
, CC_OP_SARB
+ ot
);
6733 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
6735 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
6737 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6738 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6741 case 0x1bc: /* bsf / tzcnt */
6742 case 0x1bd: /* bsr / lzcnt */
6744 modrm
= cpu_ldub_code(env
, s
->pc
++);
6745 reg
= ((modrm
>> 3) & 7) | rex_r
;
6746 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
6747 gen_extu(ot
, cpu_T
[0]);
6749 /* Note that lzcnt and tzcnt are in different extensions. */
6750 if ((prefixes
& PREFIX_REPZ
)
6752 ? s
->cpuid_ext3_features
& CPUID_EXT3_ABM
6753 : s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)) {
6755 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
6757 /* For lzcnt, reduce the target_ulong result by the
6758 number of zeros that we expect to find at the top. */
6759 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6760 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- size
);
6762 /* For tzcnt, a zero input must return the operand size:
6763 force all bits outside the operand size to 1. */
6764 target_ulong mask
= (target_ulong
)-2 << (size
- 1);
6765 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], mask
);
6766 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6768 /* For lzcnt/tzcnt, C and Z bits are defined and are
6769 related to the result. */
6770 gen_op_update1_cc();
6771 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
6773 /* For bsr/bsf, only the Z bit is defined and it is related
6774 to the input and not the result. */
6775 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
6776 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6778 /* For bsr, return the bit index of the first 1 bit,
6779 not the count of leading zeros. */
6780 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6781 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- 1);
6783 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6785 /* ??? The manual says that the output is undefined when the
6786 input is zero, but real hardware leaves it unchanged, and
6787 real programs appear to depend on that. */
6788 tcg_gen_movi_tl(cpu_tmp0
, 0);
6789 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[0], cpu_cc_dst
, cpu_tmp0
,
6790 cpu_regs
[reg
], cpu_T
[0]);
6792 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
6794 /************************/
6796 case 0x27: /* daa */
6799 gen_update_cc_op(s
);
6800 gen_helper_daa(cpu_env
);
6801 set_cc_op(s
, CC_OP_EFLAGS
);
6803 case 0x2f: /* das */
6806 gen_update_cc_op(s
);
6807 gen_helper_das(cpu_env
);
6808 set_cc_op(s
, CC_OP_EFLAGS
);
6810 case 0x37: /* aaa */
6813 gen_update_cc_op(s
);
6814 gen_helper_aaa(cpu_env
);
6815 set_cc_op(s
, CC_OP_EFLAGS
);
6817 case 0x3f: /* aas */
6820 gen_update_cc_op(s
);
6821 gen_helper_aas(cpu_env
);
6822 set_cc_op(s
, CC_OP_EFLAGS
);
6824 case 0xd4: /* aam */
6827 val
= cpu_ldub_code(env
, s
->pc
++);
6829 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6831 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6832 set_cc_op(s
, CC_OP_LOGICB
);
6835 case 0xd5: /* aad */
6838 val
= cpu_ldub_code(env
, s
->pc
++);
6839 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6840 set_cc_op(s
, CC_OP_LOGICB
);
6842 /************************/
6844 case 0x90: /* nop */
6845 /* XXX: correct lock test for all insn */
6846 if (prefixes
& PREFIX_LOCK
) {
6849 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6851 goto do_xchg_reg_eax
;
6853 if (prefixes
& PREFIX_REPZ
) {
6854 gen_update_cc_op(s
);
6855 gen_jmp_im(pc_start
- s
->cs_base
);
6856 gen_helper_pause(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6857 s
->is_jmp
= DISAS_TB_JUMP
;
6860 case 0x9b: /* fwait */
6861 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6862 (HF_MP_MASK
| HF_TS_MASK
)) {
6863 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6865 gen_update_cc_op(s
);
6866 gen_jmp_im(pc_start
- s
->cs_base
);
6867 gen_helper_fwait(cpu_env
);
6870 case 0xcc: /* int3 */
6871 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6873 case 0xcd: /* int N */
6874 val
= cpu_ldub_code(env
, s
->pc
++);
6875 if (s
->vm86
&& s
->iopl
!= 3) {
6876 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6878 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6881 case 0xce: /* into */
6884 gen_update_cc_op(s
);
6885 gen_jmp_im(pc_start
- s
->cs_base
);
6886 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6889 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6890 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6892 gen_debug(s
, pc_start
- s
->cs_base
);
6896 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6900 case 0xfa: /* cli */
6902 if (s
->cpl
<= s
->iopl
) {
6903 gen_helper_cli(cpu_env
);
6905 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6909 gen_helper_cli(cpu_env
);
6911 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6915 case 0xfb: /* sti */
6917 if (s
->cpl
<= s
->iopl
) {
6919 gen_helper_sti(cpu_env
);
6920 /* interruptions are enabled only the first insn after sti */
6921 /* If several instructions disable interrupts, only the
6923 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6924 gen_helper_set_inhibit_irq(cpu_env
);
6925 /* give a chance to handle pending irqs */
6926 gen_jmp_im(s
->pc
- s
->cs_base
);
6929 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6935 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6939 case 0x62: /* bound */
6943 modrm
= cpu_ldub_code(env
, s
->pc
++);
6944 reg
= (modrm
>> 3) & 7;
6945 mod
= (modrm
>> 6) & 3;
6948 gen_op_mov_TN_reg(ot
, 0, reg
);
6949 gen_lea_modrm(env
, s
, modrm
);
6950 gen_jmp_im(pc_start
- s
->cs_base
);
6951 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6953 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6955 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6958 case 0x1c8 ... 0x1cf: /* bswap reg */
6959 reg
= (b
& 7) | REX_B(s
);
6960 #ifdef TARGET_X86_64
6961 if (dflag
== MO_64
) {
6962 gen_op_mov_TN_reg(MO_64
, 0, reg
);
6963 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6964 gen_op_mov_reg_v(MO_64
, reg
, cpu_T
[0]);
6968 gen_op_mov_TN_reg(MO_32
, 0, reg
);
6969 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6970 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6971 gen_op_mov_reg_v(MO_32
, reg
, cpu_T
[0]);
6974 case 0xd6: /* salc */
6977 gen_compute_eflags_c(s
, cpu_T
[0]);
6978 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6979 gen_op_mov_reg_v(MO_8
, R_EAX
, cpu_T
[0]);
6981 case 0xe0: /* loopnz */
6982 case 0xe1: /* loopz */
6983 case 0xe2: /* loop */
6984 case 0xe3: /* jecxz */
6988 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6989 next_eip
= s
->pc
- s
->cs_base
;
6991 if (dflag
== MO_16
) {
6995 l1
= gen_new_label();
6996 l2
= gen_new_label();
6997 l3
= gen_new_label();
7000 case 0: /* loopnz */
7002 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7003 gen_op_jz_ecx(s
->aflag
, l3
);
7004 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7007 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7008 gen_op_jnz_ecx(s
->aflag
, l1
);
7012 gen_op_jz_ecx(s
->aflag
, l1
);
7017 gen_jmp_im(next_eip
);
7026 case 0x130: /* wrmsr */
7027 case 0x132: /* rdmsr */
7029 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7031 gen_update_cc_op(s
);
7032 gen_jmp_im(pc_start
- s
->cs_base
);
7034 gen_helper_rdmsr(cpu_env
);
7036 gen_helper_wrmsr(cpu_env
);
7040 case 0x131: /* rdtsc */
7041 gen_update_cc_op(s
);
7042 gen_jmp_im(pc_start
- s
->cs_base
);
7045 gen_helper_rdtsc(cpu_env
);
7048 gen_jmp(s
, s
->pc
- s
->cs_base
);
7051 case 0x133: /* rdpmc */
7052 gen_update_cc_op(s
);
7053 gen_jmp_im(pc_start
- s
->cs_base
);
7054 gen_helper_rdpmc(cpu_env
);
7056 case 0x134: /* sysenter */
7057 /* For Intel SYSENTER is valid on 64-bit */
7058 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7061 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7063 gen_update_cc_op(s
);
7064 gen_jmp_im(pc_start
- s
->cs_base
);
7065 gen_helper_sysenter(cpu_env
);
7069 case 0x135: /* sysexit */
7070 /* For Intel SYSEXIT is valid on 64-bit */
7071 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7074 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7076 gen_update_cc_op(s
);
7077 gen_jmp_im(pc_start
- s
->cs_base
);
7078 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
- 1));
7082 #ifdef TARGET_X86_64
7083 case 0x105: /* syscall */
7084 /* XXX: is it usable in real mode ? */
7085 gen_update_cc_op(s
);
7086 gen_jmp_im(pc_start
- s
->cs_base
);
7087 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7090 case 0x107: /* sysret */
7092 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7094 gen_update_cc_op(s
);
7095 gen_jmp_im(pc_start
- s
->cs_base
);
7096 gen_helper_sysret(cpu_env
, tcg_const_i32(dflag
- 1));
7097 /* condition codes are modified only in long mode */
7099 set_cc_op(s
, CC_OP_EFLAGS
);
7105 case 0x1a2: /* cpuid */
7106 gen_update_cc_op(s
);
7107 gen_jmp_im(pc_start
- s
->cs_base
);
7108 gen_helper_cpuid(cpu_env
);
7110 case 0xf4: /* hlt */
7112 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7114 gen_update_cc_op(s
);
7115 gen_jmp_im(pc_start
- s
->cs_base
);
7116 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7117 s
->is_jmp
= DISAS_TB_JUMP
;
7121 modrm
= cpu_ldub_code(env
, s
->pc
++);
7122 mod
= (modrm
>> 6) & 3;
7123 op
= (modrm
>> 3) & 7;
7126 if (!s
->pe
|| s
->vm86
)
7128 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7129 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7130 ot
= mod
== 3 ? dflag
: MO_16
;
7131 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7134 if (!s
->pe
|| s
->vm86
)
7137 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7139 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7140 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7141 gen_jmp_im(pc_start
- s
->cs_base
);
7142 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7143 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7147 if (!s
->pe
|| s
->vm86
)
7149 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7150 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7151 ot
= mod
== 3 ? dflag
: MO_16
;
7152 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7155 if (!s
->pe
|| s
->vm86
)
7158 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7160 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7161 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7162 gen_jmp_im(pc_start
- s
->cs_base
);
7163 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7164 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7169 if (!s
->pe
|| s
->vm86
)
7171 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7172 gen_update_cc_op(s
);
7174 gen_helper_verr(cpu_env
, cpu_T
[0]);
7176 gen_helper_verw(cpu_env
, cpu_T
[0]);
7178 set_cc_op(s
, CC_OP_EFLAGS
);
7185 modrm
= cpu_ldub_code(env
, s
->pc
++);
7186 mod
= (modrm
>> 6) & 3;
7187 op
= (modrm
>> 3) & 7;
7193 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7194 gen_lea_modrm(env
, s
, modrm
);
7195 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7196 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7197 gen_add_A0_im(s
, 2);
7198 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7199 if (dflag
== MO_16
) {
7200 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7202 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7207 case 0: /* monitor */
7208 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7211 gen_update_cc_op(s
);
7212 gen_jmp_im(pc_start
- s
->cs_base
);
7213 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EAX
]);
7214 gen_extu(s
->aflag
, cpu_A0
);
7215 gen_add_A0_ds_seg(s
);
7216 gen_helper_monitor(cpu_env
, cpu_A0
);
7219 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7222 gen_update_cc_op(s
);
7223 gen_jmp_im(pc_start
- s
->cs_base
);
7224 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7228 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7232 gen_helper_clac(cpu_env
);
7233 gen_jmp_im(s
->pc
- s
->cs_base
);
7237 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7241 gen_helper_stac(cpu_env
);
7242 gen_jmp_im(s
->pc
- s
->cs_base
);
7249 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7250 gen_lea_modrm(env
, s
, modrm
);
7251 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7252 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7253 gen_add_A0_im(s
, 2);
7254 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7255 if (dflag
== MO_16
) {
7256 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7258 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7264 gen_update_cc_op(s
);
7265 gen_jmp_im(pc_start
- s
->cs_base
);
7268 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7271 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7274 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
- 1),
7275 tcg_const_i32(s
->pc
- pc_start
));
7277 s
->is_jmp
= DISAS_TB_JUMP
;
7280 case 1: /* VMMCALL */
7281 if (!(s
->flags
& HF_SVME_MASK
))
7283 gen_helper_vmmcall(cpu_env
);
7285 case 2: /* VMLOAD */
7286 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7289 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7292 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7295 case 3: /* VMSAVE */
7296 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7299 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7302 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7306 if ((!(s
->flags
& HF_SVME_MASK
) &&
7307 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7311 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7314 gen_helper_stgi(cpu_env
);
7318 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7321 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7324 gen_helper_clgi(cpu_env
);
7327 case 6: /* SKINIT */
7328 if ((!(s
->flags
& HF_SVME_MASK
) &&
7329 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7332 gen_helper_skinit(cpu_env
);
7334 case 7: /* INVLPGA */
7335 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7338 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7341 gen_helper_invlpga(cpu_env
,
7342 tcg_const_i32(s
->aflag
- 1));
7348 } else if (s
->cpl
!= 0) {
7349 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7351 gen_svm_check_intercept(s
, pc_start
,
7352 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7353 gen_lea_modrm(env
, s
, modrm
);
7354 gen_op_ld_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
7355 gen_add_A0_im(s
, 2);
7356 gen_op_ld_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7357 if (dflag
== MO_16
) {
7358 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7361 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7362 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7364 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7365 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7370 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7371 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7372 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7374 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7376 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 1);
7380 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7382 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7383 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7384 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7385 gen_jmp_im(s
->pc
- s
->cs_base
);
7390 if (mod
!= 3) { /* invlpg */
7392 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7394 gen_update_cc_op(s
);
7395 gen_jmp_im(pc_start
- s
->cs_base
);
7396 gen_lea_modrm(env
, s
, modrm
);
7397 gen_helper_invlpg(cpu_env
, cpu_A0
);
7398 gen_jmp_im(s
->pc
- s
->cs_base
);
7403 case 0: /* swapgs */
7404 #ifdef TARGET_X86_64
7407 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7409 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7410 offsetof(CPUX86State
,segs
[R_GS
].base
));
7411 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7412 offsetof(CPUX86State
,kernelgsbase
));
7413 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7414 offsetof(CPUX86State
,segs
[R_GS
].base
));
7415 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7416 offsetof(CPUX86State
,kernelgsbase
));
7424 case 1: /* rdtscp */
7425 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7427 gen_update_cc_op(s
);
7428 gen_jmp_im(pc_start
- s
->cs_base
);
7431 gen_helper_rdtscp(cpu_env
);
7434 gen_jmp(s
, s
->pc
- s
->cs_base
);
7446 case 0x108: /* invd */
7447 case 0x109: /* wbinvd */
7449 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7451 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7455 case 0x63: /* arpl or movslS (x86_64) */
7456 #ifdef TARGET_X86_64
7459 /* d_ot is the size of destination */
7462 modrm
= cpu_ldub_code(env
, s
->pc
++);
7463 reg
= ((modrm
>> 3) & 7) | rex_r
;
7464 mod
= (modrm
>> 6) & 3;
7465 rm
= (modrm
& 7) | REX_B(s
);
7468 gen_op_mov_TN_reg(MO_32
, 0, rm
);
7470 if (d_ot
== MO_64
) {
7471 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7473 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
7475 gen_lea_modrm(env
, s
, modrm
);
7476 gen_op_ld_v(s
, MO_32
| MO_SIGN
, cpu_T
[0], cpu_A0
);
7477 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
7483 TCGv t0
, t1
, t2
, a0
;
7485 if (!s
->pe
|| s
->vm86
)
7487 t0
= tcg_temp_local_new();
7488 t1
= tcg_temp_local_new();
7489 t2
= tcg_temp_local_new();
7491 modrm
= cpu_ldub_code(env
, s
->pc
++);
7492 reg
= (modrm
>> 3) & 7;
7493 mod
= (modrm
>> 6) & 3;
7496 gen_lea_modrm(env
, s
, modrm
);
7497 gen_op_ld_v(s
, ot
, t0
, cpu_A0
);
7498 a0
= tcg_temp_local_new();
7499 tcg_gen_mov_tl(a0
, cpu_A0
);
7501 gen_op_mov_v_reg(ot
, t0
, rm
);
7504 gen_op_mov_v_reg(ot
, t1
, reg
);
7505 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7506 tcg_gen_andi_tl(t1
, t1
, 3);
7507 tcg_gen_movi_tl(t2
, 0);
7508 label1
= gen_new_label();
7509 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7510 tcg_gen_andi_tl(t0
, t0
, ~3);
7511 tcg_gen_or_tl(t0
, t0
, t1
);
7512 tcg_gen_movi_tl(t2
, CC_Z
);
7513 gen_set_label(label1
);
7515 gen_op_st_v(s
, ot
, t0
, a0
);
7518 gen_op_mov_reg_v(ot
, rm
, t0
);
7520 gen_compute_eflags(s
);
7521 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7522 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7528 case 0x102: /* lar */
7529 case 0x103: /* lsl */
7533 if (!s
->pe
|| s
->vm86
)
7535 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
7536 modrm
= cpu_ldub_code(env
, s
->pc
++);
7537 reg
= ((modrm
>> 3) & 7) | rex_r
;
7538 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7539 t0
= tcg_temp_local_new();
7540 gen_update_cc_op(s
);
7542 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7544 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7546 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7547 label1
= gen_new_label();
7548 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7549 gen_op_mov_reg_v(ot
, reg
, t0
);
7550 gen_set_label(label1
);
7551 set_cc_op(s
, CC_OP_EFLAGS
);
7556 modrm
= cpu_ldub_code(env
, s
->pc
++);
7557 mod
= (modrm
>> 6) & 3;
7558 op
= (modrm
>> 3) & 7;
7560 case 0: /* prefetchnta */
7561 case 1: /* prefetchnt0 */
7562 case 2: /* prefetchnt0 */
7563 case 3: /* prefetchnt0 */
7566 gen_lea_modrm(env
, s
, modrm
);
7567 /* nothing more to do */
7569 default: /* nop (multi byte) */
7570 gen_nop_modrm(env
, s
, modrm
);
7574 case 0x119 ... 0x11f: /* nop (multi byte) */
7575 modrm
= cpu_ldub_code(env
, s
->pc
++);
7576 gen_nop_modrm(env
, s
, modrm
);
7578 case 0x120: /* mov reg, crN */
7579 case 0x122: /* mov crN, reg */
7581 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7583 modrm
= cpu_ldub_code(env
, s
->pc
++);
7584 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7585 * AMD documentation (24594.pdf) and testing of
7586 * intel 386 and 486 processors all show that the mod bits
7587 * are assumed to be 1's, regardless of actual values.
7589 rm
= (modrm
& 7) | REX_B(s
);
7590 reg
= ((modrm
>> 3) & 7) | rex_r
;
7595 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7596 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7605 gen_update_cc_op(s
);
7606 gen_jmp_im(pc_start
- s
->cs_base
);
7608 gen_op_mov_TN_reg(ot
, 0, rm
);
7609 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7611 gen_jmp_im(s
->pc
- s
->cs_base
);
7614 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7615 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
7623 case 0x121: /* mov reg, drN */
7624 case 0x123: /* mov drN, reg */
7626 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7628 modrm
= cpu_ldub_code(env
, s
->pc
++);
7629 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7630 * AMD documentation (24594.pdf) and testing of
7631 * intel 386 and 486 processors all show that the mod bits
7632 * are assumed to be 1's, regardless of actual values.
7634 rm
= (modrm
& 7) | REX_B(s
);
7635 reg
= ((modrm
>> 3) & 7) | rex_r
;
7640 /* XXX: do it dynamically with CR4.DE bit */
7641 if (reg
== 4 || reg
== 5 || reg
>= 8)
7644 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7645 gen_op_mov_TN_reg(ot
, 0, rm
);
7646 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7647 gen_jmp_im(s
->pc
- s
->cs_base
);
7650 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7651 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7652 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
7656 case 0x106: /* clts */
7658 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7660 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7661 gen_helper_clts(cpu_env
);
7662 /* abort block because static cpu state changed */
7663 gen_jmp_im(s
->pc
- s
->cs_base
);
7667 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7668 case 0x1c3: /* MOVNTI reg, mem */
7669 if (!(s
->cpuid_features
& CPUID_SSE2
))
7671 ot
= mo_64_32(dflag
);
7672 modrm
= cpu_ldub_code(env
, s
->pc
++);
7673 mod
= (modrm
>> 6) & 3;
7676 reg
= ((modrm
>> 3) & 7) | rex_r
;
7677 /* generate a generic store */
7678 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7681 modrm
= cpu_ldub_code(env
, s
->pc
++);
7682 mod
= (modrm
>> 6) & 3;
7683 op
= (modrm
>> 3) & 7;
7685 case 0: /* fxsave */
7686 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7687 (s
->prefix
& PREFIX_LOCK
))
7689 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7690 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7693 gen_lea_modrm(env
, s
, modrm
);
7694 gen_update_cc_op(s
);
7695 gen_jmp_im(pc_start
- s
->cs_base
);
7696 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7698 case 1: /* fxrstor */
7699 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7700 (s
->prefix
& PREFIX_LOCK
))
7702 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7703 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7706 gen_lea_modrm(env
, s
, modrm
);
7707 gen_update_cc_op(s
);
7708 gen_jmp_im(pc_start
- s
->cs_base
);
7709 gen_helper_fxrstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7711 case 2: /* ldmxcsr */
7712 case 3: /* stmxcsr */
7713 if (s
->flags
& HF_TS_MASK
) {
7714 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7717 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7720 gen_lea_modrm(env
, s
, modrm
);
7722 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
7723 s
->mem_index
, MO_LEUL
);
7724 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7726 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7727 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
7730 case 5: /* lfence */
7731 case 6: /* mfence */
7732 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7735 case 7: /* sfence / clflush */
7736 if ((modrm
& 0xc7) == 0xc0) {
7738 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7739 if (!(s
->cpuid_features
& CPUID_SSE
))
7743 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7745 gen_lea_modrm(env
, s
, modrm
);
7752 case 0x10d: /* 3DNow! prefetch(w) */
7753 modrm
= cpu_ldub_code(env
, s
->pc
++);
7754 mod
= (modrm
>> 6) & 3;
7757 gen_lea_modrm(env
, s
, modrm
);
7758 /* ignore for now */
7760 case 0x1aa: /* rsm */
7761 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7762 if (!(s
->flags
& HF_SMM_MASK
))
7764 gen_update_cc_op(s
);
7765 gen_jmp_im(s
->pc
- s
->cs_base
);
7766 gen_helper_rsm(cpu_env
);
7769 case 0x1b8: /* SSE4.2 popcnt */
7770 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7773 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7776 modrm
= cpu_ldub_code(env
, s
->pc
++);
7777 reg
= ((modrm
>> 3) & 7) | rex_r
;
7779 if (s
->prefix
& PREFIX_DATA
) {
7782 ot
= mo_64_32(dflag
);
7785 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7786 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7787 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
7789 set_cc_op(s
, CC_OP_EFLAGS
);
7791 case 0x10e ... 0x10f:
7792 /* 3DNow! instructions, ignore prefixes */
7793 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7794 case 0x110 ... 0x117:
7795 case 0x128 ... 0x12f:
7796 case 0x138 ... 0x13a:
7797 case 0x150 ... 0x179:
7798 case 0x17c ... 0x17f:
7800 case 0x1c4 ... 0x1c6:
7801 case 0x1d0 ... 0x1fe:
7802 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7807 /* lock generation */
7808 if (s
->prefix
& PREFIX_LOCK
)
7809 gen_helper_unlock();
7812 if (s
->prefix
& PREFIX_LOCK
)
7813 gen_helper_unlock();
7814 /* XXX: ensure that no lock was generated */
7815 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7819 void optimize_flags_init(void)
7821 static const char reg_names
[CPU_NB_REGS
][4] = {
7822 #ifdef TARGET_X86_64
7852 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7853 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7854 offsetof(CPUX86State
, cc_op
), "cc_op");
7855 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7857 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7859 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src2
),
7862 for (i
= 0; i
< CPU_NB_REGS
; ++i
) {
7863 cpu_regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
7864 offsetof(CPUX86State
, regs
[i
]),
7869 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7870 basic block 'tb'. If search_pc is TRUE, also generate PC
7871 information for each intermediate instruction. */
7872 static inline void gen_intermediate_code_internal(X86CPU
*cpu
,
7873 TranslationBlock
*tb
,
7876 CPUState
*cs
= CPU(cpu
);
7877 CPUX86State
*env
= &cpu
->env
;
7878 DisasContext dc1
, *dc
= &dc1
;
7879 target_ulong pc_ptr
;
7880 uint16_t *gen_opc_end
;
7884 target_ulong pc_start
;
7885 target_ulong cs_base
;
7889 /* generate intermediate code */
7891 cs_base
= tb
->cs_base
;
7894 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7895 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7896 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7897 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7899 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7900 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7901 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7902 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7903 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
7904 dc
->cc_op
= CC_OP_DYNAMIC
;
7905 dc
->cc_op_dirty
= false;
7906 dc
->cs_base
= cs_base
;
7908 dc
->popl_esp_hack
= 0;
7909 /* select memory access functions */
7911 if (flags
& HF_SOFTMMU_MASK
) {
7912 dc
->mem_index
= cpu_mmu_index(env
);
7914 dc
->cpuid_features
= env
->features
[FEAT_1_EDX
];
7915 dc
->cpuid_ext_features
= env
->features
[FEAT_1_ECX
];
7916 dc
->cpuid_ext2_features
= env
->features
[FEAT_8000_0001_EDX
];
7917 dc
->cpuid_ext3_features
= env
->features
[FEAT_8000_0001_ECX
];
7918 dc
->cpuid_7_0_ebx_features
= env
->features
[FEAT_7_0_EBX
];
7919 #ifdef TARGET_X86_64
7920 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7921 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7924 dc
->jmp_opt
= !(dc
->tf
|| cs
->singlestep_enabled
||
7925 (flags
& HF_INHIBIT_IRQ_MASK
)
7926 #ifndef CONFIG_SOFTMMU
7927 || (flags
& HF_SOFTMMU_MASK
)
7931 /* check addseg logic */
7932 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7933 printf("ERROR addseg\n");
7936 cpu_T
[0] = tcg_temp_new();
7937 cpu_T
[1] = tcg_temp_new();
7938 cpu_A0
= tcg_temp_new();
7940 cpu_tmp0
= tcg_temp_new();
7941 cpu_tmp1_i64
= tcg_temp_new_i64();
7942 cpu_tmp2_i32
= tcg_temp_new_i32();
7943 cpu_tmp3_i32
= tcg_temp_new_i32();
7944 cpu_tmp4
= tcg_temp_new();
7945 cpu_ptr0
= tcg_temp_new_ptr();
7946 cpu_ptr1
= tcg_temp_new_ptr();
7947 cpu_cc_srcT
= tcg_temp_local_new();
7949 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
7951 dc
->is_jmp
= DISAS_NEXT
;
7955 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7957 max_insns
= CF_COUNT_MASK
;
7961 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7962 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7963 if (bp
->pc
== pc_ptr
&&
7964 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7965 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7971 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
7975 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
7977 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
7978 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7979 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
7980 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
7982 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7985 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
7987 /* stop translation if indicated */
7990 /* if single step mode, we generate only one instruction and
7991 generate an exception */
7992 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7993 the flag and abort the translation to give the irqs a
7994 change to be happen */
7995 if (dc
->tf
|| dc
->singlestep_enabled
||
7996 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7997 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8001 /* if too long translation, stop generation too */
8002 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
8003 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
8004 num_insns
>= max_insns
) {
8005 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8010 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8015 if (tb
->cflags
& CF_LAST_IO
)
8017 gen_tb_end(tb
, num_insns
);
8018 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
8019 /* we don't forget to fill the last values */
8021 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8024 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8028 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8030 qemu_log("----------------\n");
8031 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8032 #ifdef TARGET_X86_64
8037 disas_flags
= !dc
->code32
;
8038 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8044 tb
->size
= pc_ptr
- pc_start
;
8045 tb
->icount
= num_insns
;
8049 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8051 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, false);
8054 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8056 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, true);
8059 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8063 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8065 qemu_log("RESTORE:\n");
8066 for(i
= 0;i
<= pc_pos
; i
++) {
8067 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8068 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8069 tcg_ctx
.gen_opc_pc
[i
]);
8072 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8073 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8074 (uint32_t)tb
->cs_base
);
8077 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8078 cc_op
= gen_opc_cc_op
[pc_pos
];
8079 if (cc_op
!= CC_OP_DYNAMIC
)