4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
40 #define PREFIX_VEX 0x20
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
60 //#define MACRO_TEST 1
62 /* global register indexes */
63 static TCGv_ptr cpu_env
;
65 static TCGv cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
, cpu_cc_srcT
;
66 static TCGv_i32 cpu_cc_op
;
67 static TCGv cpu_regs
[CPU_NB_REGS
];
70 /* local register indexes (only used inside old micro ops) */
71 static TCGv cpu_tmp0
, cpu_tmp4
;
72 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
73 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
74 static TCGv_i64 cpu_tmp1_i64
;
76 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
78 #include "exec/gen-icount.h"
81 static int x86_64_hregs
;
84 typedef struct DisasContext
{
85 /* current insn context */
86 int override
; /* -1 if no override */
90 target_ulong pc
; /* pc = eip + cs_base */
91 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
92 static state change (stop translation) */
93 /* current block context */
94 target_ulong cs_base
; /* base of CS segment */
95 int pe
; /* protected mode */
96 int code32
; /* 32 bit code segment */
98 int lma
; /* long mode active */
99 int code64
; /* 64 bit code segment */
102 int vex_l
; /* vex vector length */
103 int vex_v
; /* vex vvvv register, without 1's compliment. */
104 int ss32
; /* 32 bit stack segment */
105 CCOp cc_op
; /* current CC operation */
107 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
108 int f_st
; /* currently unused */
109 int vm86
; /* vm86 mode */
112 int tf
; /* TF cpu flag */
113 int singlestep_enabled
; /* "hardware" single step enabled */
114 int jmp_opt
; /* use direct block chaining for direct jumps */
115 int mem_index
; /* select memory access functions */
116 uint64_t flags
; /* all execution flags */
117 struct TranslationBlock
*tb
;
118 int popl_esp_hack
; /* for correct popl with esp base handling */
119 int rip_offset
; /* only used in x86_64, but left for simplicity */
121 int cpuid_ext_features
;
122 int cpuid_ext2_features
;
123 int cpuid_ext3_features
;
124 int cpuid_7_0_ebx_features
;
127 static void gen_eob(DisasContext
*s
);
128 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
129 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
130 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
);
132 /* i386 arith/logic operations */
152 OP_SHL1
, /* undocumented */
168 /* I386 int registers */
169 OR_EAX
, /* MUST be even numbered */
178 OR_TMP0
= 16, /* temporary operand register */
180 OR_A0
, /* temporary register used when doing address evaluation */
190 /* Bit set if the global variable is live after setting CC_OP to X. */
191 static const uint8_t cc_op_live
[CC_OP_NB
] = {
192 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
193 [CC_OP_EFLAGS
] = USES_CC_SRC
,
194 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
195 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
196 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
197 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
198 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
199 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
200 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
202 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
204 [CC_OP_BMILGB
... CC_OP_BMILGQ
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_ADCX
] = USES_CC_DST
| USES_CC_SRC
,
206 [CC_OP_ADOX
] = USES_CC_SRC
| USES_CC_SRC2
,
207 [CC_OP_ADCOX
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
211 static void set_cc_op(DisasContext
*s
, CCOp op
)
215 if (s
->cc_op
== op
) {
219 /* Discard CC computation that will no longer be used. */
220 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
221 if (dead
& USES_CC_DST
) {
222 tcg_gen_discard_tl(cpu_cc_dst
);
224 if (dead
& USES_CC_SRC
) {
225 tcg_gen_discard_tl(cpu_cc_src
);
227 if (dead
& USES_CC_SRC2
) {
228 tcg_gen_discard_tl(cpu_cc_src2
);
230 if (dead
& USES_CC_SRCT
) {
231 tcg_gen_discard_tl(cpu_cc_srcT
);
234 if (op
== CC_OP_DYNAMIC
) {
235 /* The DYNAMIC setting is translator only, and should never be
236 stored. Thus we always consider it clean. */
237 s
->cc_op_dirty
= false;
239 /* Discard any computed CC_OP value (see shifts). */
240 if (s
->cc_op
== CC_OP_DYNAMIC
) {
241 tcg_gen_discard_i32(cpu_cc_op
);
243 s
->cc_op_dirty
= true;
248 static void gen_update_cc_op(DisasContext
*s
)
250 if (s
->cc_op_dirty
) {
251 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
252 s
->cc_op_dirty
= false;
258 #define NB_OP_SIZES 4
260 #else /* !TARGET_X86_64 */
262 #define NB_OP_SIZES 3
264 #endif /* !TARGET_X86_64 */
266 #if defined(HOST_WORDS_BIGENDIAN)
267 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
268 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
269 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
270 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
271 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
273 #define REG_B_OFFSET 0
274 #define REG_H_OFFSET 1
275 #define REG_W_OFFSET 0
276 #define REG_L_OFFSET 0
277 #define REG_LH_OFFSET 4
280 /* In instruction encodings for byte register accesses the
281 * register number usually indicates "low 8 bits of register N";
282 * however there are some special cases where N 4..7 indicates
283 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
284 * true for this special case, false otherwise.
286 static inline bool byte_reg_is_xH(int reg
)
292 if (reg
>= 8 || x86_64_hregs
) {
299 /* Select the size of a push/pop operation. */
300 static inline TCGMemOp
mo_pushpop(DisasContext
*s
, TCGMemOp ot
)
303 return ot
== MO_16
? MO_16
: MO_64
;
309 /* Select only size 64 else 32. Used for SSE operand sizes. */
310 static inline TCGMemOp
mo_64_32(TCGMemOp ot
)
313 return ot
== MO_64
? MO_64
: MO_32
;
319 /* Select size 8 if lsb of B is clear, else OT. Used for decoding
320 byte vs word opcodes. */
321 static inline TCGMemOp
mo_b_d(int b
, TCGMemOp ot
)
323 return b
& 1 ? ot
: MO_8
;
326 /* Select size 8 if lsb of B is clear, else OT capped at 32.
327 Used for decoding operand size of port opcodes. */
328 static inline TCGMemOp
mo_b_d32(int b
, TCGMemOp ot
)
330 return b
& 1 ? (ot
== MO_16
? MO_16
: MO_32
) : MO_8
;
333 static void gen_op_mov_reg_v(TCGMemOp ot
, int reg
, TCGv t0
)
337 if (!byte_reg_is_xH(reg
)) {
338 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
340 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
344 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
347 /* For x86_64, this sets the higher half of register to zero.
348 For i386, this is equivalent to a mov. */
349 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
353 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
361 static inline void gen_op_mov_reg_A0(TCGMemOp size
, int reg
)
363 gen_op_mov_reg_v(size
, reg
, cpu_A0
);
366 static inline void gen_op_mov_v_reg(TCGMemOp ot
, TCGv t0
, int reg
)
368 if (ot
== MO_8
&& byte_reg_is_xH(reg
)) {
369 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
370 tcg_gen_ext8u_tl(t0
, t0
);
372 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
376 static inline void gen_op_mov_TN_reg(TCGMemOp ot
, int t_index
, int reg
)
378 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
381 static inline void gen_op_movl_A0_reg(int reg
)
383 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
386 static inline void gen_op_addl_A0_im(int32_t val
)
388 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
390 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
395 static inline void gen_op_addq_A0_im(int64_t val
)
397 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
401 static void gen_add_A0_im(DisasContext
*s
, int val
)
405 gen_op_addq_A0_im(val
);
408 gen_op_addl_A0_im(val
);
411 static inline void gen_op_addl_T0_T1(void)
413 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
416 static inline void gen_op_jmp_T0(void)
418 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
421 static inline void gen_op_add_reg_im(TCGMemOp size
, int reg
, int32_t val
)
423 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
424 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
427 static inline void gen_op_add_reg_T0(TCGMemOp size
, int reg
)
429 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
430 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
433 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
435 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
437 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
438 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
439 /* For x86_64, this sets the higher half of register to zero.
440 For i386, this is equivalent to a nop. */
441 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
444 static inline void gen_op_movl_A0_seg(int reg
)
446 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
449 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
451 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
454 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
455 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
457 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
458 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
461 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
466 static inline void gen_op_movq_A0_seg(int reg
)
468 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
471 static inline void gen_op_addq_A0_seg(int reg
)
473 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
474 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
477 static inline void gen_op_movq_A0_reg(int reg
)
479 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
482 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
484 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
486 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
487 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
491 static inline void gen_op_ld_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
493 tcg_gen_qemu_ld_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
496 static inline void gen_op_st_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
498 tcg_gen_qemu_st_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
501 static inline void gen_op_st_rm_T0_A0(DisasContext
*s
, int idx
, int d
)
504 gen_op_st_v(s
, idx
, cpu_T
[0], cpu_A0
);
506 gen_op_mov_reg_v(idx
, d
, cpu_T
[0]);
510 static inline void gen_jmp_im(target_ulong pc
)
512 tcg_gen_movi_tl(cpu_tmp0
, pc
);
513 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
516 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
520 override
= s
->override
;
525 gen_op_movq_A0_seg(override
);
526 gen_op_addq_A0_reg_sN(0, R_ESI
);
528 gen_op_movq_A0_reg(R_ESI
);
534 if (s
->addseg
&& override
< 0)
537 gen_op_movl_A0_seg(override
);
538 gen_op_addl_A0_reg_sN(0, R_ESI
);
540 gen_op_movl_A0_reg(R_ESI
);
544 /* 16 address, always override */
547 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESI
]);
548 gen_op_addl_A0_seg(s
, override
);
555 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
560 gen_op_movq_A0_reg(R_EDI
);
565 gen_op_movl_A0_seg(R_ES
);
566 gen_op_addl_A0_reg_sN(0, R_EDI
);
568 gen_op_movl_A0_reg(R_EDI
);
572 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_EDI
]);
573 gen_op_addl_A0_seg(s
, R_ES
);
580 static inline void gen_op_movl_T0_Dshift(TCGMemOp ot
)
582 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
583 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
586 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, TCGMemOp size
, bool sign
)
591 tcg_gen_ext8s_tl(dst
, src
);
593 tcg_gen_ext8u_tl(dst
, src
);
598 tcg_gen_ext16s_tl(dst
, src
);
600 tcg_gen_ext16u_tl(dst
, src
);
606 tcg_gen_ext32s_tl(dst
, src
);
608 tcg_gen_ext32u_tl(dst
, src
);
617 static void gen_extu(TCGMemOp ot
, TCGv reg
)
619 gen_ext_tl(reg
, reg
, ot
, false);
622 static void gen_exts(TCGMemOp ot
, TCGv reg
)
624 gen_ext_tl(reg
, reg
, ot
, true);
627 static inline void gen_op_jnz_ecx(TCGMemOp size
, int label1
)
629 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
630 gen_extu(size
, cpu_tmp0
);
631 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
634 static inline void gen_op_jz_ecx(TCGMemOp size
, int label1
)
636 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
637 gen_extu(size
, cpu_tmp0
);
638 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
641 static void gen_helper_in_func(TCGMemOp ot
, TCGv v
, TCGv_i32 n
)
645 gen_helper_inb(v
, n
);
648 gen_helper_inw(v
, n
);
651 gen_helper_inl(v
, n
);
658 static void gen_helper_out_func(TCGMemOp ot
, TCGv_i32 v
, TCGv_i32 n
)
662 gen_helper_outb(v
, n
);
665 gen_helper_outw(v
, n
);
668 gen_helper_outl(v
, n
);
675 static void gen_check_io(DisasContext
*s
, TCGMemOp ot
, target_ulong cur_eip
,
679 target_ulong next_eip
;
682 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
686 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
689 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
692 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
695 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
701 if(s
->flags
& HF_SVMI_MASK
) {
706 svm_flags
|= (1 << (4 + ot
));
707 next_eip
= s
->pc
- s
->cs_base
;
708 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
709 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
710 tcg_const_i32(svm_flags
),
711 tcg_const_i32(next_eip
- cur_eip
));
715 static inline void gen_movs(DisasContext
*s
, TCGMemOp ot
)
717 gen_string_movl_A0_ESI(s
);
718 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
719 gen_string_movl_A0_EDI(s
);
720 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
721 gen_op_movl_T0_Dshift(ot
);
722 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
723 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
726 static void gen_op_update1_cc(void)
728 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
731 static void gen_op_update2_cc(void)
733 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
734 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
737 static void gen_op_update3_cc(TCGv reg
)
739 tcg_gen_mov_tl(cpu_cc_src2
, reg
);
740 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
741 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
744 static inline void gen_op_testl_T0_T1_cc(void)
746 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
749 static void gen_op_update_neg_cc(void)
751 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
752 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
753 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
756 /* compute all eflags to cc_src */
757 static void gen_compute_eflags(DisasContext
*s
)
759 TCGv zero
, dst
, src1
, src2
;
762 if (s
->cc_op
== CC_OP_EFLAGS
) {
765 if (s
->cc_op
== CC_OP_CLR
) {
766 tcg_gen_movi_tl(cpu_cc_src
, CC_Z
);
767 set_cc_op(s
, CC_OP_EFLAGS
);
776 /* Take care to not read values that are not live. */
777 live
= cc_op_live
[s
->cc_op
] & ~USES_CC_SRCT
;
778 dead
= live
^ (USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
);
780 zero
= tcg_const_tl(0);
781 if (dead
& USES_CC_DST
) {
784 if (dead
& USES_CC_SRC
) {
787 if (dead
& USES_CC_SRC2
) {
793 gen_helper_cc_compute_all(cpu_cc_src
, dst
, src1
, src2
, cpu_cc_op
);
794 set_cc_op(s
, CC_OP_EFLAGS
);
801 typedef struct CCPrepare
{
811 /* compute eflags.C to reg */
812 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
818 case CC_OP_SUBB
... CC_OP_SUBQ
:
819 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
820 size
= s
->cc_op
- CC_OP_SUBB
;
821 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
822 /* If no temporary was used, be careful not to alias t1 and t0. */
823 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
824 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
828 case CC_OP_ADDB
... CC_OP_ADDQ
:
829 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
830 size
= s
->cc_op
- CC_OP_ADDB
;
831 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
832 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
834 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
835 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
837 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
839 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
841 case CC_OP_INCB
... CC_OP_INCQ
:
842 case CC_OP_DECB
... CC_OP_DECQ
:
843 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
844 .mask
= -1, .no_setcond
= true };
846 case CC_OP_SHLB
... CC_OP_SHLQ
:
847 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
848 size
= s
->cc_op
- CC_OP_SHLB
;
849 shift
= (8 << size
) - 1;
850 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
851 .mask
= (target_ulong
)1 << shift
};
853 case CC_OP_MULB
... CC_OP_MULQ
:
854 return (CCPrepare
) { .cond
= TCG_COND_NE
,
855 .reg
= cpu_cc_src
, .mask
= -1 };
857 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
858 size
= s
->cc_op
- CC_OP_BMILGB
;
859 t0
= gen_ext_tl(reg
, cpu_cc_src
, size
, false);
860 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
864 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_dst
,
865 .mask
= -1, .no_setcond
= true };
868 case CC_OP_SARB
... CC_OP_SARQ
:
870 return (CCPrepare
) { .cond
= TCG_COND_NE
,
871 .reg
= cpu_cc_src
, .mask
= CC_C
};
874 /* The need to compute only C from CC_OP_DYNAMIC is important
875 in efficiently implementing e.g. INC at the start of a TB. */
877 gen_helper_cc_compute_c(reg
, cpu_cc_dst
, cpu_cc_src
,
878 cpu_cc_src2
, cpu_cc_op
);
879 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
880 .mask
= -1, .no_setcond
= true };
884 /* compute eflags.P to reg */
885 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
887 gen_compute_eflags(s
);
888 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
892 /* compute eflags.S to reg */
893 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
897 gen_compute_eflags(s
);
903 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
906 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
909 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
910 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
911 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
916 /* compute eflags.O to reg */
917 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
922 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src2
,
923 .mask
= -1, .no_setcond
= true };
925 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
927 gen_compute_eflags(s
);
928 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
933 /* compute eflags.Z to reg */
934 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
938 gen_compute_eflags(s
);
944 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
947 return (CCPrepare
) { .cond
= TCG_COND_ALWAYS
, .mask
= -1 };
950 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
951 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
952 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
957 /* perform a conditional store into register 'reg' according to jump opcode
958 value 'b'. In the fast case, T0 is guaranted not to be used. */
959 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
961 int inv
, jcc_op
, cond
;
967 jcc_op
= (b
>> 1) & 7;
970 case CC_OP_SUBB
... CC_OP_SUBQ
:
971 /* We optimize relational operators for the cmp/jcc case. */
972 size
= s
->cc_op
- CC_OP_SUBB
;
975 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
976 gen_extu(size
, cpu_tmp4
);
977 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
978 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
979 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
988 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
989 gen_exts(size
, cpu_tmp4
);
990 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
991 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
992 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1002 /* This actually generates good code for JC, JZ and JS. */
1005 cc
= gen_prepare_eflags_o(s
, reg
);
1008 cc
= gen_prepare_eflags_c(s
, reg
);
1011 cc
= gen_prepare_eflags_z(s
, reg
);
1014 gen_compute_eflags(s
);
1015 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1016 .mask
= CC_Z
| CC_C
};
1019 cc
= gen_prepare_eflags_s(s
, reg
);
1022 cc
= gen_prepare_eflags_p(s
, reg
);
1025 gen_compute_eflags(s
);
1026 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1029 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1030 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1031 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1036 gen_compute_eflags(s
);
1037 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1040 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1041 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1042 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1043 .mask
= CC_S
| CC_Z
};
1050 cc
.cond
= tcg_invert_cond(cc
.cond
);
1055 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1057 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1059 if (cc
.no_setcond
) {
1060 if (cc
.cond
== TCG_COND_EQ
) {
1061 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1063 tcg_gen_mov_tl(reg
, cc
.reg
);
1068 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1069 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1070 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1071 tcg_gen_andi_tl(reg
, reg
, 1);
1074 if (cc
.mask
!= -1) {
1075 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1079 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1081 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1085 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1087 gen_setcc1(s
, JCC_B
<< 1, reg
);
1090 /* generate a conditional jump to label 'l1' according to jump opcode
1091 value 'b'. In the fast case, T0 is guaranted not to be used. */
1092 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1094 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1096 if (cc
.mask
!= -1) {
1097 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1101 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1103 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1107 /* Generate a conditional jump to label 'l1' according to jump opcode
1108 value 'b'. In the fast case, T0 is guaranted not to be used.
1109 A translation block must end soon. */
1110 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1112 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1114 gen_update_cc_op(s
);
1115 if (cc
.mask
!= -1) {
1116 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1119 set_cc_op(s
, CC_OP_DYNAMIC
);
1121 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1123 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1127 /* XXX: does not work with gdbstub "ice" single step - not a
1129 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1133 l1
= gen_new_label();
1134 l2
= gen_new_label();
1135 gen_op_jnz_ecx(s
->aflag
, l1
);
1137 gen_jmp_tb(s
, next_eip
, 1);
1142 static inline void gen_stos(DisasContext
*s
, TCGMemOp ot
)
1144 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
1145 gen_string_movl_A0_EDI(s
);
1146 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1147 gen_op_movl_T0_Dshift(ot
);
1148 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1151 static inline void gen_lods(DisasContext
*s
, TCGMemOp ot
)
1153 gen_string_movl_A0_ESI(s
);
1154 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1155 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[0]);
1156 gen_op_movl_T0_Dshift(ot
);
1157 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1160 static inline void gen_scas(DisasContext
*s
, TCGMemOp ot
)
1162 gen_string_movl_A0_EDI(s
);
1163 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1164 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1165 gen_op_movl_T0_Dshift(ot
);
1166 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1169 static inline void gen_cmps(DisasContext
*s
, TCGMemOp ot
)
1171 gen_string_movl_A0_EDI(s
);
1172 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1173 gen_string_movl_A0_ESI(s
);
1174 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1175 gen_op_movl_T0_Dshift(ot
);
1176 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1177 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1180 static inline void gen_ins(DisasContext
*s
, TCGMemOp ot
)
1184 gen_string_movl_A0_EDI(s
);
1185 /* Note: we must do this dummy write first to be restartable in
1186 case of page fault. */
1187 tcg_gen_movi_tl(cpu_T
[0], 0);
1188 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1189 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1190 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1191 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1192 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1193 gen_op_movl_T0_Dshift(ot
);
1194 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1199 static inline void gen_outs(DisasContext
*s
, TCGMemOp ot
)
1203 gen_string_movl_A0_ESI(s
);
1204 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1206 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1207 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1208 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1209 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1211 gen_op_movl_T0_Dshift(ot
);
1212 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1217 /* same method as Valgrind : we generate jumps to current or next
1219 #define GEN_REPZ(op) \
1220 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1221 target_ulong cur_eip, target_ulong next_eip) \
1224 gen_update_cc_op(s); \
1225 l2 = gen_jz_ecx_string(s, next_eip); \
1226 gen_ ## op(s, ot); \
1227 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1228 /* a loop would cause two single step exceptions if ECX = 1 \
1229 before rep string_insn */ \
1231 gen_op_jz_ecx(s->aflag, l2); \
1232 gen_jmp(s, cur_eip); \
1235 #define GEN_REPZ2(op) \
1236 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1237 target_ulong cur_eip, \
1238 target_ulong next_eip, \
1242 gen_update_cc_op(s); \
1243 l2 = gen_jz_ecx_string(s, next_eip); \
1244 gen_ ## op(s, ot); \
1245 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1246 gen_update_cc_op(s); \
1247 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1249 gen_op_jz_ecx(s->aflag, l2); \
1250 gen_jmp(s, cur_eip); \
1261 static void gen_helper_fp_arith_ST0_FT0(int op
)
1265 gen_helper_fadd_ST0_FT0(cpu_env
);
1268 gen_helper_fmul_ST0_FT0(cpu_env
);
1271 gen_helper_fcom_ST0_FT0(cpu_env
);
1274 gen_helper_fcom_ST0_FT0(cpu_env
);
1277 gen_helper_fsub_ST0_FT0(cpu_env
);
1280 gen_helper_fsubr_ST0_FT0(cpu_env
);
1283 gen_helper_fdiv_ST0_FT0(cpu_env
);
1286 gen_helper_fdivr_ST0_FT0(cpu_env
);
1291 /* NOTE the exception in "r" op ordering */
1292 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1294 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1297 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1300 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1303 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1306 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1309 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1312 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1317 /* if d == OR_TMP0, it means memory operand (address in A0) */
1318 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
)
1321 gen_op_mov_TN_reg(ot
, 0, d
);
1323 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1327 gen_compute_eflags_c(s1
, cpu_tmp4
);
1328 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1329 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1330 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1331 gen_op_update3_cc(cpu_tmp4
);
1332 set_cc_op(s1
, CC_OP_ADCB
+ ot
);
1335 gen_compute_eflags_c(s1
, cpu_tmp4
);
1336 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1337 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1338 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1339 gen_op_update3_cc(cpu_tmp4
);
1340 set_cc_op(s1
, CC_OP_SBBB
+ ot
);
1343 gen_op_addl_T0_T1();
1344 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1345 gen_op_update2_cc();
1346 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1349 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1350 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1351 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1352 gen_op_update2_cc();
1353 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1357 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1358 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1359 gen_op_update1_cc();
1360 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1363 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1364 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1365 gen_op_update1_cc();
1366 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1369 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1370 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1371 gen_op_update1_cc();
1372 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1375 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1376 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1377 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1378 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1383 /* if d == OR_TMP0, it means memory operand (address in A0) */
1384 static void gen_inc(DisasContext
*s1
, TCGMemOp ot
, int d
, int c
)
1387 gen_op_mov_TN_reg(ot
, 0, d
);
1389 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1391 gen_compute_eflags_c(s1
, cpu_cc_src
);
1393 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1394 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1396 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1397 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1399 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1400 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1403 static void gen_shift_flags(DisasContext
*s
, TCGMemOp ot
, TCGv result
,
1404 TCGv shm1
, TCGv count
, bool is_right
)
1406 TCGv_i32 z32
, s32
, oldop
;
1409 /* Store the results into the CC variables. If we know that the
1410 variable must be dead, store unconditionally. Otherwise we'll
1411 need to not disrupt the current contents. */
1412 z_tl
= tcg_const_tl(0);
1413 if (cc_op_live
[s
->cc_op
] & USES_CC_DST
) {
1414 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_dst
, count
, z_tl
,
1415 result
, cpu_cc_dst
);
1417 tcg_gen_mov_tl(cpu_cc_dst
, result
);
1419 if (cc_op_live
[s
->cc_op
] & USES_CC_SRC
) {
1420 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_src
, count
, z_tl
,
1423 tcg_gen_mov_tl(cpu_cc_src
, shm1
);
1425 tcg_temp_free(z_tl
);
1427 /* Get the two potential CC_OP values into temporaries. */
1428 tcg_gen_movi_i32(cpu_tmp2_i32
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1429 if (s
->cc_op
== CC_OP_DYNAMIC
) {
1432 tcg_gen_movi_i32(cpu_tmp3_i32
, s
->cc_op
);
1433 oldop
= cpu_tmp3_i32
;
1436 /* Conditionally store the CC_OP value. */
1437 z32
= tcg_const_i32(0);
1438 s32
= tcg_temp_new_i32();
1439 tcg_gen_trunc_tl_i32(s32
, count
);
1440 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, s32
, z32
, cpu_tmp2_i32
, oldop
);
1441 tcg_temp_free_i32(z32
);
1442 tcg_temp_free_i32(s32
);
1444 /* The CC_OP value is no longer predictable. */
1445 set_cc_op(s
, CC_OP_DYNAMIC
);
1448 static void gen_shift_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1449 int is_right
, int is_arith
)
1451 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1454 if (op1
== OR_TMP0
) {
1455 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1457 gen_op_mov_TN_reg(ot
, 0, op1
);
1460 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1461 tcg_gen_subi_tl(cpu_tmp0
, cpu_T
[1], 1);
1465 gen_exts(ot
, cpu_T
[0]);
1466 tcg_gen_sar_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1467 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1469 gen_extu(ot
, cpu_T
[0]);
1470 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1471 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1474 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1475 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1479 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1481 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, cpu_T
[1], is_right
);
1484 static void gen_shift_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1485 int is_right
, int is_arith
)
1487 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1491 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1493 gen_op_mov_TN_reg(ot
, 0, op1
);
1499 gen_exts(ot
, cpu_T
[0]);
1500 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1501 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1503 gen_extu(ot
, cpu_T
[0]);
1504 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1505 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1508 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1509 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1514 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1516 /* update eflags if non zero shift */
1518 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1519 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1520 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1524 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1527 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1529 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1532 static void gen_rot_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
, int is_right
)
1534 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1538 if (op1
== OR_TMP0
) {
1539 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1541 gen_op_mov_TN_reg(ot
, 0, op1
);
1544 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1548 /* Replicate the 8-bit input so that a 32-bit rotate works. */
1549 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
1550 tcg_gen_muli_tl(cpu_T
[0], cpu_T
[0], 0x01010101);
1553 /* Replicate the 16-bit input so that a 32-bit rotate works. */
1554 tcg_gen_deposit_tl(cpu_T
[0], cpu_T
[0], cpu_T
[0], 16, 16);
1557 #ifdef TARGET_X86_64
1559 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1560 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
1562 tcg_gen_rotr_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1564 tcg_gen_rotl_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1566 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1571 tcg_gen_rotr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1573 tcg_gen_rotl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1579 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1581 /* We'll need the flags computed into CC_SRC. */
1582 gen_compute_eflags(s
);
1584 /* The value that was "rotated out" is now present at the other end
1585 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1586 since we've computed the flags into CC_SRC, these variables are
1589 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1590 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1591 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1593 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1594 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1596 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1597 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1599 /* Now conditionally store the new CC_OP value. If the shift count
1600 is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
1601 Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
1602 exactly as we computed above. */
1603 t0
= tcg_const_i32(0);
1604 t1
= tcg_temp_new_i32();
1605 tcg_gen_trunc_tl_i32(t1
, cpu_T
[1]);
1606 tcg_gen_movi_i32(cpu_tmp2_i32
, CC_OP_ADCOX
);
1607 tcg_gen_movi_i32(cpu_tmp3_i32
, CC_OP_EFLAGS
);
1608 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, t1
, t0
,
1609 cpu_tmp2_i32
, cpu_tmp3_i32
);
1610 tcg_temp_free_i32(t0
);
1611 tcg_temp_free_i32(t1
);
1613 /* The CC_OP value is no longer predictable. */
1614 set_cc_op(s
, CC_OP_DYNAMIC
);
1617 static void gen_rot_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1620 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1624 if (op1
== OR_TMP0
) {
1625 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1627 gen_op_mov_TN_reg(ot
, 0, op1
);
1633 #ifdef TARGET_X86_64
1635 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1637 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1639 tcg_gen_rotli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1641 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1646 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], op2
);
1648 tcg_gen_rotli_tl(cpu_T
[0], cpu_T
[0], op2
);
1659 shift
= mask
+ 1 - shift
;
1661 gen_extu(ot
, cpu_T
[0]);
1662 tcg_gen_shli_tl(cpu_tmp0
, cpu_T
[0], shift
);
1663 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], mask
+ 1 - shift
);
1664 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
1670 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1673 /* Compute the flags into CC_SRC. */
1674 gen_compute_eflags(s
);
1676 /* The value that was "rotated out" is now present at the other end
1677 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1678 since we've computed the flags into CC_SRC, these variables are
1681 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1682 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1683 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1685 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1686 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1688 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1689 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1690 set_cc_op(s
, CC_OP_ADCOX
);
1694 /* XXX: add faster immediate = 1 case */
1695 static void gen_rotc_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1698 gen_compute_eflags(s
);
1699 assert(s
->cc_op
== CC_OP_EFLAGS
);
1703 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1705 gen_op_mov_TN_reg(ot
, 0, op1
);
1710 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1713 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1716 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1718 #ifdef TARGET_X86_64
1720 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1729 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1732 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1735 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1737 #ifdef TARGET_X86_64
1739 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1747 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1750 /* XXX: add faster immediate case */
1751 static void gen_shiftd_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1752 bool is_right
, TCGv count_in
)
1754 target_ulong mask
= (ot
== MO_64
? 63 : 31);
1758 if (op1
== OR_TMP0
) {
1759 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1761 gen_op_mov_TN_reg(ot
, 0, op1
);
1764 count
= tcg_temp_new();
1765 tcg_gen_andi_tl(count
, count_in
, mask
);
1769 /* Note: we implement the Intel behaviour for shift count > 16.
1770 This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
1771 portion by constructing it as a 32-bit value. */
1773 tcg_gen_deposit_tl(cpu_tmp0
, cpu_T
[0], cpu_T
[1], 16, 16);
1774 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1775 tcg_gen_mov_tl(cpu_T
[0], cpu_tmp0
);
1777 tcg_gen_deposit_tl(cpu_T
[1], cpu_T
[0], cpu_T
[1], 16, 16);
1780 #ifdef TARGET_X86_64
1782 /* Concatenate the two 32-bit values and use a 64-bit shift. */
1783 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1785 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1786 tcg_gen_shr_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1787 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], count
);
1789 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[1], cpu_T
[0]);
1790 tcg_gen_shl_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1791 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], count
);
1792 tcg_gen_shri_i64(cpu_tmp0
, cpu_tmp0
, 32);
1793 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], 32);
1798 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1800 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1802 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1803 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], count
);
1804 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1806 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1808 /* Only needed if count > 16, for Intel behaviour. */
1809 tcg_gen_subfi_tl(cpu_tmp4
, 33, count
);
1810 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[1], cpu_tmp4
);
1811 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, cpu_tmp4
);
1814 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1815 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], count
);
1816 tcg_gen_shr_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1818 tcg_gen_movi_tl(cpu_tmp4
, 0);
1819 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[1], count
, cpu_tmp4
,
1820 cpu_tmp4
, cpu_T
[1]);
1821 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1826 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1828 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, count
, is_right
);
1829 tcg_temp_free(count
);
1832 static void gen_shift(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int s
)
1835 gen_op_mov_TN_reg(ot
, 1, s
);
1838 gen_rot_rm_T1(s1
, ot
, d
, 0);
1841 gen_rot_rm_T1(s1
, ot
, d
, 1);
1845 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1848 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1851 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1854 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1857 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1862 static void gen_shifti(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int c
)
1866 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1869 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1873 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1876 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1879 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1882 /* currently not optimized */
1883 tcg_gen_movi_tl(cpu_T
[1], c
);
1884 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1889 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
1896 int mod
, rm
, code
, override
, must_add_seg
;
1899 override
= s
->override
;
1900 must_add_seg
= s
->addseg
;
1903 mod
= (modrm
>> 6) & 3;
1916 code
= cpu_ldub_code(env
, s
->pc
++);
1917 scale
= (code
>> 6) & 3;
1918 index
= ((code
>> 3) & 7) | REX_X(s
);
1920 index
= -1; /* no index */
1928 if ((base
& 7) == 5) {
1930 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1932 if (CODE64(s
) && !havesib
) {
1933 disp
+= s
->pc
+ s
->rip_offset
;
1940 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
1944 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1949 /* For correct popl handling with esp. */
1950 if (base
== R_ESP
&& s
->popl_esp_hack
) {
1951 disp
+= s
->popl_esp_hack
;
1954 /* Compute the address, with a minimum number of TCG ops. */
1958 sum
= cpu_regs
[index
];
1960 tcg_gen_shli_tl(cpu_A0
, cpu_regs
[index
], scale
);
1964 tcg_gen_add_tl(cpu_A0
, sum
, cpu_regs
[base
]);
1967 } else if (base
>= 0) {
1968 sum
= cpu_regs
[base
];
1970 if (TCGV_IS_UNUSED(sum
)) {
1971 tcg_gen_movi_tl(cpu_A0
, disp
);
1973 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
1978 if (base
== R_EBP
|| base
== R_ESP
) {
1985 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
1986 offsetof(CPUX86State
, segs
[override
].base
));
1988 if (s
->aflag
== MO_32
) {
1989 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
1991 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
1995 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
1998 if (s
->aflag
== MO_32
) {
1999 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2007 disp
= cpu_lduw_code(env
, s
->pc
);
2009 tcg_gen_movi_tl(cpu_A0
, disp
);
2010 rm
= 0; /* avoid SS override */
2017 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2021 disp
= (int16_t)cpu_lduw_code(env
, s
->pc
);
2029 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_ESI
]);
2032 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_EDI
]);
2035 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_ESI
]);
2038 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_EDI
]);
2041 sum
= cpu_regs
[R_ESI
];
2044 sum
= cpu_regs
[R_EDI
];
2047 sum
= cpu_regs
[R_EBP
];
2051 sum
= cpu_regs
[R_EBX
];
2054 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
2055 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2059 if (rm
== 2 || rm
== 3 || rm
== 6) {
2065 gen_op_addl_A0_seg(s
, override
);
2074 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2076 int mod
, rm
, base
, code
;
2078 mod
= (modrm
>> 6) & 3;
2089 code
= cpu_ldub_code(env
, s
->pc
++);
2131 /* used for LEA and MOV AX, mem */
2132 static void gen_add_A0_ds_seg(DisasContext
*s
)
2134 int override
, must_add_seg
;
2135 must_add_seg
= s
->addseg
;
2137 if (s
->override
>= 0) {
2138 override
= s
->override
;
2142 #ifdef TARGET_X86_64
2144 gen_op_addq_A0_seg(override
);
2148 gen_op_addl_A0_seg(s
, override
);
2153 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2155 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2156 TCGMemOp ot
, int reg
, int is_store
)
2160 mod
= (modrm
>> 6) & 3;
2161 rm
= (modrm
& 7) | REX_B(s
);
2165 gen_op_mov_TN_reg(ot
, 0, reg
);
2166 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
2168 gen_op_mov_TN_reg(ot
, 0, rm
);
2170 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2173 gen_lea_modrm(env
, s
, modrm
);
2176 gen_op_mov_TN_reg(ot
, 0, reg
);
2177 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2179 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
2181 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2186 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
)
2192 ret
= cpu_ldub_code(env
, s
->pc
);
2196 ret
= cpu_lduw_code(env
, s
->pc
);
2200 #ifdef TARGET_X86_64
2203 ret
= cpu_ldl_code(env
, s
->pc
);
2212 static inline int insn_const_size(TCGMemOp ot
)
2221 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2223 TranslationBlock
*tb
;
2226 pc
= s
->cs_base
+ eip
;
2228 /* NOTE: we handle the case where the TB spans two pages here */
2229 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2230 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2231 /* jump to same page: we can use a direct jump */
2232 tcg_gen_goto_tb(tb_num
);
2234 tcg_gen_exit_tb((uintptr_t)tb
+ tb_num
);
2236 /* jump to another page: currently not optimized */
2242 static inline void gen_jcc(DisasContext
*s
, int b
,
2243 target_ulong val
, target_ulong next_eip
)
2248 l1
= gen_new_label();
2251 gen_goto_tb(s
, 0, next_eip
);
2254 gen_goto_tb(s
, 1, val
);
2255 s
->is_jmp
= DISAS_TB_JUMP
;
2257 l1
= gen_new_label();
2258 l2
= gen_new_label();
2261 gen_jmp_im(next_eip
);
2271 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
, int b
,
2276 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2278 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2279 if (cc
.mask
!= -1) {
2280 TCGv t0
= tcg_temp_new();
2281 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2285 cc
.reg2
= tcg_const_tl(cc
.imm
);
2288 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2289 cpu_T
[0], cpu_regs
[reg
]);
2290 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2292 if (cc
.mask
!= -1) {
2293 tcg_temp_free(cc
.reg
);
2296 tcg_temp_free(cc
.reg2
);
2300 static inline void gen_op_movl_T0_seg(int seg_reg
)
2302 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2303 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2306 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2308 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2309 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2310 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2311 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2312 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2313 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2316 /* move T0 to seg_reg and compute if the CPU state may change. Never
2317 call this function with seg_reg == R_CS */
2318 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2320 if (s
->pe
&& !s
->vm86
) {
2321 /* XXX: optimize by finding processor state dynamically */
2322 gen_update_cc_op(s
);
2323 gen_jmp_im(cur_eip
);
2324 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2325 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2326 /* abort translation because the addseg value may change or
2327 because ss32 may change. For R_SS, translation must always
2328 stop as a special handling must be done to disable hardware
2329 interrupts for the next instruction */
2330 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2331 s
->is_jmp
= DISAS_TB_JUMP
;
2333 gen_op_movl_seg_T0_vm(seg_reg
);
2334 if (seg_reg
== R_SS
)
2335 s
->is_jmp
= DISAS_TB_JUMP
;
2339 static inline int svm_is_rep(int prefixes
)
2341 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2345 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2346 uint32_t type
, uint64_t param
)
2348 /* no SVM activated; fast case */
2349 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2351 gen_update_cc_op(s
);
2352 gen_jmp_im(pc_start
- s
->cs_base
);
2353 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2354 tcg_const_i64(param
));
2358 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2360 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2363 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2365 #ifdef TARGET_X86_64
2367 gen_op_add_reg_im(MO_64
, R_ESP
, addend
);
2371 gen_op_add_reg_im(MO_32
, R_ESP
, addend
);
2373 gen_op_add_reg_im(MO_16
, R_ESP
, addend
);
2377 /* Generate a push. It depends on ss32, addseg and dflag. */
2378 static void gen_push_v(DisasContext
*s
, TCGv val
)
2380 TCGMemOp a_ot
, d_ot
= mo_pushpop(s
, s
->dflag
);
2381 int size
= 1 << d_ot
;
2382 TCGv new_esp
= cpu_A0
;
2384 tcg_gen_subi_tl(cpu_A0
, cpu_regs
[R_ESP
], size
);
2388 } else if (s
->ss32
) {
2392 tcg_gen_mov_tl(new_esp
, cpu_A0
);
2393 gen_op_addl_A0_seg(s
, R_SS
);
2395 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2400 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2401 tcg_gen_mov_tl(new_esp
, cpu_A0
);
2402 gen_op_addl_A0_seg(s
, R_SS
);
2405 gen_op_st_v(s
, d_ot
, val
, cpu_A0
);
2406 gen_op_mov_reg_v(a_ot
, R_ESP
, new_esp
);
2409 /* two step pop is necessary for precise exceptions */
2410 static TCGMemOp
gen_pop_T0(DisasContext
*s
)
2412 TCGMemOp d_ot
= mo_pushpop(s
, s
->dflag
);
2416 addr
= cpu_regs
[R_ESP
];
2417 } else if (!s
->ss32
) {
2418 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2419 gen_op_addl_A0_seg(s
, R_SS
);
2420 } else if (s
->addseg
) {
2421 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2422 gen_op_addl_A0_seg(s
, R_SS
);
2424 tcg_gen_ext32u_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2427 gen_op_ld_v(s
, d_ot
, cpu_T
[0], addr
);
2431 static void gen_pop_update(DisasContext
*s
, TCGMemOp ot
)
2433 gen_stack_update(s
, 1 << ot
);
2436 static void gen_stack_A0(DisasContext
*s
)
2438 gen_op_movl_A0_reg(R_ESP
);
2440 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2441 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2443 gen_op_addl_A0_seg(s
, R_SS
);
2446 /* NOTE: wrap around in 16 bit not fully handled */
2447 static void gen_pusha(DisasContext
*s
)
2450 gen_op_movl_A0_reg(R_ESP
);
2451 gen_op_addl_A0_im(-8 << s
->dflag
);
2453 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2454 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2456 gen_op_addl_A0_seg(s
, R_SS
);
2457 for(i
= 0;i
< 8; i
++) {
2458 gen_op_mov_TN_reg(MO_32
, 0, 7 - i
);
2459 gen_op_st_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2460 gen_op_addl_A0_im(1 << s
->dflag
);
2462 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2465 /* NOTE: wrap around in 16 bit not fully handled */
2466 static void gen_popa(DisasContext
*s
)
2469 gen_op_movl_A0_reg(R_ESP
);
2471 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2472 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2473 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 8 << s
->dflag
);
2475 gen_op_addl_A0_seg(s
, R_SS
);
2476 for(i
= 0;i
< 8; i
++) {
2477 /* ESP is not reloaded */
2479 gen_op_ld_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2480 gen_op_mov_reg_v(s
->dflag
, 7 - i
, cpu_T
[0]);
2482 gen_op_addl_A0_im(1 << s
->dflag
);
2484 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2487 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2489 TCGMemOp ot
= mo_pushpop(s
, s
->dflag
);
2490 int opsize
= 1 << ot
;
2493 #ifdef TARGET_X86_64
2495 gen_op_movl_A0_reg(R_ESP
);
2496 gen_op_addq_A0_im(-opsize
);
2497 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2500 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2501 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2503 /* XXX: must save state */
2504 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2505 tcg_const_i32((ot
== MO_64
)),
2508 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[1]);
2509 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2510 gen_op_mov_reg_v(MO_64
, R_ESP
, cpu_T
[1]);
2514 gen_op_movl_A0_reg(R_ESP
);
2515 gen_op_addl_A0_im(-opsize
);
2517 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2518 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2520 gen_op_addl_A0_seg(s
, R_SS
);
2522 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2523 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2525 /* XXX: must save state */
2526 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2527 tcg_const_i32(s
->dflag
- 1),
2530 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[1]);
2531 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2532 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2536 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2538 gen_update_cc_op(s
);
2539 gen_jmp_im(cur_eip
);
2540 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2541 s
->is_jmp
= DISAS_TB_JUMP
;
2544 /* an interrupt is different from an exception because of the
2546 static void gen_interrupt(DisasContext
*s
, int intno
,
2547 target_ulong cur_eip
, target_ulong next_eip
)
2549 gen_update_cc_op(s
);
2550 gen_jmp_im(cur_eip
);
2551 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2552 tcg_const_i32(next_eip
- cur_eip
));
2553 s
->is_jmp
= DISAS_TB_JUMP
;
2556 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2558 gen_update_cc_op(s
);
2559 gen_jmp_im(cur_eip
);
2560 gen_helper_debug(cpu_env
);
2561 s
->is_jmp
= DISAS_TB_JUMP
;
2564 /* generate a generic end of block. Trace exception is also generated
2566 static void gen_eob(DisasContext
*s
)
2568 gen_update_cc_op(s
);
2569 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2570 gen_helper_reset_inhibit_irq(cpu_env
);
2572 if (s
->tb
->flags
& HF_RF_MASK
) {
2573 gen_helper_reset_rf(cpu_env
);
2575 if (s
->singlestep_enabled
) {
2576 gen_helper_debug(cpu_env
);
2578 gen_helper_single_step(cpu_env
);
2582 s
->is_jmp
= DISAS_TB_JUMP
;
2585 /* generate a jump to eip. No segment change must happen before as a
2586 direct call to the next block may occur */
2587 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2589 gen_update_cc_op(s
);
2590 set_cc_op(s
, CC_OP_DYNAMIC
);
2592 gen_goto_tb(s
, tb_num
, eip
);
2593 s
->is_jmp
= DISAS_TB_JUMP
;
2600 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2602 gen_jmp_tb(s
, eip
, 0);
2605 static inline void gen_ldq_env_A0(DisasContext
*s
, int offset
)
2607 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2608 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2611 static inline void gen_stq_env_A0(DisasContext
*s
, int offset
)
2613 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2614 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2617 static inline void gen_ldo_env_A0(DisasContext
*s
, int offset
)
2619 int mem_index
= s
->mem_index
;
2620 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2621 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2622 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2623 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2624 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2627 static inline void gen_sto_env_A0(DisasContext
*s
, int offset
)
2629 int mem_index
= s
->mem_index
;
2630 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2631 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2632 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2633 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2634 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2637 static inline void gen_op_movo(int d_offset
, int s_offset
)
2639 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2640 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2641 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2642 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2645 static inline void gen_op_movq(int d_offset
, int s_offset
)
2647 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2648 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2651 static inline void gen_op_movl(int d_offset
, int s_offset
)
2653 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2654 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2657 static inline void gen_op_movq_env_0(int d_offset
)
2659 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2660 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2663 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2664 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2665 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2666 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2667 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2668 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2670 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2671 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2674 #define SSE_SPECIAL ((void *)1)
2675 #define SSE_DUMMY ((void *)2)
2677 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2678 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2679 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2681 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2682 /* 3DNow! extensions */
2683 [0x0e] = { SSE_DUMMY
}, /* femms */
2684 [0x0f] = { SSE_DUMMY
}, /* pf... */
2685 /* pure SSE operations */
2686 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2687 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2688 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2689 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2690 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2691 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2692 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2693 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2695 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2696 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2697 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2698 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2699 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2700 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2701 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2702 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2703 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2704 [0x51] = SSE_FOP(sqrt
),
2705 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2706 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2707 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2708 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2709 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2710 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2711 [0x58] = SSE_FOP(add
),
2712 [0x59] = SSE_FOP(mul
),
2713 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2714 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2715 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2716 [0x5c] = SSE_FOP(sub
),
2717 [0x5d] = SSE_FOP(min
),
2718 [0x5e] = SSE_FOP(div
),
2719 [0x5f] = SSE_FOP(max
),
2721 [0xc2] = SSE_FOP(cmpeq
),
2722 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2723 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2725 /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
2726 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2727 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2729 /* MMX ops and their SSE extensions */
2730 [0x60] = MMX_OP2(punpcklbw
),
2731 [0x61] = MMX_OP2(punpcklwd
),
2732 [0x62] = MMX_OP2(punpckldq
),
2733 [0x63] = MMX_OP2(packsswb
),
2734 [0x64] = MMX_OP2(pcmpgtb
),
2735 [0x65] = MMX_OP2(pcmpgtw
),
2736 [0x66] = MMX_OP2(pcmpgtl
),
2737 [0x67] = MMX_OP2(packuswb
),
2738 [0x68] = MMX_OP2(punpckhbw
),
2739 [0x69] = MMX_OP2(punpckhwd
),
2740 [0x6a] = MMX_OP2(punpckhdq
),
2741 [0x6b] = MMX_OP2(packssdw
),
2742 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2743 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2744 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2745 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2746 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2747 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2748 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2749 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2750 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2751 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2752 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2753 [0x74] = MMX_OP2(pcmpeqb
),
2754 [0x75] = MMX_OP2(pcmpeqw
),
2755 [0x76] = MMX_OP2(pcmpeql
),
2756 [0x77] = { SSE_DUMMY
}, /* emms */
2757 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2758 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2759 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2760 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2761 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2762 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2763 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2764 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2765 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2766 [0xd1] = MMX_OP2(psrlw
),
2767 [0xd2] = MMX_OP2(psrld
),
2768 [0xd3] = MMX_OP2(psrlq
),
2769 [0xd4] = MMX_OP2(paddq
),
2770 [0xd5] = MMX_OP2(pmullw
),
2771 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2772 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2773 [0xd8] = MMX_OP2(psubusb
),
2774 [0xd9] = MMX_OP2(psubusw
),
2775 [0xda] = MMX_OP2(pminub
),
2776 [0xdb] = MMX_OP2(pand
),
2777 [0xdc] = MMX_OP2(paddusb
),
2778 [0xdd] = MMX_OP2(paddusw
),
2779 [0xde] = MMX_OP2(pmaxub
),
2780 [0xdf] = MMX_OP2(pandn
),
2781 [0xe0] = MMX_OP2(pavgb
),
2782 [0xe1] = MMX_OP2(psraw
),
2783 [0xe2] = MMX_OP2(psrad
),
2784 [0xe3] = MMX_OP2(pavgw
),
2785 [0xe4] = MMX_OP2(pmulhuw
),
2786 [0xe5] = MMX_OP2(pmulhw
),
2787 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2788 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2789 [0xe8] = MMX_OP2(psubsb
),
2790 [0xe9] = MMX_OP2(psubsw
),
2791 [0xea] = MMX_OP2(pminsw
),
2792 [0xeb] = MMX_OP2(por
),
2793 [0xec] = MMX_OP2(paddsb
),
2794 [0xed] = MMX_OP2(paddsw
),
2795 [0xee] = MMX_OP2(pmaxsw
),
2796 [0xef] = MMX_OP2(pxor
),
2797 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2798 [0xf1] = MMX_OP2(psllw
),
2799 [0xf2] = MMX_OP2(pslld
),
2800 [0xf3] = MMX_OP2(psllq
),
2801 [0xf4] = MMX_OP2(pmuludq
),
2802 [0xf5] = MMX_OP2(pmaddwd
),
2803 [0xf6] = MMX_OP2(psadbw
),
2804 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
2805 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
2806 [0xf8] = MMX_OP2(psubb
),
2807 [0xf9] = MMX_OP2(psubw
),
2808 [0xfa] = MMX_OP2(psubl
),
2809 [0xfb] = MMX_OP2(psubq
),
2810 [0xfc] = MMX_OP2(paddb
),
2811 [0xfd] = MMX_OP2(paddw
),
2812 [0xfe] = MMX_OP2(paddl
),
2815 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
2816 [0 + 2] = MMX_OP2(psrlw
),
2817 [0 + 4] = MMX_OP2(psraw
),
2818 [0 + 6] = MMX_OP2(psllw
),
2819 [8 + 2] = MMX_OP2(psrld
),
2820 [8 + 4] = MMX_OP2(psrad
),
2821 [8 + 6] = MMX_OP2(pslld
),
2822 [16 + 2] = MMX_OP2(psrlq
),
2823 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2824 [16 + 6] = MMX_OP2(psllq
),
2825 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2828 static const SSEFunc_0_epi sse_op_table3ai
[] = {
2829 gen_helper_cvtsi2ss
,
2833 #ifdef TARGET_X86_64
2834 static const SSEFunc_0_epl sse_op_table3aq
[] = {
2835 gen_helper_cvtsq2ss
,
2840 static const SSEFunc_i_ep sse_op_table3bi
[] = {
2841 gen_helper_cvttss2si
,
2842 gen_helper_cvtss2si
,
2843 gen_helper_cvttsd2si
,
2847 #ifdef TARGET_X86_64
2848 static const SSEFunc_l_ep sse_op_table3bq
[] = {
2849 gen_helper_cvttss2sq
,
2850 gen_helper_cvtss2sq
,
2851 gen_helper_cvttsd2sq
,
2856 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
2867 static const SSEFunc_0_epp sse_op_table5
[256] = {
2868 [0x0c] = gen_helper_pi2fw
,
2869 [0x0d] = gen_helper_pi2fd
,
2870 [0x1c] = gen_helper_pf2iw
,
2871 [0x1d] = gen_helper_pf2id
,
2872 [0x8a] = gen_helper_pfnacc
,
2873 [0x8e] = gen_helper_pfpnacc
,
2874 [0x90] = gen_helper_pfcmpge
,
2875 [0x94] = gen_helper_pfmin
,
2876 [0x96] = gen_helper_pfrcp
,
2877 [0x97] = gen_helper_pfrsqrt
,
2878 [0x9a] = gen_helper_pfsub
,
2879 [0x9e] = gen_helper_pfadd
,
2880 [0xa0] = gen_helper_pfcmpgt
,
2881 [0xa4] = gen_helper_pfmax
,
2882 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2883 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2884 [0xaa] = gen_helper_pfsubr
,
2885 [0xae] = gen_helper_pfacc
,
2886 [0xb0] = gen_helper_pfcmpeq
,
2887 [0xb4] = gen_helper_pfmul
,
2888 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
2889 [0xb7] = gen_helper_pmulhrw_mmx
,
2890 [0xbb] = gen_helper_pswapd
,
2891 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
2894 struct SSEOpHelper_epp
{
2895 SSEFunc_0_epp op
[2];
2899 struct SSEOpHelper_eppi
{
2900 SSEFunc_0_eppi op
[2];
2904 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2905 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
2906 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
2907 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
2908 #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
2909 CPUID_EXT_PCLMULQDQ }
2910 #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
2912 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
2913 [0x00] = SSSE3_OP(pshufb
),
2914 [0x01] = SSSE3_OP(phaddw
),
2915 [0x02] = SSSE3_OP(phaddd
),
2916 [0x03] = SSSE3_OP(phaddsw
),
2917 [0x04] = SSSE3_OP(pmaddubsw
),
2918 [0x05] = SSSE3_OP(phsubw
),
2919 [0x06] = SSSE3_OP(phsubd
),
2920 [0x07] = SSSE3_OP(phsubsw
),
2921 [0x08] = SSSE3_OP(psignb
),
2922 [0x09] = SSSE3_OP(psignw
),
2923 [0x0a] = SSSE3_OP(psignd
),
2924 [0x0b] = SSSE3_OP(pmulhrsw
),
2925 [0x10] = SSE41_OP(pblendvb
),
2926 [0x14] = SSE41_OP(blendvps
),
2927 [0x15] = SSE41_OP(blendvpd
),
2928 [0x17] = SSE41_OP(ptest
),
2929 [0x1c] = SSSE3_OP(pabsb
),
2930 [0x1d] = SSSE3_OP(pabsw
),
2931 [0x1e] = SSSE3_OP(pabsd
),
2932 [0x20] = SSE41_OP(pmovsxbw
),
2933 [0x21] = SSE41_OP(pmovsxbd
),
2934 [0x22] = SSE41_OP(pmovsxbq
),
2935 [0x23] = SSE41_OP(pmovsxwd
),
2936 [0x24] = SSE41_OP(pmovsxwq
),
2937 [0x25] = SSE41_OP(pmovsxdq
),
2938 [0x28] = SSE41_OP(pmuldq
),
2939 [0x29] = SSE41_OP(pcmpeqq
),
2940 [0x2a] = SSE41_SPECIAL
, /* movntqda */
2941 [0x2b] = SSE41_OP(packusdw
),
2942 [0x30] = SSE41_OP(pmovzxbw
),
2943 [0x31] = SSE41_OP(pmovzxbd
),
2944 [0x32] = SSE41_OP(pmovzxbq
),
2945 [0x33] = SSE41_OP(pmovzxwd
),
2946 [0x34] = SSE41_OP(pmovzxwq
),
2947 [0x35] = SSE41_OP(pmovzxdq
),
2948 [0x37] = SSE42_OP(pcmpgtq
),
2949 [0x38] = SSE41_OP(pminsb
),
2950 [0x39] = SSE41_OP(pminsd
),
2951 [0x3a] = SSE41_OP(pminuw
),
2952 [0x3b] = SSE41_OP(pminud
),
2953 [0x3c] = SSE41_OP(pmaxsb
),
2954 [0x3d] = SSE41_OP(pmaxsd
),
2955 [0x3e] = SSE41_OP(pmaxuw
),
2956 [0x3f] = SSE41_OP(pmaxud
),
2957 [0x40] = SSE41_OP(pmulld
),
2958 [0x41] = SSE41_OP(phminposuw
),
2959 [0xdb] = AESNI_OP(aesimc
),
2960 [0xdc] = AESNI_OP(aesenc
),
2961 [0xdd] = AESNI_OP(aesenclast
),
2962 [0xde] = AESNI_OP(aesdec
),
2963 [0xdf] = AESNI_OP(aesdeclast
),
2966 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
2967 [0x08] = SSE41_OP(roundps
),
2968 [0x09] = SSE41_OP(roundpd
),
2969 [0x0a] = SSE41_OP(roundss
),
2970 [0x0b] = SSE41_OP(roundsd
),
2971 [0x0c] = SSE41_OP(blendps
),
2972 [0x0d] = SSE41_OP(blendpd
),
2973 [0x0e] = SSE41_OP(pblendw
),
2974 [0x0f] = SSSE3_OP(palignr
),
2975 [0x14] = SSE41_SPECIAL
, /* pextrb */
2976 [0x15] = SSE41_SPECIAL
, /* pextrw */
2977 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
2978 [0x17] = SSE41_SPECIAL
, /* extractps */
2979 [0x20] = SSE41_SPECIAL
, /* pinsrb */
2980 [0x21] = SSE41_SPECIAL
, /* insertps */
2981 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
2982 [0x40] = SSE41_OP(dpps
),
2983 [0x41] = SSE41_OP(dppd
),
2984 [0x42] = SSE41_OP(mpsadbw
),
2985 [0x44] = PCLMULQDQ_OP(pclmulqdq
),
2986 [0x60] = SSE42_OP(pcmpestrm
),
2987 [0x61] = SSE42_OP(pcmpestri
),
2988 [0x62] = SSE42_OP(pcmpistrm
),
2989 [0x63] = SSE42_OP(pcmpistri
),
2990 [0xdf] = AESNI_OP(aeskeygenassist
),
2993 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
2994 target_ulong pc_start
, int rex_r
)
2996 int b1
, op1_offset
, op2_offset
, is_xmm
, val
;
2997 int modrm
, mod
, rm
, reg
;
2998 SSEFunc_0_epp sse_fn_epp
;
2999 SSEFunc_0_eppi sse_fn_eppi
;
3000 SSEFunc_0_ppi sse_fn_ppi
;
3001 SSEFunc_0_eppt sse_fn_eppt
;
3005 if (s
->prefix
& PREFIX_DATA
)
3007 else if (s
->prefix
& PREFIX_REPZ
)
3009 else if (s
->prefix
& PREFIX_REPNZ
)
3013 sse_fn_epp
= sse_op_table1
[b
][b1
];
3017 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3027 /* simple MMX/SSE operation */
3028 if (s
->flags
& HF_TS_MASK
) {
3029 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3032 if (s
->flags
& HF_EM_MASK
) {
3034 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3037 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3038 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3041 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3044 gen_helper_emms(cpu_env
);
3049 gen_helper_emms(cpu_env
);
3052 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3053 the static cpu state) */
3055 gen_helper_enter_mmx(cpu_env
);
3058 modrm
= cpu_ldub_code(env
, s
->pc
++);
3059 reg
= ((modrm
>> 3) & 7);
3062 mod
= (modrm
>> 6) & 3;
3063 if (sse_fn_epp
== SSE_SPECIAL
) {
3066 case 0x0e7: /* movntq */
3069 gen_lea_modrm(env
, s
, modrm
);
3070 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3072 case 0x1e7: /* movntdq */
3073 case 0x02b: /* movntps */
3074 case 0x12b: /* movntps */
3077 gen_lea_modrm(env
, s
, modrm
);
3078 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3080 case 0x3f0: /* lddqu */
3083 gen_lea_modrm(env
, s
, modrm
);
3084 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3086 case 0x22b: /* movntss */
3087 case 0x32b: /* movntsd */
3090 gen_lea_modrm(env
, s
, modrm
);
3092 gen_stq_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3094 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3095 xmm_regs
[reg
].XMM_L(0)));
3096 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3099 case 0x6e: /* movd mm, ea */
3100 #ifdef TARGET_X86_64
3101 if (s
->dflag
== MO_64
) {
3102 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3103 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3107 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3108 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3109 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3110 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3111 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3114 case 0x16e: /* movd xmm, ea */
3115 #ifdef TARGET_X86_64
3116 if (s
->dflag
== MO_64
) {
3117 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3118 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3119 offsetof(CPUX86State
,xmm_regs
[reg
]));
3120 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3124 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3125 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3126 offsetof(CPUX86State
,xmm_regs
[reg
]));
3127 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3128 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3131 case 0x6f: /* movq mm, ea */
3133 gen_lea_modrm(env
, s
, modrm
);
3134 gen_ldq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3137 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3138 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3139 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3140 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3143 case 0x010: /* movups */
3144 case 0x110: /* movupd */
3145 case 0x028: /* movaps */
3146 case 0x128: /* movapd */
3147 case 0x16f: /* movdqa xmm, ea */
3148 case 0x26f: /* movdqu xmm, ea */
3150 gen_lea_modrm(env
, s
, modrm
);
3151 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3153 rm
= (modrm
& 7) | REX_B(s
);
3154 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3155 offsetof(CPUX86State
,xmm_regs
[rm
]));
3158 case 0x210: /* movss xmm, ea */
3160 gen_lea_modrm(env
, s
, modrm
);
3161 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3162 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3163 tcg_gen_movi_tl(cpu_T
[0], 0);
3164 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3165 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3166 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3168 rm
= (modrm
& 7) | REX_B(s
);
3169 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3170 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3173 case 0x310: /* movsd xmm, ea */
3175 gen_lea_modrm(env
, s
, modrm
);
3176 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3177 xmm_regs
[reg
].XMM_Q(0)));
3178 tcg_gen_movi_tl(cpu_T
[0], 0);
3179 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3180 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3182 rm
= (modrm
& 7) | REX_B(s
);
3183 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3184 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3187 case 0x012: /* movlps */
3188 case 0x112: /* movlpd */
3190 gen_lea_modrm(env
, s
, modrm
);
3191 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3192 xmm_regs
[reg
].XMM_Q(0)));
3195 rm
= (modrm
& 7) | REX_B(s
);
3196 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3197 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3200 case 0x212: /* movsldup */
3202 gen_lea_modrm(env
, s
, modrm
);
3203 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3205 rm
= (modrm
& 7) | REX_B(s
);
3206 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3207 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3208 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3209 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3211 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3212 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3213 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3214 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3216 case 0x312: /* movddup */
3218 gen_lea_modrm(env
, s
, modrm
);
3219 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3220 xmm_regs
[reg
].XMM_Q(0)));
3222 rm
= (modrm
& 7) | REX_B(s
);
3223 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3224 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3226 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3227 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3229 case 0x016: /* movhps */
3230 case 0x116: /* movhpd */
3232 gen_lea_modrm(env
, s
, modrm
);
3233 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3234 xmm_regs
[reg
].XMM_Q(1)));
3237 rm
= (modrm
& 7) | REX_B(s
);
3238 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3239 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3242 case 0x216: /* movshdup */
3244 gen_lea_modrm(env
, s
, modrm
);
3245 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3247 rm
= (modrm
& 7) | REX_B(s
);
3248 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3249 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3250 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3251 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3253 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3254 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3255 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3256 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3261 int bit_index
, field_length
;
3263 if (b1
== 1 && reg
!= 0)
3265 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3266 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3267 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3268 offsetof(CPUX86State
,xmm_regs
[reg
]));
3270 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3271 tcg_const_i32(bit_index
),
3272 tcg_const_i32(field_length
));
3274 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3275 tcg_const_i32(bit_index
),
3276 tcg_const_i32(field_length
));
3279 case 0x7e: /* movd ea, mm */
3280 #ifdef TARGET_X86_64
3281 if (s
->dflag
== MO_64
) {
3282 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3283 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3284 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3288 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3289 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3290 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3293 case 0x17e: /* movd ea, xmm */
3294 #ifdef TARGET_X86_64
3295 if (s
->dflag
== MO_64
) {
3296 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3297 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3298 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3302 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3303 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3304 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3307 case 0x27e: /* movq xmm, ea */
3309 gen_lea_modrm(env
, s
, modrm
);
3310 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3311 xmm_regs
[reg
].XMM_Q(0)));
3313 rm
= (modrm
& 7) | REX_B(s
);
3314 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3315 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3317 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3319 case 0x7f: /* movq ea, mm */
3321 gen_lea_modrm(env
, s
, modrm
);
3322 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3325 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3326 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3329 case 0x011: /* movups */
3330 case 0x111: /* movupd */
3331 case 0x029: /* movaps */
3332 case 0x129: /* movapd */
3333 case 0x17f: /* movdqa ea, xmm */
3334 case 0x27f: /* movdqu ea, xmm */
3336 gen_lea_modrm(env
, s
, modrm
);
3337 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3339 rm
= (modrm
& 7) | REX_B(s
);
3340 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3341 offsetof(CPUX86State
,xmm_regs
[reg
]));
3344 case 0x211: /* movss ea, xmm */
3346 gen_lea_modrm(env
, s
, modrm
);
3347 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3348 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3350 rm
= (modrm
& 7) | REX_B(s
);
3351 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3352 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3355 case 0x311: /* movsd ea, xmm */
3357 gen_lea_modrm(env
, s
, modrm
);
3358 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3359 xmm_regs
[reg
].XMM_Q(0)));
3361 rm
= (modrm
& 7) | REX_B(s
);
3362 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3363 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3366 case 0x013: /* movlps */
3367 case 0x113: /* movlpd */
3369 gen_lea_modrm(env
, s
, modrm
);
3370 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3371 xmm_regs
[reg
].XMM_Q(0)));
3376 case 0x017: /* movhps */
3377 case 0x117: /* movhpd */
3379 gen_lea_modrm(env
, s
, modrm
);
3380 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3381 xmm_regs
[reg
].XMM_Q(1)));
3386 case 0x71: /* shift mm, im */
3389 case 0x171: /* shift xmm, im */
3395 val
= cpu_ldub_code(env
, s
->pc
++);
3397 tcg_gen_movi_tl(cpu_T
[0], val
);
3398 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3399 tcg_gen_movi_tl(cpu_T
[0], 0);
3400 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3401 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3403 tcg_gen_movi_tl(cpu_T
[0], val
);
3404 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3405 tcg_gen_movi_tl(cpu_T
[0], 0);
3406 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3407 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3409 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3410 (((modrm
>> 3)) & 7)][b1
];
3415 rm
= (modrm
& 7) | REX_B(s
);
3416 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3419 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3421 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3422 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3423 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3425 case 0x050: /* movmskps */
3426 rm
= (modrm
& 7) | REX_B(s
);
3427 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3428 offsetof(CPUX86State
,xmm_regs
[rm
]));
3429 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3430 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3432 case 0x150: /* movmskpd */
3433 rm
= (modrm
& 7) | REX_B(s
);
3434 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3435 offsetof(CPUX86State
,xmm_regs
[rm
]));
3436 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3437 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3439 case 0x02a: /* cvtpi2ps */
3440 case 0x12a: /* cvtpi2pd */
3441 gen_helper_enter_mmx(cpu_env
);
3443 gen_lea_modrm(env
, s
, modrm
);
3444 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3445 gen_ldq_env_A0(s
, op2_offset
);
3448 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3450 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3451 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3452 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3455 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3459 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3463 case 0x22a: /* cvtsi2ss */
3464 case 0x32a: /* cvtsi2sd */
3465 ot
= mo_64_32(s
->dflag
);
3466 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3467 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3468 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3470 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3471 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3472 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3474 #ifdef TARGET_X86_64
3475 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3476 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3482 case 0x02c: /* cvttps2pi */
3483 case 0x12c: /* cvttpd2pi */
3484 case 0x02d: /* cvtps2pi */
3485 case 0x12d: /* cvtpd2pi */
3486 gen_helper_enter_mmx(cpu_env
);
3488 gen_lea_modrm(env
, s
, modrm
);
3489 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3490 gen_ldo_env_A0(s
, op2_offset
);
3492 rm
= (modrm
& 7) | REX_B(s
);
3493 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3495 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3496 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3497 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3500 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3503 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3506 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3509 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3513 case 0x22c: /* cvttss2si */
3514 case 0x32c: /* cvttsd2si */
3515 case 0x22d: /* cvtss2si */
3516 case 0x32d: /* cvtsd2si */
3517 ot
= mo_64_32(s
->dflag
);
3519 gen_lea_modrm(env
, s
, modrm
);
3521 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_Q(0)));
3523 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3524 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3526 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3528 rm
= (modrm
& 7) | REX_B(s
);
3529 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3531 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3533 SSEFunc_i_ep sse_fn_i_ep
=
3534 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3535 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3536 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3538 #ifdef TARGET_X86_64
3539 SSEFunc_l_ep sse_fn_l_ep
=
3540 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3541 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3546 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3548 case 0xc4: /* pinsrw */
3551 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
3552 val
= cpu_ldub_code(env
, s
->pc
++);
3555 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3556 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3559 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3560 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3563 case 0xc5: /* pextrw */
3567 ot
= mo_64_32(s
->dflag
);
3568 val
= cpu_ldub_code(env
, s
->pc
++);
3571 rm
= (modrm
& 7) | REX_B(s
);
3572 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3573 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3577 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3578 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3580 reg
= ((modrm
>> 3) & 7) | rex_r
;
3581 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3583 case 0x1d6: /* movq ea, xmm */
3585 gen_lea_modrm(env
, s
, modrm
);
3586 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3587 xmm_regs
[reg
].XMM_Q(0)));
3589 rm
= (modrm
& 7) | REX_B(s
);
3590 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3591 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3592 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3595 case 0x2d6: /* movq2dq */
3596 gen_helper_enter_mmx(cpu_env
);
3598 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3599 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3600 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3602 case 0x3d6: /* movdq2q */
3603 gen_helper_enter_mmx(cpu_env
);
3604 rm
= (modrm
& 7) | REX_B(s
);
3605 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3606 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3608 case 0xd7: /* pmovmskb */
3613 rm
= (modrm
& 7) | REX_B(s
);
3614 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3615 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3618 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3619 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3621 reg
= ((modrm
>> 3) & 7) | rex_r
;
3622 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3628 if ((b
& 0xf0) == 0xf0) {
3631 modrm
= cpu_ldub_code(env
, s
->pc
++);
3633 reg
= ((modrm
>> 3) & 7) | rex_r
;
3634 mod
= (modrm
>> 6) & 3;
3639 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3643 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3647 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3649 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3651 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3652 gen_lea_modrm(env
, s
, modrm
);
3654 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3655 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3656 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3657 gen_ldq_env_A0(s
, op2_offset
+
3658 offsetof(XMMReg
, XMM_Q(0)));
3660 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3661 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3662 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
3663 s
->mem_index
, MO_LEUL
);
3664 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3665 offsetof(XMMReg
, XMM_L(0)));
3667 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3668 tcg_gen_qemu_ld_tl(cpu_tmp0
, cpu_A0
,
3669 s
->mem_index
, MO_LEUW
);
3670 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3671 offsetof(XMMReg
, XMM_W(0)));
3673 case 0x2a: /* movntqda */
3674 gen_ldo_env_A0(s
, op1_offset
);
3677 gen_ldo_env_A0(s
, op2_offset
);
3681 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3683 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3685 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3686 gen_lea_modrm(env
, s
, modrm
);
3687 gen_ldq_env_A0(s
, op2_offset
);
3690 if (sse_fn_epp
== SSE_SPECIAL
) {
3694 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3695 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3696 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3699 set_cc_op(s
, CC_OP_EFLAGS
);
3706 /* Various integer extensions at 0f 38 f[0-f]. */
3707 b
= modrm
| (b1
<< 8);
3708 modrm
= cpu_ldub_code(env
, s
->pc
++);
3709 reg
= ((modrm
>> 3) & 7) | rex_r
;
3712 case 0x3f0: /* crc32 Gd,Eb */
3713 case 0x3f1: /* crc32 Gd,Ey */
3715 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
)) {
3718 if ((b
& 0xff) == 0xf0) {
3720 } else if (s
->dflag
!= MO_64
) {
3721 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3726 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[reg
]);
3727 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3728 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3729 cpu_T
[0], tcg_const_i32(8 << ot
));
3731 ot
= mo_64_32(s
->dflag
);
3732 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3735 case 0x1f0: /* crc32 or movbe */
3737 /* For these insns, the f3 prefix is supposed to have priority
3738 over the 66 prefix, but that's not what we implement above
3740 if (s
->prefix
& PREFIX_REPNZ
) {
3744 case 0x0f0: /* movbe Gy,My */
3745 case 0x0f1: /* movbe My,Gy */
3746 if (!(s
->cpuid_ext_features
& CPUID_EXT_MOVBE
)) {
3749 if (s
->dflag
!= MO_64
) {
3750 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3755 gen_lea_modrm(env
, s
, modrm
);
3757 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
3758 s
->mem_index
, ot
| MO_BE
);
3759 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3761 tcg_gen_qemu_st_tl(cpu_regs
[reg
], cpu_A0
,
3762 s
->mem_index
, ot
| MO_BE
);
3766 case 0x0f2: /* andn Gy, By, Ey */
3767 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3768 || !(s
->prefix
& PREFIX_VEX
)
3772 ot
= mo_64_32(s
->dflag
);
3773 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3774 tcg_gen_andc_tl(cpu_T
[0], cpu_regs
[s
->vex_v
], cpu_T
[0]);
3775 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3776 gen_op_update1_cc();
3777 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3780 case 0x0f7: /* bextr Gy, Ey, By */
3781 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3782 || !(s
->prefix
& PREFIX_VEX
)
3786 ot
= mo_64_32(s
->dflag
);
3790 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3791 /* Extract START, and shift the operand.
3792 Shifts larger than operand size get zeros. */
3793 tcg_gen_ext8u_tl(cpu_A0
, cpu_regs
[s
->vex_v
]);
3794 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3796 bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3797 zero
= tcg_const_tl(0);
3798 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_T
[0], cpu_A0
, bound
,
3800 tcg_temp_free(zero
);
3802 /* Extract the LEN into a mask. Lengths larger than
3803 operand size get all ones. */
3804 tcg_gen_shri_tl(cpu_A0
, cpu_regs
[s
->vex_v
], 8);
3805 tcg_gen_ext8u_tl(cpu_A0
, cpu_A0
);
3806 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_A0
, cpu_A0
, bound
,
3808 tcg_temp_free(bound
);
3809 tcg_gen_movi_tl(cpu_T
[1], 1);
3810 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_A0
);
3811 tcg_gen_subi_tl(cpu_T
[1], cpu_T
[1], 1);
3812 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3814 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3815 gen_op_update1_cc();
3816 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3820 case 0x0f5: /* bzhi Gy, Ey, By */
3821 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3822 || !(s
->prefix
& PREFIX_VEX
)
3826 ot
= mo_64_32(s
->dflag
);
3827 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3828 tcg_gen_ext8u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3830 TCGv bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3831 /* Note that since we're using BMILG (in order to get O
3832 cleared) we need to store the inverse into C. */
3833 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_cc_src
,
3835 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_T
[1], cpu_T
[1],
3836 bound
, bound
, cpu_T
[1]);
3837 tcg_temp_free(bound
);
3839 tcg_gen_movi_tl(cpu_A0
, -1);
3840 tcg_gen_shl_tl(cpu_A0
, cpu_A0
, cpu_T
[1]);
3841 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3842 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3843 gen_op_update1_cc();
3844 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
3847 case 0x3f6: /* mulx By, Gy, rdx, Ey */
3848 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3849 || !(s
->prefix
& PREFIX_VEX
)
3853 ot
= mo_64_32(s
->dflag
);
3854 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3857 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3858 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EDX
]);
3859 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
3860 cpu_tmp2_i32
, cpu_tmp3_i32
);
3861 tcg_gen_extu_i32_tl(cpu_regs
[s
->vex_v
], cpu_tmp2_i32
);
3862 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp3_i32
);
3864 #ifdef TARGET_X86_64
3866 tcg_gen_mulu2_i64(cpu_regs
[s
->vex_v
], cpu_regs
[reg
],
3867 cpu_T
[0], cpu_regs
[R_EDX
]);
3873 case 0x3f5: /* pdep Gy, By, Ey */
3874 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3875 || !(s
->prefix
& PREFIX_VEX
)
3879 ot
= mo_64_32(s
->dflag
);
3880 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3881 /* Note that by zero-extending the mask operand, we
3882 automatically handle zero-extending the result. */
3884 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3886 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3888 gen_helper_pdep(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3891 case 0x2f5: /* pext Gy, By, Ey */
3892 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3893 || !(s
->prefix
& PREFIX_VEX
)
3897 ot
= mo_64_32(s
->dflag
);
3898 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3899 /* Note that by zero-extending the mask operand, we
3900 automatically handle zero-extending the result. */
3902 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3904 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3906 gen_helper_pext(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3909 case 0x1f6: /* adcx Gy, Ey */
3910 case 0x2f6: /* adox Gy, Ey */
3911 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_ADX
)) {
3914 TCGv carry_in
, carry_out
, zero
;
3917 ot
= mo_64_32(s
->dflag
);
3918 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3920 /* Re-use the carry-out from a previous round. */
3921 TCGV_UNUSED(carry_in
);
3922 carry_out
= (b
== 0x1f6 ? cpu_cc_dst
: cpu_cc_src2
);
3926 carry_in
= cpu_cc_dst
;
3927 end_op
= CC_OP_ADCX
;
3929 end_op
= CC_OP_ADCOX
;
3934 end_op
= CC_OP_ADCOX
;
3936 carry_in
= cpu_cc_src2
;
3937 end_op
= CC_OP_ADOX
;
3941 end_op
= CC_OP_ADCOX
;
3942 carry_in
= carry_out
;
3945 end_op
= (b
== 0x1f6 ? CC_OP_ADCX
: CC_OP_ADOX
);
3948 /* If we can't reuse carry-out, get it out of EFLAGS. */
3949 if (TCGV_IS_UNUSED(carry_in
)) {
3950 if (s
->cc_op
!= CC_OP_ADCX
&& s
->cc_op
!= CC_OP_ADOX
) {
3951 gen_compute_eflags(s
);
3953 carry_in
= cpu_tmp0
;
3954 tcg_gen_shri_tl(carry_in
, cpu_cc_src
,
3955 ctz32(b
== 0x1f6 ? CC_C
: CC_O
));
3956 tcg_gen_andi_tl(carry_in
, carry_in
, 1);
3960 #ifdef TARGET_X86_64
3962 /* If we know TL is 64-bit, and we want a 32-bit
3963 result, just do everything in 64-bit arithmetic. */
3964 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_regs
[reg
]);
3965 tcg_gen_ext32u_i64(cpu_T
[0], cpu_T
[0]);
3966 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_regs
[reg
]);
3967 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], carry_in
);
3968 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_T
[0]);
3969 tcg_gen_shri_i64(carry_out
, cpu_T
[0], 32);
3973 /* Otherwise compute the carry-out in two steps. */
3974 zero
= tcg_const_tl(0);
3975 tcg_gen_add2_tl(cpu_T
[0], carry_out
,
3978 tcg_gen_add2_tl(cpu_regs
[reg
], carry_out
,
3979 cpu_regs
[reg
], carry_out
,
3981 tcg_temp_free(zero
);
3984 set_cc_op(s
, end_op
);
3988 case 0x1f7: /* shlx Gy, Ey, By */
3989 case 0x2f7: /* sarx Gy, Ey, By */
3990 case 0x3f7: /* shrx Gy, Ey, By */
3991 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3992 || !(s
->prefix
& PREFIX_VEX
)
3996 ot
= mo_64_32(s
->dflag
);
3997 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3999 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 63);
4001 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 31);
4004 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4005 } else if (b
== 0x2f7) {
4007 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4009 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4012 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4014 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4016 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4022 case 0x3f3: /* Group 17 */
4023 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
4024 || !(s
->prefix
& PREFIX_VEX
)
4028 ot
= mo_64_32(s
->dflag
);
4029 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4032 case 1: /* blsr By,Ey */
4033 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[0]);
4034 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4035 gen_op_mov_reg_v(ot
, s
->vex_v
, cpu_T
[0]);
4036 gen_op_update2_cc();
4037 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4040 case 2: /* blsmsk By,Ey */
4041 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4042 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4043 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4044 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4045 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4048 case 3: /* blsi By, Ey */
4049 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4050 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4051 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4052 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4053 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4069 modrm
= cpu_ldub_code(env
, s
->pc
++);
4071 reg
= ((modrm
>> 3) & 7) | rex_r
;
4072 mod
= (modrm
>> 6) & 3;
4077 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4081 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4084 if (sse_fn_eppi
== SSE_SPECIAL
) {
4085 ot
= mo_64_32(s
->dflag
);
4086 rm
= (modrm
& 7) | REX_B(s
);
4088 gen_lea_modrm(env
, s
, modrm
);
4089 reg
= ((modrm
>> 3) & 7) | rex_r
;
4090 val
= cpu_ldub_code(env
, s
->pc
++);
4092 case 0x14: /* pextrb */
4093 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4094 xmm_regs
[reg
].XMM_B(val
& 15)));
4096 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4098 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4099 s
->mem_index
, MO_UB
);
4102 case 0x15: /* pextrw */
4103 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4104 xmm_regs
[reg
].XMM_W(val
& 7)));
4106 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4108 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4109 s
->mem_index
, MO_LEUW
);
4113 if (ot
== MO_32
) { /* pextrd */
4114 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4115 offsetof(CPUX86State
,
4116 xmm_regs
[reg
].XMM_L(val
& 3)));
4118 tcg_gen_extu_i32_tl(cpu_regs
[rm
], cpu_tmp2_i32
);
4120 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
4121 s
->mem_index
, MO_LEUL
);
4123 } else { /* pextrq */
4124 #ifdef TARGET_X86_64
4125 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4126 offsetof(CPUX86State
,
4127 xmm_regs
[reg
].XMM_Q(val
& 1)));
4129 tcg_gen_mov_i64(cpu_regs
[rm
], cpu_tmp1_i64
);
4131 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
4132 s
->mem_index
, MO_LEQ
);
4139 case 0x17: /* extractps */
4140 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4141 xmm_regs
[reg
].XMM_L(val
& 3)));
4143 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4145 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4146 s
->mem_index
, MO_LEUL
);
4149 case 0x20: /* pinsrb */
4151 gen_op_mov_TN_reg(MO_32
, 0, rm
);
4153 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
4154 s
->mem_index
, MO_UB
);
4156 tcg_gen_st8_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4157 xmm_regs
[reg
].XMM_B(val
& 15)));
4159 case 0x21: /* insertps */
4161 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4162 offsetof(CPUX86State
,xmm_regs
[rm
]
4163 .XMM_L((val
>> 6) & 3)));
4165 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4166 s
->mem_index
, MO_LEUL
);
4168 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4169 offsetof(CPUX86State
,xmm_regs
[reg
]
4170 .XMM_L((val
>> 4) & 3)));
4172 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4173 cpu_env
, offsetof(CPUX86State
,
4174 xmm_regs
[reg
].XMM_L(0)));
4176 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4177 cpu_env
, offsetof(CPUX86State
,
4178 xmm_regs
[reg
].XMM_L(1)));
4180 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4181 cpu_env
, offsetof(CPUX86State
,
4182 xmm_regs
[reg
].XMM_L(2)));
4184 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4185 cpu_env
, offsetof(CPUX86State
,
4186 xmm_regs
[reg
].XMM_L(3)));
4189 if (ot
== MO_32
) { /* pinsrd */
4191 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[rm
]);
4193 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4194 s
->mem_index
, MO_LEUL
);
4196 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4197 offsetof(CPUX86State
,
4198 xmm_regs
[reg
].XMM_L(val
& 3)));
4199 } else { /* pinsrq */
4200 #ifdef TARGET_X86_64
4202 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4204 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
4205 s
->mem_index
, MO_LEQ
);
4207 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4208 offsetof(CPUX86State
,
4209 xmm_regs
[reg
].XMM_Q(val
& 1)));
4220 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4222 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4224 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4225 gen_lea_modrm(env
, s
, modrm
);
4226 gen_ldo_env_A0(s
, op2_offset
);
4229 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4231 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4233 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4234 gen_lea_modrm(env
, s
, modrm
);
4235 gen_ldq_env_A0(s
, op2_offset
);
4238 val
= cpu_ldub_code(env
, s
->pc
++);
4240 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4241 set_cc_op(s
, CC_OP_EFLAGS
);
4243 if (s
->dflag
== MO_64
) {
4244 /* The helper must use entire 64-bit gp registers */
4249 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4250 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4251 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4255 /* Various integer extensions at 0f 3a f[0-f]. */
4256 b
= modrm
| (b1
<< 8);
4257 modrm
= cpu_ldub_code(env
, s
->pc
++);
4258 reg
= ((modrm
>> 3) & 7) | rex_r
;
4261 case 0x3f0: /* rorx Gy,Ey, Ib */
4262 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4263 || !(s
->prefix
& PREFIX_VEX
)
4267 ot
= mo_64_32(s
->dflag
);
4268 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4269 b
= cpu_ldub_code(env
, s
->pc
++);
4271 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], b
& 63);
4273 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4274 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, b
& 31);
4275 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4277 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4289 /* generic MMX or SSE operation */
4291 case 0x70: /* pshufx insn */
4292 case 0xc6: /* pshufx insn */
4293 case 0xc2: /* compare insns */
4300 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4302 gen_lea_modrm(env
, s
, modrm
);
4303 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4304 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4306 /* specific case for SSE single instructions */
4309 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
4310 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4313 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
4317 gen_ldo_env_A0(s
, op2_offset
);
4320 rm
= (modrm
& 7) | REX_B(s
);
4321 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4324 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4326 gen_lea_modrm(env
, s
, modrm
);
4327 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4328 gen_ldq_env_A0(s
, op2_offset
);
4331 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4335 case 0x0f: /* 3DNow! data insns */
4336 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4338 val
= cpu_ldub_code(env
, s
->pc
++);
4339 sse_fn_epp
= sse_op_table5
[val
];
4343 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4344 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4345 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4347 case 0x70: /* pshufx insn */
4348 case 0xc6: /* pshufx insn */
4349 val
= cpu_ldub_code(env
, s
->pc
++);
4350 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4351 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4352 /* XXX: introduce a new table? */
4353 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4354 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4358 val
= cpu_ldub_code(env
, s
->pc
++);
4361 sse_fn_epp
= sse_op_table4
[val
][b1
];
4363 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4364 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4365 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4368 /* maskmov : we must prepare A0 */
4371 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EDI
]);
4372 gen_extu(s
->aflag
, cpu_A0
);
4373 gen_add_A0_ds_seg(s
);
4375 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4376 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4377 /* XXX: introduce a new table? */
4378 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4379 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4382 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4383 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4384 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4387 if (b
== 0x2e || b
== 0x2f) {
4388 set_cc_op(s
, CC_OP_EFLAGS
);
4393 /* convert one instruction. s->is_jmp is set if the translation must
4394 be stopped. Return the next pc value */
4395 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4396 target_ulong pc_start
)
4400 TCGMemOp ot
, aflag
, dflag
;
4401 int modrm
, reg
, rm
, mod
, op
, opreg
, val
;
4402 target_ulong next_eip
, tval
;
4405 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4406 tcg_gen_debug_insn_start(pc_start
);
4413 #ifdef TARGET_X86_64
4418 s
->rip_offset
= 0; /* for relative ip address */
4422 b
= cpu_ldub_code(env
, s
->pc
);
4424 /* Collect prefixes. */
4427 prefixes
|= PREFIX_REPZ
;
4430 prefixes
|= PREFIX_REPNZ
;
4433 prefixes
|= PREFIX_LOCK
;
4454 prefixes
|= PREFIX_DATA
;
4457 prefixes
|= PREFIX_ADR
;
4459 #ifdef TARGET_X86_64
4463 rex_w
= (b
>> 3) & 1;
4464 rex_r
= (b
& 0x4) << 1;
4465 s
->rex_x
= (b
& 0x2) << 2;
4466 REX_B(s
) = (b
& 0x1) << 3;
4467 x86_64_hregs
= 1; /* select uniform byte register addressing */
4472 case 0xc5: /* 2-byte VEX */
4473 case 0xc4: /* 3-byte VEX */
4474 /* VEX prefixes cannot be used except in 32-bit mode.
4475 Otherwise the instruction is LES or LDS. */
4476 if (s
->code32
&& !s
->vm86
) {
4477 static const int pp_prefix
[4] = {
4478 0, PREFIX_DATA
, PREFIX_REPZ
, PREFIX_REPNZ
4480 int vex3
, vex2
= cpu_ldub_code(env
, s
->pc
);
4482 if (!CODE64(s
) && (vex2
& 0xc0) != 0xc0) {
4483 /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
4484 otherwise the instruction is LES or LDS. */
4489 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
4490 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
4491 | PREFIX_LOCK
| PREFIX_DATA
)) {
4494 #ifdef TARGET_X86_64
4499 rex_r
= (~vex2
>> 4) & 8;
4502 b
= cpu_ldub_code(env
, s
->pc
++);
4504 #ifdef TARGET_X86_64
4505 s
->rex_x
= (~vex2
>> 3) & 8;
4506 s
->rex_b
= (~vex2
>> 2) & 8;
4508 vex3
= cpu_ldub_code(env
, s
->pc
++);
4509 rex_w
= (vex3
>> 7) & 1;
4510 switch (vex2
& 0x1f) {
4511 case 0x01: /* Implied 0f leading opcode bytes. */
4512 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4514 case 0x02: /* Implied 0f 38 leading opcode bytes. */
4517 case 0x03: /* Implied 0f 3a leading opcode bytes. */
4520 default: /* Reserved for future use. */
4524 s
->vex_v
= (~vex3
>> 3) & 0xf;
4525 s
->vex_l
= (vex3
>> 2) & 1;
4526 prefixes
|= pp_prefix
[vex3
& 3] | PREFIX_VEX
;
4531 /* Post-process prefixes. */
4533 /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
4534 data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
4535 over 0x66 if both are present. */
4536 dflag
= (rex_w
> 0 ? MO_64
: prefixes
& PREFIX_DATA
? MO_16
: MO_32
);
4537 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
4538 aflag
= (prefixes
& PREFIX_ADR
? MO_32
: MO_64
);
4540 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
4541 if (s
->code32
^ ((prefixes
& PREFIX_DATA
) != 0)) {
4546 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
4547 if (s
->code32
^ ((prefixes
& PREFIX_ADR
) != 0)) {
4554 s
->prefix
= prefixes
;
4558 /* lock generation */
4559 if (prefixes
& PREFIX_LOCK
)
4562 /* now check op code */
4566 /**************************/
4567 /* extended op code */
4568 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4571 /**************************/
4586 ot
= mo_b_d(b
, dflag
);
4589 case 0: /* OP Ev, Gv */
4590 modrm
= cpu_ldub_code(env
, s
->pc
++);
4591 reg
= ((modrm
>> 3) & 7) | rex_r
;
4592 mod
= (modrm
>> 6) & 3;
4593 rm
= (modrm
& 7) | REX_B(s
);
4595 gen_lea_modrm(env
, s
, modrm
);
4597 } else if (op
== OP_XORL
&& rm
== reg
) {
4599 /* xor reg, reg optimisation */
4600 set_cc_op(s
, CC_OP_CLR
);
4601 tcg_gen_movi_tl(cpu_T
[0], 0);
4602 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4607 gen_op_mov_TN_reg(ot
, 1, reg
);
4608 gen_op(s
, op
, ot
, opreg
);
4610 case 1: /* OP Gv, Ev */
4611 modrm
= cpu_ldub_code(env
, s
->pc
++);
4612 mod
= (modrm
>> 6) & 3;
4613 reg
= ((modrm
>> 3) & 7) | rex_r
;
4614 rm
= (modrm
& 7) | REX_B(s
);
4616 gen_lea_modrm(env
, s
, modrm
);
4617 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4618 } else if (op
== OP_XORL
&& rm
== reg
) {
4621 gen_op_mov_TN_reg(ot
, 1, rm
);
4623 gen_op(s
, op
, ot
, reg
);
4625 case 2: /* OP A, Iv */
4626 val
= insn_get(env
, s
, ot
);
4627 tcg_gen_movi_tl(cpu_T
[1], val
);
4628 gen_op(s
, op
, ot
, OR_EAX
);
4637 case 0x80: /* GRP1 */
4643 ot
= mo_b_d(b
, dflag
);
4645 modrm
= cpu_ldub_code(env
, s
->pc
++);
4646 mod
= (modrm
>> 6) & 3;
4647 rm
= (modrm
& 7) | REX_B(s
);
4648 op
= (modrm
>> 3) & 7;
4654 s
->rip_offset
= insn_const_size(ot
);
4655 gen_lea_modrm(env
, s
, modrm
);
4666 val
= insn_get(env
, s
, ot
);
4669 val
= (int8_t)insn_get(env
, s
, MO_8
);
4672 tcg_gen_movi_tl(cpu_T
[1], val
);
4673 gen_op(s
, op
, ot
, opreg
);
4677 /**************************/
4678 /* inc, dec, and other misc arith */
4679 case 0x40 ... 0x47: /* inc Gv */
4681 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4683 case 0x48 ... 0x4f: /* dec Gv */
4685 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4687 case 0xf6: /* GRP3 */
4689 ot
= mo_b_d(b
, dflag
);
4691 modrm
= cpu_ldub_code(env
, s
->pc
++);
4692 mod
= (modrm
>> 6) & 3;
4693 rm
= (modrm
& 7) | REX_B(s
);
4694 op
= (modrm
>> 3) & 7;
4697 s
->rip_offset
= insn_const_size(ot
);
4698 gen_lea_modrm(env
, s
, modrm
);
4699 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4701 gen_op_mov_TN_reg(ot
, 0, rm
);
4706 val
= insn_get(env
, s
, ot
);
4707 tcg_gen_movi_tl(cpu_T
[1], val
);
4708 gen_op_testl_T0_T1_cc();
4709 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4712 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4714 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4716 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4720 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4722 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4724 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4726 gen_op_update_neg_cc();
4727 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4732 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4733 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4734 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4735 /* XXX: use 32 bit mul which could be faster */
4736 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4737 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4738 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4739 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4740 set_cc_op(s
, CC_OP_MULB
);
4743 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4744 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4745 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4746 /* XXX: use 32 bit mul which could be faster */
4747 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4748 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4749 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4750 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4751 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
4752 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4753 set_cc_op(s
, CC_OP_MULW
);
4757 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4758 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4759 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4760 cpu_tmp2_i32
, cpu_tmp3_i32
);
4761 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4762 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4763 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4764 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4765 set_cc_op(s
, CC_OP_MULL
);
4767 #ifdef TARGET_X86_64
4769 tcg_gen_mulu2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4770 cpu_T
[0], cpu_regs
[R_EAX
]);
4771 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4772 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4773 set_cc_op(s
, CC_OP_MULQ
);
4781 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4782 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4783 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4784 /* XXX: use 32 bit mul which could be faster */
4785 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4786 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4787 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4788 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4789 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4790 set_cc_op(s
, CC_OP_MULB
);
4793 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4794 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4795 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4796 /* XXX: use 32 bit mul which could be faster */
4797 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4798 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4799 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4800 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4801 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4802 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4803 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
4804 set_cc_op(s
, CC_OP_MULW
);
4808 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4809 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4810 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4811 cpu_tmp2_i32
, cpu_tmp3_i32
);
4812 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4813 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4814 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
4815 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4816 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
4817 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
4818 set_cc_op(s
, CC_OP_MULL
);
4820 #ifdef TARGET_X86_64
4822 tcg_gen_muls2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4823 cpu_T
[0], cpu_regs
[R_EAX
]);
4824 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4825 tcg_gen_sari_tl(cpu_cc_src
, cpu_regs
[R_EAX
], 63);
4826 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_regs
[R_EDX
]);
4827 set_cc_op(s
, CC_OP_MULQ
);
4835 gen_jmp_im(pc_start
- s
->cs_base
);
4836 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4839 gen_jmp_im(pc_start
- s
->cs_base
);
4840 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4844 gen_jmp_im(pc_start
- s
->cs_base
);
4845 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4847 #ifdef TARGET_X86_64
4849 gen_jmp_im(pc_start
- s
->cs_base
);
4850 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4858 gen_jmp_im(pc_start
- s
->cs_base
);
4859 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4862 gen_jmp_im(pc_start
- s
->cs_base
);
4863 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4867 gen_jmp_im(pc_start
- s
->cs_base
);
4868 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4870 #ifdef TARGET_X86_64
4872 gen_jmp_im(pc_start
- s
->cs_base
);
4873 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4883 case 0xfe: /* GRP4 */
4884 case 0xff: /* GRP5 */
4885 ot
= mo_b_d(b
, dflag
);
4887 modrm
= cpu_ldub_code(env
, s
->pc
++);
4888 mod
= (modrm
>> 6) & 3;
4889 rm
= (modrm
& 7) | REX_B(s
);
4890 op
= (modrm
>> 3) & 7;
4891 if (op
>= 2 && b
== 0xfe) {
4895 if (op
== 2 || op
== 4) {
4896 /* operand size for jumps is 64 bit */
4898 } else if (op
== 3 || op
== 5) {
4899 ot
= dflag
!= MO_16
? MO_32
+ (rex_w
== 1) : MO_16
;
4900 } else if (op
== 6) {
4901 /* default push size is 64 bit */
4902 ot
= mo_pushpop(s
, dflag
);
4906 gen_lea_modrm(env
, s
, modrm
);
4907 if (op
>= 2 && op
!= 3 && op
!= 5)
4908 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4910 gen_op_mov_TN_reg(ot
, 0, rm
);
4914 case 0: /* inc Ev */
4919 gen_inc(s
, ot
, opreg
, 1);
4921 case 1: /* dec Ev */
4926 gen_inc(s
, ot
, opreg
, -1);
4928 case 2: /* call Ev */
4929 /* XXX: optimize if memory (no 'and' is necessary) */
4930 if (dflag
== MO_16
) {
4931 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4933 next_eip
= s
->pc
- s
->cs_base
;
4934 tcg_gen_movi_tl(cpu_T
[1], next_eip
);
4935 gen_push_v(s
, cpu_T
[1]);
4939 case 3: /* lcall Ev */
4940 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4941 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
4942 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4944 if (s
->pe
&& !s
->vm86
) {
4945 gen_update_cc_op(s
);
4946 gen_jmp_im(pc_start
- s
->cs_base
);
4947 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4948 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4949 tcg_const_i32(dflag
- 1),
4950 tcg_const_i32(s
->pc
- pc_start
));
4952 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4953 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4954 tcg_const_i32(dflag
- 1),
4955 tcg_const_i32(s
->pc
- s
->cs_base
));
4959 case 4: /* jmp Ev */
4960 if (dflag
== MO_16
) {
4961 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4966 case 5: /* ljmp Ev */
4967 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4968 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
4969 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4971 if (s
->pe
&& !s
->vm86
) {
4972 gen_update_cc_op(s
);
4973 gen_jmp_im(pc_start
- s
->cs_base
);
4974 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4975 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4976 tcg_const_i32(s
->pc
- pc_start
));
4978 gen_op_movl_seg_T0_vm(R_CS
);
4979 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
4984 case 6: /* push Ev */
4985 gen_push_v(s
, cpu_T
[0]);
4992 case 0x84: /* test Ev, Gv */
4994 ot
= mo_b_d(b
, dflag
);
4996 modrm
= cpu_ldub_code(env
, s
->pc
++);
4997 reg
= ((modrm
>> 3) & 7) | rex_r
;
4999 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5000 gen_op_mov_TN_reg(ot
, 1, reg
);
5001 gen_op_testl_T0_T1_cc();
5002 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5005 case 0xa8: /* test eAX, Iv */
5007 ot
= mo_b_d(b
, dflag
);
5008 val
= insn_get(env
, s
, ot
);
5010 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
5011 tcg_gen_movi_tl(cpu_T
[1], val
);
5012 gen_op_testl_T0_T1_cc();
5013 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5016 case 0x98: /* CWDE/CBW */
5018 #ifdef TARGET_X86_64
5020 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5021 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5022 gen_op_mov_reg_v(MO_64
, R_EAX
, cpu_T
[0]);
5026 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5027 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5028 gen_op_mov_reg_v(MO_32
, R_EAX
, cpu_T
[0]);
5031 gen_op_mov_TN_reg(MO_8
, 0, R_EAX
);
5032 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5033 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
5039 case 0x99: /* CDQ/CWD */
5041 #ifdef TARGET_X86_64
5043 gen_op_mov_TN_reg(MO_64
, 0, R_EAX
);
5044 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
5045 gen_op_mov_reg_v(MO_64
, R_EDX
, cpu_T
[0]);
5049 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5050 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5051 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
5052 gen_op_mov_reg_v(MO_32
, R_EDX
, cpu_T
[0]);
5055 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5056 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5057 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
5058 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
5064 case 0x1af: /* imul Gv, Ev */
5065 case 0x69: /* imul Gv, Ev, I */
5068 modrm
= cpu_ldub_code(env
, s
->pc
++);
5069 reg
= ((modrm
>> 3) & 7) | rex_r
;
5071 s
->rip_offset
= insn_const_size(ot
);
5074 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5076 val
= insn_get(env
, s
, ot
);
5077 tcg_gen_movi_tl(cpu_T
[1], val
);
5078 } else if (b
== 0x6b) {
5079 val
= (int8_t)insn_get(env
, s
, MO_8
);
5080 tcg_gen_movi_tl(cpu_T
[1], val
);
5082 gen_op_mov_TN_reg(ot
, 1, reg
);
5085 #ifdef TARGET_X86_64
5087 tcg_gen_muls2_i64(cpu_regs
[reg
], cpu_T
[1], cpu_T
[0], cpu_T
[1]);
5088 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5089 tcg_gen_sari_tl(cpu_cc_src
, cpu_cc_dst
, 63);
5090 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[1]);
5094 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5095 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5096 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
5097 cpu_tmp2_i32
, cpu_tmp3_i32
);
5098 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
5099 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
5100 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5101 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
5102 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
5105 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5106 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5107 /* XXX: use 32 bit mul which could be faster */
5108 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5109 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5110 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5111 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5112 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5115 set_cc_op(s
, CC_OP_MULB
+ ot
);
5118 case 0x1c1: /* xadd Ev, Gv */
5119 ot
= mo_b_d(b
, dflag
);
5120 modrm
= cpu_ldub_code(env
, s
->pc
++);
5121 reg
= ((modrm
>> 3) & 7) | rex_r
;
5122 mod
= (modrm
>> 6) & 3;
5124 rm
= (modrm
& 7) | REX_B(s
);
5125 gen_op_mov_TN_reg(ot
, 0, reg
);
5126 gen_op_mov_TN_reg(ot
, 1, rm
);
5127 gen_op_addl_T0_T1();
5128 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5129 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5131 gen_lea_modrm(env
, s
, modrm
);
5132 gen_op_mov_TN_reg(ot
, 0, reg
);
5133 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5134 gen_op_addl_T0_T1();
5135 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5136 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5138 gen_op_update2_cc();
5139 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5142 case 0x1b1: /* cmpxchg Ev, Gv */
5145 TCGv t0
, t1
, t2
, a0
;
5147 ot
= mo_b_d(b
, dflag
);
5148 modrm
= cpu_ldub_code(env
, s
->pc
++);
5149 reg
= ((modrm
>> 3) & 7) | rex_r
;
5150 mod
= (modrm
>> 6) & 3;
5151 t0
= tcg_temp_local_new();
5152 t1
= tcg_temp_local_new();
5153 t2
= tcg_temp_local_new();
5154 a0
= tcg_temp_local_new();
5155 gen_op_mov_v_reg(ot
, t1
, reg
);
5157 rm
= (modrm
& 7) | REX_B(s
);
5158 gen_op_mov_v_reg(ot
, t0
, rm
);
5160 gen_lea_modrm(env
, s
, modrm
);
5161 tcg_gen_mov_tl(a0
, cpu_A0
);
5162 gen_op_ld_v(s
, ot
, t0
, a0
);
5163 rm
= 0; /* avoid warning */
5165 label1
= gen_new_label();
5166 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5169 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5170 label2
= gen_new_label();
5172 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5174 gen_set_label(label1
);
5175 gen_op_mov_reg_v(ot
, rm
, t1
);
5177 /* perform no-op store cycle like physical cpu; must be
5178 before changing accumulator to ensure idempotency if
5179 the store faults and the instruction is restarted */
5180 gen_op_st_v(s
, ot
, t0
, a0
);
5181 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5183 gen_set_label(label1
);
5184 gen_op_st_v(s
, ot
, t1
, a0
);
5186 gen_set_label(label2
);
5187 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5188 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5189 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5190 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5197 case 0x1c7: /* cmpxchg8b */
5198 modrm
= cpu_ldub_code(env
, s
->pc
++);
5199 mod
= (modrm
>> 6) & 3;
5200 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5202 #ifdef TARGET_X86_64
5203 if (dflag
== MO_64
) {
5204 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5206 gen_jmp_im(pc_start
- s
->cs_base
);
5207 gen_update_cc_op(s
);
5208 gen_lea_modrm(env
, s
, modrm
);
5209 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5213 if (!(s
->cpuid_features
& CPUID_CX8
))
5215 gen_jmp_im(pc_start
- s
->cs_base
);
5216 gen_update_cc_op(s
);
5217 gen_lea_modrm(env
, s
, modrm
);
5218 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5220 set_cc_op(s
, CC_OP_EFLAGS
);
5223 /**************************/
5225 case 0x50 ... 0x57: /* push */
5226 gen_op_mov_TN_reg(MO_32
, 0, (b
& 7) | REX_B(s
));
5227 gen_push_v(s
, cpu_T
[0]);
5229 case 0x58 ... 0x5f: /* pop */
5231 /* NOTE: order is important for pop %sp */
5232 gen_pop_update(s
, ot
);
5233 gen_op_mov_reg_v(ot
, (b
& 7) | REX_B(s
), cpu_T
[0]);
5235 case 0x60: /* pusha */
5240 case 0x61: /* popa */
5245 case 0x68: /* push Iv */
5247 ot
= mo_pushpop(s
, dflag
);
5249 val
= insn_get(env
, s
, ot
);
5251 val
= (int8_t)insn_get(env
, s
, MO_8
);
5252 tcg_gen_movi_tl(cpu_T
[0], val
);
5253 gen_push_v(s
, cpu_T
[0]);
5255 case 0x8f: /* pop Ev */
5256 modrm
= cpu_ldub_code(env
, s
->pc
++);
5257 mod
= (modrm
>> 6) & 3;
5260 /* NOTE: order is important for pop %sp */
5261 gen_pop_update(s
, ot
);
5262 rm
= (modrm
& 7) | REX_B(s
);
5263 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5265 /* NOTE: order is important too for MMU exceptions */
5266 s
->popl_esp_hack
= 1 << ot
;
5267 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5268 s
->popl_esp_hack
= 0;
5269 gen_pop_update(s
, ot
);
5272 case 0xc8: /* enter */
5275 val
= cpu_lduw_code(env
, s
->pc
);
5277 level
= cpu_ldub_code(env
, s
->pc
++);
5278 gen_enter(s
, val
, level
);
5281 case 0xc9: /* leave */
5282 /* XXX: exception not precise (ESP is updated before potential exception) */
5284 gen_op_mov_TN_reg(MO_64
, 0, R_EBP
);
5285 gen_op_mov_reg_v(MO_64
, R_ESP
, cpu_T
[0]);
5286 } else if (s
->ss32
) {
5287 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
5288 gen_op_mov_reg_v(MO_32
, R_ESP
, cpu_T
[0]);
5290 gen_op_mov_TN_reg(MO_16
, 0, R_EBP
);
5291 gen_op_mov_reg_v(MO_16
, R_ESP
, cpu_T
[0]);
5294 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[0]);
5295 gen_pop_update(s
, ot
);
5297 case 0x06: /* push es */
5298 case 0x0e: /* push cs */
5299 case 0x16: /* push ss */
5300 case 0x1e: /* push ds */
5303 gen_op_movl_T0_seg(b
>> 3);
5304 gen_push_v(s
, cpu_T
[0]);
5306 case 0x1a0: /* push fs */
5307 case 0x1a8: /* push gs */
5308 gen_op_movl_T0_seg((b
>> 3) & 7);
5309 gen_push_v(s
, cpu_T
[0]);
5311 case 0x07: /* pop es */
5312 case 0x17: /* pop ss */
5313 case 0x1f: /* pop ds */
5318 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5319 gen_pop_update(s
, ot
);
5321 /* if reg == SS, inhibit interrupts/trace. */
5322 /* If several instructions disable interrupts, only the
5324 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5325 gen_helper_set_inhibit_irq(cpu_env
);
5329 gen_jmp_im(s
->pc
- s
->cs_base
);
5333 case 0x1a1: /* pop fs */
5334 case 0x1a9: /* pop gs */
5336 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5337 gen_pop_update(s
, ot
);
5339 gen_jmp_im(s
->pc
- s
->cs_base
);
5344 /**************************/
5347 case 0x89: /* mov Gv, Ev */
5348 ot
= mo_b_d(b
, dflag
);
5349 modrm
= cpu_ldub_code(env
, s
->pc
++);
5350 reg
= ((modrm
>> 3) & 7) | rex_r
;
5352 /* generate a generic store */
5353 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5356 case 0xc7: /* mov Ev, Iv */
5357 ot
= mo_b_d(b
, dflag
);
5358 modrm
= cpu_ldub_code(env
, s
->pc
++);
5359 mod
= (modrm
>> 6) & 3;
5361 s
->rip_offset
= insn_const_size(ot
);
5362 gen_lea_modrm(env
, s
, modrm
);
5364 val
= insn_get(env
, s
, ot
);
5365 tcg_gen_movi_tl(cpu_T
[0], val
);
5367 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5369 gen_op_mov_reg_v(ot
, (modrm
& 7) | REX_B(s
), cpu_T
[0]);
5373 case 0x8b: /* mov Ev, Gv */
5374 ot
= mo_b_d(b
, dflag
);
5375 modrm
= cpu_ldub_code(env
, s
->pc
++);
5376 reg
= ((modrm
>> 3) & 7) | rex_r
;
5378 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5379 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5381 case 0x8e: /* mov seg, Gv */
5382 modrm
= cpu_ldub_code(env
, s
->pc
++);
5383 reg
= (modrm
>> 3) & 7;
5384 if (reg
>= 6 || reg
== R_CS
)
5386 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
5387 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5389 /* if reg == SS, inhibit interrupts/trace */
5390 /* If several instructions disable interrupts, only the
5392 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5393 gen_helper_set_inhibit_irq(cpu_env
);
5397 gen_jmp_im(s
->pc
- s
->cs_base
);
5401 case 0x8c: /* mov Gv, seg */
5402 modrm
= cpu_ldub_code(env
, s
->pc
++);
5403 reg
= (modrm
>> 3) & 7;
5404 mod
= (modrm
>> 6) & 3;
5407 gen_op_movl_T0_seg(reg
);
5408 ot
= mod
== 3 ? dflag
: MO_16
;
5409 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5412 case 0x1b6: /* movzbS Gv, Eb */
5413 case 0x1b7: /* movzwS Gv, Eb */
5414 case 0x1be: /* movsbS Gv, Eb */
5415 case 0x1bf: /* movswS Gv, Eb */
5420 /* d_ot is the size of destination */
5422 /* ot is the size of source */
5423 ot
= (b
& 1) + MO_8
;
5424 /* s_ot is the sign+size of source */
5425 s_ot
= b
& 8 ? MO_SIGN
| ot
: ot
;
5427 modrm
= cpu_ldub_code(env
, s
->pc
++);
5428 reg
= ((modrm
>> 3) & 7) | rex_r
;
5429 mod
= (modrm
>> 6) & 3;
5430 rm
= (modrm
& 7) | REX_B(s
);
5433 gen_op_mov_TN_reg(ot
, 0, rm
);
5436 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5439 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5442 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5446 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5449 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
5451 gen_lea_modrm(env
, s
, modrm
);
5452 gen_op_ld_v(s
, s_ot
, cpu_T
[0], cpu_A0
);
5453 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
5458 case 0x8d: /* lea */
5460 modrm
= cpu_ldub_code(env
, s
->pc
++);
5461 mod
= (modrm
>> 6) & 3;
5464 reg
= ((modrm
>> 3) & 7) | rex_r
;
5465 /* we must ensure that no segment is added */
5469 gen_lea_modrm(env
, s
, modrm
);
5471 gen_op_mov_reg_A0(ot
, reg
);
5474 case 0xa0: /* mov EAX, Ov */
5476 case 0xa2: /* mov Ov, EAX */
5479 target_ulong offset_addr
;
5481 ot
= mo_b_d(b
, dflag
);
5483 #ifdef TARGET_X86_64
5485 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5490 offset_addr
= insn_get(env
, s
, s
->aflag
);
5493 tcg_gen_movi_tl(cpu_A0
, offset_addr
);
5494 gen_add_A0_ds_seg(s
);
5496 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5497 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[0]);
5499 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5500 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5504 case 0xd7: /* xlat */
5505 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EBX
]);
5506 tcg_gen_ext8u_tl(cpu_T
[0], cpu_regs
[R_EAX
]);
5507 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5508 gen_extu(s
->aflag
, cpu_A0
);
5509 gen_add_A0_ds_seg(s
);
5510 gen_op_ld_v(s
, MO_8
, cpu_T
[0], cpu_A0
);
5511 gen_op_mov_reg_v(MO_8
, R_EAX
, cpu_T
[0]);
5513 case 0xb0 ... 0xb7: /* mov R, Ib */
5514 val
= insn_get(env
, s
, MO_8
);
5515 tcg_gen_movi_tl(cpu_T
[0], val
);
5516 gen_op_mov_reg_v(MO_8
, (b
& 7) | REX_B(s
), cpu_T
[0]);
5518 case 0xb8 ... 0xbf: /* mov R, Iv */
5519 #ifdef TARGET_X86_64
5520 if (dflag
== MO_64
) {
5523 tmp
= cpu_ldq_code(env
, s
->pc
);
5525 reg
= (b
& 7) | REX_B(s
);
5526 tcg_gen_movi_tl(cpu_T
[0], tmp
);
5527 gen_op_mov_reg_v(MO_64
, reg
, cpu_T
[0]);
5532 val
= insn_get(env
, s
, ot
);
5533 reg
= (b
& 7) | REX_B(s
);
5534 tcg_gen_movi_tl(cpu_T
[0], val
);
5535 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5539 case 0x91 ... 0x97: /* xchg R, EAX */
5542 reg
= (b
& 7) | REX_B(s
);
5546 case 0x87: /* xchg Ev, Gv */
5547 ot
= mo_b_d(b
, dflag
);
5548 modrm
= cpu_ldub_code(env
, s
->pc
++);
5549 reg
= ((modrm
>> 3) & 7) | rex_r
;
5550 mod
= (modrm
>> 6) & 3;
5552 rm
= (modrm
& 7) | REX_B(s
);
5554 gen_op_mov_TN_reg(ot
, 0, reg
);
5555 gen_op_mov_TN_reg(ot
, 1, rm
);
5556 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5557 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5559 gen_lea_modrm(env
, s
, modrm
);
5560 gen_op_mov_TN_reg(ot
, 0, reg
);
5561 /* for xchg, lock is implicit */
5562 if (!(prefixes
& PREFIX_LOCK
))
5564 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5565 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5566 if (!(prefixes
& PREFIX_LOCK
))
5567 gen_helper_unlock();
5568 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5571 case 0xc4: /* les Gv */
5572 /* In CODE64 this is VEX3; see above. */
5575 case 0xc5: /* lds Gv */
5576 /* In CODE64 this is VEX2; see above. */
5579 case 0x1b2: /* lss Gv */
5582 case 0x1b4: /* lfs Gv */
5585 case 0x1b5: /* lgs Gv */
5588 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
5589 modrm
= cpu_ldub_code(env
, s
->pc
++);
5590 reg
= ((modrm
>> 3) & 7) | rex_r
;
5591 mod
= (modrm
>> 6) & 3;
5594 gen_lea_modrm(env
, s
, modrm
);
5595 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5596 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5597 /* load the segment first to handle exceptions properly */
5598 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5599 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5600 /* then put the data */
5601 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5603 gen_jmp_im(s
->pc
- s
->cs_base
);
5608 /************************/
5616 ot
= mo_b_d(b
, dflag
);
5617 modrm
= cpu_ldub_code(env
, s
->pc
++);
5618 mod
= (modrm
>> 6) & 3;
5619 op
= (modrm
>> 3) & 7;
5625 gen_lea_modrm(env
, s
, modrm
);
5628 opreg
= (modrm
& 7) | REX_B(s
);
5633 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5636 shift
= cpu_ldub_code(env
, s
->pc
++);
5638 gen_shifti(s
, op
, ot
, opreg
, shift
);
5653 case 0x1a4: /* shld imm */
5657 case 0x1a5: /* shld cl */
5661 case 0x1ac: /* shrd imm */
5665 case 0x1ad: /* shrd cl */
5670 modrm
= cpu_ldub_code(env
, s
->pc
++);
5671 mod
= (modrm
>> 6) & 3;
5672 rm
= (modrm
& 7) | REX_B(s
);
5673 reg
= ((modrm
>> 3) & 7) | rex_r
;
5675 gen_lea_modrm(env
, s
, modrm
);
5680 gen_op_mov_TN_reg(ot
, 1, reg
);
5683 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5684 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5687 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5691 /************************/
5694 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5695 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5696 /* XXX: what to do if illegal op ? */
5697 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5700 modrm
= cpu_ldub_code(env
, s
->pc
++);
5701 mod
= (modrm
>> 6) & 3;
5703 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5706 gen_lea_modrm(env
, s
, modrm
);
5708 case 0x00 ... 0x07: /* fxxxs */
5709 case 0x10 ... 0x17: /* fixxxl */
5710 case 0x20 ... 0x27: /* fxxxl */
5711 case 0x30 ... 0x37: /* fixxx */
5718 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5719 s
->mem_index
, MO_LEUL
);
5720 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5723 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5724 s
->mem_index
, MO_LEUL
);
5725 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5728 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5729 s
->mem_index
, MO_LEQ
);
5730 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5734 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5735 s
->mem_index
, MO_LESW
);
5736 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5740 gen_helper_fp_arith_ST0_FT0(op1
);
5742 /* fcomp needs pop */
5743 gen_helper_fpop(cpu_env
);
5747 case 0x08: /* flds */
5748 case 0x0a: /* fsts */
5749 case 0x0b: /* fstps */
5750 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5751 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5752 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5757 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5758 s
->mem_index
, MO_LEUL
);
5759 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5762 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5763 s
->mem_index
, MO_LEUL
);
5764 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5767 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5768 s
->mem_index
, MO_LEQ
);
5769 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5773 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5774 s
->mem_index
, MO_LESW
);
5775 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5780 /* XXX: the corresponding CPUID bit must be tested ! */
5783 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5784 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5785 s
->mem_index
, MO_LEUL
);
5788 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5789 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5790 s
->mem_index
, MO_LEQ
);
5794 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5795 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5796 s
->mem_index
, MO_LEUW
);
5799 gen_helper_fpop(cpu_env
);
5804 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5805 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5806 s
->mem_index
, MO_LEUL
);
5809 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5810 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5811 s
->mem_index
, MO_LEUL
);
5814 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5815 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5816 s
->mem_index
, MO_LEQ
);
5820 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5821 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5822 s
->mem_index
, MO_LEUW
);
5826 gen_helper_fpop(cpu_env
);
5830 case 0x0c: /* fldenv mem */
5831 gen_update_cc_op(s
);
5832 gen_jmp_im(pc_start
- s
->cs_base
);
5833 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5835 case 0x0d: /* fldcw mem */
5836 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5837 s
->mem_index
, MO_LEUW
);
5838 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5840 case 0x0e: /* fnstenv mem */
5841 gen_update_cc_op(s
);
5842 gen_jmp_im(pc_start
- s
->cs_base
);
5843 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5845 case 0x0f: /* fnstcw mem */
5846 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5847 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5848 s
->mem_index
, MO_LEUW
);
5850 case 0x1d: /* fldt mem */
5851 gen_update_cc_op(s
);
5852 gen_jmp_im(pc_start
- s
->cs_base
);
5853 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5855 case 0x1f: /* fstpt mem */
5856 gen_update_cc_op(s
);
5857 gen_jmp_im(pc_start
- s
->cs_base
);
5858 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5859 gen_helper_fpop(cpu_env
);
5861 case 0x2c: /* frstor mem */
5862 gen_update_cc_op(s
);
5863 gen_jmp_im(pc_start
- s
->cs_base
);
5864 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5866 case 0x2e: /* fnsave mem */
5867 gen_update_cc_op(s
);
5868 gen_jmp_im(pc_start
- s
->cs_base
);
5869 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5871 case 0x2f: /* fnstsw mem */
5872 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5873 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5874 s
->mem_index
, MO_LEUW
);
5876 case 0x3c: /* fbld */
5877 gen_update_cc_op(s
);
5878 gen_jmp_im(pc_start
- s
->cs_base
);
5879 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5881 case 0x3e: /* fbstp */
5882 gen_update_cc_op(s
);
5883 gen_jmp_im(pc_start
- s
->cs_base
);
5884 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5885 gen_helper_fpop(cpu_env
);
5887 case 0x3d: /* fildll */
5888 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5889 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5891 case 0x3f: /* fistpll */
5892 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5893 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5894 gen_helper_fpop(cpu_env
);
5900 /* register float ops */
5904 case 0x08: /* fld sti */
5905 gen_helper_fpush(cpu_env
);
5906 gen_helper_fmov_ST0_STN(cpu_env
,
5907 tcg_const_i32((opreg
+ 1) & 7));
5909 case 0x09: /* fxchg sti */
5910 case 0x29: /* fxchg4 sti, undocumented op */
5911 case 0x39: /* fxchg7 sti, undocumented op */
5912 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5914 case 0x0a: /* grp d9/2 */
5917 /* check exceptions (FreeBSD FPU probe) */
5918 gen_update_cc_op(s
);
5919 gen_jmp_im(pc_start
- s
->cs_base
);
5920 gen_helper_fwait(cpu_env
);
5926 case 0x0c: /* grp d9/4 */
5929 gen_helper_fchs_ST0(cpu_env
);
5932 gen_helper_fabs_ST0(cpu_env
);
5935 gen_helper_fldz_FT0(cpu_env
);
5936 gen_helper_fcom_ST0_FT0(cpu_env
);
5939 gen_helper_fxam_ST0(cpu_env
);
5945 case 0x0d: /* grp d9/5 */
5949 gen_helper_fpush(cpu_env
);
5950 gen_helper_fld1_ST0(cpu_env
);
5953 gen_helper_fpush(cpu_env
);
5954 gen_helper_fldl2t_ST0(cpu_env
);
5957 gen_helper_fpush(cpu_env
);
5958 gen_helper_fldl2e_ST0(cpu_env
);
5961 gen_helper_fpush(cpu_env
);
5962 gen_helper_fldpi_ST0(cpu_env
);
5965 gen_helper_fpush(cpu_env
);
5966 gen_helper_fldlg2_ST0(cpu_env
);
5969 gen_helper_fpush(cpu_env
);
5970 gen_helper_fldln2_ST0(cpu_env
);
5973 gen_helper_fpush(cpu_env
);
5974 gen_helper_fldz_ST0(cpu_env
);
5981 case 0x0e: /* grp d9/6 */
5984 gen_helper_f2xm1(cpu_env
);
5987 gen_helper_fyl2x(cpu_env
);
5990 gen_helper_fptan(cpu_env
);
5992 case 3: /* fpatan */
5993 gen_helper_fpatan(cpu_env
);
5995 case 4: /* fxtract */
5996 gen_helper_fxtract(cpu_env
);
5998 case 5: /* fprem1 */
5999 gen_helper_fprem1(cpu_env
);
6001 case 6: /* fdecstp */
6002 gen_helper_fdecstp(cpu_env
);
6005 case 7: /* fincstp */
6006 gen_helper_fincstp(cpu_env
);
6010 case 0x0f: /* grp d9/7 */
6013 gen_helper_fprem(cpu_env
);
6015 case 1: /* fyl2xp1 */
6016 gen_helper_fyl2xp1(cpu_env
);
6019 gen_helper_fsqrt(cpu_env
);
6021 case 3: /* fsincos */
6022 gen_helper_fsincos(cpu_env
);
6024 case 5: /* fscale */
6025 gen_helper_fscale(cpu_env
);
6027 case 4: /* frndint */
6028 gen_helper_frndint(cpu_env
);
6031 gen_helper_fsin(cpu_env
);
6035 gen_helper_fcos(cpu_env
);
6039 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6040 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6041 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6047 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6049 gen_helper_fpop(cpu_env
);
6051 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6052 gen_helper_fp_arith_ST0_FT0(op1
);
6056 case 0x02: /* fcom */
6057 case 0x22: /* fcom2, undocumented op */
6058 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6059 gen_helper_fcom_ST0_FT0(cpu_env
);
6061 case 0x03: /* fcomp */
6062 case 0x23: /* fcomp3, undocumented op */
6063 case 0x32: /* fcomp5, undocumented op */
6064 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6065 gen_helper_fcom_ST0_FT0(cpu_env
);
6066 gen_helper_fpop(cpu_env
);
6068 case 0x15: /* da/5 */
6070 case 1: /* fucompp */
6071 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6072 gen_helper_fucom_ST0_FT0(cpu_env
);
6073 gen_helper_fpop(cpu_env
);
6074 gen_helper_fpop(cpu_env
);
6082 case 0: /* feni (287 only, just do nop here) */
6084 case 1: /* fdisi (287 only, just do nop here) */
6087 gen_helper_fclex(cpu_env
);
6089 case 3: /* fninit */
6090 gen_helper_fninit(cpu_env
);
6092 case 4: /* fsetpm (287 only, just do nop here) */
6098 case 0x1d: /* fucomi */
6099 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6102 gen_update_cc_op(s
);
6103 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6104 gen_helper_fucomi_ST0_FT0(cpu_env
);
6105 set_cc_op(s
, CC_OP_EFLAGS
);
6107 case 0x1e: /* fcomi */
6108 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6111 gen_update_cc_op(s
);
6112 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6113 gen_helper_fcomi_ST0_FT0(cpu_env
);
6114 set_cc_op(s
, CC_OP_EFLAGS
);
6116 case 0x28: /* ffree sti */
6117 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6119 case 0x2a: /* fst sti */
6120 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6122 case 0x2b: /* fstp sti */
6123 case 0x0b: /* fstp1 sti, undocumented op */
6124 case 0x3a: /* fstp8 sti, undocumented op */
6125 case 0x3b: /* fstp9 sti, undocumented op */
6126 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6127 gen_helper_fpop(cpu_env
);
6129 case 0x2c: /* fucom st(i) */
6130 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6131 gen_helper_fucom_ST0_FT0(cpu_env
);
6133 case 0x2d: /* fucomp st(i) */
6134 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6135 gen_helper_fucom_ST0_FT0(cpu_env
);
6136 gen_helper_fpop(cpu_env
);
6138 case 0x33: /* de/3 */
6140 case 1: /* fcompp */
6141 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6142 gen_helper_fcom_ST0_FT0(cpu_env
);
6143 gen_helper_fpop(cpu_env
);
6144 gen_helper_fpop(cpu_env
);
6150 case 0x38: /* ffreep sti, undocumented op */
6151 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6152 gen_helper_fpop(cpu_env
);
6154 case 0x3c: /* df/4 */
6157 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6158 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6159 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
6165 case 0x3d: /* fucomip */
6166 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6169 gen_update_cc_op(s
);
6170 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6171 gen_helper_fucomi_ST0_FT0(cpu_env
);
6172 gen_helper_fpop(cpu_env
);
6173 set_cc_op(s
, CC_OP_EFLAGS
);
6175 case 0x3e: /* fcomip */
6176 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6179 gen_update_cc_op(s
);
6180 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6181 gen_helper_fcomi_ST0_FT0(cpu_env
);
6182 gen_helper_fpop(cpu_env
);
6183 set_cc_op(s
, CC_OP_EFLAGS
);
6185 case 0x10 ... 0x13: /* fcmovxx */
6189 static const uint8_t fcmov_cc
[8] = {
6196 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6199 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6200 l1
= gen_new_label();
6201 gen_jcc1_noeob(s
, op1
, l1
);
6202 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6211 /************************/
6214 case 0xa4: /* movsS */
6216 ot
= mo_b_d(b
, dflag
);
6217 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6218 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6224 case 0xaa: /* stosS */
6226 ot
= mo_b_d(b
, dflag
);
6227 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6228 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6233 case 0xac: /* lodsS */
6235 ot
= mo_b_d(b
, dflag
);
6236 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6237 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6242 case 0xae: /* scasS */
6244 ot
= mo_b_d(b
, dflag
);
6245 if (prefixes
& PREFIX_REPNZ
) {
6246 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6247 } else if (prefixes
& PREFIX_REPZ
) {
6248 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6254 case 0xa6: /* cmpsS */
6256 ot
= mo_b_d(b
, dflag
);
6257 if (prefixes
& PREFIX_REPNZ
) {
6258 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6259 } else if (prefixes
& PREFIX_REPZ
) {
6260 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6265 case 0x6c: /* insS */
6267 ot
= mo_b_d32(b
, dflag
);
6268 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6269 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6270 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6271 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6272 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6276 gen_jmp(s
, s
->pc
- s
->cs_base
);
6280 case 0x6e: /* outsS */
6282 ot
= mo_b_d32(b
, dflag
);
6283 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6284 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6285 svm_is_rep(prefixes
) | 4);
6286 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6287 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6291 gen_jmp(s
, s
->pc
- s
->cs_base
);
6296 /************************/
6301 ot
= mo_b_d32(b
, dflag
);
6302 val
= cpu_ldub_code(env
, s
->pc
++);
6303 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6304 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6307 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6308 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6309 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[1]);
6312 gen_jmp(s
, s
->pc
- s
->cs_base
);
6317 ot
= mo_b_d32(b
, dflag
);
6318 val
= cpu_ldub_code(env
, s
->pc
++);
6319 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6320 svm_is_rep(prefixes
));
6321 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6325 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6326 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6327 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6330 gen_jmp(s
, s
->pc
- s
->cs_base
);
6335 ot
= mo_b_d32(b
, dflag
);
6336 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6337 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6338 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6341 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6342 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6343 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[1]);
6346 gen_jmp(s
, s
->pc
- s
->cs_base
);
6351 ot
= mo_b_d32(b
, dflag
);
6352 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6353 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6354 svm_is_rep(prefixes
));
6355 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6359 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6360 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6361 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6364 gen_jmp(s
, s
->pc
- s
->cs_base
);
6368 /************************/
6370 case 0xc2: /* ret im */
6371 val
= cpu_ldsw_code(env
, s
->pc
);
6374 gen_stack_update(s
, val
+ (1 << ot
));
6375 /* Note that gen_pop_T0 uses a zero-extending load. */
6379 case 0xc3: /* ret */
6381 gen_pop_update(s
, ot
);
6382 /* Note that gen_pop_T0 uses a zero-extending load. */
6386 case 0xca: /* lret im */
6387 val
= cpu_ldsw_code(env
, s
->pc
);
6390 if (s
->pe
&& !s
->vm86
) {
6391 gen_update_cc_op(s
);
6392 gen_jmp_im(pc_start
- s
->cs_base
);
6393 gen_helper_lret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6394 tcg_const_i32(val
));
6398 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6399 /* NOTE: keeping EIP updated is not a problem in case of
6403 gen_op_addl_A0_im(1 << dflag
);
6404 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6405 gen_op_movl_seg_T0_vm(R_CS
);
6406 /* add stack offset */
6407 gen_stack_update(s
, val
+ (2 << dflag
));
6411 case 0xcb: /* lret */
6414 case 0xcf: /* iret */
6415 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6418 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6419 set_cc_op(s
, CC_OP_EFLAGS
);
6420 } else if (s
->vm86
) {
6422 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6424 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6425 set_cc_op(s
, CC_OP_EFLAGS
);
6428 gen_update_cc_op(s
);
6429 gen_jmp_im(pc_start
- s
->cs_base
);
6430 gen_helper_iret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6431 tcg_const_i32(s
->pc
- s
->cs_base
));
6432 set_cc_op(s
, CC_OP_EFLAGS
);
6436 case 0xe8: /* call im */
6438 if (dflag
!= MO_16
) {
6439 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6441 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6443 next_eip
= s
->pc
- s
->cs_base
;
6445 if (dflag
== MO_16
) {
6447 } else if (!CODE64(s
)) {
6450 tcg_gen_movi_tl(cpu_T
[0], next_eip
);
6451 gen_push_v(s
, cpu_T
[0]);
6455 case 0x9a: /* lcall im */
6457 unsigned int selector
, offset
;
6462 offset
= insn_get(env
, s
, ot
);
6463 selector
= insn_get(env
, s
, MO_16
);
6465 tcg_gen_movi_tl(cpu_T
[0], selector
);
6466 tcg_gen_movi_tl(cpu_T
[1], offset
);
6469 case 0xe9: /* jmp im */
6470 if (dflag
!= MO_16
) {
6471 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6473 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6475 tval
+= s
->pc
- s
->cs_base
;
6476 if (dflag
== MO_16
) {
6478 } else if (!CODE64(s
)) {
6483 case 0xea: /* ljmp im */
6485 unsigned int selector
, offset
;
6490 offset
= insn_get(env
, s
, ot
);
6491 selector
= insn_get(env
, s
, MO_16
);
6493 tcg_gen_movi_tl(cpu_T
[0], selector
);
6494 tcg_gen_movi_tl(cpu_T
[1], offset
);
6497 case 0xeb: /* jmp Jb */
6498 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6499 tval
+= s
->pc
- s
->cs_base
;
6500 if (dflag
== MO_16
) {
6505 case 0x70 ... 0x7f: /* jcc Jb */
6506 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6508 case 0x180 ... 0x18f: /* jcc Jv */
6509 if (dflag
!= MO_16
) {
6510 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6512 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6515 next_eip
= s
->pc
- s
->cs_base
;
6517 if (dflag
== MO_16
) {
6520 gen_jcc(s
, b
, tval
, next_eip
);
6523 case 0x190 ... 0x19f: /* setcc Gv */
6524 modrm
= cpu_ldub_code(env
, s
->pc
++);
6525 gen_setcc1(s
, b
, cpu_T
[0]);
6526 gen_ldst_modrm(env
, s
, modrm
, MO_8
, OR_TMP0
, 1);
6528 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6529 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6533 modrm
= cpu_ldub_code(env
, s
->pc
++);
6534 reg
= ((modrm
>> 3) & 7) | rex_r
;
6535 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6538 /************************/
6540 case 0x9c: /* pushf */
6541 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6542 if (s
->vm86
&& s
->iopl
!= 3) {
6543 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6545 gen_update_cc_op(s
);
6546 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6547 gen_push_v(s
, cpu_T
[0]);
6550 case 0x9d: /* popf */
6551 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6552 if (s
->vm86
&& s
->iopl
!= 3) {
6553 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6557 if (dflag
!= MO_16
) {
6558 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6559 tcg_const_i32((TF_MASK
| AC_MASK
|
6564 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6565 tcg_const_i32((TF_MASK
| AC_MASK
|
6567 IF_MASK
| IOPL_MASK
)
6571 if (s
->cpl
<= s
->iopl
) {
6572 if (dflag
!= MO_16
) {
6573 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6574 tcg_const_i32((TF_MASK
|
6580 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6581 tcg_const_i32((TF_MASK
|
6589 if (dflag
!= MO_16
) {
6590 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6591 tcg_const_i32((TF_MASK
| AC_MASK
|
6592 ID_MASK
| NT_MASK
)));
6594 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6595 tcg_const_i32((TF_MASK
| AC_MASK
|
6601 gen_pop_update(s
, ot
);
6602 set_cc_op(s
, CC_OP_EFLAGS
);
6603 /* abort translation because TF/AC flag may change */
6604 gen_jmp_im(s
->pc
- s
->cs_base
);
6608 case 0x9e: /* sahf */
6609 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6611 gen_op_mov_TN_reg(MO_8
, 0, R_AH
);
6612 gen_compute_eflags(s
);
6613 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6614 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6615 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6617 case 0x9f: /* lahf */
6618 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6620 gen_compute_eflags(s
);
6621 /* Note: gen_compute_eflags() only gives the condition codes */
6622 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6623 gen_op_mov_reg_v(MO_8
, R_AH
, cpu_T
[0]);
6625 case 0xf5: /* cmc */
6626 gen_compute_eflags(s
);
6627 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6629 case 0xf8: /* clc */
6630 gen_compute_eflags(s
);
6631 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6633 case 0xf9: /* stc */
6634 gen_compute_eflags(s
);
6635 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6637 case 0xfc: /* cld */
6638 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6639 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6641 case 0xfd: /* std */
6642 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6643 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6646 /************************/
6647 /* bit operations */
6648 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6650 modrm
= cpu_ldub_code(env
, s
->pc
++);
6651 op
= (modrm
>> 3) & 7;
6652 mod
= (modrm
>> 6) & 3;
6653 rm
= (modrm
& 7) | REX_B(s
);
6656 gen_lea_modrm(env
, s
, modrm
);
6657 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6659 gen_op_mov_TN_reg(ot
, 0, rm
);
6662 val
= cpu_ldub_code(env
, s
->pc
++);
6663 tcg_gen_movi_tl(cpu_T
[1], val
);
6668 case 0x1a3: /* bt Gv, Ev */
6671 case 0x1ab: /* bts */
6674 case 0x1b3: /* btr */
6677 case 0x1bb: /* btc */
6681 modrm
= cpu_ldub_code(env
, s
->pc
++);
6682 reg
= ((modrm
>> 3) & 7) | rex_r
;
6683 mod
= (modrm
>> 6) & 3;
6684 rm
= (modrm
& 7) | REX_B(s
);
6685 gen_op_mov_TN_reg(MO_32
, 1, reg
);
6687 gen_lea_modrm(env
, s
, modrm
);
6688 /* specific case: we need to add a displacement */
6689 gen_exts(ot
, cpu_T
[1]);
6690 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6691 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6692 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6693 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6695 gen_op_mov_TN_reg(ot
, 0, rm
);
6698 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6701 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6702 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6705 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6706 tcg_gen_movi_tl(cpu_tmp0
, 1);
6707 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6708 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6711 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6712 tcg_gen_movi_tl(cpu_tmp0
, 1);
6713 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6714 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6715 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6719 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6720 tcg_gen_movi_tl(cpu_tmp0
, 1);
6721 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6722 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6725 set_cc_op(s
, CC_OP_SARB
+ ot
);
6728 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
6730 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
6732 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6733 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6736 case 0x1bc: /* bsf / tzcnt */
6737 case 0x1bd: /* bsr / lzcnt */
6739 modrm
= cpu_ldub_code(env
, s
->pc
++);
6740 reg
= ((modrm
>> 3) & 7) | rex_r
;
6741 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
6742 gen_extu(ot
, cpu_T
[0]);
6744 /* Note that lzcnt and tzcnt are in different extensions. */
6745 if ((prefixes
& PREFIX_REPZ
)
6747 ? s
->cpuid_ext3_features
& CPUID_EXT3_ABM
6748 : s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)) {
6750 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
6752 /* For lzcnt, reduce the target_ulong result by the
6753 number of zeros that we expect to find at the top. */
6754 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6755 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- size
);
6757 /* For tzcnt, a zero input must return the operand size:
6758 force all bits outside the operand size to 1. */
6759 target_ulong mask
= (target_ulong
)-2 << (size
- 1);
6760 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], mask
);
6761 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6763 /* For lzcnt/tzcnt, C and Z bits are defined and are
6764 related to the result. */
6765 gen_op_update1_cc();
6766 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
6768 /* For bsr/bsf, only the Z bit is defined and it is related
6769 to the input and not the result. */
6770 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
6771 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6773 /* For bsr, return the bit index of the first 1 bit,
6774 not the count of leading zeros. */
6775 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6776 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- 1);
6778 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6780 /* ??? The manual says that the output is undefined when the
6781 input is zero, but real hardware leaves it unchanged, and
6782 real programs appear to depend on that. */
6783 tcg_gen_movi_tl(cpu_tmp0
, 0);
6784 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[0], cpu_cc_dst
, cpu_tmp0
,
6785 cpu_regs
[reg
], cpu_T
[0]);
6787 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
6789 /************************/
6791 case 0x27: /* daa */
6794 gen_update_cc_op(s
);
6795 gen_helper_daa(cpu_env
);
6796 set_cc_op(s
, CC_OP_EFLAGS
);
6798 case 0x2f: /* das */
6801 gen_update_cc_op(s
);
6802 gen_helper_das(cpu_env
);
6803 set_cc_op(s
, CC_OP_EFLAGS
);
6805 case 0x37: /* aaa */
6808 gen_update_cc_op(s
);
6809 gen_helper_aaa(cpu_env
);
6810 set_cc_op(s
, CC_OP_EFLAGS
);
6812 case 0x3f: /* aas */
6815 gen_update_cc_op(s
);
6816 gen_helper_aas(cpu_env
);
6817 set_cc_op(s
, CC_OP_EFLAGS
);
6819 case 0xd4: /* aam */
6822 val
= cpu_ldub_code(env
, s
->pc
++);
6824 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6826 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6827 set_cc_op(s
, CC_OP_LOGICB
);
6830 case 0xd5: /* aad */
6833 val
= cpu_ldub_code(env
, s
->pc
++);
6834 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6835 set_cc_op(s
, CC_OP_LOGICB
);
6837 /************************/
6839 case 0x90: /* nop */
6840 /* XXX: correct lock test for all insn */
6841 if (prefixes
& PREFIX_LOCK
) {
6844 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6846 goto do_xchg_reg_eax
;
6848 if (prefixes
& PREFIX_REPZ
) {
6849 gen_update_cc_op(s
);
6850 gen_jmp_im(pc_start
- s
->cs_base
);
6851 gen_helper_pause(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6852 s
->is_jmp
= DISAS_TB_JUMP
;
6855 case 0x9b: /* fwait */
6856 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6857 (HF_MP_MASK
| HF_TS_MASK
)) {
6858 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6860 gen_update_cc_op(s
);
6861 gen_jmp_im(pc_start
- s
->cs_base
);
6862 gen_helper_fwait(cpu_env
);
6865 case 0xcc: /* int3 */
6866 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6868 case 0xcd: /* int N */
6869 val
= cpu_ldub_code(env
, s
->pc
++);
6870 if (s
->vm86
&& s
->iopl
!= 3) {
6871 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6873 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6876 case 0xce: /* into */
6879 gen_update_cc_op(s
);
6880 gen_jmp_im(pc_start
- s
->cs_base
);
6881 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6884 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6885 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6887 gen_debug(s
, pc_start
- s
->cs_base
);
6891 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6895 case 0xfa: /* cli */
6897 if (s
->cpl
<= s
->iopl
) {
6898 gen_helper_cli(cpu_env
);
6900 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6904 gen_helper_cli(cpu_env
);
6906 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6910 case 0xfb: /* sti */
6912 if (s
->cpl
<= s
->iopl
) {
6914 gen_helper_sti(cpu_env
);
6915 /* interruptions are enabled only the first insn after sti */
6916 /* If several instructions disable interrupts, only the
6918 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6919 gen_helper_set_inhibit_irq(cpu_env
);
6920 /* give a chance to handle pending irqs */
6921 gen_jmp_im(s
->pc
- s
->cs_base
);
6924 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6930 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6934 case 0x62: /* bound */
6938 modrm
= cpu_ldub_code(env
, s
->pc
++);
6939 reg
= (modrm
>> 3) & 7;
6940 mod
= (modrm
>> 6) & 3;
6943 gen_op_mov_TN_reg(ot
, 0, reg
);
6944 gen_lea_modrm(env
, s
, modrm
);
6945 gen_jmp_im(pc_start
- s
->cs_base
);
6946 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6948 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6950 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6953 case 0x1c8 ... 0x1cf: /* bswap reg */
6954 reg
= (b
& 7) | REX_B(s
);
6955 #ifdef TARGET_X86_64
6956 if (dflag
== MO_64
) {
6957 gen_op_mov_TN_reg(MO_64
, 0, reg
);
6958 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6959 gen_op_mov_reg_v(MO_64
, reg
, cpu_T
[0]);
6963 gen_op_mov_TN_reg(MO_32
, 0, reg
);
6964 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6965 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6966 gen_op_mov_reg_v(MO_32
, reg
, cpu_T
[0]);
6969 case 0xd6: /* salc */
6972 gen_compute_eflags_c(s
, cpu_T
[0]);
6973 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6974 gen_op_mov_reg_v(MO_8
, R_EAX
, cpu_T
[0]);
6976 case 0xe0: /* loopnz */
6977 case 0xe1: /* loopz */
6978 case 0xe2: /* loop */
6979 case 0xe3: /* jecxz */
6983 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6984 next_eip
= s
->pc
- s
->cs_base
;
6986 if (dflag
== MO_16
) {
6990 l1
= gen_new_label();
6991 l2
= gen_new_label();
6992 l3
= gen_new_label();
6995 case 0: /* loopnz */
6997 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6998 gen_op_jz_ecx(s
->aflag
, l3
);
6999 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7002 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7003 gen_op_jnz_ecx(s
->aflag
, l1
);
7007 gen_op_jz_ecx(s
->aflag
, l1
);
7012 gen_jmp_im(next_eip
);
7021 case 0x130: /* wrmsr */
7022 case 0x132: /* rdmsr */
7024 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7026 gen_update_cc_op(s
);
7027 gen_jmp_im(pc_start
- s
->cs_base
);
7029 gen_helper_rdmsr(cpu_env
);
7031 gen_helper_wrmsr(cpu_env
);
7035 case 0x131: /* rdtsc */
7036 gen_update_cc_op(s
);
7037 gen_jmp_im(pc_start
- s
->cs_base
);
7040 gen_helper_rdtsc(cpu_env
);
7043 gen_jmp(s
, s
->pc
- s
->cs_base
);
7046 case 0x133: /* rdpmc */
7047 gen_update_cc_op(s
);
7048 gen_jmp_im(pc_start
- s
->cs_base
);
7049 gen_helper_rdpmc(cpu_env
);
7051 case 0x134: /* sysenter */
7052 /* For Intel SYSENTER is valid on 64-bit */
7053 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7056 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7058 gen_update_cc_op(s
);
7059 gen_jmp_im(pc_start
- s
->cs_base
);
7060 gen_helper_sysenter(cpu_env
);
7064 case 0x135: /* sysexit */
7065 /* For Intel SYSEXIT is valid on 64-bit */
7066 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7069 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7071 gen_update_cc_op(s
);
7072 gen_jmp_im(pc_start
- s
->cs_base
);
7073 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
- 1));
7077 #ifdef TARGET_X86_64
7078 case 0x105: /* syscall */
7079 /* XXX: is it usable in real mode ? */
7080 gen_update_cc_op(s
);
7081 gen_jmp_im(pc_start
- s
->cs_base
);
7082 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7085 case 0x107: /* sysret */
7087 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7089 gen_update_cc_op(s
);
7090 gen_jmp_im(pc_start
- s
->cs_base
);
7091 gen_helper_sysret(cpu_env
, tcg_const_i32(dflag
- 1));
7092 /* condition codes are modified only in long mode */
7094 set_cc_op(s
, CC_OP_EFLAGS
);
7100 case 0x1a2: /* cpuid */
7101 gen_update_cc_op(s
);
7102 gen_jmp_im(pc_start
- s
->cs_base
);
7103 gen_helper_cpuid(cpu_env
);
7105 case 0xf4: /* hlt */
7107 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7109 gen_update_cc_op(s
);
7110 gen_jmp_im(pc_start
- s
->cs_base
);
7111 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7112 s
->is_jmp
= DISAS_TB_JUMP
;
7116 modrm
= cpu_ldub_code(env
, s
->pc
++);
7117 mod
= (modrm
>> 6) & 3;
7118 op
= (modrm
>> 3) & 7;
7121 if (!s
->pe
|| s
->vm86
)
7123 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7124 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7125 ot
= mod
== 3 ? dflag
: MO_16
;
7126 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7129 if (!s
->pe
|| s
->vm86
)
7132 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7134 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7135 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7136 gen_jmp_im(pc_start
- s
->cs_base
);
7137 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7138 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7142 if (!s
->pe
|| s
->vm86
)
7144 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7145 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7146 ot
= mod
== 3 ? dflag
: MO_16
;
7147 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7150 if (!s
->pe
|| s
->vm86
)
7153 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7155 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7156 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7157 gen_jmp_im(pc_start
- s
->cs_base
);
7158 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7159 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7164 if (!s
->pe
|| s
->vm86
)
7166 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7167 gen_update_cc_op(s
);
7169 gen_helper_verr(cpu_env
, cpu_T
[0]);
7171 gen_helper_verw(cpu_env
, cpu_T
[0]);
7173 set_cc_op(s
, CC_OP_EFLAGS
);
7180 modrm
= cpu_ldub_code(env
, s
->pc
++);
7181 mod
= (modrm
>> 6) & 3;
7182 op
= (modrm
>> 3) & 7;
7188 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7189 gen_lea_modrm(env
, s
, modrm
);
7190 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7191 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7192 gen_add_A0_im(s
, 2);
7193 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7194 if (dflag
== MO_16
) {
7195 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7197 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7202 case 0: /* monitor */
7203 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7206 gen_update_cc_op(s
);
7207 gen_jmp_im(pc_start
- s
->cs_base
);
7208 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EAX
]);
7209 gen_extu(s
->aflag
, cpu_A0
);
7210 gen_add_A0_ds_seg(s
);
7211 gen_helper_monitor(cpu_env
, cpu_A0
);
7214 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7217 gen_update_cc_op(s
);
7218 gen_jmp_im(pc_start
- s
->cs_base
);
7219 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7223 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7227 gen_helper_clac(cpu_env
);
7228 gen_jmp_im(s
->pc
- s
->cs_base
);
7232 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7236 gen_helper_stac(cpu_env
);
7237 gen_jmp_im(s
->pc
- s
->cs_base
);
7244 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7245 gen_lea_modrm(env
, s
, modrm
);
7246 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7247 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7248 gen_add_A0_im(s
, 2);
7249 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7250 if (dflag
== MO_16
) {
7251 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7253 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7259 gen_update_cc_op(s
);
7260 gen_jmp_im(pc_start
- s
->cs_base
);
7263 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7266 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7269 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
- 1),
7270 tcg_const_i32(s
->pc
- pc_start
));
7272 s
->is_jmp
= DISAS_TB_JUMP
;
7275 case 1: /* VMMCALL */
7276 if (!(s
->flags
& HF_SVME_MASK
))
7278 gen_helper_vmmcall(cpu_env
);
7280 case 2: /* VMLOAD */
7281 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7284 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7287 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7290 case 3: /* VMSAVE */
7291 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7294 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7297 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7301 if ((!(s
->flags
& HF_SVME_MASK
) &&
7302 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7306 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7309 gen_helper_stgi(cpu_env
);
7313 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7316 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7319 gen_helper_clgi(cpu_env
);
7322 case 6: /* SKINIT */
7323 if ((!(s
->flags
& HF_SVME_MASK
) &&
7324 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7327 gen_helper_skinit(cpu_env
);
7329 case 7: /* INVLPGA */
7330 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7333 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7336 gen_helper_invlpga(cpu_env
,
7337 tcg_const_i32(s
->aflag
- 1));
7343 } else if (s
->cpl
!= 0) {
7344 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7346 gen_svm_check_intercept(s
, pc_start
,
7347 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7348 gen_lea_modrm(env
, s
, modrm
);
7349 gen_op_ld_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
7350 gen_add_A0_im(s
, 2);
7351 gen_op_ld_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7352 if (dflag
== MO_16
) {
7353 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7356 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7357 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7359 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7360 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7365 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7366 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7367 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7369 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7371 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 1);
7375 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7377 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7378 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7379 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7380 gen_jmp_im(s
->pc
- s
->cs_base
);
7385 if (mod
!= 3) { /* invlpg */
7387 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7389 gen_update_cc_op(s
);
7390 gen_jmp_im(pc_start
- s
->cs_base
);
7391 gen_lea_modrm(env
, s
, modrm
);
7392 gen_helper_invlpg(cpu_env
, cpu_A0
);
7393 gen_jmp_im(s
->pc
- s
->cs_base
);
7398 case 0: /* swapgs */
7399 #ifdef TARGET_X86_64
7402 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7404 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7405 offsetof(CPUX86State
,segs
[R_GS
].base
));
7406 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7407 offsetof(CPUX86State
,kernelgsbase
));
7408 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7409 offsetof(CPUX86State
,segs
[R_GS
].base
));
7410 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7411 offsetof(CPUX86State
,kernelgsbase
));
7419 case 1: /* rdtscp */
7420 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7422 gen_update_cc_op(s
);
7423 gen_jmp_im(pc_start
- s
->cs_base
);
7426 gen_helper_rdtscp(cpu_env
);
7429 gen_jmp(s
, s
->pc
- s
->cs_base
);
7441 case 0x108: /* invd */
7442 case 0x109: /* wbinvd */
7444 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7446 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7450 case 0x63: /* arpl or movslS (x86_64) */
7451 #ifdef TARGET_X86_64
7454 /* d_ot is the size of destination */
7457 modrm
= cpu_ldub_code(env
, s
->pc
++);
7458 reg
= ((modrm
>> 3) & 7) | rex_r
;
7459 mod
= (modrm
>> 6) & 3;
7460 rm
= (modrm
& 7) | REX_B(s
);
7463 gen_op_mov_TN_reg(MO_32
, 0, rm
);
7465 if (d_ot
== MO_64
) {
7466 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7468 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
7470 gen_lea_modrm(env
, s
, modrm
);
7471 gen_op_ld_v(s
, MO_32
| MO_SIGN
, cpu_T
[0], cpu_A0
);
7472 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
7478 TCGv t0
, t1
, t2
, a0
;
7480 if (!s
->pe
|| s
->vm86
)
7482 t0
= tcg_temp_local_new();
7483 t1
= tcg_temp_local_new();
7484 t2
= tcg_temp_local_new();
7486 modrm
= cpu_ldub_code(env
, s
->pc
++);
7487 reg
= (modrm
>> 3) & 7;
7488 mod
= (modrm
>> 6) & 3;
7491 gen_lea_modrm(env
, s
, modrm
);
7492 gen_op_ld_v(s
, ot
, t0
, cpu_A0
);
7493 a0
= tcg_temp_local_new();
7494 tcg_gen_mov_tl(a0
, cpu_A0
);
7496 gen_op_mov_v_reg(ot
, t0
, rm
);
7499 gen_op_mov_v_reg(ot
, t1
, reg
);
7500 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7501 tcg_gen_andi_tl(t1
, t1
, 3);
7502 tcg_gen_movi_tl(t2
, 0);
7503 label1
= gen_new_label();
7504 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7505 tcg_gen_andi_tl(t0
, t0
, ~3);
7506 tcg_gen_or_tl(t0
, t0
, t1
);
7507 tcg_gen_movi_tl(t2
, CC_Z
);
7508 gen_set_label(label1
);
7510 gen_op_st_v(s
, ot
, t0
, a0
);
7513 gen_op_mov_reg_v(ot
, rm
, t0
);
7515 gen_compute_eflags(s
);
7516 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7517 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7523 case 0x102: /* lar */
7524 case 0x103: /* lsl */
7528 if (!s
->pe
|| s
->vm86
)
7530 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
7531 modrm
= cpu_ldub_code(env
, s
->pc
++);
7532 reg
= ((modrm
>> 3) & 7) | rex_r
;
7533 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7534 t0
= tcg_temp_local_new();
7535 gen_update_cc_op(s
);
7537 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7539 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7541 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7542 label1
= gen_new_label();
7543 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7544 gen_op_mov_reg_v(ot
, reg
, t0
);
7545 gen_set_label(label1
);
7546 set_cc_op(s
, CC_OP_EFLAGS
);
7551 modrm
= cpu_ldub_code(env
, s
->pc
++);
7552 mod
= (modrm
>> 6) & 3;
7553 op
= (modrm
>> 3) & 7;
7555 case 0: /* prefetchnta */
7556 case 1: /* prefetchnt0 */
7557 case 2: /* prefetchnt0 */
7558 case 3: /* prefetchnt0 */
7561 gen_lea_modrm(env
, s
, modrm
);
7562 /* nothing more to do */
7564 default: /* nop (multi byte) */
7565 gen_nop_modrm(env
, s
, modrm
);
7569 case 0x119 ... 0x11f: /* nop (multi byte) */
7570 modrm
= cpu_ldub_code(env
, s
->pc
++);
7571 gen_nop_modrm(env
, s
, modrm
);
7573 case 0x120: /* mov reg, crN */
7574 case 0x122: /* mov crN, reg */
7576 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7578 modrm
= cpu_ldub_code(env
, s
->pc
++);
7579 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7580 * AMD documentation (24594.pdf) and testing of
7581 * intel 386 and 486 processors all show that the mod bits
7582 * are assumed to be 1's, regardless of actual values.
7584 rm
= (modrm
& 7) | REX_B(s
);
7585 reg
= ((modrm
>> 3) & 7) | rex_r
;
7590 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7591 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7600 gen_update_cc_op(s
);
7601 gen_jmp_im(pc_start
- s
->cs_base
);
7603 gen_op_mov_TN_reg(ot
, 0, rm
);
7604 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7606 gen_jmp_im(s
->pc
- s
->cs_base
);
7609 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7610 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
7618 case 0x121: /* mov reg, drN */
7619 case 0x123: /* mov drN, reg */
7621 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7623 modrm
= cpu_ldub_code(env
, s
->pc
++);
7624 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7625 * AMD documentation (24594.pdf) and testing of
7626 * intel 386 and 486 processors all show that the mod bits
7627 * are assumed to be 1's, regardless of actual values.
7629 rm
= (modrm
& 7) | REX_B(s
);
7630 reg
= ((modrm
>> 3) & 7) | rex_r
;
7635 /* XXX: do it dynamically with CR4.DE bit */
7636 if (reg
== 4 || reg
== 5 || reg
>= 8)
7639 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7640 gen_op_mov_TN_reg(ot
, 0, rm
);
7641 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7642 gen_jmp_im(s
->pc
- s
->cs_base
);
7645 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7646 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7647 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
7651 case 0x106: /* clts */
7653 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7655 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7656 gen_helper_clts(cpu_env
);
7657 /* abort block because static cpu state changed */
7658 gen_jmp_im(s
->pc
- s
->cs_base
);
7662 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7663 case 0x1c3: /* MOVNTI reg, mem */
7664 if (!(s
->cpuid_features
& CPUID_SSE2
))
7666 ot
= mo_64_32(dflag
);
7667 modrm
= cpu_ldub_code(env
, s
->pc
++);
7668 mod
= (modrm
>> 6) & 3;
7671 reg
= ((modrm
>> 3) & 7) | rex_r
;
7672 /* generate a generic store */
7673 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7676 modrm
= cpu_ldub_code(env
, s
->pc
++);
7677 mod
= (modrm
>> 6) & 3;
7678 op
= (modrm
>> 3) & 7;
7680 case 0: /* fxsave */
7681 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7682 (s
->prefix
& PREFIX_LOCK
))
7684 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7685 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7688 gen_lea_modrm(env
, s
, modrm
);
7689 gen_update_cc_op(s
);
7690 gen_jmp_im(pc_start
- s
->cs_base
);
7691 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7693 case 1: /* fxrstor */
7694 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7695 (s
->prefix
& PREFIX_LOCK
))
7697 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7698 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7701 gen_lea_modrm(env
, s
, modrm
);
7702 gen_update_cc_op(s
);
7703 gen_jmp_im(pc_start
- s
->cs_base
);
7704 gen_helper_fxrstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7706 case 2: /* ldmxcsr */
7707 case 3: /* stmxcsr */
7708 if (s
->flags
& HF_TS_MASK
) {
7709 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7712 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7715 gen_lea_modrm(env
, s
, modrm
);
7717 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
7718 s
->mem_index
, MO_LEUL
);
7719 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7721 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7722 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
7725 case 5: /* lfence */
7726 case 6: /* mfence */
7727 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7730 case 7: /* sfence / clflush */
7731 if ((modrm
& 0xc7) == 0xc0) {
7733 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7734 if (!(s
->cpuid_features
& CPUID_SSE
))
7738 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7740 gen_lea_modrm(env
, s
, modrm
);
7747 case 0x10d: /* 3DNow! prefetch(w) */
7748 modrm
= cpu_ldub_code(env
, s
->pc
++);
7749 mod
= (modrm
>> 6) & 3;
7752 gen_lea_modrm(env
, s
, modrm
);
7753 /* ignore for now */
7755 case 0x1aa: /* rsm */
7756 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7757 if (!(s
->flags
& HF_SMM_MASK
))
7759 gen_update_cc_op(s
);
7760 gen_jmp_im(s
->pc
- s
->cs_base
);
7761 gen_helper_rsm(cpu_env
);
7764 case 0x1b8: /* SSE4.2 popcnt */
7765 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7768 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7771 modrm
= cpu_ldub_code(env
, s
->pc
++);
7772 reg
= ((modrm
>> 3) & 7) | rex_r
;
7774 if (s
->prefix
& PREFIX_DATA
) {
7777 ot
= mo_64_32(dflag
);
7780 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7781 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7782 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
7784 set_cc_op(s
, CC_OP_EFLAGS
);
7786 case 0x10e ... 0x10f:
7787 /* 3DNow! instructions, ignore prefixes */
7788 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7789 case 0x110 ... 0x117:
7790 case 0x128 ... 0x12f:
7791 case 0x138 ... 0x13a:
7792 case 0x150 ... 0x179:
7793 case 0x17c ... 0x17f:
7795 case 0x1c4 ... 0x1c6:
7796 case 0x1d0 ... 0x1fe:
7797 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7802 /* lock generation */
7803 if (s
->prefix
& PREFIX_LOCK
)
7804 gen_helper_unlock();
7807 if (s
->prefix
& PREFIX_LOCK
)
7808 gen_helper_unlock();
7809 /* XXX: ensure that no lock was generated */
7810 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7814 void optimize_flags_init(void)
7816 static const char reg_names
[CPU_NB_REGS
][4] = {
7817 #ifdef TARGET_X86_64
7847 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7848 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7849 offsetof(CPUX86State
, cc_op
), "cc_op");
7850 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7852 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7854 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src2
),
7857 for (i
= 0; i
< CPU_NB_REGS
; ++i
) {
7858 cpu_regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
7859 offsetof(CPUX86State
, regs
[i
]),
7864 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7865 basic block 'tb'. If search_pc is TRUE, also generate PC
7866 information for each intermediate instruction. */
7867 static inline void gen_intermediate_code_internal(X86CPU
*cpu
,
7868 TranslationBlock
*tb
,
7871 CPUState
*cs
= CPU(cpu
);
7872 CPUX86State
*env
= &cpu
->env
;
7873 DisasContext dc1
, *dc
= &dc1
;
7874 target_ulong pc_ptr
;
7875 uint16_t *gen_opc_end
;
7879 target_ulong pc_start
;
7880 target_ulong cs_base
;
7884 /* generate intermediate code */
7886 cs_base
= tb
->cs_base
;
7889 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7890 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7891 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7892 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7894 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7895 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7896 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7897 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7898 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
7899 dc
->cc_op
= CC_OP_DYNAMIC
;
7900 dc
->cc_op_dirty
= false;
7901 dc
->cs_base
= cs_base
;
7903 dc
->popl_esp_hack
= 0;
7904 /* select memory access functions */
7906 if (flags
& HF_SOFTMMU_MASK
) {
7907 dc
->mem_index
= cpu_mmu_index(env
);
7909 dc
->cpuid_features
= env
->features
[FEAT_1_EDX
];
7910 dc
->cpuid_ext_features
= env
->features
[FEAT_1_ECX
];
7911 dc
->cpuid_ext2_features
= env
->features
[FEAT_8000_0001_EDX
];
7912 dc
->cpuid_ext3_features
= env
->features
[FEAT_8000_0001_ECX
];
7913 dc
->cpuid_7_0_ebx_features
= env
->features
[FEAT_7_0_EBX
];
7914 #ifdef TARGET_X86_64
7915 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7916 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7919 dc
->jmp_opt
= !(dc
->tf
|| cs
->singlestep_enabled
||
7920 (flags
& HF_INHIBIT_IRQ_MASK
)
7921 #ifndef CONFIG_SOFTMMU
7922 || (flags
& HF_SOFTMMU_MASK
)
7926 /* check addseg logic */
7927 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7928 printf("ERROR addseg\n");
7931 cpu_T
[0] = tcg_temp_new();
7932 cpu_T
[1] = tcg_temp_new();
7933 cpu_A0
= tcg_temp_new();
7935 cpu_tmp0
= tcg_temp_new();
7936 cpu_tmp1_i64
= tcg_temp_new_i64();
7937 cpu_tmp2_i32
= tcg_temp_new_i32();
7938 cpu_tmp3_i32
= tcg_temp_new_i32();
7939 cpu_tmp4
= tcg_temp_new();
7940 cpu_ptr0
= tcg_temp_new_ptr();
7941 cpu_ptr1
= tcg_temp_new_ptr();
7942 cpu_cc_srcT
= tcg_temp_local_new();
7944 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
7946 dc
->is_jmp
= DISAS_NEXT
;
7950 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7952 max_insns
= CF_COUNT_MASK
;
7956 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7957 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7958 if (bp
->pc
== pc_ptr
&&
7959 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7960 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7966 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
7970 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
7972 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
7973 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7974 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
7975 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
7977 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7980 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
7982 /* stop translation if indicated */
7985 /* if single step mode, we generate only one instruction and
7986 generate an exception */
7987 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7988 the flag and abort the translation to give the irqs a
7989 change to be happen */
7990 if (dc
->tf
|| dc
->singlestep_enabled
||
7991 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7992 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7996 /* if too long translation, stop generation too */
7997 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
7998 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
7999 num_insns
>= max_insns
) {
8000 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8005 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8010 if (tb
->cflags
& CF_LAST_IO
)
8012 gen_tb_end(tb
, num_insns
);
8013 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
8014 /* we don't forget to fill the last values */
8016 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8019 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8023 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8025 qemu_log("----------------\n");
8026 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8027 #ifdef TARGET_X86_64
8032 disas_flags
= !dc
->code32
;
8033 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8039 tb
->size
= pc_ptr
- pc_start
;
8040 tb
->icount
= num_insns
;
8044 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8046 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, false);
8049 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8051 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, true);
8054 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8058 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8060 qemu_log("RESTORE:\n");
8061 for(i
= 0;i
<= pc_pos
; i
++) {
8062 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8063 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8064 tcg_ctx
.gen_opc_pc
[i
]);
8067 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8068 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8069 (uint32_t)tb
->cs_base
);
8072 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8073 cc_op
= gen_opc_cc_op
[pc_pos
];
8074 if (cc_op
!= CC_OP_DYNAMIC
)