2 * LatticeMico32 virtual CPU header.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #define TARGET_LONG_BITS 32
25 #define CPUState struct CPULM32State
28 #include "qemu-common.h"
32 #define TARGET_HAS_ICE 1
34 #define ELF_MACHINE EM_LATTICEMICO32
36 #define NB_MMU_MODES 1
37 #define TARGET_PAGE_BITS 12
38 static inline int cpu_mmu_index(CPUState
*env
)
43 #define TARGET_PHYS_ADDR_SPACE_BITS 32
44 #define TARGET_VIRT_ADDR_SPACE_BITS 32
46 /* Exceptions indices */
60 R_R0
= 0, R_R1
, R_R2
, R_R3
, R_R4
, R_R5
, R_R6
, R_R7
, R_R8
, R_R9
, R_R10
,
61 R_R11
, R_R12
, R_R13
, R_R14
, R_R15
, R_R16
, R_R17
, R_R18
, R_R19
, R_R20
,
62 R_R21
, R_R22
, R_R23
, R_R24
, R_R25
, R_R26
, R_R27
, R_R28
, R_R29
, R_R30
,
66 /* Register aliases */
138 LM32_FEATURE_MULTIPLY
= 1,
139 LM32_FEATURE_DIVIDE
= 2,
140 LM32_FEATURE_SHIFT
= 4,
141 LM32_FEATURE_SIGN_EXTEND
= 8,
142 LM32_FEATURE_I_CACHE
= 16,
143 LM32_FEATURE_D_CACHE
= 32,
144 LM32_FEATURE_CYCLE_COUNT
= 64,
148 LM32_FLAG_IGNORE_MSB
= 1,
151 typedef struct CPULM32State
{
152 /* general registers */
155 /* special registers */
156 uint32_t pc
; /* program counter */
157 uint32_t ie
; /* interrupt enable */
158 uint32_t icc
; /* instruction cache control */
159 uint32_t dcc
; /* data cache control */
160 uint32_t cc
; /* cycle counter */
161 uint32_t cfg
; /* configuration */
163 /* debug registers */
164 uint32_t dc
; /* debug control */
165 uint32_t bp
[4]; /* breakpoint addresses */
166 uint32_t wp
[4]; /* watchpoint addresses */
170 uint32_t eba
; /* exception base address */
171 uint32_t deba
; /* debug exception base address */
173 /* interrupt controller handle for callbacks */
174 DeviceState
*pic_state
;
175 /* JTAG UART handle for callbacks */
176 DeviceState
*juart_state
;
178 /* processor core features */
187 CPUState
*cpu_lm32_init(const char *cpu_model
);
188 void cpu_lm32_list(FILE *f
, fprintf_function cpu_fprintf
);
189 int cpu_lm32_exec(CPUState
*s
);
190 void cpu_lm32_close(CPUState
*s
);
191 void do_interrupt(CPUState
*env
);
192 /* you can call this signal handler from your SIGBUS and SIGSEGV
193 signal handlers to inform the virtual CPU of exceptions. non zero
194 is returned if the signal was handled by the virtual CPU. */
195 int cpu_lm32_signal_handler(int host_signum
, void *pinfo
,
197 void lm32_translate_init(void);
198 void cpu_lm32_set_phys_msb_ignore(CPUState
*env
, int value
);
200 #define cpu_list cpu_lm32_list
201 #define cpu_init cpu_lm32_init
202 #define cpu_exec cpu_lm32_exec
203 #define cpu_gen_code cpu_lm32_gen_code
204 #define cpu_signal_handler cpu_lm32_signal_handler
206 #define CPU_SAVE_VERSION 1
208 int cpu_lm32_handle_mmu_fault(CPUState
*env
, target_ulong address
, int rw
,
210 #define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
212 #if defined(CONFIG_USER_ONLY)
213 static inline void cpu_clone_regs(CPUState
*env
, target_ulong newsp
)
216 env
->regs
[R_SP
] = newsp
;
222 static inline void cpu_set_tls(CPUState
*env
, target_ulong newtls
)
226 static inline int cpu_interrupts_enabled(CPUState
*env
)
228 return env
->ie
& IE_IE
;
233 static inline target_ulong
cpu_get_pc(CPUState
*env
)
238 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
239 target_ulong
*cs_base
, int *flags
)
246 static inline bool cpu_has_work(CPUState
*env
)
248 return env
->interrupt_request
& CPU_INTERRUPT_HARD
;
251 #include "exec-all.h"
253 static inline void cpu_pc_from_tb(CPUState
*env
, TranslationBlock
*tb
)