target-lm32/helper.c

   1 /*
   2  *  LatticeMico32 helper routines.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
  24                               int mmu_idx)
  25 {
  26     int prot;
  27
  28     address &= TARGET_PAGE_MASK;
  29     prot = PAGE_BITS;
  30     if (env->flags & LM32_FLAG_IGNORE_MSB) {
  31         tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
  32                 TARGET_PAGE_SIZE);
  33     } else {
  34         tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  35     }
  36
  37     return 0;
  38 }
  39
  40 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
  41 {
  42     LM32CPU *cpu = LM32_CPU(cs);
  43
  44     addr &= TARGET_PAGE_MASK;
  45     if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
  46         return addr & 0x7fffffff;
  47     } else {
  48         return addr;
  49     }
  50 }
  51
  52 void lm32_cpu_do_interrupt(CPUState *cs)
  53 {
  54     LM32CPU *cpu = LM32_CPU(cs);
  55     CPULM32State *env = &cpu->env;
  56
  57     qemu_log_mask(CPU_LOG_INT,
  58             "exception at pc=%x type=%x\n", env->pc, env->exception_index);
  59
  60     switch (env->exception_index) {
  61     case EXCP_INSN_BUS_ERROR:
  62     case EXCP_DATA_BUS_ERROR:
  63     case EXCP_DIVIDE_BY_ZERO:
  64     case EXCP_IRQ:
  65     case EXCP_SYSTEMCALL:
  66         /* non-debug exceptions */
  67         env->regs[R_EA] = env->pc;
  68         env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
  69         env->ie &= ~IE_IE;
  70         if (env->dc & DC_RE) {
  71             env->pc = env->deba + (env->exception_index * 32);
  72         } else {
  73             env->pc = env->eba + (env->exception_index * 32);
  74         }
  75         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
  76         break;
  77     case EXCP_BREAKPOINT:
  78     case EXCP_WATCHPOINT:
  79         /* debug exceptions */
  80         env->regs[R_BA] = env->pc;
  81         env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
  82         env->ie &= ~IE_IE;
  83         env->pc = env->deba + (env->exception_index * 32);
  84         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
  85         break;
  86     default:
  87         cpu_abort(env, "unhandled exception type=%d\n",
  88                   env->exception_index);
  89         break;
  90     }
  91 }
  92
  93 LM32CPU *cpu_lm32_init(const char *cpu_model)
  94 {
  95     LM32CPU *cpu;
  96     ObjectClass *oc;
  97
  98     oc = cpu_class_by_name(TYPE_LM32_CPU, cpu_model);
  99     if (oc == NULL) {
 100         return NULL;
 101     }
 102     cpu = LM32_CPU(object_new(object_class_get_name(oc)));
 103
 104     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 105
 106     return cpu;
 107 }
 108
 109 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
 110  * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
 111  * 0x80000000-0xffffffff is not cached and used to access IO devices. */
 112 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
 113 {
 114     if (value) {
 115         env->flags |= LM32_FLAG_IGNORE_MSB;
 116     } else {
 117         env->flags &= ~LM32_FLAG_IGNORE_MSB;
 118     }
 119 }