4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
36 //#define DEBUG_DISPATCH 1
38 /* Fake floating point. */
39 #define tcg_gen_mov_f64 tcg_gen_mov_i64
40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
43 #define DEFO32(name, offset) static TCGv QREG_##name;
44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
51 static TCGv_i32 cpu_halted
;
52 static TCGv_i32 cpu_exception_index
;
54 static TCGv_env cpu_env
;
56 static char cpu_reg_names
[3*8*3 + 5*4];
57 static TCGv cpu_dregs
[8];
58 static TCGv cpu_aregs
[8];
59 static TCGv_i64 cpu_fregs
[8];
60 static TCGv_i64 cpu_macc
[4];
62 #define REG(insn, pos) (((insn) >> (pos)) & 7)
63 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
64 #define AREG(insn, pos) cpu_aregs[REG(insn, pos)]
65 #define FREG(insn, pos) cpu_fregs[REG(insn, pos)]
66 #define MACREG(acc) cpu_macc[acc]
67 #define QREG_SP cpu_aregs[7]
69 static TCGv NULL_QREG
;
70 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
71 /* Used to distinguish stores from bad addressing modes. */
72 static TCGv store_dummy
;
74 #include "exec/gen-icount.h"
76 void m68k_tcg_init(void)
81 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
82 tcg_ctx
.tcg_env
= cpu_env
;
84 #define DEFO32(name, offset) \
85 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFO64(name, offset) \
88 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
89 offsetof(CPUM68KState, offset), #name);
90 #define DEFF64(name, offset) DEFO64(name, offset)
96 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
97 -offsetof(M68kCPU
, env
) +
98 offsetof(CPUState
, halted
), "HALTED");
99 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
100 -offsetof(M68kCPU
, env
) +
101 offsetof(CPUState
, exception_index
),
105 for (i
= 0; i
< 8; i
++) {
106 sprintf(p
, "D%d", i
);
107 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
108 offsetof(CPUM68KState
, dregs
[i
]), p
);
110 sprintf(p
, "A%d", i
);
111 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
112 offsetof(CPUM68KState
, aregs
[i
]), p
);
114 sprintf(p
, "F%d", i
);
115 cpu_fregs
[i
] = tcg_global_mem_new_i64(cpu_env
,
116 offsetof(CPUM68KState
, fregs
[i
]), p
);
119 for (i
= 0; i
< 4; i
++) {
120 sprintf(p
, "ACC%d", i
);
121 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
122 offsetof(CPUM68KState
, macc
[i
]), p
);
126 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
127 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
130 /* internal defines */
131 typedef struct DisasContext
{
133 target_ulong insn_pc
; /* Start of the current instruction. */
136 CCOp cc_op
; /* Current CC operation */
140 struct TranslationBlock
*tb
;
141 int singlestep_enabled
;
146 #define DISAS_JUMP_NEXT 4
148 #if defined(CONFIG_USER_ONLY)
151 #define IS_USER(s) s->user
154 /* XXX: move that elsewhere */
155 /* ??? Fix exceptions. */
156 static void *gen_throws_exception
;
157 #define gen_last_qop NULL
159 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
161 #ifdef DEBUG_DISPATCH
162 #define DISAS_INSN(name) \
163 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
165 static void disas_##name(CPUM68KState *env, DisasContext *s, \
168 qemu_log("Dispatch " #name "\n"); \
169 real_disas_##name(env, s, insn); \
171 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
174 #define DISAS_INSN(name) \
175 static void disas_##name(CPUM68KState *env, DisasContext *s, \
179 static const uint8_t cc_op_live
[CC_OP_NB
] = {
180 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
181 [CC_OP_ADD
] = CCF_X
| CCF_N
| CCF_V
,
182 [CC_OP_SUB
] = CCF_X
| CCF_N
| CCF_V
,
183 [CC_OP_CMP
] = CCF_X
| CCF_N
| CCF_V
,
184 [CC_OP_LOGIC
] = CCF_X
| CCF_N
187 static void set_cc_op(DisasContext
*s
, CCOp op
)
189 CCOp old_op
= s
->cc_op
;
198 /* Discard CC computation that will no longer be used.
199 Note that X and N are never dead. */
200 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
202 tcg_gen_discard_i32(QREG_CC_C
);
205 tcg_gen_discard_i32(QREG_CC_Z
);
208 tcg_gen_discard_i32(QREG_CC_V
);
212 /* Update the CPU env CC_OP state. */
213 static void update_cc_op(DisasContext
*s
)
215 if (!s
->cc_op_synced
) {
217 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
221 /* Generate a load from the specified address. Narrow values are
222 sign extended to full register width. */
223 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
226 int index
= IS_USER(s
);
227 tmp
= tcg_temp_new_i32();
231 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
233 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
237 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
239 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
243 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
246 g_assert_not_reached();
248 gen_throws_exception
= gen_last_qop
;
252 static inline TCGv_i64
gen_load64(DisasContext
* s
, TCGv addr
)
255 int index
= IS_USER(s
);
256 tmp
= tcg_temp_new_i64();
257 tcg_gen_qemu_ldf64(tmp
, addr
, index
);
258 gen_throws_exception
= gen_last_qop
;
262 /* Generate a store. */
263 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
265 int index
= IS_USER(s
);
268 tcg_gen_qemu_st8(val
, addr
, index
);
271 tcg_gen_qemu_st16(val
, addr
, index
);
275 tcg_gen_qemu_st32(val
, addr
, index
);
278 g_assert_not_reached();
280 gen_throws_exception
= gen_last_qop
;
283 static inline void gen_store64(DisasContext
*s
, TCGv addr
, TCGv_i64 val
)
285 int index
= IS_USER(s
);
286 tcg_gen_qemu_stf64(val
, addr
, index
);
287 gen_throws_exception
= gen_last_qop
;
296 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
297 otherwise generate a store. */
298 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
301 if (what
== EA_STORE
) {
302 gen_store(s
, opsize
, addr
, val
);
305 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
309 /* Read a 16-bit immediate constant */
310 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
313 im
= cpu_lduw_code(env
, s
->pc
);
318 /* Read an 8-bit immediate constant */
319 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
321 return read_im16(env
, s
);
324 /* Read a 32-bit immediate constant. */
325 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
328 im
= read_im16(env
, s
) << 16;
329 im
|= 0xffff & read_im16(env
, s
);
333 /* Calculate and address index. */
334 static TCGv
gen_addr_index(uint16_t ext
, TCGv tmp
)
339 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
340 if ((ext
& 0x800) == 0) {
341 tcg_gen_ext16s_i32(tmp
, add
);
344 scale
= (ext
>> 9) & 3;
346 tcg_gen_shli_i32(tmp
, add
, scale
);
352 /* Handle a base + index + displacement effective addresss.
353 A NULL_QREG base means pc-relative. */
354 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
363 ext
= read_im16(env
, s
);
365 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
368 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
369 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
374 /* full extension word format */
375 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
378 if ((ext
& 0x30) > 0x10) {
379 /* base displacement */
380 if ((ext
& 0x30) == 0x20) {
381 bd
= (int16_t)read_im16(env
, s
);
383 bd
= read_im32(env
, s
);
388 tmp
= tcg_temp_new();
389 if ((ext
& 0x44) == 0) {
391 add
= gen_addr_index(ext
, tmp
);
395 if ((ext
& 0x80) == 0) {
396 /* base not suppressed */
397 if (IS_NULL_QREG(base
)) {
398 base
= tcg_const_i32(offset
+ bd
);
401 if (!IS_NULL_QREG(add
)) {
402 tcg_gen_add_i32(tmp
, add
, base
);
408 if (!IS_NULL_QREG(add
)) {
410 tcg_gen_addi_i32(tmp
, add
, bd
);
414 add
= tcg_const_i32(bd
);
416 if ((ext
& 3) != 0) {
417 /* memory indirect */
418 base
= gen_load(s
, OS_LONG
, add
, 0);
419 if ((ext
& 0x44) == 4) {
420 add
= gen_addr_index(ext
, tmp
);
421 tcg_gen_add_i32(tmp
, add
, base
);
427 /* outer displacement */
428 if ((ext
& 3) == 2) {
429 od
= (int16_t)read_im16(env
, s
);
431 od
= read_im32(env
, s
);
437 tcg_gen_addi_i32(tmp
, add
, od
);
442 /* brief extension word format */
443 tmp
= tcg_temp_new();
444 add
= gen_addr_index(ext
, tmp
);
445 if (!IS_NULL_QREG(base
)) {
446 tcg_gen_add_i32(tmp
, add
, base
);
448 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
450 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
457 /* Evaluate all the CC flags. */
459 static void gen_flush_flags(DisasContext
*s
)
468 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
469 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
470 /* Compute signed overflow for addition. */
473 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
474 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
475 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
477 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
482 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
483 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
484 /* Compute signed overflow for subtraction. */
487 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
488 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
489 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
491 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
496 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
497 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
498 /* Compute signed overflow for subtraction. */
500 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
501 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
502 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
504 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
508 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
509 tcg_gen_movi_i32(QREG_CC_C
, 0);
510 tcg_gen_movi_i32(QREG_CC_V
, 0);
514 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
518 t0
= tcg_const_i32(s
->cc_op
);
519 gen_helper_flush_flags(cpu_env
, t0
);
524 /* Note that flush_flags also assigned to env->cc_op. */
525 s
->cc_op
= CC_OP_FLAGS
;
529 /* Sign or zero extend a value. */
531 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
536 tcg_gen_ext8s_i32(res
, val
);
538 tcg_gen_ext8u_i32(res
, val
);
543 tcg_gen_ext16s_i32(res
, val
);
545 tcg_gen_ext16u_i32(res
, val
);
549 tcg_gen_mov_i32(res
, val
);
552 g_assert_not_reached();
556 static TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
560 if (opsize
== OS_LONG
) {
563 tmp
= tcg_temp_new();
564 gen_ext(tmp
, val
, opsize
, sign
);
570 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
572 gen_ext(QREG_CC_N
, val
, opsize
, 1);
573 set_cc_op(s
, CC_OP_LOGIC
);
576 static void gen_update_cc_add(TCGv dest
, TCGv src
)
578 tcg_gen_mov_i32(QREG_CC_N
, dest
);
579 tcg_gen_mov_i32(QREG_CC_V
, src
);
582 static inline int opsize_bytes(int opsize
)
585 case OS_BYTE
: return 1;
586 case OS_WORD
: return 2;
587 case OS_LONG
: return 4;
588 case OS_SINGLE
: return 4;
589 case OS_DOUBLE
: return 8;
590 case OS_EXTENDED
: return 12;
591 case OS_PACKED
: return 12;
593 g_assert_not_reached();
597 static inline int insn_opsize(int insn
)
599 switch ((insn
>> 6) & 3) {
600 case 0: return OS_BYTE
;
601 case 1: return OS_WORD
;
602 case 2: return OS_LONG
;
604 g_assert_not_reached();
608 /* Assign value to a register. If the width is less than the register width
609 only the low part of the register is set. */
610 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
615 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
616 tmp
= tcg_temp_new();
617 tcg_gen_ext8u_i32(tmp
, val
);
618 tcg_gen_or_i32(reg
, reg
, tmp
);
621 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
622 tmp
= tcg_temp_new();
623 tcg_gen_ext16u_i32(tmp
, val
);
624 tcg_gen_or_i32(reg
, reg
, tmp
);
628 tcg_gen_mov_i32(reg
, val
);
631 g_assert_not_reached();
635 /* Generate code for an "effective address". Does not adjust the base
636 register for autoincrement addressing modes. */
637 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
645 switch ((insn
>> 3) & 7) {
646 case 0: /* Data register direct. */
647 case 1: /* Address register direct. */
649 case 2: /* Indirect register */
650 case 3: /* Indirect postincrement. */
651 return AREG(insn
, 0);
652 case 4: /* Indirect predecrememnt. */
654 tmp
= tcg_temp_new();
655 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
657 case 5: /* Indirect displacement. */
659 tmp
= tcg_temp_new();
660 ext
= read_im16(env
, s
);
661 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
663 case 6: /* Indirect index + displacement. */
665 return gen_lea_indexed(env
, s
, reg
);
668 case 0: /* Absolute short. */
669 offset
= (int16_t)read_im16(env
, s
);
670 return tcg_const_i32(offset
);
671 case 1: /* Absolute long. */
672 offset
= read_im32(env
, s
);
673 return tcg_const_i32(offset
);
674 case 2: /* pc displacement */
676 offset
+= (int16_t)read_im16(env
, s
);
677 return tcg_const_i32(offset
);
678 case 3: /* pc index+displacement. */
679 return gen_lea_indexed(env
, s
, NULL_QREG
);
680 case 4: /* Immediate. */
685 /* Should never happen. */
689 /* Helper function for gen_ea. Reuse the computed address between the
690 for read/write operands. */
691 static inline TCGv
gen_ea_once(CPUM68KState
*env
, DisasContext
*s
,
692 uint16_t insn
, int opsize
, TCGv val
,
693 TCGv
*addrp
, ea_what what
)
697 if (addrp
&& what
== EA_STORE
) {
700 tmp
= gen_lea(env
, s
, insn
, opsize
);
701 if (IS_NULL_QREG(tmp
))
706 return gen_ldst(s
, opsize
, tmp
, val
, what
);
709 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
710 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
711 ADDRP is non-null for readwrite operands. */
712 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
713 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
719 switch ((insn
>> 3) & 7) {
720 case 0: /* Data register direct. */
722 if (what
== EA_STORE
) {
723 gen_partset_reg(opsize
, reg
, val
);
726 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
728 case 1: /* Address register direct. */
730 if (what
== EA_STORE
) {
731 tcg_gen_mov_i32(reg
, val
);
734 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
736 case 2: /* Indirect register */
738 return gen_ldst(s
, opsize
, reg
, val
, what
);
739 case 3: /* Indirect postincrement. */
741 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
742 /* ??? This is not exception safe. The instruction may still
743 fault after this point. */
744 if (what
== EA_STORE
|| !addrp
)
745 tcg_gen_addi_i32(reg
, reg
, opsize_bytes(opsize
));
747 case 4: /* Indirect predecrememnt. */
750 if (addrp
&& what
== EA_STORE
) {
753 tmp
= gen_lea(env
, s
, insn
, opsize
);
754 if (IS_NULL_QREG(tmp
))
759 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
760 /* ??? This is not exception safe. The instruction may still
761 fault after this point. */
762 if (what
== EA_STORE
|| !addrp
) {
764 tcg_gen_mov_i32(reg
, tmp
);
768 case 5: /* Indirect displacement. */
769 case 6: /* Indirect index + displacement. */
770 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
773 case 0: /* Absolute short. */
774 case 1: /* Absolute long. */
775 case 2: /* pc displacement */
776 case 3: /* pc index+displacement. */
777 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
778 case 4: /* Immediate. */
779 /* Sign extend values for consistency. */
782 if (what
== EA_LOADS
) {
783 offset
= (int8_t)read_im8(env
, s
);
785 offset
= read_im8(env
, s
);
789 if (what
== EA_LOADS
) {
790 offset
= (int16_t)read_im16(env
, s
);
792 offset
= read_im16(env
, s
);
796 offset
= read_im32(env
, s
);
799 g_assert_not_reached();
801 return tcg_const_i32(offset
);
806 /* Should never happen. */
818 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
824 /* The CC_OP_CMP form can handle most normal comparisons directly. */
825 if (op
== CC_OP_CMP
) {
832 tcond
= TCG_COND_LEU
;
836 tcond
= TCG_COND_LTU
;
845 c
->v2
= tcg_const_i32(0);
846 c
->v1
= tmp
= tcg_temp_new();
847 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
862 c
->v2
= tcg_const_i32(0);
868 tcond
= TCG_COND_NEVER
;
870 case 14: /* GT (!(Z || (N ^ V))) */
871 case 15: /* LE (Z || (N ^ V)) */
872 /* Logic operations clear V, which simplifies LE to (Z || N),
873 and since Z and N are co-located, this becomes a normal
875 if (op
== CC_OP_LOGIC
) {
881 case 12: /* GE (!(N ^ V)) */
882 case 13: /* LT (N ^ V) */
883 /* Logic operations clear V, which simplifies this to N. */
884 if (op
!= CC_OP_LOGIC
) {
888 case 10: /* PL (!N) */
889 case 11: /* MI (N) */
890 /* Several cases represent N normally. */
891 if (op
== CC_OP_ADD
|| op
== CC_OP_SUB
|| op
== CC_OP_LOGIC
) {
897 case 6: /* NE (!Z) */
899 /* Some cases fold Z into N. */
900 if (op
== CC_OP_ADD
|| op
== CC_OP_SUB
|| op
== CC_OP_LOGIC
) {
906 case 4: /* CC (!C) */
908 /* Some cases fold C into X. */
909 if (op
== CC_OP_ADD
|| op
== CC_OP_SUB
) {
915 case 8: /* VC (!V) */
917 /* Logic operations clear V and C. */
918 if (op
== CC_OP_LOGIC
) {
919 tcond
= TCG_COND_NEVER
;
926 /* Otherwise, flush flag state to CC_OP_FLAGS. */
933 /* Invalid, or handled above. */
935 case 2: /* HI (!C && !Z) -> !(C || Z)*/
936 case 3: /* LS (C || Z) */
937 c
->v1
= tmp
= tcg_temp_new();
939 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
940 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
943 case 4: /* CC (!C) */
948 case 6: /* NE (!Z) */
953 case 8: /* VC (!V) */
958 case 10: /* PL (!N) */
959 case 11: /* MI (N) */
963 case 12: /* GE (!(N ^ V)) */
964 case 13: /* LT (N ^ V) */
965 c
->v1
= tmp
= tcg_temp_new();
967 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
970 case 14: /* GT (!(Z || (N ^ V))) */
971 case 15: /* LE (Z || (N ^ V)) */
972 c
->v1
= tmp
= tcg_temp_new();
974 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
975 tcg_gen_neg_i32(tmp
, tmp
);
976 tmp2
= tcg_temp_new();
977 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
978 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
985 if ((cond
& 1) == 0) {
986 tcond
= tcg_invert_cond(tcond
);
991 static void free_cond(DisasCompare
*c
)
994 tcg_temp_free(c
->v1
);
997 tcg_temp_free(c
->v2
);
1001 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1005 gen_cc_cond(&c
, s
, cond
);
1007 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1011 /* Force a TB lookup after an instruction that changes the CPU state. */
1012 static void gen_lookup_tb(DisasContext
*s
)
1015 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1016 s
->is_jmp
= DISAS_UPDATE
;
1019 /* Generate a jump to an immediate address. */
1020 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
1023 tcg_gen_movi_i32(QREG_PC
, dest
);
1024 s
->is_jmp
= DISAS_JUMP
;
1027 /* Generate a jump to the address in qreg DEST. */
1028 static void gen_jmp(DisasContext
*s
, TCGv dest
)
1031 tcg_gen_mov_i32(QREG_PC
, dest
);
1032 s
->is_jmp
= DISAS_JUMP
;
1035 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
1038 gen_jmp_im(s
, where
);
1039 gen_helper_raise_exception(cpu_env
, tcg_const_i32(nr
));
1042 static inline void gen_addr_fault(DisasContext
*s
)
1044 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
1047 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1048 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1049 op_sign ? EA_LOADS : EA_LOADU); \
1050 if (IS_NULL_QREG(result)) { \
1051 gen_addr_fault(s); \
1056 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1057 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1058 if (IS_NULL_QREG(ea_result)) { \
1059 gen_addr_fault(s); \
1064 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1066 #ifndef CONFIG_USER_ONLY
1067 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
1068 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1074 /* Generate a jump to an immediate address. */
1075 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1077 if (unlikely(s
->singlestep_enabled
)) {
1078 gen_exception(s
, dest
, EXCP_DEBUG
);
1079 } else if (use_goto_tb(s
, dest
)) {
1081 tcg_gen_movi_i32(QREG_PC
, dest
);
1082 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1084 gen_jmp_im(s
, dest
);
1087 s
->is_jmp
= DISAS_TB_JUMP
;
1096 cond
= (insn
>> 8) & 0xf;
1097 gen_cc_cond(&c
, s
, cond
);
1099 tmp
= tcg_temp_new();
1100 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1103 tcg_gen_neg_i32(tmp
, tmp
);
1104 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1116 reg
= DREG(insn
, 0);
1118 offset
= (int16_t)read_im16(env
, s
);
1119 l1
= gen_new_label();
1120 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1122 tmp
= tcg_temp_new();
1123 tcg_gen_ext16s_i32(tmp
, reg
);
1124 tcg_gen_addi_i32(tmp
, tmp
, -1);
1125 gen_partset_reg(OS_WORD
, reg
, tmp
);
1126 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1127 gen_jmp_tb(s
, 1, base
+ offset
);
1129 gen_jmp_tb(s
, 0, s
->pc
);
1132 DISAS_INSN(undef_mac
)
1134 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
1137 DISAS_INSN(undef_fpu
)
1139 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
1144 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
1146 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
1147 cpu_abort(CPU(cpu
), "Illegal instruction: %04x @ %08x", insn
, s
->pc
- 2);
1157 sign
= (insn
& 0x100) != 0;
1158 reg
= DREG(insn
, 9);
1159 tmp
= tcg_temp_new();
1161 tcg_gen_ext16s_i32(tmp
, reg
);
1163 tcg_gen_ext16u_i32(tmp
, reg
);
1164 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1165 tcg_gen_mul_i32(tmp
, tmp
, src
);
1166 tcg_gen_mov_i32(reg
, tmp
);
1167 gen_logic_cc(s
, tmp
, OS_WORD
);
1177 sign
= (insn
& 0x100) != 0;
1178 reg
= DREG(insn
, 9);
1180 tcg_gen_ext16s_i32(QREG_DIV1
, reg
);
1182 tcg_gen_ext16u_i32(QREG_DIV1
, reg
);
1184 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1185 tcg_gen_mov_i32(QREG_DIV2
, src
);
1187 gen_helper_divs(cpu_env
, tcg_const_i32(1));
1189 gen_helper_divu(cpu_env
, tcg_const_i32(1));
1192 tmp
= tcg_temp_new();
1193 src
= tcg_temp_new();
1194 tcg_gen_ext16u_i32(tmp
, QREG_DIV1
);
1195 tcg_gen_shli_i32(src
, QREG_DIV2
, 16);
1196 tcg_gen_or_i32(reg
, tmp
, src
);
1198 set_cc_op(s
, CC_OP_FLAGS
);
1208 ext
= read_im16(env
, s
);
1210 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1213 num
= DREG(ext
, 12);
1215 tcg_gen_mov_i32(QREG_DIV1
, num
);
1216 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1217 tcg_gen_mov_i32(QREG_DIV2
, den
);
1219 gen_helper_divs(cpu_env
, tcg_const_i32(0));
1221 gen_helper_divu(cpu_env
, tcg_const_i32(0));
1223 if ((ext
& 7) == ((ext
>> 12) & 7)) {
1225 tcg_gen_mov_i32 (reg
, QREG_DIV1
);
1228 tcg_gen_mov_i32 (reg
, QREG_DIV2
);
1230 set_cc_op(s
, CC_OP_FLAGS
);
1242 add
= (insn
& 0x4000) != 0;
1243 reg
= DREG(insn
, 9);
1244 dest
= tcg_temp_new();
1246 SRC_EA(env
, tmp
, OS_LONG
, 0, &addr
);
1250 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1253 tcg_gen_add_i32(dest
, tmp
, src
);
1254 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1255 set_cc_op(s
, CC_OP_ADD
);
1257 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1258 tcg_gen_sub_i32(dest
, tmp
, src
);
1259 set_cc_op(s
, CC_OP_SUB
);
1261 gen_update_cc_add(dest
, src
);
1263 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1265 tcg_gen_mov_i32(reg
, dest
);
1270 /* Reverse the order of the bits in REG. */
1274 reg
= DREG(insn
, 0);
1275 gen_helper_bitrev(reg
, reg
);
1278 DISAS_INSN(bitop_reg
)
1288 if ((insn
& 0x38) != 0)
1292 op
= (insn
>> 6) & 3;
1293 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1296 src2
= tcg_temp_new();
1297 if (opsize
== OS_BYTE
)
1298 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1300 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1302 tmp
= tcg_const_i32(1);
1303 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1304 tcg_temp_free(src2
);
1306 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1308 dest
= tcg_temp_new();
1311 tcg_gen_xor_i32(dest
, src1
, tmp
);
1314 tcg_gen_andc_i32(dest
, src1
, tmp
);
1317 tcg_gen_or_i32(dest
, src1
, tmp
);
1324 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1326 tcg_temp_free(dest
);
1332 reg
= DREG(insn
, 0);
1334 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1335 gen_logic_cc(s
, reg
, OS_LONG
);
1338 static void gen_push(DisasContext
*s
, TCGv val
)
1342 tmp
= tcg_temp_new();
1343 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1344 gen_store(s
, OS_LONG
, tmp
, val
);
1345 tcg_gen_mov_i32(QREG_SP
, tmp
);
1357 mask
= read_im16(env
, s
);
1358 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1359 if (IS_NULL_QREG(tmp
)) {
1363 addr
= tcg_temp_new();
1364 tcg_gen_mov_i32(addr
, tmp
);
1365 is_load
= ((insn
& 0x0400) != 0);
1366 for (i
= 0; i
< 16; i
++, mask
>>= 1) {
1373 tmp
= gen_load(s
, OS_LONG
, addr
, 0);
1374 tcg_gen_mov_i32(reg
, tmp
);
1376 gen_store(s
, OS_LONG
, addr
, reg
);
1379 tcg_gen_addi_i32(addr
, addr
, 4);
1384 DISAS_INSN(bitop_im
)
1394 if ((insn
& 0x38) != 0)
1398 op
= (insn
>> 6) & 3;
1400 bitnum
= read_im16(env
, s
);
1401 if (bitnum
& 0xff00) {
1402 disas_undef(env
, s
, insn
);
1406 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1409 if (opsize
== OS_BYTE
)
1415 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
1418 tmp
= tcg_temp_new();
1421 tcg_gen_xori_i32(tmp
, src1
, mask
);
1424 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
1427 tcg_gen_ori_i32(tmp
, src1
, mask
);
1432 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
1437 DISAS_INSN(arith_im
)
1445 op
= (insn
>> 9) & 7;
1446 SRC_EA(env
, src1
, OS_LONG
, 0, (op
== 6) ? NULL
: &addr
);
1447 im
= read_im32(env
, s
);
1448 dest
= tcg_temp_new();
1451 tcg_gen_ori_i32(dest
, src1
, im
);
1452 gen_logic_cc(s
, dest
, OS_LONG
);
1455 tcg_gen_andi_i32(dest
, src1
, im
);
1456 gen_logic_cc(s
, dest
, OS_LONG
);
1459 tcg_gen_mov_i32(dest
, src1
);
1460 tcg_gen_setcondi_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
1461 tcg_gen_subi_i32(dest
, dest
, im
);
1462 gen_update_cc_add(dest
, tcg_const_i32(im
));
1463 set_cc_op(s
, CC_OP_SUB
);
1466 tcg_gen_mov_i32(dest
, src1
);
1467 tcg_gen_addi_i32(dest
, dest
, im
);
1468 gen_update_cc_add(dest
, tcg_const_i32(im
));
1469 tcg_gen_setcondi_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
1470 set_cc_op(s
, CC_OP_ADD
);
1473 tcg_gen_xori_i32(dest
, src1
, im
);
1474 gen_logic_cc(s
, dest
, OS_LONG
);
1477 gen_update_cc_add(src1
, tcg_const_i32(im
));
1478 set_cc_op(s
, CC_OP_CMP
);
1484 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1492 reg
= DREG(insn
, 0);
1493 tcg_gen_bswap32_i32(reg
, reg
);
1503 switch (insn
>> 12) {
1504 case 1: /* move.b */
1507 case 2: /* move.l */
1510 case 3: /* move.w */
1516 SRC_EA(env
, src
, opsize
, 1, NULL
);
1517 op
= (insn
>> 6) & 7;
1520 /* The value will already have been sign extended. */
1521 dest
= AREG(insn
, 9);
1522 tcg_gen_mov_i32(dest
, src
);
1526 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
1527 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
1528 /* This will be correct because loads sign extend. */
1529 gen_logic_cc(s
, src
, opsize
);
1540 opsize
= insn_opsize(insn
);
1541 SRC_EA(env
, src
, opsize
, 1, &addr
);
1543 gen_flush_flags(s
); /* compute old Z */
1545 /* Perform substract with borrow.
1546 * (X, N) = -(src + X);
1549 z
= tcg_const_i32(0);
1550 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
1551 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
1553 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
1555 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
1557 /* Compute signed-overflow for negation. The normal formula for
1558 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
1559 * this simplies to res & src.
1562 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
1564 /* Copy the rest of the results into place. */
1565 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
1566 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
1568 set_cc_op(s
, CC_OP_FLAGS
);
1570 /* result is in QREG_CC_N */
1572 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
1580 reg
= AREG(insn
, 9);
1581 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1582 if (IS_NULL_QREG(tmp
)) {
1586 tcg_gen_mov_i32(reg
, tmp
);
1593 opsize
= insn_opsize(insn
);
1594 DEST_EA(env
, insn
, opsize
, tcg_const_i32(0), NULL
);
1595 gen_logic_cc(s
, tcg_const_i32(0), opsize
);
1598 static TCGv
gen_get_ccr(DisasContext
*s
)
1604 dest
= tcg_temp_new();
1605 gen_helper_get_ccr(dest
, cpu_env
);
1609 DISAS_INSN(move_from_ccr
)
1613 ccr
= gen_get_ccr(s
);
1614 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
1622 reg
= DREG(insn
, 0);
1623 src1
= tcg_temp_new();
1624 tcg_gen_mov_i32(src1
, reg
);
1625 tcg_gen_neg_i32(reg
, src1
);
1626 gen_update_cc_add(reg
, src1
);
1627 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, src1
, 0);
1628 set_cc_op(s
, CC_OP_SUB
);
1631 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
1634 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
1635 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
1636 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
1637 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
1638 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
1640 gen_helper_set_sr(cpu_env
, tcg_const_i32(val
));
1642 set_cc_op(s
, CC_OP_FLAGS
);
1645 static void gen_set_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1648 if ((insn
& 0x38) == 0) {
1650 gen_helper_set_ccr(cpu_env
, DREG(insn
, 0));
1652 gen_helper_set_sr(cpu_env
, DREG(insn
, 0));
1654 set_cc_op(s
, CC_OP_FLAGS
);
1655 } else if ((insn
& 0x3f) == 0x3c) {
1657 val
= read_im16(env
, s
);
1658 gen_set_sr_im(s
, val
, ccr_only
);
1660 disas_undef(env
, s
, insn
);
1665 DISAS_INSN(move_to_ccr
)
1667 gen_set_sr(env
, s
, insn
, 1);
1677 opsize
= insn_opsize(insn
);
1678 SRC_EA(env
, src1
, opsize
, 1, &addr
);
1679 dest
= tcg_temp_new();
1680 tcg_gen_not_i32(dest
, src1
);
1681 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1682 gen_logic_cc(s
, dest
, opsize
);
1691 src1
= tcg_temp_new();
1692 src2
= tcg_temp_new();
1693 reg
= DREG(insn
, 0);
1694 tcg_gen_shli_i32(src1
, reg
, 16);
1695 tcg_gen_shri_i32(src2
, reg
, 16);
1696 tcg_gen_or_i32(reg
, src1
, src2
);
1697 gen_logic_cc(s
, reg
, OS_LONG
);
1702 gen_exception(s
, s
->pc
- 2, EXCP_DEBUG
);
1709 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1710 if (IS_NULL_QREG(tmp
)) {
1723 reg
= DREG(insn
, 0);
1724 op
= (insn
>> 6) & 7;
1725 tmp
= tcg_temp_new();
1727 tcg_gen_ext16s_i32(tmp
, reg
);
1729 tcg_gen_ext8s_i32(tmp
, reg
);
1731 gen_partset_reg(OS_WORD
, reg
, tmp
);
1733 tcg_gen_mov_i32(reg
, tmp
);
1734 gen_logic_cc(s
, tmp
, OS_LONG
);
1742 opsize
= insn_opsize(insn
);
1743 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
1744 gen_logic_cc(s
, tmp
, opsize
);
1749 /* Implemented as a NOP. */
1754 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
1757 /* ??? This should be atomic. */
1764 dest
= tcg_temp_new();
1765 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
1766 gen_logic_cc(s
, src1
, OS_BYTE
);
1767 tcg_gen_ori_i32(dest
, src1
, 0x80);
1768 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1778 /* The upper 32 bits of the product are discarded, so
1779 muls.l and mulu.l are functionally equivalent. */
1780 ext
= read_im16(env
, s
);
1782 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1785 reg
= DREG(ext
, 12);
1786 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
1787 dest
= tcg_temp_new();
1788 tcg_gen_mul_i32(dest
, src1
, reg
);
1789 tcg_gen_mov_i32(reg
, dest
);
1790 /* Unlike m68k, coldfire always clears the overflow bit. */
1791 gen_logic_cc(s
, dest
, OS_LONG
);
1794 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
1799 reg
= AREG(insn
, 0);
1800 tmp
= tcg_temp_new();
1801 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1802 gen_store(s
, OS_LONG
, tmp
, reg
);
1803 if ((insn
& 7) != 7) {
1804 tcg_gen_mov_i32(reg
, tmp
);
1806 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
1814 offset
= read_im16(env
, s
);
1815 gen_link(s
, insn
, offset
);
1822 offset
= read_im32(env
, s
);
1823 gen_link(s
, insn
, offset
);
1832 src
= tcg_temp_new();
1833 reg
= AREG(insn
, 0);
1834 tcg_gen_mov_i32(src
, reg
);
1835 tmp
= gen_load(s
, OS_LONG
, src
, 0);
1836 tcg_gen_mov_i32(reg
, tmp
);
1837 tcg_gen_addi_i32(QREG_SP
, src
, 4);
1848 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
1849 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
1857 /* Load the target address first to ensure correct exception
1859 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1860 if (IS_NULL_QREG(tmp
)) {
1864 if ((insn
& 0x40) == 0) {
1866 gen_push(s
, tcg_const_i32(s
->pc
));
1879 SRC_EA(env
, src1
, OS_LONG
, 0, &addr
);
1880 val
= (insn
>> 9) & 7;
1883 dest
= tcg_temp_new();
1884 tcg_gen_mov_i32(dest
, src1
);
1885 if ((insn
& 0x38) == 0x08) {
1886 /* Don't update condition codes if the destination is an
1887 address register. */
1888 if (insn
& 0x0100) {
1889 tcg_gen_subi_i32(dest
, dest
, val
);
1891 tcg_gen_addi_i32(dest
, dest
, val
);
1894 src2
= tcg_const_i32(val
);
1895 if (insn
& 0x0100) {
1896 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src2
);
1897 tcg_gen_sub_i32(dest
, dest
, src2
);
1898 set_cc_op(s
, CC_OP_SUB
);
1900 tcg_gen_add_i32(dest
, dest
, src2
);
1901 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src2
);
1902 set_cc_op(s
, CC_OP_ADD
);
1904 gen_update_cc_add(dest
, src2
);
1906 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1912 case 2: /* One extension word. */
1915 case 3: /* Two extension words. */
1918 case 4: /* No extension words. */
1921 disas_undef(env
, s
, insn
);
1933 op
= (insn
>> 8) & 0xf;
1934 offset
= (int8_t)insn
;
1936 offset
= (int16_t)read_im16(env
, s
);
1937 } else if (offset
== -1) {
1938 offset
= read_im32(env
, s
);
1942 gen_push(s
, tcg_const_i32(s
->pc
));
1946 l1
= gen_new_label();
1947 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
1948 gen_jmp_tb(s
, 1, base
+ offset
);
1950 gen_jmp_tb(s
, 0, s
->pc
);
1952 /* Unconditional branch. */
1953 gen_jmp_tb(s
, 0, base
+ offset
);
1962 tcg_gen_movi_i32(DREG(insn
, 9), val
);
1963 gen_logic_cc(s
, tcg_const_i32(val
), OS_LONG
);
1976 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
1977 reg
= DREG(insn
, 9);
1978 tcg_gen_mov_i32(reg
, src
);
1979 gen_logic_cc(s
, src
, opsize
);
1990 opsize
= insn_opsize(insn
);
1991 reg
= gen_extend(DREG(insn
, 9), opsize
, 0);
1992 dest
= tcg_temp_new();
1994 SRC_EA(env
, src
, opsize
, 0, &addr
);
1995 tcg_gen_or_i32(dest
, src
, reg
);
1996 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1998 SRC_EA(env
, src
, opsize
, 0, NULL
);
1999 tcg_gen_or_i32(dest
, src
, reg
);
2000 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
2002 gen_logic_cc(s
, dest
, opsize
);
2010 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
2011 reg
= AREG(insn
, 9);
2012 tcg_gen_sub_i32(reg
, reg
, src
);
2015 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
2019 gen_flush_flags(s
); /* compute old Z */
2021 /* Perform substract with borrow.
2022 * (X, N) = dest - (src + X);
2025 tmp
= tcg_const_i32(0);
2026 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
2027 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
2028 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2029 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2031 /* Compute signed-overflow for substract. */
2033 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
2034 tcg_gen_xor_i32(tmp
, dest
, src
);
2035 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
2038 /* Copy the rest of the results into place. */
2039 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2040 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2042 set_cc_op(s
, CC_OP_FLAGS
);
2044 /* result is in QREG_CC_N */
2047 DISAS_INSN(subx_reg
)
2053 opsize
= insn_opsize(insn
);
2055 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
2056 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
2058 gen_subx(s
, src
, dest
, opsize
);
2060 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
2063 DISAS_INSN(subx_mem
)
2071 opsize
= insn_opsize(insn
);
2073 addr_src
= AREG(insn
, 0);
2074 tcg_gen_subi_i32(addr_src
, addr_src
, opsize
);
2075 src
= gen_load(s
, opsize
, addr_src
, 1);
2077 addr_dest
= AREG(insn
, 9);
2078 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize
);
2079 dest
= gen_load(s
, opsize
, addr_dest
, 1);
2081 gen_subx(s
, src
, dest
, opsize
);
2083 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
2091 val
= (insn
>> 9) & 7;
2094 src
= tcg_const_i32(val
);
2095 gen_logic_cc(s
, src
, OS_LONG
);
2096 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
2105 opsize
= insn_opsize(insn
);
2106 SRC_EA(env
, src
, opsize
, -1, NULL
);
2107 reg
= DREG(insn
, 9);
2108 gen_update_cc_add(reg
, src
);
2109 set_cc_op(s
, CC_OP_CMP
);
2123 SRC_EA(env
, src
, opsize
, 1, NULL
);
2124 reg
= AREG(insn
, 9);
2125 gen_update_cc_add(reg
, src
);
2126 set_cc_op(s
, CC_OP_CMP
);
2136 opsize
= insn_opsize(insn
);
2138 SRC_EA(env
, src
, opsize
, 0, &addr
);
2139 dest
= tcg_temp_new();
2140 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
2141 gen_logic_cc(s
, dest
, opsize
);
2142 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2145 static void do_exg(TCGv reg1
, TCGv reg2
)
2147 TCGv temp
= tcg_temp_new();
2148 tcg_gen_mov_i32(temp
, reg1
);
2149 tcg_gen_mov_i32(reg1
, reg2
);
2150 tcg_gen_mov_i32(reg2
, temp
);
2151 tcg_temp_free(temp
);
2156 /* exchange Dx and Dy */
2157 do_exg(DREG(insn
, 9), DREG(insn
, 0));
2162 /* exchange Ax and Ay */
2163 do_exg(AREG(insn
, 9), AREG(insn
, 0));
2168 /* exchange Dx and Ay */
2169 do_exg(DREG(insn
, 9), AREG(insn
, 0));
2180 dest
= tcg_temp_new();
2182 opsize
= insn_opsize(insn
);
2183 reg
= DREG(insn
, 9);
2185 SRC_EA(env
, src
, opsize
, 0, &addr
);
2186 tcg_gen_and_i32(dest
, src
, reg
);
2187 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2189 SRC_EA(env
, src
, opsize
, 0, NULL
);
2190 tcg_gen_and_i32(dest
, src
, reg
);
2191 gen_partset_reg(opsize
, reg
, dest
);
2193 tcg_temp_free(dest
);
2194 gen_logic_cc(s
, dest
, opsize
);
2202 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
2203 reg
= AREG(insn
, 9);
2204 tcg_gen_add_i32(reg
, reg
, src
);
2207 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
2211 gen_flush_flags(s
); /* compute old Z */
2213 /* Perform addition with carry.
2214 * (X, N) = src + dest + X;
2217 tmp
= tcg_const_i32(0);
2218 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
2219 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
2220 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2222 /* Compute signed-overflow for addition. */
2224 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
2225 tcg_gen_xor_i32(tmp
, dest
, src
);
2226 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
2229 /* Copy the rest of the results into place. */
2230 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2231 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2233 set_cc_op(s
, CC_OP_FLAGS
);
2235 /* result is in QREG_CC_N */
2238 DISAS_INSN(addx_reg
)
2244 opsize
= insn_opsize(insn
);
2246 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
2247 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
2249 gen_addx(s
, src
, dest
, opsize
);
2251 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
2254 DISAS_INSN(addx_mem
)
2262 opsize
= insn_opsize(insn
);
2264 addr_src
= AREG(insn
, 0);
2265 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
2266 src
= gen_load(s
, opsize
, addr_src
, 1);
2268 addr_dest
= AREG(insn
, 9);
2269 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
2270 dest
= gen_load(s
, opsize
, addr_dest
, 1);
2272 gen_addx(s
, src
, dest
, opsize
);
2274 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
2277 /* TODO: This could be implemented without helper functions. */
2278 DISAS_INSN(shift_im
)
2284 set_cc_op(s
, CC_OP_FLAGS
);
2286 reg
= DREG(insn
, 0);
2287 tmp
= (insn
>> 9) & 7;
2290 shift
= tcg_const_i32(tmp
);
2291 /* No need to flush flags becuse we know we will set C flag. */
2293 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
2296 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
2298 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
2303 DISAS_INSN(shift_reg
)
2308 reg
= DREG(insn
, 0);
2309 shift
= DREG(insn
, 9);
2311 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
2314 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
2316 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
2319 set_cc_op(s
, CC_OP_FLAGS
);
2325 reg
= DREG(insn
, 0);
2326 gen_logic_cc(s
, reg
, OS_LONG
);
2327 gen_helper_ff1(reg
, reg
);
2330 static TCGv
gen_get_sr(DisasContext
*s
)
2335 ccr
= gen_get_ccr(s
);
2336 sr
= tcg_temp_new();
2337 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2338 tcg_gen_or_i32(sr
, sr
, ccr
);
2348 ext
= read_im16(env
, s
);
2349 if (ext
!= 0x46FC) {
2350 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
2353 ext
= read_im16(env
, s
);
2354 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
2355 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
2358 gen_push(s
, gen_get_sr(s
));
2359 gen_set_sr_im(s
, ext
, 0);
2362 DISAS_INSN(move_from_sr
)
2366 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
2367 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2371 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
2374 DISAS_INSN(move_to_sr
)
2377 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2380 gen_set_sr(env
, s
, insn
, 0);
2384 DISAS_INSN(move_from_usp
)
2387 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2390 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
2391 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2394 DISAS_INSN(move_to_usp
)
2397 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2400 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
2401 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2406 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
2414 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2418 ext
= read_im16(env
, s
);
2420 gen_set_sr_im(s
, ext
, 0);
2421 tcg_gen_movi_i32(cpu_halted
, 1);
2422 gen_exception(s
, s
->pc
, EXCP_HLT
);
2428 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2431 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
2440 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2444 ext
= read_im16(env
, s
);
2447 reg
= AREG(ext
, 12);
2449 reg
= DREG(ext
, 12);
2451 gen_helper_movec(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
2458 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2461 /* ICache fetch. Implement as no-op. */
2467 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2470 /* Cache push/invalidate. Implement as no-op. */
2475 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2480 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2483 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2486 /* TODO: Implement wdebug. */
2487 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
2492 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
2495 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2496 immediately before the next FP instruction is executed. */
2510 ext
= read_im16(env
, s
);
2511 opmode
= ext
& 0x7f;
2512 switch ((ext
>> 13) & 7) {
2517 case 3: /* fmove out */
2519 tmp32
= tcg_temp_new_i32();
2521 /* ??? TODO: Proper behavior on overflow. */
2522 switch ((ext
>> 10) & 7) {
2525 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2529 gen_helper_f64_to_f32(tmp32
, cpu_env
, src
);
2533 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2535 case 5: /* OS_DOUBLE */
2536 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2537 switch ((insn
>> 3) & 7) {
2542 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2545 offset
= cpu_ldsw_code(env
, s
->pc
);
2547 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2552 gen_store64(s
, tmp32
, src
);
2553 switch ((insn
>> 3) & 7) {
2555 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2556 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2559 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2562 tcg_temp_free_i32(tmp32
);
2566 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2571 DEST_EA(env
, insn
, opsize
, tmp32
, NULL
);
2572 tcg_temp_free_i32(tmp32
);
2574 case 4: /* fmove to control register. */
2575 switch ((ext
>> 10) & 7) {
2577 /* Not implemented. Ignore writes. */
2582 cpu_abort(NULL
, "Unimplemented: fmove to control %d",
2586 case 5: /* fmove from control register. */
2587 switch ((ext
>> 10) & 7) {
2589 /* Not implemented. Always return zero. */
2590 tmp32
= tcg_const_i32(0);
2595 cpu_abort(NULL
, "Unimplemented: fmove from control %d",
2599 DEST_EA(env
, insn
, OS_LONG
, tmp32
, NULL
);
2601 case 6: /* fmovem */
2607 if ((ext
& 0x1f00) != 0x1000 || (ext
& 0xff) == 0)
2609 tmp32
= gen_lea(env
, s
, insn
, OS_LONG
);
2610 if (IS_NULL_QREG(tmp32
)) {
2614 addr
= tcg_temp_new_i32();
2615 tcg_gen_mov_i32(addr
, tmp32
);
2617 for (i
= 0; i
< 8; i
++) {
2620 if (ext
& (1 << 13)) {
2622 tcg_gen_qemu_stf64(dest
, addr
, IS_USER(s
));
2625 tcg_gen_qemu_ldf64(dest
, addr
, IS_USER(s
));
2627 if (ext
& (mask
- 1))
2628 tcg_gen_addi_i32(addr
, addr
, 8);
2632 tcg_temp_free_i32(addr
);
2636 if (ext
& (1 << 14)) {
2637 /* Source effective address. */
2638 switch ((ext
>> 10) & 7) {
2639 case 0: opsize
= OS_LONG
; break;
2640 case 1: opsize
= OS_SINGLE
; break;
2641 case 4: opsize
= OS_WORD
; break;
2642 case 5: opsize
= OS_DOUBLE
; break;
2643 case 6: opsize
= OS_BYTE
; break;
2647 if (opsize
== OS_DOUBLE
) {
2648 tmp32
= tcg_temp_new_i32();
2649 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2650 switch ((insn
>> 3) & 7) {
2655 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2658 offset
= cpu_ldsw_code(env
, s
->pc
);
2660 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2663 offset
= cpu_ldsw_code(env
, s
->pc
);
2664 offset
+= s
->pc
- 2;
2666 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2671 src
= gen_load64(s
, tmp32
);
2672 switch ((insn
>> 3) & 7) {
2674 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2675 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2678 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2681 tcg_temp_free_i32(tmp32
);
2683 SRC_EA(env
, tmp32
, opsize
, 1, NULL
);
2684 src
= tcg_temp_new_i64();
2689 gen_helper_i32_to_f64(src
, cpu_env
, tmp32
);
2692 gen_helper_f32_to_f64(src
, cpu_env
, tmp32
);
2697 /* Source register. */
2698 src
= FREG(ext
, 10);
2700 dest
= FREG(ext
, 7);
2701 res
= tcg_temp_new_i64();
2703 tcg_gen_mov_f64(res
, dest
);
2707 case 0: case 0x40: case 0x44: /* fmove */
2708 tcg_gen_mov_f64(res
, src
);
2711 gen_helper_iround_f64(res
, cpu_env
, src
);
2714 case 3: /* fintrz */
2715 gen_helper_itrunc_f64(res
, cpu_env
, src
);
2718 case 4: case 0x41: case 0x45: /* fsqrt */
2719 gen_helper_sqrt_f64(res
, cpu_env
, src
);
2721 case 0x18: case 0x58: case 0x5c: /* fabs */
2722 gen_helper_abs_f64(res
, src
);
2724 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2725 gen_helper_chs_f64(res
, src
);
2727 case 0x20: case 0x60: case 0x64: /* fdiv */
2728 gen_helper_div_f64(res
, cpu_env
, res
, src
);
2730 case 0x22: case 0x62: case 0x66: /* fadd */
2731 gen_helper_add_f64(res
, cpu_env
, res
, src
);
2733 case 0x23: case 0x63: case 0x67: /* fmul */
2734 gen_helper_mul_f64(res
, cpu_env
, res
, src
);
2736 case 0x28: case 0x68: case 0x6c: /* fsub */
2737 gen_helper_sub_f64(res
, cpu_env
, res
, src
);
2739 case 0x38: /* fcmp */
2740 gen_helper_sub_cmp_f64(res
, cpu_env
, res
, src
);
2744 case 0x3a: /* ftst */
2745 tcg_gen_mov_f64(res
, src
);
2752 if (ext
& (1 << 14)) {
2753 tcg_temp_free_i64(src
);
2756 if (opmode
& 0x40) {
2757 if ((opmode
& 0x4) != 0)
2759 } else if ((s
->fpcr
& M68K_FPCR_PREC
) == 0) {
2764 TCGv tmp
= tcg_temp_new_i32();
2765 gen_helper_f64_to_f32(tmp
, cpu_env
, res
);
2766 gen_helper_f32_to_f64(res
, cpu_env
, tmp
);
2767 tcg_temp_free_i32(tmp
);
2769 tcg_gen_mov_f64(QREG_FP_RESULT
, res
);
2771 tcg_gen_mov_f64(dest
, res
);
2773 tcg_temp_free_i64(res
);
2776 /* FIXME: Is this right for offset addressing modes? */
2778 disas_undef_fpu(env
, s
, insn
);
2789 offset
= cpu_ldsw_code(env
, s
->pc
);
2791 if (insn
& (1 << 6)) {
2792 offset
= (offset
<< 16) | read_im16(env
, s
);
2795 l1
= gen_new_label();
2796 /* TODO: Raise BSUN exception. */
2797 flag
= tcg_temp_new();
2798 gen_helper_compare_f64(flag
, cpu_env
, QREG_FP_RESULT
);
2799 /* Jump to l1 if condition is true. */
2800 switch (insn
& 0xf) {
2803 case 1: /* eq (=0) */
2804 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2806 case 2: /* ogt (=1) */
2807 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(1), l1
);
2809 case 3: /* oge (=0 or =1) */
2810 tcg_gen_brcond_i32(TCG_COND_LEU
, flag
, tcg_const_i32(1), l1
);
2812 case 4: /* olt (=-1) */
2813 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(0), l1
);
2815 case 5: /* ole (=-1 or =0) */
2816 tcg_gen_brcond_i32(TCG_COND_LE
, flag
, tcg_const_i32(0), l1
);
2818 case 6: /* ogl (=-1 or =1) */
2819 tcg_gen_andi_i32(flag
, flag
, 1);
2820 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2822 case 7: /* or (=2) */
2823 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(2), l1
);
2825 case 8: /* un (<2) */
2826 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(2), l1
);
2828 case 9: /* ueq (=0 or =2) */
2829 tcg_gen_andi_i32(flag
, flag
, 1);
2830 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2832 case 10: /* ugt (>0) */
2833 tcg_gen_brcond_i32(TCG_COND_GT
, flag
, tcg_const_i32(0), l1
);
2835 case 11: /* uge (>=0) */
2836 tcg_gen_brcond_i32(TCG_COND_GE
, flag
, tcg_const_i32(0), l1
);
2838 case 12: /* ult (=-1 or =2) */
2839 tcg_gen_brcond_i32(TCG_COND_GEU
, flag
, tcg_const_i32(2), l1
);
2841 case 13: /* ule (!=1) */
2842 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(1), l1
);
2844 case 14: /* ne (!=0) */
2845 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2851 gen_jmp_tb(s
, 0, s
->pc
);
2853 gen_jmp_tb(s
, 1, addr
+ offset
);
2856 DISAS_INSN(frestore
)
2858 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2860 /* TODO: Implement frestore. */
2861 cpu_abort(CPU(cpu
), "FRESTORE not implemented");
2866 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2868 /* TODO: Implement fsave. */
2869 cpu_abort(CPU(cpu
), "FSAVE not implemented");
2872 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
2874 TCGv tmp
= tcg_temp_new();
2875 if (s
->env
->macsr
& MACSR_FI
) {
2877 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
2879 tcg_gen_shli_i32(tmp
, val
, 16);
2880 } else if (s
->env
->macsr
& MACSR_SU
) {
2882 tcg_gen_sari_i32(tmp
, val
, 16);
2884 tcg_gen_ext16s_i32(tmp
, val
);
2887 tcg_gen_shri_i32(tmp
, val
, 16);
2889 tcg_gen_ext16u_i32(tmp
, val
);
2894 static void gen_mac_clear_flags(void)
2896 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
2897 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
2913 s
->mactmp
= tcg_temp_new_i64();
2917 ext
= read_im16(env
, s
);
2919 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
2920 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
2921 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
2922 disas_undef(env
, s
, insn
);
2926 /* MAC with load. */
2927 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2928 addr
= tcg_temp_new();
2929 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
2930 /* Load the value now to ensure correct exception behavior.
2931 Perform writeback after reading the MAC inputs. */
2932 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
2935 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
2936 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
2938 loadval
= addr
= NULL_QREG
;
2939 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2940 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2943 gen_mac_clear_flags();
2946 /* Disabled because conditional branches clobber temporary vars. */
2947 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
2948 /* Skip the multiply if we know we will ignore it. */
2949 l1
= gen_new_label();
2950 tmp
= tcg_temp_new();
2951 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
2952 gen_op_jmp_nz32(tmp
, l1
);
2956 if ((ext
& 0x0800) == 0) {
2958 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
2959 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
2961 if (s
->env
->macsr
& MACSR_FI
) {
2962 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
2964 if (s
->env
->macsr
& MACSR_SU
)
2965 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
2967 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
2968 switch ((ext
>> 9) & 3) {
2970 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
2973 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
2979 /* Save the overflow flag from the multiply. */
2980 saved_flags
= tcg_temp_new();
2981 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
2983 saved_flags
= NULL_QREG
;
2987 /* Disabled because conditional branches clobber temporary vars. */
2988 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
2989 /* Skip the accumulate if the value is already saturated. */
2990 l1
= gen_new_label();
2991 tmp
= tcg_temp_new();
2992 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2993 gen_op_jmp_nz32(tmp
, l1
);
2998 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
3000 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
3002 if (s
->env
->macsr
& MACSR_FI
)
3003 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
3004 else if (s
->env
->macsr
& MACSR_SU
)
3005 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
3007 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
3010 /* Disabled because conditional branches clobber temporary vars. */
3016 /* Dual accumulate variant. */
3017 acc
= (ext
>> 2) & 3;
3018 /* Restore the overflow flag from the multiplier. */
3019 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
3021 /* Disabled because conditional branches clobber temporary vars. */
3022 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
3023 /* Skip the accumulate if the value is already saturated. */
3024 l1
= gen_new_label();
3025 tmp
= tcg_temp_new();
3026 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
3027 gen_op_jmp_nz32(tmp
, l1
);
3031 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
3033 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
3034 if (s
->env
->macsr
& MACSR_FI
)
3035 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
3036 else if (s
->env
->macsr
& MACSR_SU
)
3037 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
3039 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
3041 /* Disabled because conditional branches clobber temporary vars. */
3046 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
3050 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
3051 tcg_gen_mov_i32(rw
, loadval
);
3052 /* FIXME: Should address writeback happen with the masked or
3054 switch ((insn
>> 3) & 7) {
3055 case 3: /* Post-increment. */
3056 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
3058 case 4: /* Pre-decrement. */
3059 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
3064 DISAS_INSN(from_mac
)
3070 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
3071 accnum
= (insn
>> 9) & 3;
3072 acc
= MACREG(accnum
);
3073 if (s
->env
->macsr
& MACSR_FI
) {
3074 gen_helper_get_macf(rx
, cpu_env
, acc
);
3075 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
3076 tcg_gen_extrl_i64_i32(rx
, acc
);
3077 } else if (s
->env
->macsr
& MACSR_SU
) {
3078 gen_helper_get_macs(rx
, acc
);
3080 gen_helper_get_macu(rx
, acc
);
3083 tcg_gen_movi_i64(acc
, 0);
3084 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
3088 DISAS_INSN(move_mac
)
3090 /* FIXME: This can be done without a helper. */
3094 dest
= tcg_const_i32((insn
>> 9) & 3);
3095 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
3096 gen_mac_clear_flags();
3097 gen_helper_mac_set_flags(cpu_env
, dest
);
3100 DISAS_INSN(from_macsr
)
3104 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
3105 tcg_gen_mov_i32(reg
, QREG_MACSR
);
3108 DISAS_INSN(from_mask
)
3111 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
3112 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
3115 DISAS_INSN(from_mext
)
3119 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
3120 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
3121 if (s
->env
->macsr
& MACSR_FI
)
3122 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
3124 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
3127 DISAS_INSN(macsr_to_ccr
)
3129 TCGv tmp
= tcg_temp_new();
3130 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
3131 gen_helper_set_sr(cpu_env
, tmp
);
3133 set_cc_op(s
, CC_OP_FLAGS
);
3141 accnum
= (insn
>> 9) & 3;
3142 acc
= MACREG(accnum
);
3143 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
3144 if (s
->env
->macsr
& MACSR_FI
) {
3145 tcg_gen_ext_i32_i64(acc
, val
);
3146 tcg_gen_shli_i64(acc
, acc
, 8);
3147 } else if (s
->env
->macsr
& MACSR_SU
) {
3148 tcg_gen_ext_i32_i64(acc
, val
);
3150 tcg_gen_extu_i32_i64(acc
, val
);
3152 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
3153 gen_mac_clear_flags();
3154 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
3157 DISAS_INSN(to_macsr
)
3160 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
3161 gen_helper_set_macsr(cpu_env
, val
);
3168 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
3169 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
3176 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
3177 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
3178 if (s
->env
->macsr
& MACSR_FI
)
3179 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
3180 else if (s
->env
->macsr
& MACSR_SU
)
3181 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
3183 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
3186 static disas_proc opcode_table
[65536];
3189 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
3195 /* Sanity check. All set bits must be included in the mask. */
3196 if (opcode
& ~mask
) {
3198 "qemu internal error: bogus opcode definition %04x/%04x\n",
3202 /* This could probably be cleverer. For now just optimize the case where
3203 the top bits are known. */
3204 /* Find the first zero bit in the mask. */
3206 while ((i
& mask
) != 0)
3208 /* Iterate over all combinations of this and lower bits. */
3213 from
= opcode
& ~(i
- 1);
3215 for (i
= from
; i
< to
; i
++) {
3216 if ((i
& mask
) == opcode
)
3217 opcode_table
[i
] = proc
;
3221 /* Register m68k opcode handlers. Order is important.
3222 Later insn override earlier ones. */
3223 void register_m68k_insns (CPUM68KState
*env
)
3225 /* Build the opcode table only once to avoid
3226 multithreading issues. */
3227 if (opcode_table
[0] != NULL
) {
3231 /* use BASE() for instruction available
3232 * for CF_ISA_A and M68000.
3234 #define BASE(name, opcode, mask) \
3235 register_opcode(disas_##name, 0x##opcode, 0x##mask)
3236 #define INSN(name, opcode, mask, feature) do { \
3237 if (m68k_feature(env, M68K_FEATURE_##feature)) \
3238 BASE(name, opcode, mask); \
3240 BASE(undef
, 0000, 0000);
3241 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
3242 INSN(arith_im
, 0000, ff00
, M68000
);
3243 INSN(undef
, 00c0
, ffc0
, M68000
);
3244 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
3245 BASE(bitop_reg
, 0100, f1c0
);
3246 BASE(bitop_reg
, 0140, f1c0
);
3247 BASE(bitop_reg
, 0180, f1c0
);
3248 BASE(bitop_reg
, 01c0
, f1c0
);
3249 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
3250 INSN(arith_im
, 0200, ff00
, M68000
);
3251 INSN(undef
, 02c0
, ffc0
, M68000
);
3252 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
3253 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
3254 INSN(arith_im
, 0400, ff00
, M68000
);
3255 INSN(undef
, 04c0
, ffc0
, M68000
);
3256 INSN(arith_im
, 0600, ff00
, M68000
);
3257 INSN(undef
, 06c0
, ffc0
, M68000
);
3258 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
3259 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
3260 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
3261 INSN(arith_im
, 0c00
, ff00
, M68000
);
3262 BASE(bitop_im
, 0800, ffc0
);
3263 BASE(bitop_im
, 0840, ffc0
);
3264 BASE(bitop_im
, 0880, ffc0
);
3265 BASE(bitop_im
, 08c0
, ffc0
);
3266 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
3267 INSN(arith_im
, 0a00
, ff00
, M68000
);
3268 BASE(move
, 1000, f000
);
3269 BASE(move
, 2000, f000
);
3270 BASE(move
, 3000, f000
);
3271 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
3272 INSN(negx
, 4080, fff8
, CF_ISA_A
);
3273 INSN(negx
, 4000, ff00
, M68000
);
3274 INSN(undef
, 40c0
, ffc0
, M68000
);
3275 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
3276 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
3277 BASE(lea
, 41c0
, f1c0
);
3278 BASE(clr
, 4200, ff00
);
3279 BASE(undef
, 42c0
, ffc0
);
3280 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
3281 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
3282 INSN(neg
, 4480, fff8
, CF_ISA_A
);
3283 INSN(neg
, 4400, ff00
, M68000
);
3284 INSN(undef
, 44c0
, ffc0
, M68000
);
3285 BASE(move_to_ccr
, 44c0
, ffc0
);
3286 INSN(not, 4680, fff8
, CF_ISA_A
);
3287 INSN(not, 4600, ff00
, M68000
);
3288 INSN(undef
, 46c0
, ffc0
, M68000
);
3289 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
3290 INSN(linkl
, 4808, fff8
, M68000
);
3291 BASE(pea
, 4840, ffc0
);
3292 BASE(swap
, 4840, fff8
);
3293 INSN(bkpt
, 4848, fff8
, BKPT
);
3294 BASE(movem
, 48c0
, fbc0
);
3295 BASE(ext
, 4880, fff8
);
3296 BASE(ext
, 48c0
, fff8
);
3297 BASE(ext
, 49c0
, fff8
);
3298 BASE(tst
, 4a00
, ff00
);
3299 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
3300 INSN(tas
, 4ac0
, ffc0
, M68000
);
3301 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
3302 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
3303 BASE(illegal
, 4afc
, ffff
);
3304 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
3305 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
3306 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
3307 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
3308 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
3309 BASE(trap
, 4e40
, fff0
);
3310 BASE(link
, 4e50
, fff8
);
3311 BASE(unlk
, 4e58
, fff8
);
3312 INSN(move_to_usp
, 4e60
, fff8
, USP
);
3313 INSN(move_from_usp
, 4e68
, fff8
, USP
);
3314 BASE(nop
, 4e71
, ffff
);
3315 BASE(stop
, 4e72
, ffff
);
3316 BASE(rte
, 4e73
, ffff
);
3317 BASE(rts
, 4e75
, ffff
);
3318 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
3319 BASE(jump
, 4e80
, ffc0
);
3320 INSN(jump
, 4ec0
, ffc0
, CF_ISA_A
);
3321 INSN(addsubq
, 5180, f1c0
, CF_ISA_A
);
3322 INSN(jump
, 4ec0
, ffc0
, M68000
);
3323 INSN(addsubq
, 5000, f080
, M68000
);
3324 INSN(addsubq
, 5080, f0c0
, M68000
);
3325 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
3326 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
3327 INSN(dbcc
, 50c8
, f0f8
, M68000
);
3328 INSN(addsubq
, 5080, f1c0
, CF_ISA_A
);
3329 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
3331 /* Branch instructions. */
3332 BASE(branch
, 6000, f000
);
3333 /* Disable long branch instructions, then add back the ones we want. */
3334 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
3335 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
3336 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
3337 INSN(branch
, 60ff
, ffff
, BRAL
);
3338 INSN(branch
, 60ff
, f0ff
, BCCL
);
3340 BASE(moveq
, 7000, f100
);
3341 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
3342 BASE(or, 8000, f000
);
3343 BASE(divw
, 80c0
, f0c0
);
3344 BASE(addsub
, 9000, f000
);
3345 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
3346 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
3347 INSN(subx_reg
, 9100, f138
, M68000
);
3348 INSN(subx_mem
, 9108, f138
, M68000
);
3349 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
3350 INSN(suba
, 90c0
, f0c0
, M68000
);
3352 BASE(undef_mac
, a000
, f000
);
3353 INSN(mac
, a000
, f100
, CF_EMAC
);
3354 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
3355 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
3356 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
3357 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
3358 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
3359 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
3360 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
3361 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
3362 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
3363 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
3365 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
3366 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
3367 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
3368 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
3369 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
3370 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
3371 INSN(cmp
, b000
, f100
, M68000
);
3372 INSN(eor
, b100
, f100
, M68000
);
3373 INSN(cmpa
, b0c0
, f0c0
, M68000
);
3374 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
3375 BASE(and, c000
, f000
);
3376 INSN(exg_dd
, c140
, f1f8
, M68000
);
3377 INSN(exg_aa
, c148
, f1f8
, M68000
);
3378 INSN(exg_da
, c188
, f1f8
, M68000
);
3379 BASE(mulw
, c0c0
, f0c0
);
3380 BASE(addsub
, d000
, f000
);
3381 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
3382 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
3383 INSN(addx_reg
, d100
, f138
, M68000
);
3384 INSN(addx_mem
, d108
, f138
, M68000
);
3385 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
3386 INSN(adda
, d0c0
, f0c0
, M68000
);
3387 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
3388 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
3389 INSN(undef_fpu
, f000
, f000
, CF_ISA_A
);
3390 INSN(fpu
, f200
, ffc0
, CF_FPU
);
3391 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
3392 INSN(frestore
, f340
, ffc0
, CF_FPU
);
3393 INSN(fsave
, f340
, ffc0
, CF_FPU
);
3394 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
3395 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
3396 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
3397 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
3401 /* ??? Some of this implementation is not exception safe. We should always
3402 write back the result to memory before setting the condition codes. */
3403 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
3407 insn
= read_im16(env
, s
);
3409 opcode_table
[insn
](env
, s
, insn
);
3412 /* generate intermediate code for basic block 'tb'. */
3413 void gen_intermediate_code(CPUM68KState
*env
, TranslationBlock
*tb
)
3415 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
3416 CPUState
*cs
= CPU(cpu
);
3417 DisasContext dc1
, *dc
= &dc1
;
3418 target_ulong pc_start
;
3423 /* generate intermediate code */
3429 dc
->is_jmp
= DISAS_NEXT
;
3431 dc
->cc_op
= CC_OP_DYNAMIC
;
3432 dc
->cc_op_synced
= 1;
3433 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3434 dc
->fpcr
= env
->fpcr
;
3435 dc
->user
= (env
->sr
& SR_S
) == 0;
3438 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3439 if (max_insns
== 0) {
3440 max_insns
= CF_COUNT_MASK
;
3442 if (max_insns
> TCG_MAX_INSNS
) {
3443 max_insns
= TCG_MAX_INSNS
;
3448 pc_offset
= dc
->pc
- pc_start
;
3449 gen_throws_exception
= NULL
;
3450 tcg_gen_insn_start(dc
->pc
, dc
->cc_op
);
3453 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3454 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
3455 dc
->is_jmp
= DISAS_JUMP
;
3456 /* The address covered by the breakpoint must be included in
3457 [tb->pc, tb->pc + tb->size) in order to for it to be
3458 properly cleared -- thus we increment the PC here so that
3459 the logic setting tb->size below does the right thing. */
3464 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3468 dc
->insn_pc
= dc
->pc
;
3469 disas_m68k_insn(env
, dc
);
3470 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
3471 !cs
->singlestep_enabled
&&
3473 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
3474 num_insns
< max_insns
);
3476 if (tb
->cflags
& CF_LAST_IO
)
3478 if (unlikely(cs
->singlestep_enabled
)) {
3479 /* Make sure the pc is updated, and raise a debug exception. */
3482 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
3484 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
3486 switch(dc
->is_jmp
) {
3489 gen_jmp_tb(dc
, 0, dc
->pc
);
3495 /* indicate that the hash table must be used to find the next TB */
3499 /* nothing more to generate */
3503 gen_tb_end(tb
, num_insns
);
3506 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
3507 && qemu_log_in_addr_range(pc_start
)) {
3508 qemu_log("----------------\n");
3509 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3510 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
3514 tb
->size
= dc
->pc
- pc_start
;
3515 tb
->icount
= num_insns
;
3518 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3521 M68kCPU
*cpu
= M68K_CPU(cs
);
3522 CPUM68KState
*env
= &cpu
->env
;
3526 for (i
= 0; i
< 8; i
++)
3528 u
.d
= env
->fregs
[i
];
3529 cpu_fprintf(f
, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3530 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
3531 i
, u
.l
.upper
, u
.l
.lower
, *(double *)&u
.d
);
3533 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
3534 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
3535 cpu_fprintf(f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& CCF_X
) ? 'X' : '-',
3536 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
3537 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
3538 cpu_fprintf (f
, "FPRESULT = %12g\n", *(double *)&env
->fp_result
);
3541 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
3544 int cc_op
= data
[1];
3546 if (cc_op
!= CC_OP_DYNAMIC
) {