4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
36 //#define DEBUG_DISPATCH 1
38 /* Fake floating point. */
39 #define tcg_gen_mov_f64 tcg_gen_mov_i64
40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
43 #define DEFO32(name, offset) static TCGv QREG_##name;
44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
51 static TCGv_i32 cpu_halted
;
52 static TCGv_i32 cpu_exception_index
;
54 static TCGv_env cpu_env
;
56 static char cpu_reg_names
[3*8*3 + 5*4];
57 static TCGv cpu_dregs
[8];
58 static TCGv cpu_aregs
[8];
59 static TCGv_i64 cpu_fregs
[8];
60 static TCGv_i64 cpu_macc
[4];
62 #define REG(insn, pos) (((insn) >> (pos)) & 7)
63 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
64 #define AREG(insn, pos) cpu_aregs[REG(insn, pos)]
65 #define FREG(insn, pos) cpu_fregs[REG(insn, pos)]
66 #define MACREG(acc) cpu_macc[acc]
67 #define QREG_SP cpu_aregs[7]
69 static TCGv NULL_QREG
;
70 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
71 /* Used to distinguish stores from bad addressing modes. */
72 static TCGv store_dummy
;
74 #include "exec/gen-icount.h"
76 void m68k_tcg_init(void)
81 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
82 tcg_ctx
.tcg_env
= cpu_env
;
84 #define DEFO32(name, offset) \
85 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFO64(name, offset) \
88 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
89 offsetof(CPUM68KState, offset), #name);
90 #define DEFF64(name, offset) DEFO64(name, offset)
96 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
97 -offsetof(M68kCPU
, env
) +
98 offsetof(CPUState
, halted
), "HALTED");
99 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
100 -offsetof(M68kCPU
, env
) +
101 offsetof(CPUState
, exception_index
),
105 for (i
= 0; i
< 8; i
++) {
106 sprintf(p
, "D%d", i
);
107 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
108 offsetof(CPUM68KState
, dregs
[i
]), p
);
110 sprintf(p
, "A%d", i
);
111 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
112 offsetof(CPUM68KState
, aregs
[i
]), p
);
114 sprintf(p
, "F%d", i
);
115 cpu_fregs
[i
] = tcg_global_mem_new_i64(cpu_env
,
116 offsetof(CPUM68KState
, fregs
[i
]), p
);
119 for (i
= 0; i
< 4; i
++) {
120 sprintf(p
, "ACC%d", i
);
121 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
122 offsetof(CPUM68KState
, macc
[i
]), p
);
126 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
127 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
130 /* internal defines */
131 typedef struct DisasContext
{
133 target_ulong insn_pc
; /* Start of the current instruction. */
136 CCOp cc_op
; /* Current CC operation */
140 struct TranslationBlock
*tb
;
141 int singlestep_enabled
;
146 #define DISAS_JUMP_NEXT 4
148 #if defined(CONFIG_USER_ONLY)
151 #define IS_USER(s) s->user
154 /* XXX: move that elsewhere */
155 /* ??? Fix exceptions. */
156 static void *gen_throws_exception
;
157 #define gen_last_qop NULL
159 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
161 #ifdef DEBUG_DISPATCH
162 #define DISAS_INSN(name) \
163 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
165 static void disas_##name(CPUM68KState *env, DisasContext *s, \
168 qemu_log("Dispatch " #name "\n"); \
169 real_disas_##name(env, s, insn); \
171 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
174 #define DISAS_INSN(name) \
175 static void disas_##name(CPUM68KState *env, DisasContext *s, \
179 static const uint8_t cc_op_live
[CC_OP_NB
] = {
180 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
181 [CC_OP_ADD
] = CCF_X
| CCF_N
| CCF_V
,
182 [CC_OP_SUB
] = CCF_X
| CCF_N
| CCF_V
,
183 [CC_OP_CMP
] = CCF_X
| CCF_N
| CCF_V
,
184 [CC_OP_LOGIC
] = CCF_X
| CCF_N
187 static void set_cc_op(DisasContext
*s
, CCOp op
)
189 CCOp old_op
= s
->cc_op
;
198 /* Discard CC computation that will no longer be used.
199 Note that X and N are never dead. */
200 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
202 tcg_gen_discard_i32(QREG_CC_C
);
205 tcg_gen_discard_i32(QREG_CC_Z
);
208 tcg_gen_discard_i32(QREG_CC_V
);
212 /* Update the CPU env CC_OP state. */
213 static void update_cc_op(DisasContext
*s
)
215 if (!s
->cc_op_synced
) {
217 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
221 /* Generate a load from the specified address. Narrow values are
222 sign extended to full register width. */
223 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
226 int index
= IS_USER(s
);
227 tmp
= tcg_temp_new_i32();
231 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
233 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
237 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
239 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
243 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
246 g_assert_not_reached();
248 gen_throws_exception
= gen_last_qop
;
252 static inline TCGv_i64
gen_load64(DisasContext
* s
, TCGv addr
)
255 int index
= IS_USER(s
);
256 tmp
= tcg_temp_new_i64();
257 tcg_gen_qemu_ldf64(tmp
, addr
, index
);
258 gen_throws_exception
= gen_last_qop
;
262 /* Generate a store. */
263 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
265 int index
= IS_USER(s
);
268 tcg_gen_qemu_st8(val
, addr
, index
);
271 tcg_gen_qemu_st16(val
, addr
, index
);
275 tcg_gen_qemu_st32(val
, addr
, index
);
278 g_assert_not_reached();
280 gen_throws_exception
= gen_last_qop
;
283 static inline void gen_store64(DisasContext
*s
, TCGv addr
, TCGv_i64 val
)
285 int index
= IS_USER(s
);
286 tcg_gen_qemu_stf64(val
, addr
, index
);
287 gen_throws_exception
= gen_last_qop
;
296 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
297 otherwise generate a store. */
298 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
301 if (what
== EA_STORE
) {
302 gen_store(s
, opsize
, addr
, val
);
305 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
309 /* Read a 16-bit immediate constant */
310 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
313 im
= cpu_lduw_code(env
, s
->pc
);
318 /* Read an 8-bit immediate constant */
319 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
321 return read_im16(env
, s
);
324 /* Read a 32-bit immediate constant. */
325 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
328 im
= read_im16(env
, s
) << 16;
329 im
|= 0xffff & read_im16(env
, s
);
333 /* Calculate and address index. */
334 static TCGv
gen_addr_index(uint16_t ext
, TCGv tmp
)
339 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
340 if ((ext
& 0x800) == 0) {
341 tcg_gen_ext16s_i32(tmp
, add
);
344 scale
= (ext
>> 9) & 3;
346 tcg_gen_shli_i32(tmp
, add
, scale
);
352 /* Handle a base + index + displacement effective addresss.
353 A NULL_QREG base means pc-relative. */
354 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
363 ext
= read_im16(env
, s
);
365 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
368 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
369 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
374 /* full extension word format */
375 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
378 if ((ext
& 0x30) > 0x10) {
379 /* base displacement */
380 if ((ext
& 0x30) == 0x20) {
381 bd
= (int16_t)read_im16(env
, s
);
383 bd
= read_im32(env
, s
);
388 tmp
= tcg_temp_new();
389 if ((ext
& 0x44) == 0) {
391 add
= gen_addr_index(ext
, tmp
);
395 if ((ext
& 0x80) == 0) {
396 /* base not suppressed */
397 if (IS_NULL_QREG(base
)) {
398 base
= tcg_const_i32(offset
+ bd
);
401 if (!IS_NULL_QREG(add
)) {
402 tcg_gen_add_i32(tmp
, add
, base
);
408 if (!IS_NULL_QREG(add
)) {
410 tcg_gen_addi_i32(tmp
, add
, bd
);
414 add
= tcg_const_i32(bd
);
416 if ((ext
& 3) != 0) {
417 /* memory indirect */
418 base
= gen_load(s
, OS_LONG
, add
, 0);
419 if ((ext
& 0x44) == 4) {
420 add
= gen_addr_index(ext
, tmp
);
421 tcg_gen_add_i32(tmp
, add
, base
);
427 /* outer displacement */
428 if ((ext
& 3) == 2) {
429 od
= (int16_t)read_im16(env
, s
);
431 od
= read_im32(env
, s
);
437 tcg_gen_addi_i32(tmp
, add
, od
);
442 /* brief extension word format */
443 tmp
= tcg_temp_new();
444 add
= gen_addr_index(ext
, tmp
);
445 if (!IS_NULL_QREG(base
)) {
446 tcg_gen_add_i32(tmp
, add
, base
);
448 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
450 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
457 /* Evaluate all the CC flags. */
459 static void gen_flush_flags(DisasContext
*s
)
468 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
469 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
470 /* Compute signed overflow for addition. */
473 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
474 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
475 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
477 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
482 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
483 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
484 /* Compute signed overflow for subtraction. */
487 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
488 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
489 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
491 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
496 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
497 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
498 /* Compute signed overflow for subtraction. */
500 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
501 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
502 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
504 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
508 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
509 tcg_gen_movi_i32(QREG_CC_C
, 0);
510 tcg_gen_movi_i32(QREG_CC_V
, 0);
514 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
518 t0
= tcg_const_i32(s
->cc_op
);
519 gen_helper_flush_flags(cpu_env
, t0
);
524 /* Note that flush_flags also assigned to env->cc_op. */
525 s
->cc_op
= CC_OP_FLAGS
;
529 /* Sign or zero extend a value. */
531 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
536 tcg_gen_ext8s_i32(res
, val
);
538 tcg_gen_ext8u_i32(res
, val
);
543 tcg_gen_ext16s_i32(res
, val
);
545 tcg_gen_ext16u_i32(res
, val
);
549 tcg_gen_mov_i32(res
, val
);
552 g_assert_not_reached();
556 static TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
560 if (opsize
== OS_LONG
) {
563 tmp
= tcg_temp_new();
564 gen_ext(tmp
, val
, opsize
, sign
);
570 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
572 gen_ext(QREG_CC_N
, val
, opsize
, 1);
573 set_cc_op(s
, CC_OP_LOGIC
);
576 static void gen_update_cc_add(TCGv dest
, TCGv src
)
578 tcg_gen_mov_i32(QREG_CC_N
, dest
);
579 tcg_gen_mov_i32(QREG_CC_V
, src
);
582 static inline int opsize_bytes(int opsize
)
585 case OS_BYTE
: return 1;
586 case OS_WORD
: return 2;
587 case OS_LONG
: return 4;
588 case OS_SINGLE
: return 4;
589 case OS_DOUBLE
: return 8;
590 case OS_EXTENDED
: return 12;
591 case OS_PACKED
: return 12;
593 g_assert_not_reached();
597 static inline int insn_opsize(int insn
)
599 switch ((insn
>> 6) & 3) {
600 case 0: return OS_BYTE
;
601 case 1: return OS_WORD
;
602 case 2: return OS_LONG
;
604 g_assert_not_reached();
608 /* Assign value to a register. If the width is less than the register width
609 only the low part of the register is set. */
610 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
615 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
616 tmp
= tcg_temp_new();
617 tcg_gen_ext8u_i32(tmp
, val
);
618 tcg_gen_or_i32(reg
, reg
, tmp
);
621 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
622 tmp
= tcg_temp_new();
623 tcg_gen_ext16u_i32(tmp
, val
);
624 tcg_gen_or_i32(reg
, reg
, tmp
);
628 tcg_gen_mov_i32(reg
, val
);
631 g_assert_not_reached();
635 /* Generate code for an "effective address". Does not adjust the base
636 register for autoincrement addressing modes. */
637 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
645 switch ((insn
>> 3) & 7) {
646 case 0: /* Data register direct. */
647 case 1: /* Address register direct. */
649 case 2: /* Indirect register */
650 case 3: /* Indirect postincrement. */
651 return AREG(insn
, 0);
652 case 4: /* Indirect predecrememnt. */
654 tmp
= tcg_temp_new();
655 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
657 case 5: /* Indirect displacement. */
659 tmp
= tcg_temp_new();
660 ext
= read_im16(env
, s
);
661 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
663 case 6: /* Indirect index + displacement. */
665 return gen_lea_indexed(env
, s
, reg
);
668 case 0: /* Absolute short. */
669 offset
= (int16_t)read_im16(env
, s
);
670 return tcg_const_i32(offset
);
671 case 1: /* Absolute long. */
672 offset
= read_im32(env
, s
);
673 return tcg_const_i32(offset
);
674 case 2: /* pc displacement */
676 offset
+= (int16_t)read_im16(env
, s
);
677 return tcg_const_i32(offset
);
678 case 3: /* pc index+displacement. */
679 return gen_lea_indexed(env
, s
, NULL_QREG
);
680 case 4: /* Immediate. */
685 /* Should never happen. */
689 /* Helper function for gen_ea. Reuse the computed address between the
690 for read/write operands. */
691 static inline TCGv
gen_ea_once(CPUM68KState
*env
, DisasContext
*s
,
692 uint16_t insn
, int opsize
, TCGv val
,
693 TCGv
*addrp
, ea_what what
)
697 if (addrp
&& what
== EA_STORE
) {
700 tmp
= gen_lea(env
, s
, insn
, opsize
);
701 if (IS_NULL_QREG(tmp
))
706 return gen_ldst(s
, opsize
, tmp
, val
, what
);
709 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
710 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
711 ADDRP is non-null for readwrite operands. */
712 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
713 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
719 switch ((insn
>> 3) & 7) {
720 case 0: /* Data register direct. */
722 if (what
== EA_STORE
) {
723 gen_partset_reg(opsize
, reg
, val
);
726 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
728 case 1: /* Address register direct. */
730 if (what
== EA_STORE
) {
731 tcg_gen_mov_i32(reg
, val
);
734 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
736 case 2: /* Indirect register */
738 return gen_ldst(s
, opsize
, reg
, val
, what
);
739 case 3: /* Indirect postincrement. */
741 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
742 /* ??? This is not exception safe. The instruction may still
743 fault after this point. */
744 if (what
== EA_STORE
|| !addrp
)
745 tcg_gen_addi_i32(reg
, reg
, opsize_bytes(opsize
));
747 case 4: /* Indirect predecrememnt. */
750 if (addrp
&& what
== EA_STORE
) {
753 tmp
= gen_lea(env
, s
, insn
, opsize
);
754 if (IS_NULL_QREG(tmp
))
759 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
760 /* ??? This is not exception safe. The instruction may still
761 fault after this point. */
762 if (what
== EA_STORE
|| !addrp
) {
764 tcg_gen_mov_i32(reg
, tmp
);
768 case 5: /* Indirect displacement. */
769 case 6: /* Indirect index + displacement. */
770 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
773 case 0: /* Absolute short. */
774 case 1: /* Absolute long. */
775 case 2: /* pc displacement */
776 case 3: /* pc index+displacement. */
777 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
778 case 4: /* Immediate. */
779 /* Sign extend values for consistency. */
782 if (what
== EA_LOADS
) {
783 offset
= (int8_t)read_im8(env
, s
);
785 offset
= read_im8(env
, s
);
789 if (what
== EA_LOADS
) {
790 offset
= (int16_t)read_im16(env
, s
);
792 offset
= read_im16(env
, s
);
796 offset
= read_im32(env
, s
);
799 g_assert_not_reached();
801 return tcg_const_i32(offset
);
806 /* Should never happen. */
818 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
824 /* The CC_OP_CMP form can handle most normal comparisons directly. */
825 if (op
== CC_OP_CMP
) {
832 tcond
= TCG_COND_LEU
;
836 tcond
= TCG_COND_LTU
;
845 c
->v2
= tcg_const_i32(0);
846 c
->v1
= tmp
= tcg_temp_new();
847 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
862 c
->v2
= tcg_const_i32(0);
868 tcond
= TCG_COND_NEVER
;
870 case 14: /* GT (!(Z || (N ^ V))) */
871 case 15: /* LE (Z || (N ^ V)) */
872 /* Logic operations clear V, which simplifies LE to (Z || N),
873 and since Z and N are co-located, this becomes a normal
875 if (op
== CC_OP_LOGIC
) {
881 case 12: /* GE (!(N ^ V)) */
882 case 13: /* LT (N ^ V) */
883 /* Logic operations clear V, which simplifies this to N. */
884 if (op
!= CC_OP_LOGIC
) {
888 case 10: /* PL (!N) */
889 case 11: /* MI (N) */
890 /* Several cases represent N normally. */
891 if (op
== CC_OP_ADD
|| op
== CC_OP_SUB
|| op
== CC_OP_LOGIC
) {
897 case 6: /* NE (!Z) */
899 /* Some cases fold Z into N. */
900 if (op
== CC_OP_ADD
|| op
== CC_OP_SUB
|| op
== CC_OP_LOGIC
) {
906 case 4: /* CC (!C) */
908 /* Some cases fold C into X. */
909 if (op
== CC_OP_ADD
|| op
== CC_OP_SUB
) {
915 case 8: /* VC (!V) */
917 /* Logic operations clear V and C. */
918 if (op
== CC_OP_LOGIC
) {
919 tcond
= TCG_COND_NEVER
;
926 /* Otherwise, flush flag state to CC_OP_FLAGS. */
933 /* Invalid, or handled above. */
935 case 2: /* HI (!C && !Z) -> !(C || Z)*/
936 case 3: /* LS (C || Z) */
937 c
->v1
= tmp
= tcg_temp_new();
939 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
940 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
943 case 4: /* CC (!C) */
948 case 6: /* NE (!Z) */
953 case 8: /* VC (!V) */
958 case 10: /* PL (!N) */
959 case 11: /* MI (N) */
963 case 12: /* GE (!(N ^ V)) */
964 case 13: /* LT (N ^ V) */
965 c
->v1
= tmp
= tcg_temp_new();
967 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
970 case 14: /* GT (!(Z || (N ^ V))) */
971 case 15: /* LE (Z || (N ^ V)) */
972 c
->v1
= tmp
= tcg_temp_new();
974 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
975 tcg_gen_neg_i32(tmp
, tmp
);
976 tmp2
= tcg_temp_new();
977 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
978 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
985 if ((cond
& 1) == 0) {
986 tcond
= tcg_invert_cond(tcond
);
991 static void free_cond(DisasCompare
*c
)
994 tcg_temp_free(c
->v1
);
997 tcg_temp_free(c
->v2
);
1001 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1005 gen_cc_cond(&c
, s
, cond
);
1007 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1011 /* Force a TB lookup after an instruction that changes the CPU state. */
1012 static void gen_lookup_tb(DisasContext
*s
)
1015 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1016 s
->is_jmp
= DISAS_UPDATE
;
1019 /* Generate a jump to an immediate address. */
1020 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
1023 tcg_gen_movi_i32(QREG_PC
, dest
);
1024 s
->is_jmp
= DISAS_JUMP
;
1027 /* Generate a jump to the address in qreg DEST. */
1028 static void gen_jmp(DisasContext
*s
, TCGv dest
)
1031 tcg_gen_mov_i32(QREG_PC
, dest
);
1032 s
->is_jmp
= DISAS_JUMP
;
1035 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
1038 gen_jmp_im(s
, where
);
1039 gen_helper_raise_exception(cpu_env
, tcg_const_i32(nr
));
1042 static inline void gen_addr_fault(DisasContext
*s
)
1044 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
1047 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1048 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1049 op_sign ? EA_LOADS : EA_LOADU); \
1050 if (IS_NULL_QREG(result)) { \
1051 gen_addr_fault(s); \
1056 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1057 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1058 if (IS_NULL_QREG(ea_result)) { \
1059 gen_addr_fault(s); \
1064 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1066 #ifndef CONFIG_USER_ONLY
1067 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
1068 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1074 /* Generate a jump to an immediate address. */
1075 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1077 if (unlikely(s
->singlestep_enabled
)) {
1078 gen_exception(s
, dest
, EXCP_DEBUG
);
1079 } else if (use_goto_tb(s
, dest
)) {
1081 tcg_gen_movi_i32(QREG_PC
, dest
);
1082 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1084 gen_jmp_im(s
, dest
);
1087 s
->is_jmp
= DISAS_TB_JUMP
;
1096 cond
= (insn
>> 8) & 0xf;
1097 gen_cc_cond(&c
, s
, cond
);
1099 tmp
= tcg_temp_new();
1100 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1103 tcg_gen_neg_i32(tmp
, tmp
);
1104 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1108 DISAS_INSN(undef_mac
)
1110 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
1113 DISAS_INSN(undef_fpu
)
1115 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
1120 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
1122 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
1123 cpu_abort(CPU(cpu
), "Illegal instruction: %04x @ %08x", insn
, s
->pc
- 2);
1133 sign
= (insn
& 0x100) != 0;
1134 reg
= DREG(insn
, 9);
1135 tmp
= tcg_temp_new();
1137 tcg_gen_ext16s_i32(tmp
, reg
);
1139 tcg_gen_ext16u_i32(tmp
, reg
);
1140 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1141 tcg_gen_mul_i32(tmp
, tmp
, src
);
1142 tcg_gen_mov_i32(reg
, tmp
);
1143 gen_logic_cc(s
, tmp
, OS_WORD
);
1153 sign
= (insn
& 0x100) != 0;
1154 reg
= DREG(insn
, 9);
1156 tcg_gen_ext16s_i32(QREG_DIV1
, reg
);
1158 tcg_gen_ext16u_i32(QREG_DIV1
, reg
);
1160 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1161 tcg_gen_mov_i32(QREG_DIV2
, src
);
1163 gen_helper_divs(cpu_env
, tcg_const_i32(1));
1165 gen_helper_divu(cpu_env
, tcg_const_i32(1));
1168 tmp
= tcg_temp_new();
1169 src
= tcg_temp_new();
1170 tcg_gen_ext16u_i32(tmp
, QREG_DIV1
);
1171 tcg_gen_shli_i32(src
, QREG_DIV2
, 16);
1172 tcg_gen_or_i32(reg
, tmp
, src
);
1174 set_cc_op(s
, CC_OP_FLAGS
);
1184 ext
= read_im16(env
, s
);
1186 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1189 num
= DREG(ext
, 12);
1191 tcg_gen_mov_i32(QREG_DIV1
, num
);
1192 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1193 tcg_gen_mov_i32(QREG_DIV2
, den
);
1195 gen_helper_divs(cpu_env
, tcg_const_i32(0));
1197 gen_helper_divu(cpu_env
, tcg_const_i32(0));
1199 if ((ext
& 7) == ((ext
>> 12) & 7)) {
1201 tcg_gen_mov_i32 (reg
, QREG_DIV1
);
1204 tcg_gen_mov_i32 (reg
, QREG_DIV2
);
1206 set_cc_op(s
, CC_OP_FLAGS
);
1218 add
= (insn
& 0x4000) != 0;
1219 reg
= DREG(insn
, 9);
1220 dest
= tcg_temp_new();
1222 SRC_EA(env
, tmp
, OS_LONG
, 0, &addr
);
1226 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1229 tcg_gen_add_i32(dest
, tmp
, src
);
1230 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1231 set_cc_op(s
, CC_OP_ADD
);
1233 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1234 tcg_gen_sub_i32(dest
, tmp
, src
);
1235 set_cc_op(s
, CC_OP_SUB
);
1237 gen_update_cc_add(dest
, src
);
1239 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1241 tcg_gen_mov_i32(reg
, dest
);
1246 /* Reverse the order of the bits in REG. */
1250 reg
= DREG(insn
, 0);
1251 gen_helper_bitrev(reg
, reg
);
1254 DISAS_INSN(bitop_reg
)
1264 if ((insn
& 0x38) != 0)
1268 op
= (insn
>> 6) & 3;
1272 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1273 src2
= DREG(insn
, 9);
1274 dest
= tcg_temp_new();
1276 tmp
= tcg_temp_new();
1277 if (opsize
== OS_BYTE
)
1278 tcg_gen_andi_i32(tmp
, src2
, 7);
1280 tcg_gen_andi_i32(tmp
, src2
, 31);
1282 src2
= tcg_const_i32(1);
1283 tcg_gen_shl_i32(src2
, src2
, tmp
);
1286 tcg_gen_and_i32(QREG_CC_Z
, src1
, src2
);
1290 tcg_gen_xor_i32(dest
, src1
, src2
);
1293 tcg_gen_andc_i32(dest
, src1
, src2
);
1296 tcg_gen_or_i32(dest
, src1
, src2
);
1301 tcg_temp_free(src2
);
1303 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1305 tcg_temp_free(dest
);
1311 reg
= DREG(insn
, 0);
1313 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1314 gen_logic_cc(s
, reg
, OS_LONG
);
1317 static void gen_push(DisasContext
*s
, TCGv val
)
1321 tmp
= tcg_temp_new();
1322 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1323 gen_store(s
, OS_LONG
, tmp
, val
);
1324 tcg_gen_mov_i32(QREG_SP
, tmp
);
1336 mask
= read_im16(env
, s
);
1337 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1338 if (IS_NULL_QREG(tmp
)) {
1342 addr
= tcg_temp_new();
1343 tcg_gen_mov_i32(addr
, tmp
);
1344 is_load
= ((insn
& 0x0400) != 0);
1345 for (i
= 0; i
< 16; i
++, mask
>>= 1) {
1352 tmp
= gen_load(s
, OS_LONG
, addr
, 0);
1353 tcg_gen_mov_i32(reg
, tmp
);
1355 gen_store(s
, OS_LONG
, addr
, reg
);
1358 tcg_gen_addi_i32(addr
, addr
, 4);
1363 DISAS_INSN(bitop_im
)
1373 if ((insn
& 0x38) != 0)
1377 op
= (insn
>> 6) & 3;
1379 bitnum
= read_im16(env
, s
);
1380 if (bitnum
& 0xff00) {
1381 disas_undef(env
, s
, insn
);
1387 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1389 if (opsize
== OS_BYTE
)
1395 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
1398 tmp
= tcg_temp_new();
1401 tcg_gen_xori_i32(tmp
, src1
, mask
);
1404 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
1407 tcg_gen_ori_i32(tmp
, src1
, mask
);
1412 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
1417 DISAS_INSN(arith_im
)
1425 op
= (insn
>> 9) & 7;
1426 SRC_EA(env
, src1
, OS_LONG
, 0, (op
== 6) ? NULL
: &addr
);
1427 im
= read_im32(env
, s
);
1428 dest
= tcg_temp_new();
1431 tcg_gen_ori_i32(dest
, src1
, im
);
1432 gen_logic_cc(s
, dest
, OS_LONG
);
1435 tcg_gen_andi_i32(dest
, src1
, im
);
1436 gen_logic_cc(s
, dest
, OS_LONG
);
1439 tcg_gen_mov_i32(dest
, src1
);
1440 tcg_gen_setcondi_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
1441 tcg_gen_subi_i32(dest
, dest
, im
);
1442 gen_update_cc_add(dest
, tcg_const_i32(im
));
1443 set_cc_op(s
, CC_OP_SUB
);
1446 tcg_gen_mov_i32(dest
, src1
);
1447 tcg_gen_addi_i32(dest
, dest
, im
);
1448 gen_update_cc_add(dest
, tcg_const_i32(im
));
1449 tcg_gen_setcondi_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
1450 set_cc_op(s
, CC_OP_ADD
);
1453 tcg_gen_xori_i32(dest
, src1
, im
);
1454 gen_logic_cc(s
, dest
, OS_LONG
);
1457 gen_update_cc_add(src1
, tcg_const_i32(im
));
1458 set_cc_op(s
, CC_OP_CMP
);
1464 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1472 reg
= DREG(insn
, 0);
1473 tcg_gen_bswap32_i32(reg
, reg
);
1483 switch (insn
>> 12) {
1484 case 1: /* move.b */
1487 case 2: /* move.l */
1490 case 3: /* move.w */
1496 SRC_EA(env
, src
, opsize
, 1, NULL
);
1497 op
= (insn
>> 6) & 7;
1500 /* The value will already have been sign extended. */
1501 dest
= AREG(insn
, 9);
1502 tcg_gen_mov_i32(dest
, src
);
1506 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
1507 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
1508 /* This will be correct because loads sign extend. */
1509 gen_logic_cc(s
, src
, opsize
);
1518 reg
= DREG(insn
, 0);
1519 gen_helper_subx_cc(reg
, cpu_env
, tcg_const_i32(0), reg
);
1527 reg
= AREG(insn
, 9);
1528 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1529 if (IS_NULL_QREG(tmp
)) {
1533 tcg_gen_mov_i32(reg
, tmp
);
1540 opsize
= insn_opsize(insn
);
1541 DEST_EA(env
, insn
, opsize
, tcg_const_i32(0), NULL
);
1542 gen_logic_cc(s
, tcg_const_i32(0), opsize
);
1545 static TCGv
gen_get_ccr(DisasContext
*s
)
1551 dest
= tcg_temp_new();
1552 gen_helper_get_ccr(dest
, cpu_env
);
1556 DISAS_INSN(move_from_ccr
)
1560 ccr
= gen_get_ccr(s
);
1561 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
1569 reg
= DREG(insn
, 0);
1570 src1
= tcg_temp_new();
1571 tcg_gen_mov_i32(src1
, reg
);
1572 tcg_gen_neg_i32(reg
, src1
);
1573 gen_update_cc_add(reg
, src1
);
1574 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, src1
, 0);
1575 set_cc_op(s
, CC_OP_SUB
);
1578 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
1581 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
1582 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
1583 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
1584 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
1585 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
1587 gen_helper_set_sr(cpu_env
, tcg_const_i32(val
));
1589 set_cc_op(s
, CC_OP_FLAGS
);
1592 static void gen_set_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1595 if ((insn
& 0x38) == 0) {
1597 gen_helper_set_ccr(cpu_env
, DREG(insn
, 0));
1599 gen_helper_set_sr(cpu_env
, DREG(insn
, 0));
1601 set_cc_op(s
, CC_OP_FLAGS
);
1602 } else if ((insn
& 0x3f) == 0x3c) {
1604 val
= read_im16(env
, s
);
1605 gen_set_sr_im(s
, val
, ccr_only
);
1607 disas_undef(env
, s
, insn
);
1612 DISAS_INSN(move_to_ccr
)
1614 gen_set_sr(env
, s
, insn
, 1);
1621 reg
= DREG(insn
, 0);
1622 tcg_gen_not_i32(reg
, reg
);
1623 gen_logic_cc(s
, reg
, OS_LONG
);
1632 src1
= tcg_temp_new();
1633 src2
= tcg_temp_new();
1634 reg
= DREG(insn
, 0);
1635 tcg_gen_shli_i32(src1
, reg
, 16);
1636 tcg_gen_shri_i32(src2
, reg
, 16);
1637 tcg_gen_or_i32(reg
, src1
, src2
);
1638 gen_logic_cc(s
, reg
, OS_LONG
);
1643 gen_exception(s
, s
->pc
- 2, EXCP_DEBUG
);
1650 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1651 if (IS_NULL_QREG(tmp
)) {
1664 reg
= DREG(insn
, 0);
1665 op
= (insn
>> 6) & 7;
1666 tmp
= tcg_temp_new();
1668 tcg_gen_ext16s_i32(tmp
, reg
);
1670 tcg_gen_ext8s_i32(tmp
, reg
);
1672 gen_partset_reg(OS_WORD
, reg
, tmp
);
1674 tcg_gen_mov_i32(reg
, tmp
);
1675 gen_logic_cc(s
, tmp
, OS_LONG
);
1683 opsize
= insn_opsize(insn
);
1684 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
1685 gen_logic_cc(s
, tmp
, opsize
);
1690 /* Implemented as a NOP. */
1695 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
1698 /* ??? This should be atomic. */
1705 dest
= tcg_temp_new();
1706 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
1707 gen_logic_cc(s
, src1
, OS_BYTE
);
1708 tcg_gen_ori_i32(dest
, src1
, 0x80);
1709 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1719 /* The upper 32 bits of the product are discarded, so
1720 muls.l and mulu.l are functionally equivalent. */
1721 ext
= read_im16(env
, s
);
1723 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1726 reg
= DREG(ext
, 12);
1727 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
1728 dest
= tcg_temp_new();
1729 tcg_gen_mul_i32(dest
, src1
, reg
);
1730 tcg_gen_mov_i32(reg
, dest
);
1731 /* Unlike m68k, coldfire always clears the overflow bit. */
1732 gen_logic_cc(s
, dest
, OS_LONG
);
1735 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
1740 reg
= AREG(insn
, 0);
1741 tmp
= tcg_temp_new();
1742 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1743 gen_store(s
, OS_LONG
, tmp
, reg
);
1744 if ((insn
& 7) != 7) {
1745 tcg_gen_mov_i32(reg
, tmp
);
1747 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
1755 offset
= read_im16(env
, s
);
1756 gen_link(s
, insn
, offset
);
1763 offset
= read_im32(env
, s
);
1764 gen_link(s
, insn
, offset
);
1773 src
= tcg_temp_new();
1774 reg
= AREG(insn
, 0);
1775 tcg_gen_mov_i32(src
, reg
);
1776 tmp
= gen_load(s
, OS_LONG
, src
, 0);
1777 tcg_gen_mov_i32(reg
, tmp
);
1778 tcg_gen_addi_i32(QREG_SP
, src
, 4);
1789 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
1790 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
1798 /* Load the target address first to ensure correct exception
1800 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1801 if (IS_NULL_QREG(tmp
)) {
1805 if ((insn
& 0x40) == 0) {
1807 gen_push(s
, tcg_const_i32(s
->pc
));
1820 SRC_EA(env
, src1
, OS_LONG
, 0, &addr
);
1821 val
= (insn
>> 9) & 7;
1824 dest
= tcg_temp_new();
1825 tcg_gen_mov_i32(dest
, src1
);
1826 if ((insn
& 0x38) == 0x08) {
1827 /* Don't update condition codes if the destination is an
1828 address register. */
1829 if (insn
& 0x0100) {
1830 tcg_gen_subi_i32(dest
, dest
, val
);
1832 tcg_gen_addi_i32(dest
, dest
, val
);
1835 src2
= tcg_const_i32(val
);
1836 if (insn
& 0x0100) {
1837 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src2
);
1838 tcg_gen_sub_i32(dest
, dest
, src2
);
1839 set_cc_op(s
, CC_OP_SUB
);
1841 tcg_gen_add_i32(dest
, dest
, src2
);
1842 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src2
);
1843 set_cc_op(s
, CC_OP_ADD
);
1845 gen_update_cc_add(dest
, src2
);
1847 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1853 case 2: /* One extension word. */
1856 case 3: /* Two extension words. */
1859 case 4: /* No extension words. */
1862 disas_undef(env
, s
, insn
);
1874 op
= (insn
>> 8) & 0xf;
1875 offset
= (int8_t)insn
;
1877 offset
= (int16_t)read_im16(env
, s
);
1878 } else if (offset
== -1) {
1879 offset
= read_im32(env
, s
);
1883 gen_push(s
, tcg_const_i32(s
->pc
));
1887 l1
= gen_new_label();
1888 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
1889 gen_jmp_tb(s
, 1, base
+ offset
);
1891 gen_jmp_tb(s
, 0, s
->pc
);
1893 /* Unconditional branch. */
1894 gen_jmp_tb(s
, 0, base
+ offset
);
1903 tcg_gen_movi_i32(DREG(insn
, 9), val
);
1904 gen_logic_cc(s
, tcg_const_i32(val
), OS_LONG
);
1917 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
1918 reg
= DREG(insn
, 9);
1919 tcg_gen_mov_i32(reg
, src
);
1920 gen_logic_cc(s
, src
, opsize
);
1930 reg
= DREG(insn
, 9);
1931 dest
= tcg_temp_new();
1933 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1934 tcg_gen_or_i32(dest
, src
, reg
);
1935 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1937 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1938 tcg_gen_or_i32(dest
, src
, reg
);
1939 tcg_gen_mov_i32(reg
, dest
);
1941 gen_logic_cc(s
, dest
, OS_LONG
);
1949 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1950 reg
= AREG(insn
, 9);
1951 tcg_gen_sub_i32(reg
, reg
, src
);
1960 reg
= DREG(insn
, 9);
1961 src
= DREG(insn
, 0);
1962 gen_helper_subx_cc(reg
, cpu_env
, reg
, src
);
1970 val
= (insn
>> 9) & 7;
1973 src
= tcg_const_i32(val
);
1974 gen_logic_cc(s
, src
, OS_LONG
);
1975 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
1984 opsize
= insn_opsize(insn
);
1985 SRC_EA(env
, src
, opsize
, -1, NULL
);
1986 reg
= DREG(insn
, 9);
1987 gen_update_cc_add(reg
, src
);
1988 set_cc_op(s
, CC_OP_CMP
);
2002 SRC_EA(env
, src
, opsize
, 1, NULL
);
2003 reg
= AREG(insn
, 9);
2004 gen_update_cc_add(reg
, src
);
2005 set_cc_op(s
, CC_OP_CMP
);
2015 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
2016 reg
= DREG(insn
, 9);
2017 dest
= tcg_temp_new();
2018 tcg_gen_xor_i32(dest
, src
, reg
);
2019 gen_logic_cc(s
, dest
, OS_LONG
);
2020 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
2023 static void do_exg(TCGv reg1
, TCGv reg2
)
2025 TCGv temp
= tcg_temp_new();
2026 tcg_gen_mov_i32(temp
, reg1
);
2027 tcg_gen_mov_i32(reg1
, reg2
);
2028 tcg_gen_mov_i32(reg2
, temp
);
2029 tcg_temp_free(temp
);
2034 /* exchange Dx and Dy */
2035 do_exg(DREG(insn
, 9), DREG(insn
, 0));
2040 /* exchange Ax and Ay */
2041 do_exg(AREG(insn
, 9), AREG(insn
, 0));
2046 /* exchange Dx and Ay */
2047 do_exg(DREG(insn
, 9), AREG(insn
, 0));
2057 reg
= DREG(insn
, 9);
2058 dest
= tcg_temp_new();
2060 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
2061 tcg_gen_and_i32(dest
, src
, reg
);
2062 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
2064 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
2065 tcg_gen_and_i32(dest
, src
, reg
);
2066 tcg_gen_mov_i32(reg
, dest
);
2068 gen_logic_cc(s
, dest
, OS_LONG
);
2076 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
2077 reg
= AREG(insn
, 9);
2078 tcg_gen_add_i32(reg
, reg
, src
);
2087 reg
= DREG(insn
, 9);
2088 src
= DREG(insn
, 0);
2089 gen_helper_addx_cc(reg
, cpu_env
, reg
, src
);
2092 /* TODO: This could be implemented without helper functions. */
2093 DISAS_INSN(shift_im
)
2099 set_cc_op(s
, CC_OP_FLAGS
);
2101 reg
= DREG(insn
, 0);
2102 tmp
= (insn
>> 9) & 7;
2105 shift
= tcg_const_i32(tmp
);
2106 /* No need to flush flags becuse we know we will set C flag. */
2108 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
2111 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
2113 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
2118 DISAS_INSN(shift_reg
)
2123 reg
= DREG(insn
, 0);
2124 shift
= DREG(insn
, 9);
2126 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
2129 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
2131 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
2134 set_cc_op(s
, CC_OP_FLAGS
);
2140 reg
= DREG(insn
, 0);
2141 gen_logic_cc(s
, reg
, OS_LONG
);
2142 gen_helper_ff1(reg
, reg
);
2145 static TCGv
gen_get_sr(DisasContext
*s
)
2150 ccr
= gen_get_ccr(s
);
2151 sr
= tcg_temp_new();
2152 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2153 tcg_gen_or_i32(sr
, sr
, ccr
);
2163 ext
= read_im16(env
, s
);
2164 if (ext
!= 0x46FC) {
2165 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
2168 ext
= read_im16(env
, s
);
2169 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
2170 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
2173 gen_push(s
, gen_get_sr(s
));
2174 gen_set_sr_im(s
, ext
, 0);
2177 DISAS_INSN(move_from_sr
)
2181 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
2182 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2186 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
2189 DISAS_INSN(move_to_sr
)
2192 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2195 gen_set_sr(env
, s
, insn
, 0);
2199 DISAS_INSN(move_from_usp
)
2202 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2205 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
2206 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2209 DISAS_INSN(move_to_usp
)
2212 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2215 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
2216 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2221 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
2229 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2233 ext
= read_im16(env
, s
);
2235 gen_set_sr_im(s
, ext
, 0);
2236 tcg_gen_movi_i32(cpu_halted
, 1);
2237 gen_exception(s
, s
->pc
, EXCP_HLT
);
2243 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2246 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
2255 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2259 ext
= read_im16(env
, s
);
2262 reg
= AREG(ext
, 12);
2264 reg
= DREG(ext
, 12);
2266 gen_helper_movec(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
2273 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2276 /* ICache fetch. Implement as no-op. */
2282 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2285 /* Cache push/invalidate. Implement as no-op. */
2290 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2295 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2298 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2301 /* TODO: Implement wdebug. */
2302 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
2307 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
2310 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2311 immediately before the next FP instruction is executed. */
2325 ext
= read_im16(env
, s
);
2326 opmode
= ext
& 0x7f;
2327 switch ((ext
>> 13) & 7) {
2332 case 3: /* fmove out */
2334 tmp32
= tcg_temp_new_i32();
2336 /* ??? TODO: Proper behavior on overflow. */
2337 switch ((ext
>> 10) & 7) {
2340 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2344 gen_helper_f64_to_f32(tmp32
, cpu_env
, src
);
2348 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2350 case 5: /* OS_DOUBLE */
2351 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2352 switch ((insn
>> 3) & 7) {
2357 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2360 offset
= cpu_ldsw_code(env
, s
->pc
);
2362 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2367 gen_store64(s
, tmp32
, src
);
2368 switch ((insn
>> 3) & 7) {
2370 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2371 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2374 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2377 tcg_temp_free_i32(tmp32
);
2381 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2386 DEST_EA(env
, insn
, opsize
, tmp32
, NULL
);
2387 tcg_temp_free_i32(tmp32
);
2389 case 4: /* fmove to control register. */
2390 switch ((ext
>> 10) & 7) {
2392 /* Not implemented. Ignore writes. */
2397 cpu_abort(NULL
, "Unimplemented: fmove to control %d",
2401 case 5: /* fmove from control register. */
2402 switch ((ext
>> 10) & 7) {
2404 /* Not implemented. Always return zero. */
2405 tmp32
= tcg_const_i32(0);
2410 cpu_abort(NULL
, "Unimplemented: fmove from control %d",
2414 DEST_EA(env
, insn
, OS_LONG
, tmp32
, NULL
);
2416 case 6: /* fmovem */
2422 if ((ext
& 0x1f00) != 0x1000 || (ext
& 0xff) == 0)
2424 tmp32
= gen_lea(env
, s
, insn
, OS_LONG
);
2425 if (IS_NULL_QREG(tmp32
)) {
2429 addr
= tcg_temp_new_i32();
2430 tcg_gen_mov_i32(addr
, tmp32
);
2432 for (i
= 0; i
< 8; i
++) {
2435 if (ext
& (1 << 13)) {
2437 tcg_gen_qemu_stf64(dest
, addr
, IS_USER(s
));
2440 tcg_gen_qemu_ldf64(dest
, addr
, IS_USER(s
));
2442 if (ext
& (mask
- 1))
2443 tcg_gen_addi_i32(addr
, addr
, 8);
2447 tcg_temp_free_i32(addr
);
2451 if (ext
& (1 << 14)) {
2452 /* Source effective address. */
2453 switch ((ext
>> 10) & 7) {
2454 case 0: opsize
= OS_LONG
; break;
2455 case 1: opsize
= OS_SINGLE
; break;
2456 case 4: opsize
= OS_WORD
; break;
2457 case 5: opsize
= OS_DOUBLE
; break;
2458 case 6: opsize
= OS_BYTE
; break;
2462 if (opsize
== OS_DOUBLE
) {
2463 tmp32
= tcg_temp_new_i32();
2464 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2465 switch ((insn
>> 3) & 7) {
2470 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2473 offset
= cpu_ldsw_code(env
, s
->pc
);
2475 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2478 offset
= cpu_ldsw_code(env
, s
->pc
);
2479 offset
+= s
->pc
- 2;
2481 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2486 src
= gen_load64(s
, tmp32
);
2487 switch ((insn
>> 3) & 7) {
2489 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2490 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2493 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2496 tcg_temp_free_i32(tmp32
);
2498 SRC_EA(env
, tmp32
, opsize
, 1, NULL
);
2499 src
= tcg_temp_new_i64();
2504 gen_helper_i32_to_f64(src
, cpu_env
, tmp32
);
2507 gen_helper_f32_to_f64(src
, cpu_env
, tmp32
);
2512 /* Source register. */
2513 src
= FREG(ext
, 10);
2515 dest
= FREG(ext
, 7);
2516 res
= tcg_temp_new_i64();
2518 tcg_gen_mov_f64(res
, dest
);
2522 case 0: case 0x40: case 0x44: /* fmove */
2523 tcg_gen_mov_f64(res
, src
);
2526 gen_helper_iround_f64(res
, cpu_env
, src
);
2529 case 3: /* fintrz */
2530 gen_helper_itrunc_f64(res
, cpu_env
, src
);
2533 case 4: case 0x41: case 0x45: /* fsqrt */
2534 gen_helper_sqrt_f64(res
, cpu_env
, src
);
2536 case 0x18: case 0x58: case 0x5c: /* fabs */
2537 gen_helper_abs_f64(res
, src
);
2539 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2540 gen_helper_chs_f64(res
, src
);
2542 case 0x20: case 0x60: case 0x64: /* fdiv */
2543 gen_helper_div_f64(res
, cpu_env
, res
, src
);
2545 case 0x22: case 0x62: case 0x66: /* fadd */
2546 gen_helper_add_f64(res
, cpu_env
, res
, src
);
2548 case 0x23: case 0x63: case 0x67: /* fmul */
2549 gen_helper_mul_f64(res
, cpu_env
, res
, src
);
2551 case 0x28: case 0x68: case 0x6c: /* fsub */
2552 gen_helper_sub_f64(res
, cpu_env
, res
, src
);
2554 case 0x38: /* fcmp */
2555 gen_helper_sub_cmp_f64(res
, cpu_env
, res
, src
);
2559 case 0x3a: /* ftst */
2560 tcg_gen_mov_f64(res
, src
);
2567 if (ext
& (1 << 14)) {
2568 tcg_temp_free_i64(src
);
2571 if (opmode
& 0x40) {
2572 if ((opmode
& 0x4) != 0)
2574 } else if ((s
->fpcr
& M68K_FPCR_PREC
) == 0) {
2579 TCGv tmp
= tcg_temp_new_i32();
2580 gen_helper_f64_to_f32(tmp
, cpu_env
, res
);
2581 gen_helper_f32_to_f64(res
, cpu_env
, tmp
);
2582 tcg_temp_free_i32(tmp
);
2584 tcg_gen_mov_f64(QREG_FP_RESULT
, res
);
2586 tcg_gen_mov_f64(dest
, res
);
2588 tcg_temp_free_i64(res
);
2591 /* FIXME: Is this right for offset addressing modes? */
2593 disas_undef_fpu(env
, s
, insn
);
2604 offset
= cpu_ldsw_code(env
, s
->pc
);
2606 if (insn
& (1 << 6)) {
2607 offset
= (offset
<< 16) | read_im16(env
, s
);
2610 l1
= gen_new_label();
2611 /* TODO: Raise BSUN exception. */
2612 flag
= tcg_temp_new();
2613 gen_helper_compare_f64(flag
, cpu_env
, QREG_FP_RESULT
);
2614 /* Jump to l1 if condition is true. */
2615 switch (insn
& 0xf) {
2618 case 1: /* eq (=0) */
2619 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2621 case 2: /* ogt (=1) */
2622 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(1), l1
);
2624 case 3: /* oge (=0 or =1) */
2625 tcg_gen_brcond_i32(TCG_COND_LEU
, flag
, tcg_const_i32(1), l1
);
2627 case 4: /* olt (=-1) */
2628 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(0), l1
);
2630 case 5: /* ole (=-1 or =0) */
2631 tcg_gen_brcond_i32(TCG_COND_LE
, flag
, tcg_const_i32(0), l1
);
2633 case 6: /* ogl (=-1 or =1) */
2634 tcg_gen_andi_i32(flag
, flag
, 1);
2635 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2637 case 7: /* or (=2) */
2638 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(2), l1
);
2640 case 8: /* un (<2) */
2641 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(2), l1
);
2643 case 9: /* ueq (=0 or =2) */
2644 tcg_gen_andi_i32(flag
, flag
, 1);
2645 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2647 case 10: /* ugt (>0) */
2648 tcg_gen_brcond_i32(TCG_COND_GT
, flag
, tcg_const_i32(0), l1
);
2650 case 11: /* uge (>=0) */
2651 tcg_gen_brcond_i32(TCG_COND_GE
, flag
, tcg_const_i32(0), l1
);
2653 case 12: /* ult (=-1 or =2) */
2654 tcg_gen_brcond_i32(TCG_COND_GEU
, flag
, tcg_const_i32(2), l1
);
2656 case 13: /* ule (!=1) */
2657 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(1), l1
);
2659 case 14: /* ne (!=0) */
2660 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2666 gen_jmp_tb(s
, 0, s
->pc
);
2668 gen_jmp_tb(s
, 1, addr
+ offset
);
2671 DISAS_INSN(frestore
)
2673 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2675 /* TODO: Implement frestore. */
2676 cpu_abort(CPU(cpu
), "FRESTORE not implemented");
2681 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2683 /* TODO: Implement fsave. */
2684 cpu_abort(CPU(cpu
), "FSAVE not implemented");
2687 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
2689 TCGv tmp
= tcg_temp_new();
2690 if (s
->env
->macsr
& MACSR_FI
) {
2692 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
2694 tcg_gen_shli_i32(tmp
, val
, 16);
2695 } else if (s
->env
->macsr
& MACSR_SU
) {
2697 tcg_gen_sari_i32(tmp
, val
, 16);
2699 tcg_gen_ext16s_i32(tmp
, val
);
2702 tcg_gen_shri_i32(tmp
, val
, 16);
2704 tcg_gen_ext16u_i32(tmp
, val
);
2709 static void gen_mac_clear_flags(void)
2711 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
2712 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
2728 s
->mactmp
= tcg_temp_new_i64();
2732 ext
= read_im16(env
, s
);
2734 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
2735 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
2736 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
2737 disas_undef(env
, s
, insn
);
2741 /* MAC with load. */
2742 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2743 addr
= tcg_temp_new();
2744 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
2745 /* Load the value now to ensure correct exception behavior.
2746 Perform writeback after reading the MAC inputs. */
2747 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
2750 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
2751 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
2753 loadval
= addr
= NULL_QREG
;
2754 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2755 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2758 gen_mac_clear_flags();
2761 /* Disabled because conditional branches clobber temporary vars. */
2762 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
2763 /* Skip the multiply if we know we will ignore it. */
2764 l1
= gen_new_label();
2765 tmp
= tcg_temp_new();
2766 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
2767 gen_op_jmp_nz32(tmp
, l1
);
2771 if ((ext
& 0x0800) == 0) {
2773 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
2774 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
2776 if (s
->env
->macsr
& MACSR_FI
) {
2777 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
2779 if (s
->env
->macsr
& MACSR_SU
)
2780 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
2782 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
2783 switch ((ext
>> 9) & 3) {
2785 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
2788 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
2794 /* Save the overflow flag from the multiply. */
2795 saved_flags
= tcg_temp_new();
2796 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
2798 saved_flags
= NULL_QREG
;
2802 /* Disabled because conditional branches clobber temporary vars. */
2803 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
2804 /* Skip the accumulate if the value is already saturated. */
2805 l1
= gen_new_label();
2806 tmp
= tcg_temp_new();
2807 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2808 gen_op_jmp_nz32(tmp
, l1
);
2813 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2815 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2817 if (s
->env
->macsr
& MACSR_FI
)
2818 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
2819 else if (s
->env
->macsr
& MACSR_SU
)
2820 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
2822 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
2825 /* Disabled because conditional branches clobber temporary vars. */
2831 /* Dual accumulate variant. */
2832 acc
= (ext
>> 2) & 3;
2833 /* Restore the overflow flag from the multiplier. */
2834 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
2836 /* Disabled because conditional branches clobber temporary vars. */
2837 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
2838 /* Skip the accumulate if the value is already saturated. */
2839 l1
= gen_new_label();
2840 tmp
= tcg_temp_new();
2841 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2842 gen_op_jmp_nz32(tmp
, l1
);
2846 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2848 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2849 if (s
->env
->macsr
& MACSR_FI
)
2850 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
2851 else if (s
->env
->macsr
& MACSR_SU
)
2852 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
2854 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
2856 /* Disabled because conditional branches clobber temporary vars. */
2861 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
2865 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2866 tcg_gen_mov_i32(rw
, loadval
);
2867 /* FIXME: Should address writeback happen with the masked or
2869 switch ((insn
>> 3) & 7) {
2870 case 3: /* Post-increment. */
2871 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
2873 case 4: /* Pre-decrement. */
2874 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2879 DISAS_INSN(from_mac
)
2885 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2886 accnum
= (insn
>> 9) & 3;
2887 acc
= MACREG(accnum
);
2888 if (s
->env
->macsr
& MACSR_FI
) {
2889 gen_helper_get_macf(rx
, cpu_env
, acc
);
2890 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
2891 tcg_gen_extrl_i64_i32(rx
, acc
);
2892 } else if (s
->env
->macsr
& MACSR_SU
) {
2893 gen_helper_get_macs(rx
, acc
);
2895 gen_helper_get_macu(rx
, acc
);
2898 tcg_gen_movi_i64(acc
, 0);
2899 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
2903 DISAS_INSN(move_mac
)
2905 /* FIXME: This can be done without a helper. */
2909 dest
= tcg_const_i32((insn
>> 9) & 3);
2910 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
2911 gen_mac_clear_flags();
2912 gen_helper_mac_set_flags(cpu_env
, dest
);
2915 DISAS_INSN(from_macsr
)
2919 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2920 tcg_gen_mov_i32(reg
, QREG_MACSR
);
2923 DISAS_INSN(from_mask
)
2926 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2927 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
2930 DISAS_INSN(from_mext
)
2934 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2935 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
2936 if (s
->env
->macsr
& MACSR_FI
)
2937 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
2939 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
2942 DISAS_INSN(macsr_to_ccr
)
2944 TCGv tmp
= tcg_temp_new();
2945 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
2946 gen_helper_set_sr(cpu_env
, tmp
);
2948 set_cc_op(s
, CC_OP_FLAGS
);
2956 accnum
= (insn
>> 9) & 3;
2957 acc
= MACREG(accnum
);
2958 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2959 if (s
->env
->macsr
& MACSR_FI
) {
2960 tcg_gen_ext_i32_i64(acc
, val
);
2961 tcg_gen_shli_i64(acc
, acc
, 8);
2962 } else if (s
->env
->macsr
& MACSR_SU
) {
2963 tcg_gen_ext_i32_i64(acc
, val
);
2965 tcg_gen_extu_i32_i64(acc
, val
);
2967 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
2968 gen_mac_clear_flags();
2969 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
2972 DISAS_INSN(to_macsr
)
2975 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2976 gen_helper_set_macsr(cpu_env
, val
);
2983 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2984 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
2991 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2992 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
2993 if (s
->env
->macsr
& MACSR_FI
)
2994 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
2995 else if (s
->env
->macsr
& MACSR_SU
)
2996 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
2998 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
3001 static disas_proc opcode_table
[65536];
3004 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
3010 /* Sanity check. All set bits must be included in the mask. */
3011 if (opcode
& ~mask
) {
3013 "qemu internal error: bogus opcode definition %04x/%04x\n",
3017 /* This could probably be cleverer. For now just optimize the case where
3018 the top bits are known. */
3019 /* Find the first zero bit in the mask. */
3021 while ((i
& mask
) != 0)
3023 /* Iterate over all combinations of this and lower bits. */
3028 from
= opcode
& ~(i
- 1);
3030 for (i
= from
; i
< to
; i
++) {
3031 if ((i
& mask
) == opcode
)
3032 opcode_table
[i
] = proc
;
3036 /* Register m68k opcode handlers. Order is important.
3037 Later insn override earlier ones. */
3038 void register_m68k_insns (CPUM68KState
*env
)
3040 /* Build the opcode table only once to avoid
3041 multithreading issues. */
3042 if (opcode_table
[0] != NULL
) {
3046 /* use BASE() for instruction available
3047 * for CF_ISA_A and M68000.
3049 #define BASE(name, opcode, mask) \
3050 register_opcode(disas_##name, 0x##opcode, 0x##mask)
3051 #define INSN(name, opcode, mask, feature) do { \
3052 if (m68k_feature(env, M68K_FEATURE_##feature)) \
3053 BASE(name, opcode, mask); \
3055 BASE(undef
, 0000, 0000);
3056 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
3057 INSN(arith_im
, 0000, ff00
, M68000
);
3058 INSN(undef
, 00c0
, ffc0
, M68000
);
3059 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
3060 BASE(bitop_reg
, 0100, f1c0
);
3061 BASE(bitop_reg
, 0140, f1c0
);
3062 BASE(bitop_reg
, 0180, f1c0
);
3063 BASE(bitop_reg
, 01c0
, f1c0
);
3064 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
3065 INSN(arith_im
, 0200, ff00
, M68000
);
3066 INSN(undef
, 02c0
, ffc0
, M68000
);
3067 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
3068 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
3069 INSN(arith_im
, 0400, ff00
, M68000
);
3070 INSN(undef
, 04c0
, ffc0
, M68000
);
3071 INSN(arith_im
, 0600, ff00
, M68000
);
3072 INSN(undef
, 06c0
, ffc0
, M68000
);
3073 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
3074 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
3075 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
3076 INSN(arith_im
, 0c00
, ff00
, M68000
);
3077 BASE(bitop_im
, 0800, ffc0
);
3078 BASE(bitop_im
, 0840, ffc0
);
3079 BASE(bitop_im
, 0880, ffc0
);
3080 BASE(bitop_im
, 08c0
, ffc0
);
3081 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
3082 INSN(arith_im
, 0a00
, ff00
, M68000
);
3083 BASE(move
, 1000, f000
);
3084 BASE(move
, 2000, f000
);
3085 BASE(move
, 3000, f000
);
3086 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
3087 INSN(negx
, 4080, fff8
, CF_ISA_A
);
3088 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
3089 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
3090 BASE(lea
, 41c0
, f1c0
);
3091 BASE(clr
, 4200, ff00
);
3092 BASE(undef
, 42c0
, ffc0
);
3093 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
3094 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
3095 INSN(neg
, 4480, fff8
, CF_ISA_A
);
3096 INSN(neg
, 4400, ff00
, M68000
);
3097 INSN(undef
, 44c0
, ffc0
, M68000
);
3098 BASE(move_to_ccr
, 44c0
, ffc0
);
3099 INSN(not, 4680, fff8
, CF_ISA_A
);
3100 INSN(not, 4600, ff00
, M68000
);
3101 INSN(undef
, 46c0
, ffc0
, M68000
);
3102 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
3103 INSN(linkl
, 4808, fff8
, M68000
);
3104 BASE(pea
, 4840, ffc0
);
3105 BASE(swap
, 4840, fff8
);
3106 INSN(bkpt
, 4848, fff8
, BKPT
);
3107 BASE(movem
, 48c0
, fbc0
);
3108 BASE(ext
, 4880, fff8
);
3109 BASE(ext
, 48c0
, fff8
);
3110 BASE(ext
, 49c0
, fff8
);
3111 BASE(tst
, 4a00
, ff00
);
3112 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
3113 INSN(tas
, 4ac0
, ffc0
, M68000
);
3114 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
3115 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
3116 BASE(illegal
, 4afc
, ffff
);
3117 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
3118 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
3119 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
3120 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
3121 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
3122 BASE(trap
, 4e40
, fff0
);
3123 BASE(link
, 4e50
, fff8
);
3124 BASE(unlk
, 4e58
, fff8
);
3125 INSN(move_to_usp
, 4e60
, fff8
, USP
);
3126 INSN(move_from_usp
, 4e68
, fff8
, USP
);
3127 BASE(nop
, 4e71
, ffff
);
3128 BASE(stop
, 4e72
, ffff
);
3129 BASE(rte
, 4e73
, ffff
);
3130 BASE(rts
, 4e75
, ffff
);
3131 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
3132 BASE(jump
, 4e80
, ffc0
);
3133 INSN(jump
, 4ec0
, ffc0
, CF_ISA_A
);
3134 INSN(addsubq
, 5180, f1c0
, CF_ISA_A
);
3135 INSN(jump
, 4ec0
, ffc0
, M68000
);
3136 INSN(addsubq
, 5000, f080
, M68000
);
3137 INSN(addsubq
, 5080, f0c0
, M68000
);
3138 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
3139 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
3140 INSN(addsubq
, 5080, f1c0
, CF_ISA_A
);
3141 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
3143 /* Branch instructions. */
3144 BASE(branch
, 6000, f000
);
3145 /* Disable long branch instructions, then add back the ones we want. */
3146 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
3147 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
3148 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
3149 INSN(branch
, 60ff
, ffff
, BRAL
);
3150 INSN(branch
, 60ff
, f0ff
, BCCL
);
3152 BASE(moveq
, 7000, f100
);
3153 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
3154 BASE(or, 8000, f000
);
3155 BASE(divw
, 80c0
, f0c0
);
3156 BASE(addsub
, 9000, f000
);
3157 INSN(subx
, 9180, f1f8
, CF_ISA_A
);
3158 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
3160 BASE(undef_mac
, a000
, f000
);
3161 INSN(mac
, a000
, f100
, CF_EMAC
);
3162 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
3163 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
3164 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
3165 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
3166 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
3167 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
3168 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
3169 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
3170 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
3171 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
3173 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
3174 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
3175 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
3176 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
3177 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
3178 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
3179 INSN(cmp
, b000
, f100
, M68000
);
3180 INSN(eor
, b100
, f100
, M68000
);
3181 INSN(cmpa
, b0c0
, f0c0
, M68000
);
3182 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
3183 BASE(and, c000
, f000
);
3184 INSN(exg_dd
, c140
, f1f8
, M68000
);
3185 INSN(exg_aa
, c148
, f1f8
, M68000
);
3186 INSN(exg_da
, c188
, f1f8
, M68000
);
3187 BASE(mulw
, c0c0
, f0c0
);
3188 BASE(addsub
, d000
, f000
);
3189 INSN(addx
, d180
, f1f8
, CF_ISA_A
);
3190 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
3191 INSN(adda
, d0c0
, f0c0
, M68000
);
3192 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
3193 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
3194 INSN(undef_fpu
, f000
, f000
, CF_ISA_A
);
3195 INSN(fpu
, f200
, ffc0
, CF_FPU
);
3196 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
3197 INSN(frestore
, f340
, ffc0
, CF_FPU
);
3198 INSN(fsave
, f340
, ffc0
, CF_FPU
);
3199 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
3200 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
3201 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
3202 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
3206 /* ??? Some of this implementation is not exception safe. We should always
3207 write back the result to memory before setting the condition codes. */
3208 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
3212 insn
= read_im16(env
, s
);
3214 opcode_table
[insn
](env
, s
, insn
);
3217 /* generate intermediate code for basic block 'tb'. */
3218 void gen_intermediate_code(CPUM68KState
*env
, TranslationBlock
*tb
)
3220 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
3221 CPUState
*cs
= CPU(cpu
);
3222 DisasContext dc1
, *dc
= &dc1
;
3223 target_ulong pc_start
;
3228 /* generate intermediate code */
3234 dc
->is_jmp
= DISAS_NEXT
;
3236 dc
->cc_op
= CC_OP_DYNAMIC
;
3237 dc
->cc_op_synced
= 1;
3238 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3239 dc
->fpcr
= env
->fpcr
;
3240 dc
->user
= (env
->sr
& SR_S
) == 0;
3243 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3244 if (max_insns
== 0) {
3245 max_insns
= CF_COUNT_MASK
;
3247 if (max_insns
> TCG_MAX_INSNS
) {
3248 max_insns
= TCG_MAX_INSNS
;
3253 pc_offset
= dc
->pc
- pc_start
;
3254 gen_throws_exception
= NULL
;
3255 tcg_gen_insn_start(dc
->pc
, dc
->cc_op
);
3258 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3259 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
3260 dc
->is_jmp
= DISAS_JUMP
;
3261 /* The address covered by the breakpoint must be included in
3262 [tb->pc, tb->pc + tb->size) in order to for it to be
3263 properly cleared -- thus we increment the PC here so that
3264 the logic setting tb->size below does the right thing. */
3269 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3273 dc
->insn_pc
= dc
->pc
;
3274 disas_m68k_insn(env
, dc
);
3275 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
3276 !cs
->singlestep_enabled
&&
3278 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
3279 num_insns
< max_insns
);
3281 if (tb
->cflags
& CF_LAST_IO
)
3283 if (unlikely(cs
->singlestep_enabled
)) {
3284 /* Make sure the pc is updated, and raise a debug exception. */
3287 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
3289 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
3291 switch(dc
->is_jmp
) {
3294 gen_jmp_tb(dc
, 0, dc
->pc
);
3300 /* indicate that the hash table must be used to find the next TB */
3304 /* nothing more to generate */
3308 gen_tb_end(tb
, num_insns
);
3311 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
3312 && qemu_log_in_addr_range(pc_start
)) {
3313 qemu_log("----------------\n");
3314 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3315 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
3319 tb
->size
= dc
->pc
- pc_start
;
3320 tb
->icount
= num_insns
;
3323 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3326 M68kCPU
*cpu
= M68K_CPU(cs
);
3327 CPUM68KState
*env
= &cpu
->env
;
3331 for (i
= 0; i
< 8; i
++)
3333 u
.d
= env
->fregs
[i
];
3334 cpu_fprintf(f
, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3335 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
3336 i
, u
.l
.upper
, u
.l
.lower
, *(double *)&u
.d
);
3338 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
3339 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
3340 cpu_fprintf(f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& CCF_X
) ? 'X' : '-',
3341 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
3342 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
3343 cpu_fprintf (f
, "FPRESULT = %12g\n", *(double *)&env
->fp_result
);
3346 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
3349 int cc_op
= data
[1];
3351 if (cc_op
!= CC_OP_DYNAMIC
) {