4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
36 //#define DEBUG_DISPATCH 1
38 /* Fake floating point. */
39 #define tcg_gen_mov_f64 tcg_gen_mov_i64
40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
43 #define DEFO32(name, offset) static TCGv QREG_##name;
44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
51 static TCGv_i32 cpu_halted
;
52 static TCGv_i32 cpu_exception_index
;
54 static TCGv_env cpu_env
;
56 static char cpu_reg_names
[3*8*3 + 5*4];
57 static TCGv cpu_dregs
[8];
58 static TCGv cpu_aregs
[8];
59 static TCGv_i64 cpu_fregs
[8];
60 static TCGv_i64 cpu_macc
[4];
62 #define REG(insn, pos) (((insn) >> (pos)) & 7)
63 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
64 #define AREG(insn, pos) cpu_aregs[REG(insn, pos)]
65 #define FREG(insn, pos) cpu_fregs[REG(insn, pos)]
66 #define MACREG(acc) cpu_macc[acc]
67 #define QREG_SP cpu_aregs[7]
69 static TCGv NULL_QREG
;
70 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
71 /* Used to distinguish stores from bad addressing modes. */
72 static TCGv store_dummy
;
74 #include "exec/gen-icount.h"
76 void m68k_tcg_init(void)
81 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
82 tcg_ctx
.tcg_env
= cpu_env
;
84 #define DEFO32(name, offset) \
85 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFO64(name, offset) \
88 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
89 offsetof(CPUM68KState, offset), #name);
90 #define DEFF64(name, offset) DEFO64(name, offset)
96 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
97 -offsetof(M68kCPU
, env
) +
98 offsetof(CPUState
, halted
), "HALTED");
99 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
100 -offsetof(M68kCPU
, env
) +
101 offsetof(CPUState
, exception_index
),
105 for (i
= 0; i
< 8; i
++) {
106 sprintf(p
, "D%d", i
);
107 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
108 offsetof(CPUM68KState
, dregs
[i
]), p
);
110 sprintf(p
, "A%d", i
);
111 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
112 offsetof(CPUM68KState
, aregs
[i
]), p
);
114 sprintf(p
, "F%d", i
);
115 cpu_fregs
[i
] = tcg_global_mem_new_i64(cpu_env
,
116 offsetof(CPUM68KState
, fregs
[i
]), p
);
119 for (i
= 0; i
< 4; i
++) {
120 sprintf(p
, "ACC%d", i
);
121 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
122 offsetof(CPUM68KState
, macc
[i
]), p
);
126 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
127 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
130 /* internal defines */
131 typedef struct DisasContext
{
133 target_ulong insn_pc
; /* Start of the current instruction. */
136 CCOp cc_op
; /* Current CC operation */
140 struct TranslationBlock
*tb
;
141 int singlestep_enabled
;
146 #define DISAS_JUMP_NEXT 4
148 #if defined(CONFIG_USER_ONLY)
151 #define IS_USER(s) s->user
154 /* XXX: move that elsewhere */
155 /* ??? Fix exceptions. */
156 static void *gen_throws_exception
;
157 #define gen_last_qop NULL
159 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
161 #ifdef DEBUG_DISPATCH
162 #define DISAS_INSN(name) \
163 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
165 static void disas_##name(CPUM68KState *env, DisasContext *s, \
168 qemu_log("Dispatch " #name "\n"); \
169 real_disas_##name(env, s, insn); \
171 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
174 #define DISAS_INSN(name) \
175 static void disas_##name(CPUM68KState *env, DisasContext *s, \
179 static const uint8_t cc_op_live
[CC_OP_NB
] = {
180 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
181 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
182 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
183 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
184 [CC_OP_LOGIC
] = CCF_X
| CCF_N
187 static void set_cc_op(DisasContext
*s
, CCOp op
)
189 CCOp old_op
= s
->cc_op
;
198 /* Discard CC computation that will no longer be used.
199 Note that X and N are never dead. */
200 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
202 tcg_gen_discard_i32(QREG_CC_C
);
205 tcg_gen_discard_i32(QREG_CC_Z
);
208 tcg_gen_discard_i32(QREG_CC_V
);
212 /* Update the CPU env CC_OP state. */
213 static void update_cc_op(DisasContext
*s
)
215 if (!s
->cc_op_synced
) {
217 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
221 /* Generate a load from the specified address. Narrow values are
222 sign extended to full register width. */
223 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
226 int index
= IS_USER(s
);
227 tmp
= tcg_temp_new_i32();
231 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
233 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
237 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
239 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
243 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
246 g_assert_not_reached();
248 gen_throws_exception
= gen_last_qop
;
252 static inline TCGv_i64
gen_load64(DisasContext
* s
, TCGv addr
)
255 int index
= IS_USER(s
);
256 tmp
= tcg_temp_new_i64();
257 tcg_gen_qemu_ldf64(tmp
, addr
, index
);
258 gen_throws_exception
= gen_last_qop
;
262 /* Generate a store. */
263 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
265 int index
= IS_USER(s
);
268 tcg_gen_qemu_st8(val
, addr
, index
);
271 tcg_gen_qemu_st16(val
, addr
, index
);
275 tcg_gen_qemu_st32(val
, addr
, index
);
278 g_assert_not_reached();
280 gen_throws_exception
= gen_last_qop
;
283 static inline void gen_store64(DisasContext
*s
, TCGv addr
, TCGv_i64 val
)
285 int index
= IS_USER(s
);
286 tcg_gen_qemu_stf64(val
, addr
, index
);
287 gen_throws_exception
= gen_last_qop
;
296 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
297 otherwise generate a store. */
298 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
301 if (what
== EA_STORE
) {
302 gen_store(s
, opsize
, addr
, val
);
305 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
309 /* Read a 16-bit immediate constant */
310 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
313 im
= cpu_lduw_code(env
, s
->pc
);
318 /* Read an 8-bit immediate constant */
319 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
321 return read_im16(env
, s
);
324 /* Read a 32-bit immediate constant. */
325 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
328 im
= read_im16(env
, s
) << 16;
329 im
|= 0xffff & read_im16(env
, s
);
333 /* Calculate and address index. */
334 static TCGv
gen_addr_index(uint16_t ext
, TCGv tmp
)
339 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
340 if ((ext
& 0x800) == 0) {
341 tcg_gen_ext16s_i32(tmp
, add
);
344 scale
= (ext
>> 9) & 3;
346 tcg_gen_shli_i32(tmp
, add
, scale
);
352 /* Handle a base + index + displacement effective addresss.
353 A NULL_QREG base means pc-relative. */
354 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
363 ext
= read_im16(env
, s
);
365 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
368 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
369 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
374 /* full extension word format */
375 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
378 if ((ext
& 0x30) > 0x10) {
379 /* base displacement */
380 if ((ext
& 0x30) == 0x20) {
381 bd
= (int16_t)read_im16(env
, s
);
383 bd
= read_im32(env
, s
);
388 tmp
= tcg_temp_new();
389 if ((ext
& 0x44) == 0) {
391 add
= gen_addr_index(ext
, tmp
);
395 if ((ext
& 0x80) == 0) {
396 /* base not suppressed */
397 if (IS_NULL_QREG(base
)) {
398 base
= tcg_const_i32(offset
+ bd
);
401 if (!IS_NULL_QREG(add
)) {
402 tcg_gen_add_i32(tmp
, add
, base
);
408 if (!IS_NULL_QREG(add
)) {
410 tcg_gen_addi_i32(tmp
, add
, bd
);
414 add
= tcg_const_i32(bd
);
416 if ((ext
& 3) != 0) {
417 /* memory indirect */
418 base
= gen_load(s
, OS_LONG
, add
, 0);
419 if ((ext
& 0x44) == 4) {
420 add
= gen_addr_index(ext
, tmp
);
421 tcg_gen_add_i32(tmp
, add
, base
);
427 /* outer displacement */
428 if ((ext
& 3) == 2) {
429 od
= (int16_t)read_im16(env
, s
);
431 od
= read_im32(env
, s
);
437 tcg_gen_addi_i32(tmp
, add
, od
);
442 /* brief extension word format */
443 tmp
= tcg_temp_new();
444 add
= gen_addr_index(ext
, tmp
);
445 if (!IS_NULL_QREG(base
)) {
446 tcg_gen_add_i32(tmp
, add
, base
);
448 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
450 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
457 /* Sign or zero extend a value. */
459 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
464 tcg_gen_ext8s_i32(res
, val
);
466 tcg_gen_ext8u_i32(res
, val
);
471 tcg_gen_ext16s_i32(res
, val
);
473 tcg_gen_ext16u_i32(res
, val
);
477 tcg_gen_mov_i32(res
, val
);
480 g_assert_not_reached();
484 /* Evaluate all the CC flags. */
486 static void gen_flush_flags(DisasContext
*s
)
497 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
498 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
499 /* Compute signed overflow for addition. */
502 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
503 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
504 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
505 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
507 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
514 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
515 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
516 /* Compute signed overflow for subtraction. */
519 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
520 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
521 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
522 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
524 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
531 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
532 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
533 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
534 /* Compute signed overflow for subtraction. */
536 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
537 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
538 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
540 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
544 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
545 tcg_gen_movi_i32(QREG_CC_C
, 0);
546 tcg_gen_movi_i32(QREG_CC_V
, 0);
550 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
554 t0
= tcg_const_i32(s
->cc_op
);
555 gen_helper_flush_flags(cpu_env
, t0
);
560 /* Note that flush_flags also assigned to env->cc_op. */
561 s
->cc_op
= CC_OP_FLAGS
;
565 static inline TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
569 if (opsize
== OS_LONG
) {
572 tmp
= tcg_temp_new();
573 gen_ext(tmp
, val
, opsize
, sign
);
579 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
581 gen_ext(QREG_CC_N
, val
, opsize
, 1);
582 set_cc_op(s
, CC_OP_LOGIC
);
585 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
587 tcg_gen_mov_i32(QREG_CC_N
, dest
);
588 tcg_gen_mov_i32(QREG_CC_V
, src
);
589 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
592 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
594 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
595 tcg_gen_mov_i32(QREG_CC_V
, src
);
598 static inline int opsize_bytes(int opsize
)
601 case OS_BYTE
: return 1;
602 case OS_WORD
: return 2;
603 case OS_LONG
: return 4;
604 case OS_SINGLE
: return 4;
605 case OS_DOUBLE
: return 8;
606 case OS_EXTENDED
: return 12;
607 case OS_PACKED
: return 12;
609 g_assert_not_reached();
613 static inline int insn_opsize(int insn
)
615 switch ((insn
>> 6) & 3) {
616 case 0: return OS_BYTE
;
617 case 1: return OS_WORD
;
618 case 2: return OS_LONG
;
620 g_assert_not_reached();
624 /* Assign value to a register. If the width is less than the register width
625 only the low part of the register is set. */
626 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
631 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
632 tmp
= tcg_temp_new();
633 tcg_gen_ext8u_i32(tmp
, val
);
634 tcg_gen_or_i32(reg
, reg
, tmp
);
637 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
638 tmp
= tcg_temp_new();
639 tcg_gen_ext16u_i32(tmp
, val
);
640 tcg_gen_or_i32(reg
, reg
, tmp
);
644 tcg_gen_mov_i32(reg
, val
);
647 g_assert_not_reached();
651 /* Generate code for an "effective address". Does not adjust the base
652 register for autoincrement addressing modes. */
653 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
661 switch ((insn
>> 3) & 7) {
662 case 0: /* Data register direct. */
663 case 1: /* Address register direct. */
665 case 2: /* Indirect register */
666 case 3: /* Indirect postincrement. */
667 return AREG(insn
, 0);
668 case 4: /* Indirect predecrememnt. */
670 tmp
= tcg_temp_new();
671 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
673 case 5: /* Indirect displacement. */
675 tmp
= tcg_temp_new();
676 ext
= read_im16(env
, s
);
677 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
679 case 6: /* Indirect index + displacement. */
681 return gen_lea_indexed(env
, s
, reg
);
684 case 0: /* Absolute short. */
685 offset
= (int16_t)read_im16(env
, s
);
686 return tcg_const_i32(offset
);
687 case 1: /* Absolute long. */
688 offset
= read_im32(env
, s
);
689 return tcg_const_i32(offset
);
690 case 2: /* pc displacement */
692 offset
+= (int16_t)read_im16(env
, s
);
693 return tcg_const_i32(offset
);
694 case 3: /* pc index+displacement. */
695 return gen_lea_indexed(env
, s
, NULL_QREG
);
696 case 4: /* Immediate. */
701 /* Should never happen. */
705 /* Helper function for gen_ea. Reuse the computed address between the
706 for read/write operands. */
707 static inline TCGv
gen_ea_once(CPUM68KState
*env
, DisasContext
*s
,
708 uint16_t insn
, int opsize
, TCGv val
,
709 TCGv
*addrp
, ea_what what
)
713 if (addrp
&& what
== EA_STORE
) {
716 tmp
= gen_lea(env
, s
, insn
, opsize
);
717 if (IS_NULL_QREG(tmp
))
722 return gen_ldst(s
, opsize
, tmp
, val
, what
);
725 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
726 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
727 ADDRP is non-null for readwrite operands. */
728 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
729 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
735 switch ((insn
>> 3) & 7) {
736 case 0: /* Data register direct. */
738 if (what
== EA_STORE
) {
739 gen_partset_reg(opsize
, reg
, val
);
742 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
744 case 1: /* Address register direct. */
746 if (what
== EA_STORE
) {
747 tcg_gen_mov_i32(reg
, val
);
750 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
752 case 2: /* Indirect register */
754 return gen_ldst(s
, opsize
, reg
, val
, what
);
755 case 3: /* Indirect postincrement. */
757 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
758 /* ??? This is not exception safe. The instruction may still
759 fault after this point. */
760 if (what
== EA_STORE
|| !addrp
)
761 tcg_gen_addi_i32(reg
, reg
, opsize_bytes(opsize
));
763 case 4: /* Indirect predecrememnt. */
766 if (addrp
&& what
== EA_STORE
) {
769 tmp
= gen_lea(env
, s
, insn
, opsize
);
770 if (IS_NULL_QREG(tmp
))
775 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
776 /* ??? This is not exception safe. The instruction may still
777 fault after this point. */
778 if (what
== EA_STORE
|| !addrp
) {
780 tcg_gen_mov_i32(reg
, tmp
);
784 case 5: /* Indirect displacement. */
785 case 6: /* Indirect index + displacement. */
786 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
789 case 0: /* Absolute short. */
790 case 1: /* Absolute long. */
791 case 2: /* pc displacement */
792 case 3: /* pc index+displacement. */
793 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
794 case 4: /* Immediate. */
795 /* Sign extend values for consistency. */
798 if (what
== EA_LOADS
) {
799 offset
= (int8_t)read_im8(env
, s
);
801 offset
= read_im8(env
, s
);
805 if (what
== EA_LOADS
) {
806 offset
= (int16_t)read_im16(env
, s
);
808 offset
= read_im16(env
, s
);
812 offset
= read_im32(env
, s
);
815 g_assert_not_reached();
817 return tcg_const_i32(offset
);
822 /* Should never happen. */
834 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
840 /* The CC_OP_CMP form can handle most normal comparisons directly. */
841 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
848 tcond
= TCG_COND_LEU
;
852 tcond
= TCG_COND_LTU
;
861 c
->v2
= tcg_const_i32(0);
862 c
->v1
= tmp
= tcg_temp_new();
863 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
864 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
879 c
->v2
= tcg_const_i32(0);
885 tcond
= TCG_COND_NEVER
;
887 case 14: /* GT (!(Z || (N ^ V))) */
888 case 15: /* LE (Z || (N ^ V)) */
889 /* Logic operations clear V, which simplifies LE to (Z || N),
890 and since Z and N are co-located, this becomes a normal
892 if (op
== CC_OP_LOGIC
) {
898 case 12: /* GE (!(N ^ V)) */
899 case 13: /* LT (N ^ V) */
900 /* Logic operations clear V, which simplifies this to N. */
901 if (op
!= CC_OP_LOGIC
) {
905 case 10: /* PL (!N) */
906 case 11: /* MI (N) */
907 /* Several cases represent N normally. */
908 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
909 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
916 case 6: /* NE (!Z) */
918 /* Some cases fold Z into N. */
919 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
920 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
927 case 4: /* CC (!C) */
929 /* Some cases fold C into X. */
930 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
931 op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
) {
937 case 8: /* VC (!V) */
939 /* Logic operations clear V and C. */
940 if (op
== CC_OP_LOGIC
) {
941 tcond
= TCG_COND_NEVER
;
948 /* Otherwise, flush flag state to CC_OP_FLAGS. */
955 /* Invalid, or handled above. */
957 case 2: /* HI (!C && !Z) -> !(C || Z)*/
958 case 3: /* LS (C || Z) */
959 c
->v1
= tmp
= tcg_temp_new();
961 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
962 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
965 case 4: /* CC (!C) */
970 case 6: /* NE (!Z) */
975 case 8: /* VC (!V) */
980 case 10: /* PL (!N) */
981 case 11: /* MI (N) */
985 case 12: /* GE (!(N ^ V)) */
986 case 13: /* LT (N ^ V) */
987 c
->v1
= tmp
= tcg_temp_new();
989 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
992 case 14: /* GT (!(Z || (N ^ V))) */
993 case 15: /* LE (Z || (N ^ V)) */
994 c
->v1
= tmp
= tcg_temp_new();
996 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
997 tcg_gen_neg_i32(tmp
, tmp
);
998 tmp2
= tcg_temp_new();
999 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1000 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1001 tcg_temp_free(tmp2
);
1002 tcond
= TCG_COND_LT
;
1007 if ((cond
& 1) == 0) {
1008 tcond
= tcg_invert_cond(tcond
);
1013 static void free_cond(DisasCompare
*c
)
1016 tcg_temp_free(c
->v1
);
1019 tcg_temp_free(c
->v2
);
1023 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1027 gen_cc_cond(&c
, s
, cond
);
1029 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1033 /* Force a TB lookup after an instruction that changes the CPU state. */
1034 static void gen_lookup_tb(DisasContext
*s
)
1037 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1038 s
->is_jmp
= DISAS_UPDATE
;
1041 /* Generate a jump to an immediate address. */
1042 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
1045 tcg_gen_movi_i32(QREG_PC
, dest
);
1046 s
->is_jmp
= DISAS_JUMP
;
1049 /* Generate a jump to the address in qreg DEST. */
1050 static void gen_jmp(DisasContext
*s
, TCGv dest
)
1053 tcg_gen_mov_i32(QREG_PC
, dest
);
1054 s
->is_jmp
= DISAS_JUMP
;
1057 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
1060 gen_jmp_im(s
, where
);
1061 gen_helper_raise_exception(cpu_env
, tcg_const_i32(nr
));
1064 static inline void gen_addr_fault(DisasContext
*s
)
1066 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
1069 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1070 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1071 op_sign ? EA_LOADS : EA_LOADU); \
1072 if (IS_NULL_QREG(result)) { \
1073 gen_addr_fault(s); \
1078 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1079 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1080 if (IS_NULL_QREG(ea_result)) { \
1081 gen_addr_fault(s); \
1086 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1088 #ifndef CONFIG_USER_ONLY
1089 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
1090 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1096 /* Generate a jump to an immediate address. */
1097 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1099 if (unlikely(s
->singlestep_enabled
)) {
1100 gen_exception(s
, dest
, EXCP_DEBUG
);
1101 } else if (use_goto_tb(s
, dest
)) {
1103 tcg_gen_movi_i32(QREG_PC
, dest
);
1104 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1106 gen_jmp_im(s
, dest
);
1109 s
->is_jmp
= DISAS_TB_JUMP
;
1118 cond
= (insn
>> 8) & 0xf;
1119 gen_cc_cond(&c
, s
, cond
);
1121 tmp
= tcg_temp_new();
1122 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1125 tcg_gen_neg_i32(tmp
, tmp
);
1126 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1138 reg
= DREG(insn
, 0);
1140 offset
= (int16_t)read_im16(env
, s
);
1141 l1
= gen_new_label();
1142 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1144 tmp
= tcg_temp_new();
1145 tcg_gen_ext16s_i32(tmp
, reg
);
1146 tcg_gen_addi_i32(tmp
, tmp
, -1);
1147 gen_partset_reg(OS_WORD
, reg
, tmp
);
1148 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1149 gen_jmp_tb(s
, 1, base
+ offset
);
1151 gen_jmp_tb(s
, 0, s
->pc
);
1154 DISAS_INSN(undef_mac
)
1156 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
1159 DISAS_INSN(undef_fpu
)
1161 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
1166 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
1168 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
1169 cpu_abort(CPU(cpu
), "Illegal instruction: %04x @ %08x", insn
, s
->pc
- 2);
1179 sign
= (insn
& 0x100) != 0;
1180 reg
= DREG(insn
, 9);
1181 tmp
= tcg_temp_new();
1183 tcg_gen_ext16s_i32(tmp
, reg
);
1185 tcg_gen_ext16u_i32(tmp
, reg
);
1186 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1187 tcg_gen_mul_i32(tmp
, tmp
, src
);
1188 tcg_gen_mov_i32(reg
, tmp
);
1189 gen_logic_cc(s
, tmp
, OS_WORD
);
1199 sign
= (insn
& 0x100) != 0;
1200 reg
= DREG(insn
, 9);
1202 tcg_gen_ext16s_i32(QREG_DIV1
, reg
);
1204 tcg_gen_ext16u_i32(QREG_DIV1
, reg
);
1206 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1207 tcg_gen_mov_i32(QREG_DIV2
, src
);
1209 gen_helper_divs(cpu_env
, tcg_const_i32(1));
1211 gen_helper_divu(cpu_env
, tcg_const_i32(1));
1214 tmp
= tcg_temp_new();
1215 src
= tcg_temp_new();
1216 tcg_gen_ext16u_i32(tmp
, QREG_DIV1
);
1217 tcg_gen_shli_i32(src
, QREG_DIV2
, 16);
1218 tcg_gen_or_i32(reg
, tmp
, src
);
1220 set_cc_op(s
, CC_OP_FLAGS
);
1230 ext
= read_im16(env
, s
);
1232 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1235 num
= DREG(ext
, 12);
1237 tcg_gen_mov_i32(QREG_DIV1
, num
);
1238 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1239 tcg_gen_mov_i32(QREG_DIV2
, den
);
1241 gen_helper_divs(cpu_env
, tcg_const_i32(0));
1243 gen_helper_divu(cpu_env
, tcg_const_i32(0));
1245 if ((ext
& 7) == ((ext
>> 12) & 7)) {
1247 tcg_gen_mov_i32 (reg
, QREG_DIV1
);
1250 tcg_gen_mov_i32 (reg
, QREG_DIV2
);
1252 set_cc_op(s
, CC_OP_FLAGS
);
1265 add
= (insn
& 0x4000) != 0;
1266 opsize
= insn_opsize(insn
);
1267 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
1268 dest
= tcg_temp_new();
1270 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1274 SRC_EA(env
, src
, opsize
, 1, NULL
);
1277 tcg_gen_add_i32(dest
, tmp
, src
);
1278 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1279 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1281 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1282 tcg_gen_sub_i32(dest
, tmp
, src
);
1283 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1285 gen_update_cc_add(dest
, src
, opsize
);
1287 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1289 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1291 tcg_temp_free(dest
);
1294 /* Reverse the order of the bits in REG. */
1298 reg
= DREG(insn
, 0);
1299 gen_helper_bitrev(reg
, reg
);
1302 DISAS_INSN(bitop_reg
)
1312 if ((insn
& 0x38) != 0)
1316 op
= (insn
>> 6) & 3;
1317 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1320 src2
= tcg_temp_new();
1321 if (opsize
== OS_BYTE
)
1322 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1324 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1326 tmp
= tcg_const_i32(1);
1327 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1328 tcg_temp_free(src2
);
1330 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1332 dest
= tcg_temp_new();
1335 tcg_gen_xor_i32(dest
, src1
, tmp
);
1338 tcg_gen_andc_i32(dest
, src1
, tmp
);
1341 tcg_gen_or_i32(dest
, src1
, tmp
);
1348 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1350 tcg_temp_free(dest
);
1356 reg
= DREG(insn
, 0);
1358 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1359 gen_logic_cc(s
, reg
, OS_LONG
);
1362 static void gen_push(DisasContext
*s
, TCGv val
)
1366 tmp
= tcg_temp_new();
1367 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1368 gen_store(s
, OS_LONG
, tmp
, val
);
1369 tcg_gen_mov_i32(QREG_SP
, tmp
);
1381 mask
= read_im16(env
, s
);
1382 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1383 if (IS_NULL_QREG(tmp
)) {
1387 addr
= tcg_temp_new();
1388 tcg_gen_mov_i32(addr
, tmp
);
1389 is_load
= ((insn
& 0x0400) != 0);
1390 for (i
= 0; i
< 16; i
++, mask
>>= 1) {
1397 tmp
= gen_load(s
, OS_LONG
, addr
, 0);
1398 tcg_gen_mov_i32(reg
, tmp
);
1400 gen_store(s
, OS_LONG
, addr
, reg
);
1403 tcg_gen_addi_i32(addr
, addr
, 4);
1408 DISAS_INSN(bitop_im
)
1418 if ((insn
& 0x38) != 0)
1422 op
= (insn
>> 6) & 3;
1424 bitnum
= read_im16(env
, s
);
1425 if (bitnum
& 0xff00) {
1426 disas_undef(env
, s
, insn
);
1430 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1433 if (opsize
== OS_BYTE
)
1439 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
1442 tmp
= tcg_temp_new();
1445 tcg_gen_xori_i32(tmp
, src1
, mask
);
1448 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
1451 tcg_gen_ori_i32(tmp
, src1
, mask
);
1456 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
1461 DISAS_INSN(arith_im
)
1469 op
= (insn
>> 9) & 7;
1470 SRC_EA(env
, src1
, OS_LONG
, 0, (op
== 6) ? NULL
: &addr
);
1471 im
= read_im32(env
, s
);
1472 dest
= tcg_temp_new();
1475 tcg_gen_ori_i32(dest
, src1
, im
);
1476 gen_logic_cc(s
, dest
, OS_LONG
);
1479 tcg_gen_andi_i32(dest
, src1
, im
);
1480 gen_logic_cc(s
, dest
, OS_LONG
);
1483 tcg_gen_mov_i32(dest
, src1
);
1484 tcg_gen_setcondi_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
1485 tcg_gen_subi_i32(dest
, dest
, im
);
1486 gen_update_cc_add(dest
, tcg_const_i32(im
), OS_LONG
);
1487 set_cc_op(s
, CC_OP_SUBL
);
1490 tcg_gen_mov_i32(dest
, src1
);
1491 tcg_gen_addi_i32(dest
, dest
, im
);
1492 gen_update_cc_add(dest
, tcg_const_i32(im
), OS_LONG
);
1493 tcg_gen_setcondi_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
1494 set_cc_op(s
, CC_OP_ADDL
);
1497 tcg_gen_xori_i32(dest
, src1
, im
);
1498 gen_logic_cc(s
, dest
, OS_LONG
);
1501 gen_update_cc_add(src1
, tcg_const_i32(im
), OS_LONG
);
1502 set_cc_op(s
, CC_OP_CMPL
);
1508 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1516 reg
= DREG(insn
, 0);
1517 tcg_gen_bswap32_i32(reg
, reg
);
1527 switch (insn
>> 12) {
1528 case 1: /* move.b */
1531 case 2: /* move.l */
1534 case 3: /* move.w */
1540 SRC_EA(env
, src
, opsize
, 1, NULL
);
1541 op
= (insn
>> 6) & 7;
1544 /* The value will already have been sign extended. */
1545 dest
= AREG(insn
, 9);
1546 tcg_gen_mov_i32(dest
, src
);
1550 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
1551 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
1552 /* This will be correct because loads sign extend. */
1553 gen_logic_cc(s
, src
, opsize
);
1564 opsize
= insn_opsize(insn
);
1565 SRC_EA(env
, src
, opsize
, 1, &addr
);
1567 gen_flush_flags(s
); /* compute old Z */
1569 /* Perform substract with borrow.
1570 * (X, N) = -(src + X);
1573 z
= tcg_const_i32(0);
1574 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
1575 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
1577 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
1579 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
1581 /* Compute signed-overflow for negation. The normal formula for
1582 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
1583 * this simplies to res & src.
1586 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
1588 /* Copy the rest of the results into place. */
1589 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
1590 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
1592 set_cc_op(s
, CC_OP_FLAGS
);
1594 /* result is in QREG_CC_N */
1596 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
1604 reg
= AREG(insn
, 9);
1605 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1606 if (IS_NULL_QREG(tmp
)) {
1610 tcg_gen_mov_i32(reg
, tmp
);
1617 opsize
= insn_opsize(insn
);
1618 DEST_EA(env
, insn
, opsize
, tcg_const_i32(0), NULL
);
1619 gen_logic_cc(s
, tcg_const_i32(0), opsize
);
1622 static TCGv
gen_get_ccr(DisasContext
*s
)
1628 dest
= tcg_temp_new();
1629 gen_helper_get_ccr(dest
, cpu_env
);
1633 DISAS_INSN(move_from_ccr
)
1637 ccr
= gen_get_ccr(s
);
1638 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
1648 opsize
= insn_opsize(insn
);
1649 SRC_EA(env
, src1
, opsize
, 1, &addr
);
1650 dest
= tcg_temp_new();
1651 tcg_gen_neg_i32(dest
, src1
);
1652 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1653 gen_update_cc_add(dest
, src1
, opsize
);
1654 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
1655 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1656 tcg_temp_free(dest
);
1659 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
1662 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
1663 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
1664 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
1665 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
1666 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
1668 gen_helper_set_sr(cpu_env
, tcg_const_i32(val
));
1670 set_cc_op(s
, CC_OP_FLAGS
);
1673 static void gen_set_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1676 if ((insn
& 0x38) == 0) {
1678 gen_helper_set_ccr(cpu_env
, DREG(insn
, 0));
1680 gen_helper_set_sr(cpu_env
, DREG(insn
, 0));
1682 set_cc_op(s
, CC_OP_FLAGS
);
1683 } else if ((insn
& 0x3f) == 0x3c) {
1685 val
= read_im16(env
, s
);
1686 gen_set_sr_im(s
, val
, ccr_only
);
1688 disas_undef(env
, s
, insn
);
1693 DISAS_INSN(move_to_ccr
)
1695 gen_set_sr(env
, s
, insn
, 1);
1705 opsize
= insn_opsize(insn
);
1706 SRC_EA(env
, src1
, opsize
, 1, &addr
);
1707 dest
= tcg_temp_new();
1708 tcg_gen_not_i32(dest
, src1
);
1709 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1710 gen_logic_cc(s
, dest
, opsize
);
1719 src1
= tcg_temp_new();
1720 src2
= tcg_temp_new();
1721 reg
= DREG(insn
, 0);
1722 tcg_gen_shli_i32(src1
, reg
, 16);
1723 tcg_gen_shri_i32(src2
, reg
, 16);
1724 tcg_gen_or_i32(reg
, src1
, src2
);
1725 gen_logic_cc(s
, reg
, OS_LONG
);
1730 gen_exception(s
, s
->pc
- 2, EXCP_DEBUG
);
1737 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1738 if (IS_NULL_QREG(tmp
)) {
1751 reg
= DREG(insn
, 0);
1752 op
= (insn
>> 6) & 7;
1753 tmp
= tcg_temp_new();
1755 tcg_gen_ext16s_i32(tmp
, reg
);
1757 tcg_gen_ext8s_i32(tmp
, reg
);
1759 gen_partset_reg(OS_WORD
, reg
, tmp
);
1761 tcg_gen_mov_i32(reg
, tmp
);
1762 gen_logic_cc(s
, tmp
, OS_LONG
);
1770 opsize
= insn_opsize(insn
);
1771 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
1772 gen_logic_cc(s
, tmp
, opsize
);
1777 /* Implemented as a NOP. */
1782 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
1785 /* ??? This should be atomic. */
1792 dest
= tcg_temp_new();
1793 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
1794 gen_logic_cc(s
, src1
, OS_BYTE
);
1795 tcg_gen_ori_i32(dest
, src1
, 0x80);
1796 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1806 /* The upper 32 bits of the product are discarded, so
1807 muls.l and mulu.l are functionally equivalent. */
1808 ext
= read_im16(env
, s
);
1810 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1813 reg
= DREG(ext
, 12);
1814 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
1815 dest
= tcg_temp_new();
1816 tcg_gen_mul_i32(dest
, src1
, reg
);
1817 tcg_gen_mov_i32(reg
, dest
);
1818 /* Unlike m68k, coldfire always clears the overflow bit. */
1819 gen_logic_cc(s
, dest
, OS_LONG
);
1822 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
1827 reg
= AREG(insn
, 0);
1828 tmp
= tcg_temp_new();
1829 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1830 gen_store(s
, OS_LONG
, tmp
, reg
);
1831 if ((insn
& 7) != 7) {
1832 tcg_gen_mov_i32(reg
, tmp
);
1834 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
1842 offset
= read_im16(env
, s
);
1843 gen_link(s
, insn
, offset
);
1850 offset
= read_im32(env
, s
);
1851 gen_link(s
, insn
, offset
);
1860 src
= tcg_temp_new();
1861 reg
= AREG(insn
, 0);
1862 tcg_gen_mov_i32(src
, reg
);
1863 tmp
= gen_load(s
, OS_LONG
, src
, 0);
1864 tcg_gen_mov_i32(reg
, tmp
);
1865 tcg_gen_addi_i32(QREG_SP
, src
, 4);
1876 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
1877 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
1885 /* Load the target address first to ensure correct exception
1887 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1888 if (IS_NULL_QREG(tmp
)) {
1892 if ((insn
& 0x40) == 0) {
1894 gen_push(s
, tcg_const_i32(s
->pc
));
1908 if ((insn
& 070) == 010) {
1909 /* Operation on address register is always long. */
1912 opsize
= insn_opsize(insn
);
1914 SRC_EA(env
, src
, opsize
, 1, &addr
);
1915 imm
= (insn
>> 9) & 7;
1919 val
= tcg_const_i32(imm
);
1920 dest
= tcg_temp_new();
1921 tcg_gen_mov_i32(dest
, src
);
1922 if ((insn
& 0x38) == 0x08) {
1923 /* Don't update condition codes if the destination is an
1924 address register. */
1925 if (insn
& 0x0100) {
1926 tcg_gen_sub_i32(dest
, dest
, val
);
1928 tcg_gen_add_i32(dest
, dest
, val
);
1931 if (insn
& 0x0100) {
1932 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
1933 tcg_gen_sub_i32(dest
, dest
, val
);
1934 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1936 tcg_gen_add_i32(dest
, dest
, val
);
1937 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
1938 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1940 gen_update_cc_add(dest
, val
, opsize
);
1942 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1948 case 2: /* One extension word. */
1951 case 3: /* Two extension words. */
1954 case 4: /* No extension words. */
1957 disas_undef(env
, s
, insn
);
1969 op
= (insn
>> 8) & 0xf;
1970 offset
= (int8_t)insn
;
1972 offset
= (int16_t)read_im16(env
, s
);
1973 } else if (offset
== -1) {
1974 offset
= read_im32(env
, s
);
1978 gen_push(s
, tcg_const_i32(s
->pc
));
1982 l1
= gen_new_label();
1983 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
1984 gen_jmp_tb(s
, 1, base
+ offset
);
1986 gen_jmp_tb(s
, 0, s
->pc
);
1988 /* Unconditional branch. */
1989 gen_jmp_tb(s
, 0, base
+ offset
);
1998 tcg_gen_movi_i32(DREG(insn
, 9), val
);
1999 gen_logic_cc(s
, tcg_const_i32(val
), OS_LONG
);
2012 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
2013 reg
= DREG(insn
, 9);
2014 tcg_gen_mov_i32(reg
, src
);
2015 gen_logic_cc(s
, src
, opsize
);
2026 opsize
= insn_opsize(insn
);
2027 reg
= gen_extend(DREG(insn
, 9), opsize
, 0);
2028 dest
= tcg_temp_new();
2030 SRC_EA(env
, src
, opsize
, 0, &addr
);
2031 tcg_gen_or_i32(dest
, src
, reg
);
2032 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2034 SRC_EA(env
, src
, opsize
, 0, NULL
);
2035 tcg_gen_or_i32(dest
, src
, reg
);
2036 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
2038 gen_logic_cc(s
, dest
, opsize
);
2046 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
2047 reg
= AREG(insn
, 9);
2048 tcg_gen_sub_i32(reg
, reg
, src
);
2051 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
2055 gen_flush_flags(s
); /* compute old Z */
2057 /* Perform substract with borrow.
2058 * (X, N) = dest - (src + X);
2061 tmp
= tcg_const_i32(0);
2062 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
2063 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
2064 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2065 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2067 /* Compute signed-overflow for substract. */
2069 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
2070 tcg_gen_xor_i32(tmp
, dest
, src
);
2071 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
2074 /* Copy the rest of the results into place. */
2075 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2076 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2078 set_cc_op(s
, CC_OP_FLAGS
);
2080 /* result is in QREG_CC_N */
2083 DISAS_INSN(subx_reg
)
2089 opsize
= insn_opsize(insn
);
2091 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
2092 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
2094 gen_subx(s
, src
, dest
, opsize
);
2096 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
2099 DISAS_INSN(subx_mem
)
2107 opsize
= insn_opsize(insn
);
2109 addr_src
= AREG(insn
, 0);
2110 tcg_gen_subi_i32(addr_src
, addr_src
, opsize
);
2111 src
= gen_load(s
, opsize
, addr_src
, 1);
2113 addr_dest
= AREG(insn
, 9);
2114 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize
);
2115 dest
= gen_load(s
, opsize
, addr_dest
, 1);
2117 gen_subx(s
, src
, dest
, opsize
);
2119 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
2127 val
= (insn
>> 9) & 7;
2130 src
= tcg_const_i32(val
);
2131 gen_logic_cc(s
, src
, OS_LONG
);
2132 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
2141 opsize
= insn_opsize(insn
);
2142 SRC_EA(env
, src
, opsize
, 1, NULL
);
2143 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
2144 gen_update_cc_cmp(s
, reg
, src
, opsize
);
2158 SRC_EA(env
, src
, opsize
, 1, NULL
);
2159 reg
= AREG(insn
, 9);
2160 gen_update_cc_cmp(s
, reg
, src
, opsize
);
2170 opsize
= insn_opsize(insn
);
2172 SRC_EA(env
, src
, opsize
, 0, &addr
);
2173 dest
= tcg_temp_new();
2174 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
2175 gen_logic_cc(s
, dest
, opsize
);
2176 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2179 static void do_exg(TCGv reg1
, TCGv reg2
)
2181 TCGv temp
= tcg_temp_new();
2182 tcg_gen_mov_i32(temp
, reg1
);
2183 tcg_gen_mov_i32(reg1
, reg2
);
2184 tcg_gen_mov_i32(reg2
, temp
);
2185 tcg_temp_free(temp
);
2190 /* exchange Dx and Dy */
2191 do_exg(DREG(insn
, 9), DREG(insn
, 0));
2196 /* exchange Ax and Ay */
2197 do_exg(AREG(insn
, 9), AREG(insn
, 0));
2202 /* exchange Dx and Ay */
2203 do_exg(DREG(insn
, 9), AREG(insn
, 0));
2214 dest
= tcg_temp_new();
2216 opsize
= insn_opsize(insn
);
2217 reg
= DREG(insn
, 9);
2219 SRC_EA(env
, src
, opsize
, 0, &addr
);
2220 tcg_gen_and_i32(dest
, src
, reg
);
2221 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2223 SRC_EA(env
, src
, opsize
, 0, NULL
);
2224 tcg_gen_and_i32(dest
, src
, reg
);
2225 gen_partset_reg(opsize
, reg
, dest
);
2227 tcg_temp_free(dest
);
2228 gen_logic_cc(s
, dest
, opsize
);
2236 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
2237 reg
= AREG(insn
, 9);
2238 tcg_gen_add_i32(reg
, reg
, src
);
2241 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
2245 gen_flush_flags(s
); /* compute old Z */
2247 /* Perform addition with carry.
2248 * (X, N) = src + dest + X;
2251 tmp
= tcg_const_i32(0);
2252 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
2253 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
2254 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2256 /* Compute signed-overflow for addition. */
2258 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
2259 tcg_gen_xor_i32(tmp
, dest
, src
);
2260 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
2263 /* Copy the rest of the results into place. */
2264 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2265 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2267 set_cc_op(s
, CC_OP_FLAGS
);
2269 /* result is in QREG_CC_N */
2272 DISAS_INSN(addx_reg
)
2278 opsize
= insn_opsize(insn
);
2280 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
2281 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
2283 gen_addx(s
, src
, dest
, opsize
);
2285 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
2288 DISAS_INSN(addx_mem
)
2296 opsize
= insn_opsize(insn
);
2298 addr_src
= AREG(insn
, 0);
2299 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
2300 src
= gen_load(s
, opsize
, addr_src
, 1);
2302 addr_dest
= AREG(insn
, 9);
2303 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
2304 dest
= gen_load(s
, opsize
, addr_dest
, 1);
2306 gen_addx(s
, src
, dest
, opsize
);
2308 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
2311 /* TODO: This could be implemented without helper functions. */
2312 DISAS_INSN(shift_im
)
2318 set_cc_op(s
, CC_OP_FLAGS
);
2320 reg
= DREG(insn
, 0);
2321 tmp
= (insn
>> 9) & 7;
2324 shift
= tcg_const_i32(tmp
);
2325 /* No need to flush flags becuse we know we will set C flag. */
2327 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
2330 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
2332 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
2337 DISAS_INSN(shift_reg
)
2342 reg
= DREG(insn
, 0);
2343 shift
= DREG(insn
, 9);
2345 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
2348 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
2350 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
2353 set_cc_op(s
, CC_OP_FLAGS
);
2359 reg
= DREG(insn
, 0);
2360 gen_logic_cc(s
, reg
, OS_LONG
);
2361 gen_helper_ff1(reg
, reg
);
2364 static TCGv
gen_get_sr(DisasContext
*s
)
2369 ccr
= gen_get_ccr(s
);
2370 sr
= tcg_temp_new();
2371 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2372 tcg_gen_or_i32(sr
, sr
, ccr
);
2382 ext
= read_im16(env
, s
);
2383 if (ext
!= 0x46FC) {
2384 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
2387 ext
= read_im16(env
, s
);
2388 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
2389 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
2392 gen_push(s
, gen_get_sr(s
));
2393 gen_set_sr_im(s
, ext
, 0);
2396 DISAS_INSN(move_from_sr
)
2400 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
2401 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2405 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
2408 DISAS_INSN(move_to_sr
)
2411 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2414 gen_set_sr(env
, s
, insn
, 0);
2418 DISAS_INSN(move_from_usp
)
2421 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2424 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
2425 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2428 DISAS_INSN(move_to_usp
)
2431 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2434 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
2435 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2440 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
2448 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2452 ext
= read_im16(env
, s
);
2454 gen_set_sr_im(s
, ext
, 0);
2455 tcg_gen_movi_i32(cpu_halted
, 1);
2456 gen_exception(s
, s
->pc
, EXCP_HLT
);
2462 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2465 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
2474 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2478 ext
= read_im16(env
, s
);
2481 reg
= AREG(ext
, 12);
2483 reg
= DREG(ext
, 12);
2485 gen_helper_movec(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
2492 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2495 /* ICache fetch. Implement as no-op. */
2501 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2504 /* Cache push/invalidate. Implement as no-op. */
2509 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2514 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2517 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2520 /* TODO: Implement wdebug. */
2521 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
2526 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
2529 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2530 immediately before the next FP instruction is executed. */
2544 ext
= read_im16(env
, s
);
2545 opmode
= ext
& 0x7f;
2546 switch ((ext
>> 13) & 7) {
2551 case 3: /* fmove out */
2553 tmp32
= tcg_temp_new_i32();
2555 /* ??? TODO: Proper behavior on overflow. */
2556 switch ((ext
>> 10) & 7) {
2559 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2563 gen_helper_f64_to_f32(tmp32
, cpu_env
, src
);
2567 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2569 case 5: /* OS_DOUBLE */
2570 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2571 switch ((insn
>> 3) & 7) {
2576 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2579 offset
= cpu_ldsw_code(env
, s
->pc
);
2581 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2586 gen_store64(s
, tmp32
, src
);
2587 switch ((insn
>> 3) & 7) {
2589 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2590 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2593 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2596 tcg_temp_free_i32(tmp32
);
2600 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2605 DEST_EA(env
, insn
, opsize
, tmp32
, NULL
);
2606 tcg_temp_free_i32(tmp32
);
2608 case 4: /* fmove to control register. */
2609 switch ((ext
>> 10) & 7) {
2611 /* Not implemented. Ignore writes. */
2616 cpu_abort(NULL
, "Unimplemented: fmove to control %d",
2620 case 5: /* fmove from control register. */
2621 switch ((ext
>> 10) & 7) {
2623 /* Not implemented. Always return zero. */
2624 tmp32
= tcg_const_i32(0);
2629 cpu_abort(NULL
, "Unimplemented: fmove from control %d",
2633 DEST_EA(env
, insn
, OS_LONG
, tmp32
, NULL
);
2635 case 6: /* fmovem */
2641 if ((ext
& 0x1f00) != 0x1000 || (ext
& 0xff) == 0)
2643 tmp32
= gen_lea(env
, s
, insn
, OS_LONG
);
2644 if (IS_NULL_QREG(tmp32
)) {
2648 addr
= tcg_temp_new_i32();
2649 tcg_gen_mov_i32(addr
, tmp32
);
2651 for (i
= 0; i
< 8; i
++) {
2654 if (ext
& (1 << 13)) {
2656 tcg_gen_qemu_stf64(dest
, addr
, IS_USER(s
));
2659 tcg_gen_qemu_ldf64(dest
, addr
, IS_USER(s
));
2661 if (ext
& (mask
- 1))
2662 tcg_gen_addi_i32(addr
, addr
, 8);
2666 tcg_temp_free_i32(addr
);
2670 if (ext
& (1 << 14)) {
2671 /* Source effective address. */
2672 switch ((ext
>> 10) & 7) {
2673 case 0: opsize
= OS_LONG
; break;
2674 case 1: opsize
= OS_SINGLE
; break;
2675 case 4: opsize
= OS_WORD
; break;
2676 case 5: opsize
= OS_DOUBLE
; break;
2677 case 6: opsize
= OS_BYTE
; break;
2681 if (opsize
== OS_DOUBLE
) {
2682 tmp32
= tcg_temp_new_i32();
2683 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2684 switch ((insn
>> 3) & 7) {
2689 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2692 offset
= cpu_ldsw_code(env
, s
->pc
);
2694 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2697 offset
= cpu_ldsw_code(env
, s
->pc
);
2698 offset
+= s
->pc
- 2;
2700 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2705 src
= gen_load64(s
, tmp32
);
2706 switch ((insn
>> 3) & 7) {
2708 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2709 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2712 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2715 tcg_temp_free_i32(tmp32
);
2717 SRC_EA(env
, tmp32
, opsize
, 1, NULL
);
2718 src
= tcg_temp_new_i64();
2723 gen_helper_i32_to_f64(src
, cpu_env
, tmp32
);
2726 gen_helper_f32_to_f64(src
, cpu_env
, tmp32
);
2731 /* Source register. */
2732 src
= FREG(ext
, 10);
2734 dest
= FREG(ext
, 7);
2735 res
= tcg_temp_new_i64();
2737 tcg_gen_mov_f64(res
, dest
);
2741 case 0: case 0x40: case 0x44: /* fmove */
2742 tcg_gen_mov_f64(res
, src
);
2745 gen_helper_iround_f64(res
, cpu_env
, src
);
2748 case 3: /* fintrz */
2749 gen_helper_itrunc_f64(res
, cpu_env
, src
);
2752 case 4: case 0x41: case 0x45: /* fsqrt */
2753 gen_helper_sqrt_f64(res
, cpu_env
, src
);
2755 case 0x18: case 0x58: case 0x5c: /* fabs */
2756 gen_helper_abs_f64(res
, src
);
2758 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2759 gen_helper_chs_f64(res
, src
);
2761 case 0x20: case 0x60: case 0x64: /* fdiv */
2762 gen_helper_div_f64(res
, cpu_env
, res
, src
);
2764 case 0x22: case 0x62: case 0x66: /* fadd */
2765 gen_helper_add_f64(res
, cpu_env
, res
, src
);
2767 case 0x23: case 0x63: case 0x67: /* fmul */
2768 gen_helper_mul_f64(res
, cpu_env
, res
, src
);
2770 case 0x28: case 0x68: case 0x6c: /* fsub */
2771 gen_helper_sub_f64(res
, cpu_env
, res
, src
);
2773 case 0x38: /* fcmp */
2774 gen_helper_sub_cmp_f64(res
, cpu_env
, res
, src
);
2778 case 0x3a: /* ftst */
2779 tcg_gen_mov_f64(res
, src
);
2786 if (ext
& (1 << 14)) {
2787 tcg_temp_free_i64(src
);
2790 if (opmode
& 0x40) {
2791 if ((opmode
& 0x4) != 0)
2793 } else if ((s
->fpcr
& M68K_FPCR_PREC
) == 0) {
2798 TCGv tmp
= tcg_temp_new_i32();
2799 gen_helper_f64_to_f32(tmp
, cpu_env
, res
);
2800 gen_helper_f32_to_f64(res
, cpu_env
, tmp
);
2801 tcg_temp_free_i32(tmp
);
2803 tcg_gen_mov_f64(QREG_FP_RESULT
, res
);
2805 tcg_gen_mov_f64(dest
, res
);
2807 tcg_temp_free_i64(res
);
2810 /* FIXME: Is this right for offset addressing modes? */
2812 disas_undef_fpu(env
, s
, insn
);
2823 offset
= cpu_ldsw_code(env
, s
->pc
);
2825 if (insn
& (1 << 6)) {
2826 offset
= (offset
<< 16) | read_im16(env
, s
);
2829 l1
= gen_new_label();
2830 /* TODO: Raise BSUN exception. */
2831 flag
= tcg_temp_new();
2832 gen_helper_compare_f64(flag
, cpu_env
, QREG_FP_RESULT
);
2833 /* Jump to l1 if condition is true. */
2834 switch (insn
& 0xf) {
2837 case 1: /* eq (=0) */
2838 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2840 case 2: /* ogt (=1) */
2841 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(1), l1
);
2843 case 3: /* oge (=0 or =1) */
2844 tcg_gen_brcond_i32(TCG_COND_LEU
, flag
, tcg_const_i32(1), l1
);
2846 case 4: /* olt (=-1) */
2847 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(0), l1
);
2849 case 5: /* ole (=-1 or =0) */
2850 tcg_gen_brcond_i32(TCG_COND_LE
, flag
, tcg_const_i32(0), l1
);
2852 case 6: /* ogl (=-1 or =1) */
2853 tcg_gen_andi_i32(flag
, flag
, 1);
2854 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2856 case 7: /* or (=2) */
2857 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(2), l1
);
2859 case 8: /* un (<2) */
2860 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(2), l1
);
2862 case 9: /* ueq (=0 or =2) */
2863 tcg_gen_andi_i32(flag
, flag
, 1);
2864 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2866 case 10: /* ugt (>0) */
2867 tcg_gen_brcond_i32(TCG_COND_GT
, flag
, tcg_const_i32(0), l1
);
2869 case 11: /* uge (>=0) */
2870 tcg_gen_brcond_i32(TCG_COND_GE
, flag
, tcg_const_i32(0), l1
);
2872 case 12: /* ult (=-1 or =2) */
2873 tcg_gen_brcond_i32(TCG_COND_GEU
, flag
, tcg_const_i32(2), l1
);
2875 case 13: /* ule (!=1) */
2876 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(1), l1
);
2878 case 14: /* ne (!=0) */
2879 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2885 gen_jmp_tb(s
, 0, s
->pc
);
2887 gen_jmp_tb(s
, 1, addr
+ offset
);
2890 DISAS_INSN(frestore
)
2892 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2894 /* TODO: Implement frestore. */
2895 cpu_abort(CPU(cpu
), "FRESTORE not implemented");
2900 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2902 /* TODO: Implement fsave. */
2903 cpu_abort(CPU(cpu
), "FSAVE not implemented");
2906 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
2908 TCGv tmp
= tcg_temp_new();
2909 if (s
->env
->macsr
& MACSR_FI
) {
2911 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
2913 tcg_gen_shli_i32(tmp
, val
, 16);
2914 } else if (s
->env
->macsr
& MACSR_SU
) {
2916 tcg_gen_sari_i32(tmp
, val
, 16);
2918 tcg_gen_ext16s_i32(tmp
, val
);
2921 tcg_gen_shri_i32(tmp
, val
, 16);
2923 tcg_gen_ext16u_i32(tmp
, val
);
2928 static void gen_mac_clear_flags(void)
2930 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
2931 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
2947 s
->mactmp
= tcg_temp_new_i64();
2951 ext
= read_im16(env
, s
);
2953 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
2954 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
2955 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
2956 disas_undef(env
, s
, insn
);
2960 /* MAC with load. */
2961 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2962 addr
= tcg_temp_new();
2963 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
2964 /* Load the value now to ensure correct exception behavior.
2965 Perform writeback after reading the MAC inputs. */
2966 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
2969 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
2970 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
2972 loadval
= addr
= NULL_QREG
;
2973 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2974 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2977 gen_mac_clear_flags();
2980 /* Disabled because conditional branches clobber temporary vars. */
2981 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
2982 /* Skip the multiply if we know we will ignore it. */
2983 l1
= gen_new_label();
2984 tmp
= tcg_temp_new();
2985 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
2986 gen_op_jmp_nz32(tmp
, l1
);
2990 if ((ext
& 0x0800) == 0) {
2992 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
2993 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
2995 if (s
->env
->macsr
& MACSR_FI
) {
2996 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
2998 if (s
->env
->macsr
& MACSR_SU
)
2999 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
3001 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
3002 switch ((ext
>> 9) & 3) {
3004 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
3007 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
3013 /* Save the overflow flag from the multiply. */
3014 saved_flags
= tcg_temp_new();
3015 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
3017 saved_flags
= NULL_QREG
;
3021 /* Disabled because conditional branches clobber temporary vars. */
3022 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
3023 /* Skip the accumulate if the value is already saturated. */
3024 l1
= gen_new_label();
3025 tmp
= tcg_temp_new();
3026 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
3027 gen_op_jmp_nz32(tmp
, l1
);
3032 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
3034 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
3036 if (s
->env
->macsr
& MACSR_FI
)
3037 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
3038 else if (s
->env
->macsr
& MACSR_SU
)
3039 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
3041 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
3044 /* Disabled because conditional branches clobber temporary vars. */
3050 /* Dual accumulate variant. */
3051 acc
= (ext
>> 2) & 3;
3052 /* Restore the overflow flag from the multiplier. */
3053 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
3055 /* Disabled because conditional branches clobber temporary vars. */
3056 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
3057 /* Skip the accumulate if the value is already saturated. */
3058 l1
= gen_new_label();
3059 tmp
= tcg_temp_new();
3060 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
3061 gen_op_jmp_nz32(tmp
, l1
);
3065 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
3067 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
3068 if (s
->env
->macsr
& MACSR_FI
)
3069 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
3070 else if (s
->env
->macsr
& MACSR_SU
)
3071 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
3073 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
3075 /* Disabled because conditional branches clobber temporary vars. */
3080 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
3084 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
3085 tcg_gen_mov_i32(rw
, loadval
);
3086 /* FIXME: Should address writeback happen with the masked or
3088 switch ((insn
>> 3) & 7) {
3089 case 3: /* Post-increment. */
3090 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
3092 case 4: /* Pre-decrement. */
3093 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
3098 DISAS_INSN(from_mac
)
3104 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
3105 accnum
= (insn
>> 9) & 3;
3106 acc
= MACREG(accnum
);
3107 if (s
->env
->macsr
& MACSR_FI
) {
3108 gen_helper_get_macf(rx
, cpu_env
, acc
);
3109 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
3110 tcg_gen_extrl_i64_i32(rx
, acc
);
3111 } else if (s
->env
->macsr
& MACSR_SU
) {
3112 gen_helper_get_macs(rx
, acc
);
3114 gen_helper_get_macu(rx
, acc
);
3117 tcg_gen_movi_i64(acc
, 0);
3118 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
3122 DISAS_INSN(move_mac
)
3124 /* FIXME: This can be done without a helper. */
3128 dest
= tcg_const_i32((insn
>> 9) & 3);
3129 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
3130 gen_mac_clear_flags();
3131 gen_helper_mac_set_flags(cpu_env
, dest
);
3134 DISAS_INSN(from_macsr
)
3138 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
3139 tcg_gen_mov_i32(reg
, QREG_MACSR
);
3142 DISAS_INSN(from_mask
)
3145 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
3146 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
3149 DISAS_INSN(from_mext
)
3153 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
3154 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
3155 if (s
->env
->macsr
& MACSR_FI
)
3156 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
3158 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
3161 DISAS_INSN(macsr_to_ccr
)
3163 TCGv tmp
= tcg_temp_new();
3164 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
3165 gen_helper_set_sr(cpu_env
, tmp
);
3167 set_cc_op(s
, CC_OP_FLAGS
);
3175 accnum
= (insn
>> 9) & 3;
3176 acc
= MACREG(accnum
);
3177 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
3178 if (s
->env
->macsr
& MACSR_FI
) {
3179 tcg_gen_ext_i32_i64(acc
, val
);
3180 tcg_gen_shli_i64(acc
, acc
, 8);
3181 } else if (s
->env
->macsr
& MACSR_SU
) {
3182 tcg_gen_ext_i32_i64(acc
, val
);
3184 tcg_gen_extu_i32_i64(acc
, val
);
3186 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
3187 gen_mac_clear_flags();
3188 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
3191 DISAS_INSN(to_macsr
)
3194 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
3195 gen_helper_set_macsr(cpu_env
, val
);
3202 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
3203 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
3210 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
3211 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
3212 if (s
->env
->macsr
& MACSR_FI
)
3213 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
3214 else if (s
->env
->macsr
& MACSR_SU
)
3215 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
3217 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
3220 static disas_proc opcode_table
[65536];
3223 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
3229 /* Sanity check. All set bits must be included in the mask. */
3230 if (opcode
& ~mask
) {
3232 "qemu internal error: bogus opcode definition %04x/%04x\n",
3236 /* This could probably be cleverer. For now just optimize the case where
3237 the top bits are known. */
3238 /* Find the first zero bit in the mask. */
3240 while ((i
& mask
) != 0)
3242 /* Iterate over all combinations of this and lower bits. */
3247 from
= opcode
& ~(i
- 1);
3249 for (i
= from
; i
< to
; i
++) {
3250 if ((i
& mask
) == opcode
)
3251 opcode_table
[i
] = proc
;
3255 /* Register m68k opcode handlers. Order is important.
3256 Later insn override earlier ones. */
3257 void register_m68k_insns (CPUM68KState
*env
)
3259 /* Build the opcode table only once to avoid
3260 multithreading issues. */
3261 if (opcode_table
[0] != NULL
) {
3265 /* use BASE() for instruction available
3266 * for CF_ISA_A and M68000.
3268 #define BASE(name, opcode, mask) \
3269 register_opcode(disas_##name, 0x##opcode, 0x##mask)
3270 #define INSN(name, opcode, mask, feature) do { \
3271 if (m68k_feature(env, M68K_FEATURE_##feature)) \
3272 BASE(name, opcode, mask); \
3274 BASE(undef
, 0000, 0000);
3275 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
3276 INSN(arith_im
, 0000, ff00
, M68000
);
3277 INSN(undef
, 00c0
, ffc0
, M68000
);
3278 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
3279 BASE(bitop_reg
, 0100, f1c0
);
3280 BASE(bitop_reg
, 0140, f1c0
);
3281 BASE(bitop_reg
, 0180, f1c0
);
3282 BASE(bitop_reg
, 01c0
, f1c0
);
3283 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
3284 INSN(arith_im
, 0200, ff00
, M68000
);
3285 INSN(undef
, 02c0
, ffc0
, M68000
);
3286 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
3287 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
3288 INSN(arith_im
, 0400, ff00
, M68000
);
3289 INSN(undef
, 04c0
, ffc0
, M68000
);
3290 INSN(arith_im
, 0600, ff00
, M68000
);
3291 INSN(undef
, 06c0
, ffc0
, M68000
);
3292 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
3293 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
3294 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
3295 INSN(arith_im
, 0c00
, ff00
, M68000
);
3296 BASE(bitop_im
, 0800, ffc0
);
3297 BASE(bitop_im
, 0840, ffc0
);
3298 BASE(bitop_im
, 0880, ffc0
);
3299 BASE(bitop_im
, 08c0
, ffc0
);
3300 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
3301 INSN(arith_im
, 0a00
, ff00
, M68000
);
3302 BASE(move
, 1000, f000
);
3303 BASE(move
, 2000, f000
);
3304 BASE(move
, 3000, f000
);
3305 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
3306 INSN(negx
, 4080, fff8
, CF_ISA_A
);
3307 INSN(negx
, 4000, ff00
, M68000
);
3308 INSN(undef
, 40c0
, ffc0
, M68000
);
3309 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
3310 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
3311 BASE(lea
, 41c0
, f1c0
);
3312 BASE(clr
, 4200, ff00
);
3313 BASE(undef
, 42c0
, ffc0
);
3314 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
3315 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
3316 INSN(neg
, 4480, fff8
, CF_ISA_A
);
3317 INSN(neg
, 4400, ff00
, M68000
);
3318 INSN(undef
, 44c0
, ffc0
, M68000
);
3319 BASE(move_to_ccr
, 44c0
, ffc0
);
3320 INSN(not, 4680, fff8
, CF_ISA_A
);
3321 INSN(not, 4600, ff00
, M68000
);
3322 INSN(undef
, 46c0
, ffc0
, M68000
);
3323 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
3324 INSN(linkl
, 4808, fff8
, M68000
);
3325 BASE(pea
, 4840, ffc0
);
3326 BASE(swap
, 4840, fff8
);
3327 INSN(bkpt
, 4848, fff8
, BKPT
);
3328 BASE(movem
, 48c0
, fbc0
);
3329 BASE(ext
, 4880, fff8
);
3330 BASE(ext
, 48c0
, fff8
);
3331 BASE(ext
, 49c0
, fff8
);
3332 BASE(tst
, 4a00
, ff00
);
3333 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
3334 INSN(tas
, 4ac0
, ffc0
, M68000
);
3335 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
3336 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
3337 BASE(illegal
, 4afc
, ffff
);
3338 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
3339 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
3340 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
3341 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
3342 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
3343 BASE(trap
, 4e40
, fff0
);
3344 BASE(link
, 4e50
, fff8
);
3345 BASE(unlk
, 4e58
, fff8
);
3346 INSN(move_to_usp
, 4e60
, fff8
, USP
);
3347 INSN(move_from_usp
, 4e68
, fff8
, USP
);
3348 BASE(nop
, 4e71
, ffff
);
3349 BASE(stop
, 4e72
, ffff
);
3350 BASE(rte
, 4e73
, ffff
);
3351 BASE(rts
, 4e75
, ffff
);
3352 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
3353 BASE(jump
, 4e80
, ffc0
);
3354 BASE(jump
, 4ec0
, ffc0
);
3355 INSN(addsubq
, 5000, f080
, M68000
);
3356 BASE(addsubq
, 5080, f0c0
);
3357 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
3358 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
3359 INSN(dbcc
, 50c8
, f0f8
, M68000
);
3360 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
3362 /* Branch instructions. */
3363 BASE(branch
, 6000, f000
);
3364 /* Disable long branch instructions, then add back the ones we want. */
3365 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
3366 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
3367 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
3368 INSN(branch
, 60ff
, ffff
, BRAL
);
3369 INSN(branch
, 60ff
, f0ff
, BCCL
);
3371 BASE(moveq
, 7000, f100
);
3372 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
3373 BASE(or, 8000, f000
);
3374 BASE(divw
, 80c0
, f0c0
);
3375 BASE(addsub
, 9000, f000
);
3376 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
3377 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
3378 INSN(subx_reg
, 9100, f138
, M68000
);
3379 INSN(subx_mem
, 9108, f138
, M68000
);
3380 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
3381 INSN(suba
, 90c0
, f0c0
, M68000
);
3383 BASE(undef_mac
, a000
, f000
);
3384 INSN(mac
, a000
, f100
, CF_EMAC
);
3385 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
3386 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
3387 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
3388 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
3389 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
3390 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
3391 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
3392 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
3393 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
3394 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
3396 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
3397 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
3398 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
3399 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
3400 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
3401 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
3402 INSN(cmp
, b000
, f100
, M68000
);
3403 INSN(eor
, b100
, f100
, M68000
);
3404 INSN(cmpa
, b0c0
, f0c0
, M68000
);
3405 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
3406 BASE(and, c000
, f000
);
3407 INSN(exg_dd
, c140
, f1f8
, M68000
);
3408 INSN(exg_aa
, c148
, f1f8
, M68000
);
3409 INSN(exg_da
, c188
, f1f8
, M68000
);
3410 BASE(mulw
, c0c0
, f0c0
);
3411 BASE(addsub
, d000
, f000
);
3412 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
3413 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
3414 INSN(addx_reg
, d100
, f138
, M68000
);
3415 INSN(addx_mem
, d108
, f138
, M68000
);
3416 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
3417 INSN(adda
, d0c0
, f0c0
, M68000
);
3418 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
3419 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
3420 INSN(undef_fpu
, f000
, f000
, CF_ISA_A
);
3421 INSN(fpu
, f200
, ffc0
, CF_FPU
);
3422 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
3423 INSN(frestore
, f340
, ffc0
, CF_FPU
);
3424 INSN(fsave
, f340
, ffc0
, CF_FPU
);
3425 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
3426 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
3427 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
3428 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
3432 /* ??? Some of this implementation is not exception safe. We should always
3433 write back the result to memory before setting the condition codes. */
3434 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
3438 insn
= read_im16(env
, s
);
3440 opcode_table
[insn
](env
, s
, insn
);
3443 /* generate intermediate code for basic block 'tb'. */
3444 void gen_intermediate_code(CPUM68KState
*env
, TranslationBlock
*tb
)
3446 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
3447 CPUState
*cs
= CPU(cpu
);
3448 DisasContext dc1
, *dc
= &dc1
;
3449 target_ulong pc_start
;
3454 /* generate intermediate code */
3460 dc
->is_jmp
= DISAS_NEXT
;
3462 dc
->cc_op
= CC_OP_DYNAMIC
;
3463 dc
->cc_op_synced
= 1;
3464 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3465 dc
->fpcr
= env
->fpcr
;
3466 dc
->user
= (env
->sr
& SR_S
) == 0;
3469 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3470 if (max_insns
== 0) {
3471 max_insns
= CF_COUNT_MASK
;
3473 if (max_insns
> TCG_MAX_INSNS
) {
3474 max_insns
= TCG_MAX_INSNS
;
3479 pc_offset
= dc
->pc
- pc_start
;
3480 gen_throws_exception
= NULL
;
3481 tcg_gen_insn_start(dc
->pc
, dc
->cc_op
);
3484 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3485 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
3486 dc
->is_jmp
= DISAS_JUMP
;
3487 /* The address covered by the breakpoint must be included in
3488 [tb->pc, tb->pc + tb->size) in order to for it to be
3489 properly cleared -- thus we increment the PC here so that
3490 the logic setting tb->size below does the right thing. */
3495 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3499 dc
->insn_pc
= dc
->pc
;
3500 disas_m68k_insn(env
, dc
);
3501 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
3502 !cs
->singlestep_enabled
&&
3504 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
3505 num_insns
< max_insns
);
3507 if (tb
->cflags
& CF_LAST_IO
)
3509 if (unlikely(cs
->singlestep_enabled
)) {
3510 /* Make sure the pc is updated, and raise a debug exception. */
3513 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
3515 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
3517 switch(dc
->is_jmp
) {
3520 gen_jmp_tb(dc
, 0, dc
->pc
);
3526 /* indicate that the hash table must be used to find the next TB */
3530 /* nothing more to generate */
3534 gen_tb_end(tb
, num_insns
);
3537 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
3538 && qemu_log_in_addr_range(pc_start
)) {
3539 qemu_log("----------------\n");
3540 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3541 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
3545 tb
->size
= dc
->pc
- pc_start
;
3546 tb
->icount
= num_insns
;
3549 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3552 M68kCPU
*cpu
= M68K_CPU(cs
);
3553 CPUM68KState
*env
= &cpu
->env
;
3557 for (i
= 0; i
< 8; i
++)
3559 u
.d
= env
->fregs
[i
];
3560 cpu_fprintf(f
, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3561 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
3562 i
, u
.l
.upper
, u
.l
.lower
, *(double *)&u
.d
);
3564 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
3565 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
3566 cpu_fprintf(f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& CCF_X
) ? 'X' : '-',
3567 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
3568 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
3569 cpu_fprintf (f
, "FPRESULT = %12g\n", *(double *)&env
->fp_result
);
3572 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
3575 int cc_op
= data
[1];
3577 if (cc_op
!= CC_OP_DYNAMIC
) {