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microblaze: Improve srl
[mirror_qemu.git] / target-microblaze / translate.c
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "helper.h"
25 #include "microblaze-decode.h"
26
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define SIM_COMPAT 0
31 #define DISAS_GNU 1
32 #define DISAS_MB 1
33 #if DISAS_MB && !SIM_COMPAT
34 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
35 #else
36 # define LOG_DIS(...) do { } while (0)
37 #endif
38
39 #define D(x)
40
41 #define EXTRACT_FIELD(src, start, end) \
42 (((src) >> start) & ((1 << (end - start + 1)) - 1))
43
44 static TCGv env_debug;
45 static TCGv_ptr cpu_env;
46 static TCGv cpu_R[32];
47 static TCGv cpu_SR[18];
48 static TCGv env_imm;
49 static TCGv env_btaken;
50 static TCGv env_btarget;
51 static TCGv env_iflags;
52
53 #include "exec/gen-icount.h"
54
55 /* This is the state at translation time. */
56 typedef struct DisasContext {
57 CPUMBState *env;
58 target_ulong pc;
59
60 /* Decoder. */
61 int type_b;
62 uint32_t ir;
63 uint8_t opcode;
64 uint8_t rd, ra, rb;
65 uint16_t imm;
66
67 unsigned int cpustate_changed;
68 unsigned int delayed_branch;
69 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
70 unsigned int clear_imm;
71 int is_jmp;
72
73 #define JMP_NOJMP 0
74 #define JMP_DIRECT 1
75 #define JMP_DIRECT_CC 2
76 #define JMP_INDIRECT 3
77 unsigned int jmp;
78 uint32_t jmp_pc;
79
80 int abort_at_next_insn;
81 int nr_nops;
82 struct TranslationBlock *tb;
83 int singlestep_enabled;
84 } DisasContext;
85
86 static const char *regnames[] =
87 {
88 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
89 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
90 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
91 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
92 };
93
94 static const char *special_regnames[] =
95 {
96 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
97 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
98 "sr16", "sr17", "sr18"
99 };
100
101 /* Sign extend at translation time. */
102 static inline int sign_extend(unsigned int val, unsigned int width)
103 {
104 int sval;
105
106 /* LSL. */
107 val <<= 31 - width;
108 sval = val;
109 /* ASR. */
110 sval >>= 31 - width;
111 return sval;
112 }
113
114 static inline void t_sync_flags(DisasContext *dc)
115 {
116 /* Synch the tb dependent flags between translator and runtime. */
117 if (dc->tb_flags != dc->synced_flags) {
118 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
119 dc->synced_flags = dc->tb_flags;
120 }
121 }
122
123 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
124 {
125 TCGv_i32 tmp = tcg_const_i32(index);
126
127 t_sync_flags(dc);
128 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
129 gen_helper_raise_exception(cpu_env, tmp);
130 tcg_temp_free_i32(tmp);
131 dc->is_jmp = DISAS_UPDATE;
132 }
133
134 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
135 {
136 TranslationBlock *tb;
137 tb = dc->tb;
138 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
139 tcg_gen_goto_tb(n);
140 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
141 tcg_gen_exit_tb((uintptr_t)tb + n);
142 } else {
143 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
144 tcg_gen_exit_tb(0);
145 }
146 }
147
148 static void read_carry(DisasContext *dc, TCGv d)
149 {
150 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
151 }
152
153 /*
154 * write_carry sets the carry bits in MSR based on bit 0 of v.
155 * v[31:1] are ignored.
156 */
157 static void write_carry(DisasContext *dc, TCGv v)
158 {
159 TCGv t0 = tcg_temp_new();
160 tcg_gen_shli_tl(t0, v, 31);
161 tcg_gen_sari_tl(t0, t0, 31);
162 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
163 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
164 ~(MSR_C | MSR_CC));
165 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
166 tcg_temp_free(t0);
167 }
168
169 static void write_carryi(DisasContext *dc, bool carry)
170 {
171 TCGv t0 = tcg_temp_new();
172 tcg_gen_movi_tl(t0, carry);
173 write_carry(dc, t0);
174 tcg_temp_free(t0);
175 }
176
177 /* True if ALU operand b is a small immediate that may deserve
178 faster treatment. */
179 static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
180 {
181 /* Immediate insn without the imm prefix ? */
182 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
183 }
184
185 static inline TCGv *dec_alu_op_b(DisasContext *dc)
186 {
187 if (dc->type_b) {
188 if (dc->tb_flags & IMM_FLAG)
189 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
190 else
191 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
192 return &env_imm;
193 } else
194 return &cpu_R[dc->rb];
195 }
196
197 static void dec_add(DisasContext *dc)
198 {
199 unsigned int k, c;
200 TCGv cf;
201
202 k = dc->opcode & 4;
203 c = dc->opcode & 2;
204
205 LOG_DIS("add%s%s%s r%d r%d r%d\n",
206 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
207 dc->rd, dc->ra, dc->rb);
208
209 /* Take care of the easy cases first. */
210 if (k) {
211 /* k - keep carry, no need to update MSR. */
212 /* If rd == r0, it's a nop. */
213 if (dc->rd) {
214 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
215
216 if (c) {
217 /* c - Add carry into the result. */
218 cf = tcg_temp_new();
219
220 read_carry(dc, cf);
221 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
222 tcg_temp_free(cf);
223 }
224 }
225 return;
226 }
227
228 /* From now on, we can assume k is zero. So we need to update MSR. */
229 /* Extract carry. */
230 cf = tcg_temp_new();
231 if (c) {
232 read_carry(dc, cf);
233 } else {
234 tcg_gen_movi_tl(cf, 0);
235 }
236
237 if (dc->rd) {
238 TCGv ncf = tcg_temp_new();
239 gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
240 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
241 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
242 write_carry(dc, ncf);
243 tcg_temp_free(ncf);
244 } else {
245 gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
246 write_carry(dc, cf);
247 }
248 tcg_temp_free(cf);
249 }
250
251 static void dec_sub(DisasContext *dc)
252 {
253 unsigned int u, cmp, k, c;
254 TCGv cf, na;
255
256 u = dc->imm & 2;
257 k = dc->opcode & 4;
258 c = dc->opcode & 2;
259 cmp = (dc->imm & 1) && (!dc->type_b) && k;
260
261 if (cmp) {
262 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
263 if (dc->rd) {
264 if (u)
265 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
266 else
267 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
268 }
269 return;
270 }
271
272 LOG_DIS("sub%s%s r%d, r%d r%d\n",
273 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
274
275 /* Take care of the easy cases first. */
276 if (k) {
277 /* k - keep carry, no need to update MSR. */
278 /* If rd == r0, it's a nop. */
279 if (dc->rd) {
280 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
281
282 if (c) {
283 /* c - Add carry into the result. */
284 cf = tcg_temp_new();
285
286 read_carry(dc, cf);
287 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
288 tcg_temp_free(cf);
289 }
290 }
291 return;
292 }
293
294 /* From now on, we can assume k is zero. So we need to update MSR. */
295 /* Extract carry. And complement a into na. */
296 cf = tcg_temp_new();
297 na = tcg_temp_new();
298 if (c) {
299 read_carry(dc, cf);
300 } else {
301 tcg_gen_movi_tl(cf, 1);
302 }
303
304 /* d = b + ~a + c. carry defaults to 1. */
305 tcg_gen_not_tl(na, cpu_R[dc->ra]);
306
307 if (dc->rd) {
308 TCGv ncf = tcg_temp_new();
309 gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
310 tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
311 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
312 write_carry(dc, ncf);
313 tcg_temp_free(ncf);
314 } else {
315 gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
316 write_carry(dc, cf);
317 }
318 tcg_temp_free(cf);
319 tcg_temp_free(na);
320 }
321
322 static void dec_pattern(DisasContext *dc)
323 {
324 unsigned int mode;
325 int l1;
326
327 if ((dc->tb_flags & MSR_EE_FLAG)
328 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
329 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
330 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
331 t_gen_raise_exception(dc, EXCP_HW_EXCP);
332 }
333
334 mode = dc->opcode & 3;
335 switch (mode) {
336 case 0:
337 /* pcmpbf. */
338 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
339 if (dc->rd)
340 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
341 break;
342 case 2:
343 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
344 if (dc->rd) {
345 TCGv t0 = tcg_temp_local_new();
346 l1 = gen_new_label();
347 tcg_gen_movi_tl(t0, 1);
348 tcg_gen_brcond_tl(TCG_COND_EQ,
349 cpu_R[dc->ra], cpu_R[dc->rb], l1);
350 tcg_gen_movi_tl(t0, 0);
351 gen_set_label(l1);
352 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
353 tcg_temp_free(t0);
354 }
355 break;
356 case 3:
357 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
358 l1 = gen_new_label();
359 if (dc->rd) {
360 TCGv t0 = tcg_temp_local_new();
361 tcg_gen_movi_tl(t0, 1);
362 tcg_gen_brcond_tl(TCG_COND_NE,
363 cpu_R[dc->ra], cpu_R[dc->rb], l1);
364 tcg_gen_movi_tl(t0, 0);
365 gen_set_label(l1);
366 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
367 tcg_temp_free(t0);
368 }
369 break;
370 default:
371 cpu_abort(dc->env,
372 "unsupported pattern insn opcode=%x\n", dc->opcode);
373 break;
374 }
375 }
376
377 static void dec_and(DisasContext *dc)
378 {
379 unsigned int not;
380
381 if (!dc->type_b && (dc->imm & (1 << 10))) {
382 dec_pattern(dc);
383 return;
384 }
385
386 not = dc->opcode & (1 << 1);
387 LOG_DIS("and%s\n", not ? "n" : "");
388
389 if (!dc->rd)
390 return;
391
392 if (not) {
393 tcg_gen_andc_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
394 } else
395 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
396 }
397
398 static void dec_or(DisasContext *dc)
399 {
400 if (!dc->type_b && (dc->imm & (1 << 10))) {
401 dec_pattern(dc);
402 return;
403 }
404
405 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
406 if (dc->rd)
407 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
408 }
409
410 static void dec_xor(DisasContext *dc)
411 {
412 if (!dc->type_b && (dc->imm & (1 << 10))) {
413 dec_pattern(dc);
414 return;
415 }
416
417 LOG_DIS("xor r%d\n", dc->rd);
418 if (dc->rd)
419 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
420 }
421
422 static inline void msr_read(DisasContext *dc, TCGv d)
423 {
424 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
425 }
426
427 static inline void msr_write(DisasContext *dc, TCGv v)
428 {
429 TCGv t;
430
431 t = tcg_temp_new();
432 dc->cpustate_changed = 1;
433 /* PVR bit is not writable. */
434 tcg_gen_andi_tl(t, v, ~MSR_PVR);
435 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
436 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
437 tcg_temp_free(t);
438 }
439
440 static void dec_msr(DisasContext *dc)
441 {
442 TCGv t0, t1;
443 unsigned int sr, to, rn;
444 int mem_index = cpu_mmu_index(dc->env);
445
446 sr = dc->imm & ((1 << 14) - 1);
447 to = dc->imm & (1 << 14);
448 dc->type_b = 1;
449 if (to)
450 dc->cpustate_changed = 1;
451
452 /* msrclr and msrset. */
453 if (!(dc->imm & (1 << 15))) {
454 unsigned int clr = dc->ir & (1 << 16);
455
456 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
457 dc->rd, dc->imm);
458
459 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
460 /* nop??? */
461 return;
462 }
463
464 if ((dc->tb_flags & MSR_EE_FLAG)
465 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
466 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
467 t_gen_raise_exception(dc, EXCP_HW_EXCP);
468 return;
469 }
470
471 if (dc->rd)
472 msr_read(dc, cpu_R[dc->rd]);
473
474 t0 = tcg_temp_new();
475 t1 = tcg_temp_new();
476 msr_read(dc, t0);
477 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
478
479 if (clr) {
480 tcg_gen_not_tl(t1, t1);
481 tcg_gen_and_tl(t0, t0, t1);
482 } else
483 tcg_gen_or_tl(t0, t0, t1);
484 msr_write(dc, t0);
485 tcg_temp_free(t0);
486 tcg_temp_free(t1);
487 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
488 dc->is_jmp = DISAS_UPDATE;
489 return;
490 }
491
492 if (to) {
493 if ((dc->tb_flags & MSR_EE_FLAG)
494 && mem_index == MMU_USER_IDX) {
495 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
496 t_gen_raise_exception(dc, EXCP_HW_EXCP);
497 return;
498 }
499 }
500
501 #if !defined(CONFIG_USER_ONLY)
502 /* Catch read/writes to the mmu block. */
503 if ((sr & ~0xff) == 0x1000) {
504 sr &= 7;
505 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
506 if (to)
507 gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
508 else
509 gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
510 return;
511 }
512 #endif
513
514 if (to) {
515 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
516 switch (sr) {
517 case 0:
518 break;
519 case 1:
520 msr_write(dc, cpu_R[dc->ra]);
521 break;
522 case 0x3:
523 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
524 break;
525 case 0x5:
526 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
527 break;
528 case 0x7:
529 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
530 break;
531 case 0x800:
532 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr));
533 break;
534 case 0x802:
535 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
536 break;
537 default:
538 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
539 break;
540 }
541 } else {
542 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
543
544 switch (sr) {
545 case 0:
546 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
547 break;
548 case 1:
549 msr_read(dc, cpu_R[dc->rd]);
550 break;
551 case 0x3:
552 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
553 break;
554 case 0x5:
555 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
556 break;
557 case 0x7:
558 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
559 break;
560 case 0xb:
561 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
562 break;
563 case 0x800:
564 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr));
565 break;
566 case 0x802:
567 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr));
568 break;
569 case 0x2000:
570 case 0x2001:
571 case 0x2002:
572 case 0x2003:
573 case 0x2004:
574 case 0x2005:
575 case 0x2006:
576 case 0x2007:
577 case 0x2008:
578 case 0x2009:
579 case 0x200a:
580 case 0x200b:
581 case 0x200c:
582 rn = sr & 0xf;
583 tcg_gen_ld_tl(cpu_R[dc->rd],
584 cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
585 break;
586 default:
587 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
588 break;
589 }
590 }
591
592 if (dc->rd == 0) {
593 tcg_gen_movi_tl(cpu_R[0], 0);
594 }
595 }
596
597 /* 64-bit signed mul, lower result in d and upper in d2. */
598 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
599 {
600 TCGv_i64 t0, t1;
601
602 t0 = tcg_temp_new_i64();
603 t1 = tcg_temp_new_i64();
604
605 tcg_gen_ext_i32_i64(t0, a);
606 tcg_gen_ext_i32_i64(t1, b);
607 tcg_gen_mul_i64(t0, t0, t1);
608
609 tcg_gen_trunc_i64_i32(d, t0);
610 tcg_gen_shri_i64(t0, t0, 32);
611 tcg_gen_trunc_i64_i32(d2, t0);
612
613 tcg_temp_free_i64(t0);
614 tcg_temp_free_i64(t1);
615 }
616
617 /* 64-bit unsigned muls, lower result in d and upper in d2. */
618 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
619 {
620 TCGv_i64 t0, t1;
621
622 t0 = tcg_temp_new_i64();
623 t1 = tcg_temp_new_i64();
624
625 tcg_gen_extu_i32_i64(t0, a);
626 tcg_gen_extu_i32_i64(t1, b);
627 tcg_gen_mul_i64(t0, t0, t1);
628
629 tcg_gen_trunc_i64_i32(d, t0);
630 tcg_gen_shri_i64(t0, t0, 32);
631 tcg_gen_trunc_i64_i32(d2, t0);
632
633 tcg_temp_free_i64(t0);
634 tcg_temp_free_i64(t1);
635 }
636
637 /* Multiplier unit. */
638 static void dec_mul(DisasContext *dc)
639 {
640 TCGv d[2];
641 unsigned int subcode;
642
643 if ((dc->tb_flags & MSR_EE_FLAG)
644 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
645 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
646 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
647 t_gen_raise_exception(dc, EXCP_HW_EXCP);
648 return;
649 }
650
651 subcode = dc->imm & 3;
652 d[0] = tcg_temp_new();
653 d[1] = tcg_temp_new();
654
655 if (dc->type_b) {
656 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
657 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
658 goto done;
659 }
660
661 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
662 if (subcode >= 1 && subcode <= 3
663 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
664 /* nop??? */
665 }
666
667 switch (subcode) {
668 case 0:
669 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
670 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
671 break;
672 case 1:
673 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
674 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
675 break;
676 case 2:
677 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
678 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
679 break;
680 case 3:
681 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
682 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
683 break;
684 default:
685 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
686 break;
687 }
688 done:
689 tcg_temp_free(d[0]);
690 tcg_temp_free(d[1]);
691 }
692
693 /* Div unit. */
694 static void dec_div(DisasContext *dc)
695 {
696 unsigned int u;
697
698 u = dc->imm & 2;
699 LOG_DIS("div\n");
700
701 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
702 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
703 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
704 t_gen_raise_exception(dc, EXCP_HW_EXCP);
705 }
706
707 if (u)
708 gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
709 cpu_R[dc->ra]);
710 else
711 gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
712 cpu_R[dc->ra]);
713 if (!dc->rd)
714 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
715 }
716
717 static void dec_barrel(DisasContext *dc)
718 {
719 TCGv t0;
720 unsigned int s, t;
721
722 if ((dc->tb_flags & MSR_EE_FLAG)
723 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
724 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
725 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
726 t_gen_raise_exception(dc, EXCP_HW_EXCP);
727 return;
728 }
729
730 s = dc->imm & (1 << 10);
731 t = dc->imm & (1 << 9);
732
733 LOG_DIS("bs%s%s r%d r%d r%d\n",
734 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
735
736 t0 = tcg_temp_new();
737
738 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
739 tcg_gen_andi_tl(t0, t0, 31);
740
741 if (s)
742 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
743 else {
744 if (t)
745 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
746 else
747 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
748 }
749 }
750
751 static void dec_bit(DisasContext *dc)
752 {
753 TCGv t0, t1;
754 unsigned int op;
755 int mem_index = cpu_mmu_index(dc->env);
756
757 op = dc->ir & ((1 << 9) - 1);
758 switch (op) {
759 case 0x21:
760 /* src. */
761 t0 = tcg_temp_new();
762
763 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
764 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
765 if (dc->rd) {
766 t1 = tcg_temp_new();
767 read_carry(dc, t1);
768 tcg_gen_shli_tl(t1, t1, 31);
769
770 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
771 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
772 tcg_temp_free(t1);
773 }
774
775 /* Update carry. */
776 write_carry(dc, t0);
777 tcg_temp_free(t0);
778 break;
779
780 case 0x1:
781 case 0x41:
782 /* srl. */
783 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
784
785 /* Update carry. Note that write carry only looks at the LSB. */
786 write_carry(dc, cpu_R[dc->ra]);
787 if (dc->rd) {
788 if (op == 0x41)
789 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
790 else
791 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
792 }
793 break;
794 case 0x60:
795 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
796 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
797 break;
798 case 0x61:
799 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
800 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
801 break;
802 case 0x64:
803 case 0x66:
804 case 0x74:
805 case 0x76:
806 /* wdc. */
807 LOG_DIS("wdc r%d\n", dc->ra);
808 if ((dc->tb_flags & MSR_EE_FLAG)
809 && mem_index == MMU_USER_IDX) {
810 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
811 t_gen_raise_exception(dc, EXCP_HW_EXCP);
812 return;
813 }
814 break;
815 case 0x68:
816 /* wic. */
817 LOG_DIS("wic r%d\n", dc->ra);
818 if ((dc->tb_flags & MSR_EE_FLAG)
819 && mem_index == MMU_USER_IDX) {
820 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
821 t_gen_raise_exception(dc, EXCP_HW_EXCP);
822 return;
823 }
824 break;
825 case 0xe0:
826 if ((dc->tb_flags & MSR_EE_FLAG)
827 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
828 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
829 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
830 t_gen_raise_exception(dc, EXCP_HW_EXCP);
831 }
832 if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
833 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
834 }
835 break;
836 case 0x1e0:
837 /* swapb */
838 LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
839 tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
840 break;
841 case 0x1e2:
842 /*swaph */
843 LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
844 tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
845 break;
846 default:
847 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
848 dc->pc, op, dc->rd, dc->ra, dc->rb);
849 break;
850 }
851 }
852
853 static inline void sync_jmpstate(DisasContext *dc)
854 {
855 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
856 if (dc->jmp == JMP_DIRECT) {
857 tcg_gen_movi_tl(env_btaken, 1);
858 }
859 dc->jmp = JMP_INDIRECT;
860 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
861 }
862 }
863
864 static void dec_imm(DisasContext *dc)
865 {
866 LOG_DIS("imm %x\n", dc->imm << 16);
867 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
868 dc->tb_flags |= IMM_FLAG;
869 dc->clear_imm = 0;
870 }
871
872 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
873 unsigned int size)
874 {
875 int mem_index = cpu_mmu_index(dc->env);
876
877 if (size == 1) {
878 tcg_gen_qemu_ld8u(dst, addr, mem_index);
879 } else if (size == 2) {
880 tcg_gen_qemu_ld16u(dst, addr, mem_index);
881 } else if (size == 4) {
882 tcg_gen_qemu_ld32u(dst, addr, mem_index);
883 } else
884 cpu_abort(dc->env, "Incorrect load size %d\n", size);
885 }
886
887 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
888 {
889 unsigned int extimm = dc->tb_flags & IMM_FLAG;
890 /* Should be set to one if r1 is used by loadstores. */
891 int stackprot = 0;
892
893 /* All load/stores use ra. */
894 if (dc->ra == 1) {
895 stackprot = 1;
896 }
897
898 /* Treat the common cases first. */
899 if (!dc->type_b) {
900 /* If any of the regs is r0, return a ptr to the other. */
901 if (dc->ra == 0) {
902 return &cpu_R[dc->rb];
903 } else if (dc->rb == 0) {
904 return &cpu_R[dc->ra];
905 }
906
907 if (dc->rb == 1) {
908 stackprot = 1;
909 }
910
911 *t = tcg_temp_new();
912 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
913
914 if (stackprot) {
915 gen_helper_stackprot(cpu_env, *t);
916 }
917 return t;
918 }
919 /* Immediate. */
920 if (!extimm) {
921 if (dc->imm == 0) {
922 return &cpu_R[dc->ra];
923 }
924 *t = tcg_temp_new();
925 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
926 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
927 } else {
928 *t = tcg_temp_new();
929 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
930 }
931
932 if (stackprot) {
933 gen_helper_stackprot(cpu_env, *t);
934 }
935 return t;
936 }
937
938 static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
939 {
940 if (size == 4) {
941 tcg_gen_bswap32_tl(dst, src);
942 } else if (size == 2) {
943 TCGv t = tcg_temp_new();
944
945 /* bswap16 assumes the high bits are zero. */
946 tcg_gen_andi_tl(t, src, 0xffff);
947 tcg_gen_bswap16_tl(dst, t);
948 tcg_temp_free(t);
949 } else {
950 /* Ignore.
951 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
952 */
953 }
954 }
955
956 static void dec_load(DisasContext *dc)
957 {
958 TCGv t, *addr;
959 unsigned int size, rev = 0, ex = 0;
960
961 size = 1 << (dc->opcode & 3);
962
963 if (!dc->type_b) {
964 rev = (dc->ir >> 9) & 1;
965 ex = (dc->ir >> 10) & 1;
966 }
967
968 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
969 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
970 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
971 t_gen_raise_exception(dc, EXCP_HW_EXCP);
972 return;
973 }
974
975 LOG_DIS("l%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
976 ex ? "x" : "");
977
978 t_sync_flags(dc);
979 addr = compute_ldst_addr(dc, &t);
980
981 /*
982 * When doing reverse accesses we need to do two things.
983 *
984 * 1. Reverse the address wrt endianness.
985 * 2. Byteswap the data lanes on the way back into the CPU core.
986 */
987 if (rev && size != 4) {
988 /* Endian reverse the address. t is addr. */
989 switch (size) {
990 case 1:
991 {
992 /* 00 -> 11
993 01 -> 10
994 10 -> 10
995 11 -> 00 */
996 TCGv low = tcg_temp_new();
997
998 /* Force addr into the temp. */
999 if (addr != &t) {
1000 t = tcg_temp_new();
1001 tcg_gen_mov_tl(t, *addr);
1002 addr = &t;
1003 }
1004
1005 tcg_gen_andi_tl(low, t, 3);
1006 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1007 tcg_gen_andi_tl(t, t, ~3);
1008 tcg_gen_or_tl(t, t, low);
1009 tcg_gen_mov_tl(env_imm, t);
1010 tcg_temp_free(low);
1011 break;
1012 }
1013
1014 case 2:
1015 /* 00 -> 10
1016 10 -> 00. */
1017 /* Force addr into the temp. */
1018 if (addr != &t) {
1019 t = tcg_temp_new();
1020 tcg_gen_xori_tl(t, *addr, 2);
1021 addr = &t;
1022 } else {
1023 tcg_gen_xori_tl(t, t, 2);
1024 }
1025 break;
1026 default:
1027 cpu_abort(dc->env, "Invalid reverse size\n");
1028 break;
1029 }
1030 }
1031
1032 /* lwx does not throw unaligned access errors, so force alignment */
1033 if (ex) {
1034 /* Force addr into the temp. */
1035 if (addr != &t) {
1036 t = tcg_temp_new();
1037 tcg_gen_mov_tl(t, *addr);
1038 addr = &t;
1039 }
1040 tcg_gen_andi_tl(t, t, ~3);
1041 }
1042
1043 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1044 sync_jmpstate(dc);
1045
1046 /* Verify alignment if needed. */
1047 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1048 TCGv v = tcg_temp_new();
1049
1050 /*
1051 * Microblaze gives MMU faults priority over faults due to
1052 * unaligned addresses. That's why we speculatively do the load
1053 * into v. If the load succeeds, we verify alignment of the
1054 * address and if that succeeds we write into the destination reg.
1055 */
1056 gen_load(dc, v, *addr, size);
1057
1058 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1059 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
1060 tcg_const_tl(0), tcg_const_tl(size - 1));
1061 if (dc->rd) {
1062 if (rev) {
1063 dec_byteswap(dc, cpu_R[dc->rd], v, size);
1064 } else {
1065 tcg_gen_mov_tl(cpu_R[dc->rd], v);
1066 }
1067 }
1068 tcg_temp_free(v);
1069 } else {
1070 if (dc->rd) {
1071 gen_load(dc, cpu_R[dc->rd], *addr, size);
1072 if (rev) {
1073 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1074 }
1075 } else {
1076 /* We are loading into r0, no need to reverse. */
1077 gen_load(dc, env_imm, *addr, size);
1078 }
1079 }
1080
1081 if (ex) { /* lwx */
1082 /* no support for for AXI exclusive so always clear C */
1083 write_carryi(dc, 0);
1084 tcg_gen_st_tl(*addr, cpu_env, offsetof(CPUMBState, res_addr));
1085 }
1086
1087 if (addr == &t)
1088 tcg_temp_free(t);
1089 }
1090
1091 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1092 unsigned int size)
1093 {
1094 int mem_index = cpu_mmu_index(dc->env);
1095
1096 if (size == 1)
1097 tcg_gen_qemu_st8(val, addr, mem_index);
1098 else if (size == 2) {
1099 tcg_gen_qemu_st16(val, addr, mem_index);
1100 } else if (size == 4) {
1101 tcg_gen_qemu_st32(val, addr, mem_index);
1102 } else
1103 cpu_abort(dc->env, "Incorrect store size %d\n", size);
1104 }
1105
1106 static void dec_store(DisasContext *dc)
1107 {
1108 TCGv t, *addr, swx_addr, r_check;
1109 int swx_skip = 0;
1110 unsigned int size, rev = 0, ex = 0;
1111
1112 size = 1 << (dc->opcode & 3);
1113 if (!dc->type_b) {
1114 rev = (dc->ir >> 9) & 1;
1115 ex = (dc->ir >> 10) & 1;
1116 }
1117
1118 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
1119 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1120 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1121 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1122 return;
1123 }
1124
1125 LOG_DIS("s%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
1126 ex ? "x" : "");
1127 t_sync_flags(dc);
1128 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1129 sync_jmpstate(dc);
1130 addr = compute_ldst_addr(dc, &t);
1131
1132 r_check = tcg_temp_new();
1133 swx_addr = tcg_temp_local_new();
1134 if (ex) { /* swx */
1135
1136 /* Force addr into the swx_addr. */
1137 tcg_gen_mov_tl(swx_addr, *addr);
1138 addr = &swx_addr;
1139 /* swx does not throw unaligned access errors, so force alignment */
1140 tcg_gen_andi_tl(swx_addr, swx_addr, ~3);
1141
1142 tcg_gen_ld_tl(r_check, cpu_env, offsetof(CPUMBState, res_addr));
1143 write_carryi(dc, 1);
1144 swx_skip = gen_new_label();
1145 tcg_gen_brcond_tl(TCG_COND_NE, r_check, swx_addr, swx_skip);
1146 write_carryi(dc, 0);
1147 }
1148
1149 if (rev && size != 4) {
1150 /* Endian reverse the address. t is addr. */
1151 switch (size) {
1152 case 1:
1153 {
1154 /* 00 -> 11
1155 01 -> 10
1156 10 -> 10
1157 11 -> 00 */
1158 TCGv low = tcg_temp_new();
1159
1160 /* Force addr into the temp. */
1161 if (addr != &t) {
1162 t = tcg_temp_new();
1163 tcg_gen_mov_tl(t, *addr);
1164 addr = &t;
1165 }
1166
1167 tcg_gen_andi_tl(low, t, 3);
1168 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1169 tcg_gen_andi_tl(t, t, ~3);
1170 tcg_gen_or_tl(t, t, low);
1171 tcg_gen_mov_tl(env_imm, t);
1172 tcg_temp_free(low);
1173 break;
1174 }
1175
1176 case 2:
1177 /* 00 -> 10
1178 10 -> 00. */
1179 /* Force addr into the temp. */
1180 if (addr != &t) {
1181 t = tcg_temp_new();
1182 tcg_gen_xori_tl(t, *addr, 2);
1183 addr = &t;
1184 } else {
1185 tcg_gen_xori_tl(t, t, 2);
1186 }
1187 break;
1188 default:
1189 cpu_abort(dc->env, "Invalid reverse size\n");
1190 break;
1191 }
1192
1193 if (size != 1) {
1194 TCGv bs_data = tcg_temp_new();
1195 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1196 gen_store(dc, *addr, bs_data, size);
1197 tcg_temp_free(bs_data);
1198 } else {
1199 gen_store(dc, *addr, cpu_R[dc->rd], size);
1200 }
1201 } else {
1202 if (rev) {
1203 TCGv bs_data = tcg_temp_new();
1204 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1205 gen_store(dc, *addr, bs_data, size);
1206 tcg_temp_free(bs_data);
1207 } else {
1208 gen_store(dc, *addr, cpu_R[dc->rd], size);
1209 }
1210 }
1211
1212 /* Verify alignment if needed. */
1213 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1214 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1215 /* FIXME: if the alignment is wrong, we should restore the value
1216 * in memory. One possible way to achieve this is to probe
1217 * the MMU prior to the memaccess, thay way we could put
1218 * the alignment checks in between the probe and the mem
1219 * access.
1220 */
1221 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
1222 tcg_const_tl(1), tcg_const_tl(size - 1));
1223 }
1224
1225 if (ex) {
1226 gen_set_label(swx_skip);
1227 }
1228 tcg_temp_free(r_check);
1229 tcg_temp_free(swx_addr);
1230
1231 if (addr == &t)
1232 tcg_temp_free(t);
1233 }
1234
1235 static inline void eval_cc(DisasContext *dc, unsigned int cc,
1236 TCGv d, TCGv a, TCGv b)
1237 {
1238 switch (cc) {
1239 case CC_EQ:
1240 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
1241 break;
1242 case CC_NE:
1243 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
1244 break;
1245 case CC_LT:
1246 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
1247 break;
1248 case CC_LE:
1249 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
1250 break;
1251 case CC_GE:
1252 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
1253 break;
1254 case CC_GT:
1255 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
1256 break;
1257 default:
1258 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1259 break;
1260 }
1261 }
1262
1263 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1264 {
1265 int l1;
1266
1267 l1 = gen_new_label();
1268 /* Conditional jmp. */
1269 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1270 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1271 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1272 gen_set_label(l1);
1273 }
1274
1275 static void dec_bcc(DisasContext *dc)
1276 {
1277 unsigned int cc;
1278 unsigned int dslot;
1279
1280 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1281 dslot = dc->ir & (1 << 25);
1282 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1283
1284 dc->delayed_branch = 1;
1285 if (dslot) {
1286 dc->delayed_branch = 2;
1287 dc->tb_flags |= D_FLAG;
1288 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1289 cpu_env, offsetof(CPUMBState, bimm));
1290 }
1291
1292 if (dec_alu_op_b_is_small_imm(dc)) {
1293 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1294
1295 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
1296 dc->jmp = JMP_DIRECT_CC;
1297 dc->jmp_pc = dc->pc + offset;
1298 } else {
1299 dc->jmp = JMP_INDIRECT;
1300 tcg_gen_movi_tl(env_btarget, dc->pc);
1301 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1302 }
1303 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
1304 }
1305
1306 static void dec_br(DisasContext *dc)
1307 {
1308 unsigned int dslot, link, abs, mbar;
1309 int mem_index = cpu_mmu_index(dc->env);
1310
1311 dslot = dc->ir & (1 << 20);
1312 abs = dc->ir & (1 << 19);
1313 link = dc->ir & (1 << 18);
1314
1315 /* Memory barrier. */
1316 mbar = (dc->ir >> 16) & 31;
1317 if (mbar == 2 && dc->imm == 4) {
1318 /* mbar IMM & 16 decodes to sleep. */
1319 if (dc->rd & 16) {
1320 TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
1321 TCGv_i32 tmp_1 = tcg_const_i32(1);
1322
1323 LOG_DIS("sleep\n");
1324
1325 t_sync_flags(dc);
1326 tcg_gen_st_i32(tmp_1, cpu_env,
1327 -offsetof(MicroBlazeCPU, env)
1328 +offsetof(CPUState, halted));
1329 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
1330 gen_helper_raise_exception(cpu_env, tmp_hlt);
1331 tcg_temp_free_i32(tmp_hlt);
1332 tcg_temp_free_i32(tmp_1);
1333 return;
1334 }
1335 LOG_DIS("mbar %d\n", dc->rd);
1336 /* Break the TB. */
1337 dc->cpustate_changed = 1;
1338 return;
1339 }
1340
1341 LOG_DIS("br%s%s%s%s imm=%x\n",
1342 abs ? "a" : "", link ? "l" : "",
1343 dc->type_b ? "i" : "", dslot ? "d" : "",
1344 dc->imm);
1345
1346 dc->delayed_branch = 1;
1347 if (dslot) {
1348 dc->delayed_branch = 2;
1349 dc->tb_flags |= D_FLAG;
1350 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1351 cpu_env, offsetof(CPUMBState, bimm));
1352 }
1353 if (link && dc->rd)
1354 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1355
1356 dc->jmp = JMP_INDIRECT;
1357 if (abs) {
1358 tcg_gen_movi_tl(env_btaken, 1);
1359 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1360 if (link && !dslot) {
1361 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1362 t_gen_raise_exception(dc, EXCP_BREAK);
1363 if (dc->imm == 0) {
1364 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1365 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1366 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1367 return;
1368 }
1369
1370 t_gen_raise_exception(dc, EXCP_DEBUG);
1371 }
1372 }
1373 } else {
1374 if (dec_alu_op_b_is_small_imm(dc)) {
1375 dc->jmp = JMP_DIRECT;
1376 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1377 } else {
1378 tcg_gen_movi_tl(env_btaken, 1);
1379 tcg_gen_movi_tl(env_btarget, dc->pc);
1380 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1381 }
1382 }
1383 }
1384
1385 static inline void do_rti(DisasContext *dc)
1386 {
1387 TCGv t0, t1;
1388 t0 = tcg_temp_new();
1389 t1 = tcg_temp_new();
1390 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1391 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1392 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1393
1394 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1395 tcg_gen_or_tl(t1, t1, t0);
1396 msr_write(dc, t1);
1397 tcg_temp_free(t1);
1398 tcg_temp_free(t0);
1399 dc->tb_flags &= ~DRTI_FLAG;
1400 }
1401
1402 static inline void do_rtb(DisasContext *dc)
1403 {
1404 TCGv t0, t1;
1405 t0 = tcg_temp_new();
1406 t1 = tcg_temp_new();
1407 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1408 tcg_gen_shri_tl(t0, t1, 1);
1409 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1410
1411 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1412 tcg_gen_or_tl(t1, t1, t0);
1413 msr_write(dc, t1);
1414 tcg_temp_free(t1);
1415 tcg_temp_free(t0);
1416 dc->tb_flags &= ~DRTB_FLAG;
1417 }
1418
1419 static inline void do_rte(DisasContext *dc)
1420 {
1421 TCGv t0, t1;
1422 t0 = tcg_temp_new();
1423 t1 = tcg_temp_new();
1424
1425 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1426 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1427 tcg_gen_shri_tl(t0, t1, 1);
1428 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1429
1430 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1431 tcg_gen_or_tl(t1, t1, t0);
1432 msr_write(dc, t1);
1433 tcg_temp_free(t1);
1434 tcg_temp_free(t0);
1435 dc->tb_flags &= ~DRTE_FLAG;
1436 }
1437
1438 static void dec_rts(DisasContext *dc)
1439 {
1440 unsigned int b_bit, i_bit, e_bit;
1441 int mem_index = cpu_mmu_index(dc->env);
1442
1443 i_bit = dc->ir & (1 << 21);
1444 b_bit = dc->ir & (1 << 22);
1445 e_bit = dc->ir & (1 << 23);
1446
1447 dc->delayed_branch = 2;
1448 dc->tb_flags |= D_FLAG;
1449 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1450 cpu_env, offsetof(CPUMBState, bimm));
1451
1452 if (i_bit) {
1453 LOG_DIS("rtid ir=%x\n", dc->ir);
1454 if ((dc->tb_flags & MSR_EE_FLAG)
1455 && mem_index == MMU_USER_IDX) {
1456 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1457 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1458 }
1459 dc->tb_flags |= DRTI_FLAG;
1460 } else if (b_bit) {
1461 LOG_DIS("rtbd ir=%x\n", dc->ir);
1462 if ((dc->tb_flags & MSR_EE_FLAG)
1463 && mem_index == MMU_USER_IDX) {
1464 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1465 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1466 }
1467 dc->tb_flags |= DRTB_FLAG;
1468 } else if (e_bit) {
1469 LOG_DIS("rted ir=%x\n", dc->ir);
1470 if ((dc->tb_flags & MSR_EE_FLAG)
1471 && mem_index == MMU_USER_IDX) {
1472 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1473 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1474 }
1475 dc->tb_flags |= DRTE_FLAG;
1476 } else
1477 LOG_DIS("rts ir=%x\n", dc->ir);
1478
1479 dc->jmp = JMP_INDIRECT;
1480 tcg_gen_movi_tl(env_btaken, 1);
1481 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1482 }
1483
1484 static int dec_check_fpuv2(DisasContext *dc)
1485 {
1486 int r;
1487
1488 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1489
1490 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1491 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1492 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1493 }
1494 return r;
1495 }
1496
1497 static void dec_fpu(DisasContext *dc)
1498 {
1499 unsigned int fpu_insn;
1500
1501 if ((dc->tb_flags & MSR_EE_FLAG)
1502 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1503 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1504 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1505 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1506 return;
1507 }
1508
1509 fpu_insn = (dc->ir >> 7) & 7;
1510
1511 switch (fpu_insn) {
1512 case 0:
1513 gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1514 cpu_R[dc->rb]);
1515 break;
1516
1517 case 1:
1518 gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1519 cpu_R[dc->rb]);
1520 break;
1521
1522 case 2:
1523 gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1524 cpu_R[dc->rb]);
1525 break;
1526
1527 case 3:
1528 gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1529 cpu_R[dc->rb]);
1530 break;
1531
1532 case 4:
1533 switch ((dc->ir >> 4) & 7) {
1534 case 0:
1535 gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
1536 cpu_R[dc->ra], cpu_R[dc->rb]);
1537 break;
1538 case 1:
1539 gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
1540 cpu_R[dc->ra], cpu_R[dc->rb]);
1541 break;
1542 case 2:
1543 gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
1544 cpu_R[dc->ra], cpu_R[dc->rb]);
1545 break;
1546 case 3:
1547 gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
1548 cpu_R[dc->ra], cpu_R[dc->rb]);
1549 break;
1550 case 4:
1551 gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
1552 cpu_R[dc->ra], cpu_R[dc->rb]);
1553 break;
1554 case 5:
1555 gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
1556 cpu_R[dc->ra], cpu_R[dc->rb]);
1557 break;
1558 case 6:
1559 gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
1560 cpu_R[dc->ra], cpu_R[dc->rb]);
1561 break;
1562 default:
1563 qemu_log_mask(LOG_UNIMP,
1564 "unimplemented fcmp fpu_insn=%x pc=%x"
1565 " opc=%x\n",
1566 fpu_insn, dc->pc, dc->opcode);
1567 dc->abort_at_next_insn = 1;
1568 break;
1569 }
1570 break;
1571
1572 case 5:
1573 if (!dec_check_fpuv2(dc)) {
1574 return;
1575 }
1576 gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1577 break;
1578
1579 case 6:
1580 if (!dec_check_fpuv2(dc)) {
1581 return;
1582 }
1583 gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1584 break;
1585
1586 case 7:
1587 if (!dec_check_fpuv2(dc)) {
1588 return;
1589 }
1590 gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1591 break;
1592
1593 default:
1594 qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
1595 " opc=%x\n",
1596 fpu_insn, dc->pc, dc->opcode);
1597 dc->abort_at_next_insn = 1;
1598 break;
1599 }
1600 }
1601
1602 static void dec_null(DisasContext *dc)
1603 {
1604 if ((dc->tb_flags & MSR_EE_FLAG)
1605 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1606 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1607 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1608 return;
1609 }
1610 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1611 dc->abort_at_next_insn = 1;
1612 }
1613
1614 /* Insns connected to FSL or AXI stream attached devices. */
1615 static void dec_stream(DisasContext *dc)
1616 {
1617 int mem_index = cpu_mmu_index(dc->env);
1618 TCGv_i32 t_id, t_ctrl;
1619 int ctrl;
1620
1621 LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1622 dc->type_b ? "" : "d", dc->imm);
1623
1624 if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1625 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1626 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1627 return;
1628 }
1629
1630 t_id = tcg_temp_new();
1631 if (dc->type_b) {
1632 tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1633 ctrl = dc->imm >> 10;
1634 } else {
1635 tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1636 ctrl = dc->imm >> 5;
1637 }
1638
1639 t_ctrl = tcg_const_tl(ctrl);
1640
1641 if (dc->rd == 0) {
1642 gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1643 } else {
1644 gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1645 }
1646 tcg_temp_free(t_id);
1647 tcg_temp_free(t_ctrl);
1648 }
1649
1650 static struct decoder_info {
1651 struct {
1652 uint32_t bits;
1653 uint32_t mask;
1654 };
1655 void (*dec)(DisasContext *dc);
1656 } decinfo[] = {
1657 {DEC_ADD, dec_add},
1658 {DEC_SUB, dec_sub},
1659 {DEC_AND, dec_and},
1660 {DEC_XOR, dec_xor},
1661 {DEC_OR, dec_or},
1662 {DEC_BIT, dec_bit},
1663 {DEC_BARREL, dec_barrel},
1664 {DEC_LD, dec_load},
1665 {DEC_ST, dec_store},
1666 {DEC_IMM, dec_imm},
1667 {DEC_BR, dec_br},
1668 {DEC_BCC, dec_bcc},
1669 {DEC_RTS, dec_rts},
1670 {DEC_FPU, dec_fpu},
1671 {DEC_MUL, dec_mul},
1672 {DEC_DIV, dec_div},
1673 {DEC_MSR, dec_msr},
1674 {DEC_STREAM, dec_stream},
1675 {{0, 0}, dec_null}
1676 };
1677
1678 static inline void decode(DisasContext *dc, uint32_t ir)
1679 {
1680 int i;
1681
1682 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1683 tcg_gen_debug_insn_start(dc->pc);
1684 }
1685
1686 dc->ir = ir;
1687 LOG_DIS("%8.8x\t", dc->ir);
1688
1689 if (dc->ir)
1690 dc->nr_nops = 0;
1691 else {
1692 if ((dc->tb_flags & MSR_EE_FLAG)
1693 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1694 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1695 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1696 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1697 return;
1698 }
1699
1700 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1701 dc->nr_nops++;
1702 if (dc->nr_nops > 4)
1703 cpu_abort(dc->env, "fetching nop sequence\n");
1704 }
1705 /* bit 2 seems to indicate insn type. */
1706 dc->type_b = ir & (1 << 29);
1707
1708 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1709 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1710 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1711 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1712 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1713
1714 /* Large switch for all insns. */
1715 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1716 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1717 decinfo[i].dec(dc);
1718 break;
1719 }
1720 }
1721 }
1722
1723 static void check_breakpoint(CPUMBState *env, DisasContext *dc)
1724 {
1725 CPUBreakpoint *bp;
1726
1727 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1728 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1729 if (bp->pc == dc->pc) {
1730 t_gen_raise_exception(dc, EXCP_DEBUG);
1731 dc->is_jmp = DISAS_UPDATE;
1732 }
1733 }
1734 }
1735 }
1736
1737 /* generate intermediate code for basic block 'tb'. */
1738 static inline void
1739 gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
1740 bool search_pc)
1741 {
1742 CPUState *cs = CPU(cpu);
1743 CPUMBState *env = &cpu->env;
1744 uint16_t *gen_opc_end;
1745 uint32_t pc_start;
1746 int j, lj;
1747 struct DisasContext ctx;
1748 struct DisasContext *dc = &ctx;
1749 uint32_t next_page_start, org_flags;
1750 target_ulong npc;
1751 int num_insns;
1752 int max_insns;
1753
1754 pc_start = tb->pc;
1755 dc->env = env;
1756 dc->tb = tb;
1757 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1758
1759 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1760
1761 dc->is_jmp = DISAS_NEXT;
1762 dc->jmp = 0;
1763 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1764 if (dc->delayed_branch) {
1765 dc->jmp = JMP_INDIRECT;
1766 }
1767 dc->pc = pc_start;
1768 dc->singlestep_enabled = cs->singlestep_enabled;
1769 dc->cpustate_changed = 0;
1770 dc->abort_at_next_insn = 0;
1771 dc->nr_nops = 0;
1772
1773 if (pc_start & 3)
1774 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1775
1776 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1777 #if !SIM_COMPAT
1778 qemu_log("--------------\n");
1779 log_cpu_state(CPU(cpu), 0);
1780 #endif
1781 }
1782
1783 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1784 lj = -1;
1785 num_insns = 0;
1786 max_insns = tb->cflags & CF_COUNT_MASK;
1787 if (max_insns == 0)
1788 max_insns = CF_COUNT_MASK;
1789
1790 gen_tb_start();
1791 do
1792 {
1793 #if SIM_COMPAT
1794 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1795 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1796 gen_helper_debug();
1797 }
1798 #endif
1799 check_breakpoint(env, dc);
1800
1801 if (search_pc) {
1802 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1803 if (lj < j) {
1804 lj++;
1805 while (lj < j)
1806 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1807 }
1808 tcg_ctx.gen_opc_pc[lj] = dc->pc;
1809 tcg_ctx.gen_opc_instr_start[lj] = 1;
1810 tcg_ctx.gen_opc_icount[lj] = num_insns;
1811 }
1812
1813 /* Pretty disas. */
1814 LOG_DIS("%8.8x:\t", dc->pc);
1815
1816 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1817 gen_io_start();
1818
1819 dc->clear_imm = 1;
1820 decode(dc, cpu_ldl_code(env, dc->pc));
1821 if (dc->clear_imm)
1822 dc->tb_flags &= ~IMM_FLAG;
1823 dc->pc += 4;
1824 num_insns++;
1825
1826 if (dc->delayed_branch) {
1827 dc->delayed_branch--;
1828 if (!dc->delayed_branch) {
1829 if (dc->tb_flags & DRTI_FLAG)
1830 do_rti(dc);
1831 if (dc->tb_flags & DRTB_FLAG)
1832 do_rtb(dc);
1833 if (dc->tb_flags & DRTE_FLAG)
1834 do_rte(dc);
1835 /* Clear the delay slot flag. */
1836 dc->tb_flags &= ~D_FLAG;
1837 /* If it is a direct jump, try direct chaining. */
1838 if (dc->jmp == JMP_INDIRECT) {
1839 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1840 dc->is_jmp = DISAS_JUMP;
1841 } else if (dc->jmp == JMP_DIRECT) {
1842 t_sync_flags(dc);
1843 gen_goto_tb(dc, 0, dc->jmp_pc);
1844 dc->is_jmp = DISAS_TB_JUMP;
1845 } else if (dc->jmp == JMP_DIRECT_CC) {
1846 int l1;
1847
1848 t_sync_flags(dc);
1849 l1 = gen_new_label();
1850 /* Conditional jmp. */
1851 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1852 gen_goto_tb(dc, 1, dc->pc);
1853 gen_set_label(l1);
1854 gen_goto_tb(dc, 0, dc->jmp_pc);
1855
1856 dc->is_jmp = DISAS_TB_JUMP;
1857 }
1858 break;
1859 }
1860 }
1861 if (cs->singlestep_enabled) {
1862 break;
1863 }
1864 } while (!dc->is_jmp && !dc->cpustate_changed
1865 && tcg_ctx.gen_opc_ptr < gen_opc_end
1866 && !singlestep
1867 && (dc->pc < next_page_start)
1868 && num_insns < max_insns);
1869
1870 npc = dc->pc;
1871 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1872 if (dc->tb_flags & D_FLAG) {
1873 dc->is_jmp = DISAS_UPDATE;
1874 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1875 sync_jmpstate(dc);
1876 } else
1877 npc = dc->jmp_pc;
1878 }
1879
1880 if (tb->cflags & CF_LAST_IO)
1881 gen_io_end();
1882 /* Force an update if the per-tb cpu state has changed. */
1883 if (dc->is_jmp == DISAS_NEXT
1884 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1885 dc->is_jmp = DISAS_UPDATE;
1886 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1887 }
1888 t_sync_flags(dc);
1889
1890 if (unlikely(cs->singlestep_enabled)) {
1891 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1892
1893 if (dc->is_jmp != DISAS_JUMP) {
1894 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1895 }
1896 gen_helper_raise_exception(cpu_env, tmp);
1897 tcg_temp_free_i32(tmp);
1898 } else {
1899 switch(dc->is_jmp) {
1900 case DISAS_NEXT:
1901 gen_goto_tb(dc, 1, npc);
1902 break;
1903 default:
1904 case DISAS_JUMP:
1905 case DISAS_UPDATE:
1906 /* indicate that the hash table must be used
1907 to find the next TB */
1908 tcg_gen_exit_tb(0);
1909 break;
1910 case DISAS_TB_JUMP:
1911 /* nothing more to generate */
1912 break;
1913 }
1914 }
1915 gen_tb_end(tb, num_insns);
1916 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1917 if (search_pc) {
1918 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1919 lj++;
1920 while (lj <= j)
1921 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1922 } else {
1923 tb->size = dc->pc - pc_start;
1924 tb->icount = num_insns;
1925 }
1926
1927 #ifdef DEBUG_DISAS
1928 #if !SIM_COMPAT
1929 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1930 qemu_log("\n");
1931 #if DISAS_GNU
1932 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
1933 #endif
1934 qemu_log("\nisize=%d osize=%td\n",
1935 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1936 tcg_ctx.gen_opc_buf);
1937 }
1938 #endif
1939 #endif
1940 assert(!dc->abort_at_next_insn);
1941 }
1942
1943 void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
1944 {
1945 gen_intermediate_code_internal(mb_env_get_cpu(env), tb, false);
1946 }
1947
1948 void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
1949 {
1950 gen_intermediate_code_internal(mb_env_get_cpu(env), tb, true);
1951 }
1952
1953 void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1954 int flags)
1955 {
1956 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
1957 CPUMBState *env = &cpu->env;
1958 int i;
1959
1960 if (!env || !f)
1961 return;
1962
1963 cpu_fprintf(f, "IN: PC=%x %s\n",
1964 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1965 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1966 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1967 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
1968 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1969 env->btaken, env->btarget,
1970 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1971 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1972 (env->sregs[SR_MSR] & MSR_EIP),
1973 (env->sregs[SR_MSR] & MSR_IE));
1974
1975 for (i = 0; i < 32; i++) {
1976 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1977 if ((i + 1) % 4 == 0)
1978 cpu_fprintf(f, "\n");
1979 }
1980 cpu_fprintf(f, "\n\n");
1981 }
1982
1983 MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
1984 {
1985 MicroBlazeCPU *cpu;
1986
1987 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
1988
1989 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1990
1991 return cpu;
1992 }
1993
1994 void mb_tcg_init(void)
1995 {
1996 int i;
1997
1998 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1999
2000 env_debug = tcg_global_mem_new(TCG_AREG0,
2001 offsetof(CPUMBState, debug),
2002 "debug0");
2003 env_iflags = tcg_global_mem_new(TCG_AREG0,
2004 offsetof(CPUMBState, iflags),
2005 "iflags");
2006 env_imm = tcg_global_mem_new(TCG_AREG0,
2007 offsetof(CPUMBState, imm),
2008 "imm");
2009 env_btarget = tcg_global_mem_new(TCG_AREG0,
2010 offsetof(CPUMBState, btarget),
2011 "btarget");
2012 env_btaken = tcg_global_mem_new(TCG_AREG0,
2013 offsetof(CPUMBState, btaken),
2014 "btaken");
2015 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
2016 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
2017 offsetof(CPUMBState, regs[i]),
2018 regnames[i]);
2019 }
2020 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
2021 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
2022 offsetof(CPUMBState, sregs[i]),
2023 special_regnames[i]);
2024 }
2025 }
2026
2027 void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
2028 {
2029 env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos];
2030 }
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