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[qemu.git] / target-microblaze / translate.c
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <assert.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "helper.h"
32 #include "microblaze-decode.h"
33 #include "qemu-common.h"
34
35 #define GEN_HELPER 1
36 #include "helper.h"
37
38 #define SIM_COMPAT 0
39 #define DISAS_GNU 1
40 #define DISAS_MB 1
41 #if DISAS_MB && !SIM_COMPAT
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DIS(...) do { } while (0)
45 #endif
46
47 #define D(x)
48
49 #define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52 static TCGv env_debug;
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_R[32];
55 static TCGv cpu_SR[18];
56 static TCGv env_imm;
57 static TCGv env_btaken;
58 static TCGv env_btarget;
59 static TCGv env_iflags;
60
61 #include "gen-icount.h"
62
63 /* This is the state at translation time. */
64 typedef struct DisasContext {
65 CPUState *env;
66 target_ulong pc;
67
68 /* Decoder. */
69 int type_b;
70 uint32_t ir;
71 uint8_t opcode;
72 uint8_t rd, ra, rb;
73 uint16_t imm;
74
75 unsigned int cpustate_changed;
76 unsigned int delayed_branch;
77 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
78 unsigned int clear_imm;
79 int is_jmp;
80
81 #define JMP_NOJMP 0
82 #define JMP_DIRECT 1
83 #define JMP_DIRECT_CC 2
84 #define JMP_INDIRECT 3
85 unsigned int jmp;
86 uint32_t jmp_pc;
87
88 int abort_at_next_insn;
89 int nr_nops;
90 struct TranslationBlock *tb;
91 int singlestep_enabled;
92 } DisasContext;
93
94 static const char *regnames[] =
95 {
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
100 };
101
102 static const char *special_regnames[] =
103 {
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
107 };
108
109 /* Sign extend at translation time. */
110 static inline int sign_extend(unsigned int val, unsigned int width)
111 {
112 int sval;
113
114 /* LSL. */
115 val <<= 31 - width;
116 sval = val;
117 /* ASR. */
118 sval >>= 31 - width;
119 return sval;
120 }
121
122 static inline void t_sync_flags(DisasContext *dc)
123 {
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc->tb_flags != dc->synced_flags) {
126 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
127 dc->synced_flags = dc->tb_flags;
128 }
129 }
130
131 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132 {
133 TCGv_i32 tmp = tcg_const_i32(index);
134
135 t_sync_flags(dc);
136 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
137 gen_helper_raise_exception(tmp);
138 tcg_temp_free_i32(tmp);
139 dc->is_jmp = DISAS_UPDATE;
140 }
141
142 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143 {
144 TranslationBlock *tb;
145 tb = dc->tb;
146 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147 tcg_gen_goto_tb(n);
148 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
149 tcg_gen_exit_tb((long)tb + n);
150 } else {
151 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
152 tcg_gen_exit_tb(0);
153 }
154 }
155
156 static void read_carry(DisasContext *dc, TCGv d)
157 {
158 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
159 }
160
161 static void write_carry(DisasContext *dc, TCGv v)
162 {
163 TCGv t0 = tcg_temp_new();
164 tcg_gen_shli_tl(t0, v, 31);
165 tcg_gen_sari_tl(t0, t0, 31);
166 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
167 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
168 ~(MSR_C | MSR_CC));
169 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
170 tcg_temp_free(t0);
171 }
172
173 /* True if ALU operand b is a small immediate that may deserve
174 faster treatment. */
175 static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
176 {
177 /* Immediate insn without the imm prefix ? */
178 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
179 }
180
181 static inline TCGv *dec_alu_op_b(DisasContext *dc)
182 {
183 if (dc->type_b) {
184 if (dc->tb_flags & IMM_FLAG)
185 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
186 else
187 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
188 return &env_imm;
189 } else
190 return &cpu_R[dc->rb];
191 }
192
193 static void dec_add(DisasContext *dc)
194 {
195 unsigned int k, c;
196
197 k = dc->opcode & 4;
198 c = dc->opcode & 2;
199
200 LOG_DIS("add%s%s%s r%d r%d r%d\n",
201 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
202 dc->rd, dc->ra, dc->rb);
203
204 if (k && !c && dc->rd)
205 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
206 else if (dc->rd)
207 gen_helper_addkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
208 tcg_const_tl(k), tcg_const_tl(c));
209 else {
210 TCGv d = tcg_temp_new();
211 gen_helper_addkc(d, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
212 tcg_const_tl(k), tcg_const_tl(c));
213 tcg_temp_free(d);
214 }
215 }
216
217 static void dec_sub(DisasContext *dc)
218 {
219 unsigned int u, cmp, k, c;
220
221 u = dc->imm & 2;
222 k = dc->opcode & 4;
223 c = dc->opcode & 2;
224 cmp = (dc->imm & 1) && (!dc->type_b) && k;
225
226 if (cmp) {
227 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
228 if (dc->rd) {
229 if (u)
230 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
231 else
232 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
233 }
234 } else {
235 LOG_DIS("sub%s%s r%d, r%d r%d\n",
236 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
237
238 if (!k || c) {
239 TCGv t;
240 t = tcg_temp_new();
241 if (dc->rd)
242 gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
243 tcg_const_tl(k), tcg_const_tl(c));
244 else
245 gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
246 tcg_const_tl(k), tcg_const_tl(c));
247 tcg_temp_free(t);
248 }
249 else if (dc->rd)
250 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
251 }
252 }
253
254 static void dec_pattern(DisasContext *dc)
255 {
256 unsigned int mode;
257 int l1;
258
259 if ((dc->tb_flags & MSR_EE_FLAG)
260 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
261 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
262 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
263 t_gen_raise_exception(dc, EXCP_HW_EXCP);
264 }
265
266 mode = dc->opcode & 3;
267 switch (mode) {
268 case 0:
269 /* pcmpbf. */
270 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
271 if (dc->rd)
272 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
273 break;
274 case 2:
275 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
276 if (dc->rd) {
277 TCGv t0 = tcg_temp_local_new();
278 l1 = gen_new_label();
279 tcg_gen_movi_tl(t0, 1);
280 tcg_gen_brcond_tl(TCG_COND_EQ,
281 cpu_R[dc->ra], cpu_R[dc->rb], l1);
282 tcg_gen_movi_tl(t0, 0);
283 gen_set_label(l1);
284 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
285 tcg_temp_free(t0);
286 }
287 break;
288 case 3:
289 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
290 l1 = gen_new_label();
291 if (dc->rd) {
292 TCGv t0 = tcg_temp_local_new();
293 tcg_gen_movi_tl(t0, 1);
294 tcg_gen_brcond_tl(TCG_COND_NE,
295 cpu_R[dc->ra], cpu_R[dc->rb], l1);
296 tcg_gen_movi_tl(t0, 0);
297 gen_set_label(l1);
298 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
299 tcg_temp_free(t0);
300 }
301 break;
302 default:
303 cpu_abort(dc->env,
304 "unsupported pattern insn opcode=%x\n", dc->opcode);
305 break;
306 }
307 }
308
309 static void dec_and(DisasContext *dc)
310 {
311 unsigned int not;
312
313 if (!dc->type_b && (dc->imm & (1 << 10))) {
314 dec_pattern(dc);
315 return;
316 }
317
318 not = dc->opcode & (1 << 1);
319 LOG_DIS("and%s\n", not ? "n" : "");
320
321 if (!dc->rd)
322 return;
323
324 if (not) {
325 TCGv t = tcg_temp_new();
326 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
327 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
328 tcg_temp_free(t);
329 } else
330 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
331 }
332
333 static void dec_or(DisasContext *dc)
334 {
335 if (!dc->type_b && (dc->imm & (1 << 10))) {
336 dec_pattern(dc);
337 return;
338 }
339
340 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
341 if (dc->rd)
342 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
343 }
344
345 static void dec_xor(DisasContext *dc)
346 {
347 if (!dc->type_b && (dc->imm & (1 << 10))) {
348 dec_pattern(dc);
349 return;
350 }
351
352 LOG_DIS("xor r%d\n", dc->rd);
353 if (dc->rd)
354 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
355 }
356
357 static inline void msr_read(DisasContext *dc, TCGv d)
358 {
359 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
360 }
361
362 static inline void msr_write(DisasContext *dc, TCGv v)
363 {
364 dc->cpustate_changed = 1;
365 tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
366 /* PVR, we have a processor version register. */
367 tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
368 }
369
370 static void dec_msr(DisasContext *dc)
371 {
372 TCGv t0, t1;
373 unsigned int sr, to, rn;
374 int mem_index = cpu_mmu_index(dc->env);
375
376 sr = dc->imm & ((1 << 14) - 1);
377 to = dc->imm & (1 << 14);
378 dc->type_b = 1;
379 if (to)
380 dc->cpustate_changed = 1;
381
382 /* msrclr and msrset. */
383 if (!(dc->imm & (1 << 15))) {
384 unsigned int clr = dc->ir & (1 << 16);
385
386 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
387 dc->rd, dc->imm);
388
389 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
390 /* nop??? */
391 return;
392 }
393
394 if ((dc->tb_flags & MSR_EE_FLAG)
395 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
396 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
397 t_gen_raise_exception(dc, EXCP_HW_EXCP);
398 return;
399 }
400
401 if (dc->rd)
402 msr_read(dc, cpu_R[dc->rd]);
403
404 t0 = tcg_temp_new();
405 t1 = tcg_temp_new();
406 msr_read(dc, t0);
407 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
408
409 if (clr) {
410 tcg_gen_not_tl(t1, t1);
411 tcg_gen_and_tl(t0, t0, t1);
412 } else
413 tcg_gen_or_tl(t0, t0, t1);
414 msr_write(dc, t0);
415 tcg_temp_free(t0);
416 tcg_temp_free(t1);
417 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
418 dc->is_jmp = DISAS_UPDATE;
419 return;
420 }
421
422 if (to) {
423 if ((dc->tb_flags & MSR_EE_FLAG)
424 && mem_index == MMU_USER_IDX) {
425 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
426 t_gen_raise_exception(dc, EXCP_HW_EXCP);
427 return;
428 }
429 }
430
431 #if !defined(CONFIG_USER_ONLY)
432 /* Catch read/writes to the mmu block. */
433 if ((sr & ~0xff) == 0x1000) {
434 sr &= 7;
435 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
436 if (to)
437 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
438 else
439 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
440 return;
441 }
442 #endif
443
444 if (to) {
445 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
446 switch (sr) {
447 case 0:
448 break;
449 case 1:
450 msr_write(dc, cpu_R[dc->ra]);
451 break;
452 case 0x3:
453 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
454 break;
455 case 0x5:
456 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
457 break;
458 case 0x7:
459 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
460 break;
461 default:
462 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
463 break;
464 }
465 } else {
466 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
467
468 switch (sr) {
469 case 0:
470 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
471 break;
472 case 1:
473 msr_read(dc, cpu_R[dc->rd]);
474 break;
475 case 0x3:
476 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
477 break;
478 case 0x5:
479 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
480 break;
481 case 0x7:
482 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
483 break;
484 case 0xb:
485 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
486 break;
487 case 0x2000:
488 case 0x2001:
489 case 0x2002:
490 case 0x2003:
491 case 0x2004:
492 case 0x2005:
493 case 0x2006:
494 case 0x2007:
495 case 0x2008:
496 case 0x2009:
497 case 0x200a:
498 case 0x200b:
499 case 0x200c:
500 rn = sr & 0xf;
501 tcg_gen_ld_tl(cpu_R[dc->rd],
502 cpu_env, offsetof(CPUState, pvr.regs[rn]));
503 break;
504 default:
505 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
506 break;
507 }
508 }
509
510 if (dc->rd == 0) {
511 tcg_gen_movi_tl(cpu_R[0], 0);
512 }
513 }
514
515 /* 64-bit signed mul, lower result in d and upper in d2. */
516 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
517 {
518 TCGv_i64 t0, t1;
519
520 t0 = tcg_temp_new_i64();
521 t1 = tcg_temp_new_i64();
522
523 tcg_gen_ext_i32_i64(t0, a);
524 tcg_gen_ext_i32_i64(t1, b);
525 tcg_gen_mul_i64(t0, t0, t1);
526
527 tcg_gen_trunc_i64_i32(d, t0);
528 tcg_gen_shri_i64(t0, t0, 32);
529 tcg_gen_trunc_i64_i32(d2, t0);
530
531 tcg_temp_free_i64(t0);
532 tcg_temp_free_i64(t1);
533 }
534
535 /* 64-bit unsigned muls, lower result in d and upper in d2. */
536 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
537 {
538 TCGv_i64 t0, t1;
539
540 t0 = tcg_temp_new_i64();
541 t1 = tcg_temp_new_i64();
542
543 tcg_gen_extu_i32_i64(t0, a);
544 tcg_gen_extu_i32_i64(t1, b);
545 tcg_gen_mul_i64(t0, t0, t1);
546
547 tcg_gen_trunc_i64_i32(d, t0);
548 tcg_gen_shri_i64(t0, t0, 32);
549 tcg_gen_trunc_i64_i32(d2, t0);
550
551 tcg_temp_free_i64(t0);
552 tcg_temp_free_i64(t1);
553 }
554
555 /* Multiplier unit. */
556 static void dec_mul(DisasContext *dc)
557 {
558 TCGv d[2];
559 unsigned int subcode;
560
561 if ((dc->tb_flags & MSR_EE_FLAG)
562 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
563 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
564 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
565 t_gen_raise_exception(dc, EXCP_HW_EXCP);
566 return;
567 }
568
569 subcode = dc->imm & 3;
570 d[0] = tcg_temp_new();
571 d[1] = tcg_temp_new();
572
573 if (dc->type_b) {
574 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
575 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
576 goto done;
577 }
578
579 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
580 if (subcode >= 1 && subcode <= 3
581 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
582 /* nop??? */
583 }
584
585 switch (subcode) {
586 case 0:
587 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
588 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
589 break;
590 case 1:
591 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
592 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
593 break;
594 case 2:
595 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
596 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
597 break;
598 case 3:
599 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
600 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
601 break;
602 default:
603 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
604 break;
605 }
606 done:
607 tcg_temp_free(d[0]);
608 tcg_temp_free(d[1]);
609 }
610
611 /* Div unit. */
612 static void dec_div(DisasContext *dc)
613 {
614 unsigned int u;
615
616 u = dc->imm & 2;
617 LOG_DIS("div\n");
618
619 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
620 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
621 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
622 t_gen_raise_exception(dc, EXCP_HW_EXCP);
623 }
624
625 if (u)
626 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
627 else
628 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
629 if (!dc->rd)
630 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
631 }
632
633 static void dec_barrel(DisasContext *dc)
634 {
635 TCGv t0;
636 unsigned int s, t;
637
638 if ((dc->tb_flags & MSR_EE_FLAG)
639 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
640 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
641 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
642 t_gen_raise_exception(dc, EXCP_HW_EXCP);
643 return;
644 }
645
646 s = dc->imm & (1 << 10);
647 t = dc->imm & (1 << 9);
648
649 LOG_DIS("bs%s%s r%d r%d r%d\n",
650 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
651
652 t0 = tcg_temp_new();
653
654 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
655 tcg_gen_andi_tl(t0, t0, 31);
656
657 if (s)
658 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
659 else {
660 if (t)
661 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
662 else
663 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
664 }
665 }
666
667 static void dec_bit(DisasContext *dc)
668 {
669 TCGv t0, t1;
670 unsigned int op;
671 int mem_index = cpu_mmu_index(dc->env);
672
673 op = dc->ir & ((1 << 8) - 1);
674 switch (op) {
675 case 0x21:
676 /* src. */
677 t0 = tcg_temp_new();
678
679 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
680 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
681 if (dc->rd) {
682 t1 = tcg_temp_new();
683 read_carry(dc, t1);
684 tcg_gen_shli_tl(t1, t1, 31);
685
686 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
687 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
688 tcg_temp_free(t1);
689 }
690
691 /* Update carry. */
692 write_carry(dc, t0);
693 tcg_temp_free(t0);
694 break;
695
696 case 0x1:
697 case 0x41:
698 /* srl. */
699 t0 = tcg_temp_new();
700 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
701
702 /* Update carry. */
703 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
704 write_carry(dc, t0);
705 tcg_temp_free(t0);
706 if (dc->rd) {
707 if (op == 0x41)
708 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
709 else
710 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
711 }
712 break;
713 case 0x60:
714 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
715 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
716 break;
717 case 0x61:
718 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
719 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
720 break;
721 case 0x64:
722 case 0x66:
723 case 0x74:
724 case 0x76:
725 /* wdc. */
726 LOG_DIS("wdc r%d\n", dc->ra);
727 if ((dc->tb_flags & MSR_EE_FLAG)
728 && mem_index == MMU_USER_IDX) {
729 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
730 t_gen_raise_exception(dc, EXCP_HW_EXCP);
731 return;
732 }
733 break;
734 case 0x68:
735 /* wic. */
736 LOG_DIS("wic r%d\n", dc->ra);
737 if ((dc->tb_flags & MSR_EE_FLAG)
738 && mem_index == MMU_USER_IDX) {
739 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
740 t_gen_raise_exception(dc, EXCP_HW_EXCP);
741 return;
742 }
743 break;
744 default:
745 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
746 dc->pc, op, dc->rd, dc->ra, dc->rb);
747 break;
748 }
749 }
750
751 static inline void sync_jmpstate(DisasContext *dc)
752 {
753 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
754 if (dc->jmp == JMP_DIRECT) {
755 tcg_gen_movi_tl(env_btaken, 1);
756 }
757 dc->jmp = JMP_INDIRECT;
758 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
759 }
760 }
761
762 static void dec_imm(DisasContext *dc)
763 {
764 LOG_DIS("imm %x\n", dc->imm << 16);
765 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
766 dc->tb_flags |= IMM_FLAG;
767 dc->clear_imm = 0;
768 }
769
770 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
771 unsigned int size)
772 {
773 int mem_index = cpu_mmu_index(dc->env);
774
775 if (size == 1) {
776 tcg_gen_qemu_ld8u(dst, addr, mem_index);
777 } else if (size == 2) {
778 tcg_gen_qemu_ld16u(dst, addr, mem_index);
779 } else if (size == 4) {
780 tcg_gen_qemu_ld32u(dst, addr, mem_index);
781 } else
782 cpu_abort(dc->env, "Incorrect load size %d\n", size);
783 }
784
785 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
786 {
787 unsigned int extimm = dc->tb_flags & IMM_FLAG;
788
789 /* Treat the common cases first. */
790 if (!dc->type_b) {
791 /* If any of the regs is r0, return a ptr to the other. */
792 if (dc->ra == 0) {
793 return &cpu_R[dc->rb];
794 } else if (dc->rb == 0) {
795 return &cpu_R[dc->ra];
796 }
797
798 *t = tcg_temp_new();
799 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
800 return t;
801 }
802 /* Immediate. */
803 if (!extimm) {
804 if (dc->imm == 0) {
805 return &cpu_R[dc->ra];
806 }
807 *t = tcg_temp_new();
808 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
809 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
810 } else {
811 *t = tcg_temp_new();
812 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
813 }
814
815 return t;
816 }
817
818 static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
819 {
820 if (size == 4) {
821 tcg_gen_bswap32_tl(dst, src);
822 } else if (size == 2) {
823 TCGv t = tcg_temp_new();
824
825 /* bswap16 assumes the high bits are zero. */
826 tcg_gen_andi_tl(t, src, 0xffff);
827 tcg_gen_bswap16_tl(dst, t);
828 tcg_temp_free(t);
829 } else {
830 /* Ignore.
831 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
832 */
833 }
834 }
835
836 static void dec_load(DisasContext *dc)
837 {
838 TCGv t, *addr;
839 unsigned int size, rev = 0;
840
841 size = 1 << (dc->opcode & 3);
842
843 if (!dc->type_b) {
844 rev = (dc->ir >> 9) & 1;
845 }
846
847 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
848 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
849 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
850 t_gen_raise_exception(dc, EXCP_HW_EXCP);
851 return;
852 }
853
854 LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
855
856 t_sync_flags(dc);
857 addr = compute_ldst_addr(dc, &t);
858
859 /*
860 * When doing reverse accesses we need to do two things.
861 *
862 * 1. Reverse the address wrt endianess.
863 * 2. Byteswap the data lanes on the way back into the CPU core.
864 */
865 if (rev && size != 4) {
866 /* Endian reverse the address. t is addr. */
867 switch (size) {
868 case 1:
869 {
870 /* 00 -> 11
871 01 -> 10
872 10 -> 10
873 11 -> 00 */
874 TCGv low = tcg_temp_new();
875
876 /* Force addr into the temp. */
877 if (addr != &t) {
878 t = tcg_temp_new();
879 tcg_gen_mov_tl(t, *addr);
880 addr = &t;
881 }
882
883 tcg_gen_andi_tl(low, t, 3);
884 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
885 tcg_gen_andi_tl(t, t, ~3);
886 tcg_gen_or_tl(t, t, low);
887 tcg_gen_mov_tl(env_debug, low);
888 tcg_gen_mov_tl(env_imm, t);
889 tcg_temp_free(low);
890 break;
891 }
892
893 case 2:
894 /* 00 -> 10
895 10 -> 00. */
896 /* Force addr into the temp. */
897 if (addr != &t) {
898 t = tcg_temp_new();
899 tcg_gen_xori_tl(t, *addr, 2);
900 addr = &t;
901 } else {
902 tcg_gen_xori_tl(t, t, 2);
903 }
904 break;
905 default:
906 cpu_abort(dc->env, "Invalid reverse size\n");
907 break;
908 }
909 }
910
911 /* If we get a fault on a dslot, the jmpstate better be in sync. */
912 sync_jmpstate(dc);
913
914 /* Verify alignment if needed. */
915 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
916 TCGv v = tcg_temp_new();
917
918 /*
919 * Microblaze gives MMU faults priority over faults due to
920 * unaligned addresses. That's why we speculatively do the load
921 * into v. If the load succeeds, we verify alignment of the
922 * address and if that succeeds we write into the destination reg.
923 */
924 gen_load(dc, v, *addr, size);
925
926 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
927 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
928 tcg_const_tl(0), tcg_const_tl(size - 1));
929 if (dc->rd) {
930 if (rev) {
931 dec_byteswap(dc, cpu_R[dc->rd], v, size);
932 } else {
933 tcg_gen_mov_tl(cpu_R[dc->rd], v);
934 }
935 }
936 tcg_temp_free(v);
937 } else {
938 if (dc->rd) {
939 gen_load(dc, cpu_R[dc->rd], *addr, size);
940 if (rev) {
941 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
942 }
943 } else {
944 /* We are loading into r0, no need to reverse. */
945 gen_load(dc, env_imm, *addr, size);
946 }
947 }
948
949 if (addr == &t)
950 tcg_temp_free(t);
951 }
952
953 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
954 unsigned int size)
955 {
956 int mem_index = cpu_mmu_index(dc->env);
957
958 if (size == 1)
959 tcg_gen_qemu_st8(val, addr, mem_index);
960 else if (size == 2) {
961 tcg_gen_qemu_st16(val, addr, mem_index);
962 } else if (size == 4) {
963 tcg_gen_qemu_st32(val, addr, mem_index);
964 } else
965 cpu_abort(dc->env, "Incorrect store size %d\n", size);
966 }
967
968 static void dec_store(DisasContext *dc)
969 {
970 TCGv t, *addr;
971 unsigned int size, rev = 0;
972
973 size = 1 << (dc->opcode & 3);
974 if (!dc->type_b) {
975 rev = (dc->ir >> 9) & 1;
976 }
977
978 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
979 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
980 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
981 t_gen_raise_exception(dc, EXCP_HW_EXCP);
982 return;
983 }
984
985 LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
986 t_sync_flags(dc);
987 /* If we get a fault on a dslot, the jmpstate better be in sync. */
988 sync_jmpstate(dc);
989 addr = compute_ldst_addr(dc, &t);
990
991 if (rev && size != 4) {
992 /* Endian reverse the address. t is addr. */
993 switch (size) {
994 case 1:
995 {
996 /* 00 -> 11
997 01 -> 10
998 10 -> 10
999 11 -> 00 */
1000 TCGv low = tcg_temp_new();
1001
1002 /* Force addr into the temp. */
1003 if (addr != &t) {
1004 t = tcg_temp_new();
1005 tcg_gen_mov_tl(t, *addr);
1006 addr = &t;
1007 }
1008
1009 tcg_gen_andi_tl(low, t, 3);
1010 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1011 tcg_gen_andi_tl(t, t, ~3);
1012 tcg_gen_or_tl(t, t, low);
1013 tcg_gen_mov_tl(env_debug, low);
1014 tcg_gen_mov_tl(env_imm, t);
1015 tcg_temp_free(low);
1016 break;
1017 }
1018
1019 case 2:
1020 /* 00 -> 10
1021 10 -> 00. */
1022 /* Force addr into the temp. */
1023 if (addr != &t) {
1024 t = tcg_temp_new();
1025 tcg_gen_xori_tl(t, *addr, 2);
1026 addr = &t;
1027 } else {
1028 tcg_gen_xori_tl(t, t, 2);
1029 }
1030 break;
1031 default:
1032 cpu_abort(dc->env, "Invalid reverse size\n");
1033 break;
1034 }
1035
1036 if (size != 1) {
1037 TCGv bs_data = tcg_temp_new();
1038 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1039 gen_store(dc, *addr, bs_data, size);
1040 tcg_temp_free(bs_data);
1041 } else {
1042 gen_store(dc, *addr, cpu_R[dc->rd], size);
1043 }
1044 } else {
1045 if (rev) {
1046 TCGv bs_data = tcg_temp_new();
1047 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1048 gen_store(dc, *addr, bs_data, size);
1049 tcg_temp_free(bs_data);
1050 } else {
1051 gen_store(dc, *addr, cpu_R[dc->rd], size);
1052 }
1053 }
1054
1055 /* Verify alignment if needed. */
1056 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1057 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1058 /* FIXME: if the alignment is wrong, we should restore the value
1059 * in memory. One possible way to acheive this is to probe
1060 * the MMU prior to the memaccess, thay way we could put
1061 * the alignment checks in between the probe and the mem
1062 * access.
1063 */
1064 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
1065 tcg_const_tl(1), tcg_const_tl(size - 1));
1066 }
1067
1068 if (addr == &t)
1069 tcg_temp_free(t);
1070 }
1071
1072 static inline void eval_cc(DisasContext *dc, unsigned int cc,
1073 TCGv d, TCGv a, TCGv b)
1074 {
1075 switch (cc) {
1076 case CC_EQ:
1077 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
1078 break;
1079 case CC_NE:
1080 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
1081 break;
1082 case CC_LT:
1083 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
1084 break;
1085 case CC_LE:
1086 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
1087 break;
1088 case CC_GE:
1089 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
1090 break;
1091 case CC_GT:
1092 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
1093 break;
1094 default:
1095 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1096 break;
1097 }
1098 }
1099
1100 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1101 {
1102 int l1;
1103
1104 l1 = gen_new_label();
1105 /* Conditional jmp. */
1106 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1107 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1108 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1109 gen_set_label(l1);
1110 }
1111
1112 static void dec_bcc(DisasContext *dc)
1113 {
1114 unsigned int cc;
1115 unsigned int dslot;
1116
1117 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1118 dslot = dc->ir & (1 << 25);
1119 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1120
1121 dc->delayed_branch = 1;
1122 if (dslot) {
1123 dc->delayed_branch = 2;
1124 dc->tb_flags |= D_FLAG;
1125 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1126 cpu_env, offsetof(CPUState, bimm));
1127 }
1128
1129 if (dec_alu_op_b_is_small_imm(dc)) {
1130 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1131
1132 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
1133 dc->jmp = JMP_DIRECT_CC;
1134 dc->jmp_pc = dc->pc + offset;
1135 } else {
1136 dc->jmp = JMP_INDIRECT;
1137 tcg_gen_movi_tl(env_btarget, dc->pc);
1138 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1139 }
1140 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
1141 }
1142
1143 static void dec_br(DisasContext *dc)
1144 {
1145 unsigned int dslot, link, abs;
1146 int mem_index = cpu_mmu_index(dc->env);
1147
1148 dslot = dc->ir & (1 << 20);
1149 abs = dc->ir & (1 << 19);
1150 link = dc->ir & (1 << 18);
1151 LOG_DIS("br%s%s%s%s imm=%x\n",
1152 abs ? "a" : "", link ? "l" : "",
1153 dc->type_b ? "i" : "", dslot ? "d" : "",
1154 dc->imm);
1155
1156 dc->delayed_branch = 1;
1157 if (dslot) {
1158 dc->delayed_branch = 2;
1159 dc->tb_flags |= D_FLAG;
1160 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1161 cpu_env, offsetof(CPUState, bimm));
1162 }
1163 if (link && dc->rd)
1164 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1165
1166 dc->jmp = JMP_INDIRECT;
1167 if (abs) {
1168 tcg_gen_movi_tl(env_btaken, 1);
1169 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1170 if (link && !dslot) {
1171 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1172 t_gen_raise_exception(dc, EXCP_BREAK);
1173 if (dc->imm == 0) {
1174 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1175 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1176 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1177 return;
1178 }
1179
1180 t_gen_raise_exception(dc, EXCP_DEBUG);
1181 }
1182 }
1183 } else {
1184 if (dec_alu_op_b_is_small_imm(dc)) {
1185 dc->jmp = JMP_DIRECT;
1186 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1187 } else {
1188 tcg_gen_movi_tl(env_btaken, 1);
1189 tcg_gen_movi_tl(env_btarget, dc->pc);
1190 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1191 }
1192 }
1193 }
1194
1195 static inline void do_rti(DisasContext *dc)
1196 {
1197 TCGv t0, t1;
1198 t0 = tcg_temp_new();
1199 t1 = tcg_temp_new();
1200 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1201 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1202 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1203
1204 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1205 tcg_gen_or_tl(t1, t1, t0);
1206 msr_write(dc, t1);
1207 tcg_temp_free(t1);
1208 tcg_temp_free(t0);
1209 dc->tb_flags &= ~DRTI_FLAG;
1210 }
1211
1212 static inline void do_rtb(DisasContext *dc)
1213 {
1214 TCGv t0, t1;
1215 t0 = tcg_temp_new();
1216 t1 = tcg_temp_new();
1217 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1218 tcg_gen_shri_tl(t0, t1, 1);
1219 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1220
1221 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1222 tcg_gen_or_tl(t1, t1, t0);
1223 msr_write(dc, t1);
1224 tcg_temp_free(t1);
1225 tcg_temp_free(t0);
1226 dc->tb_flags &= ~DRTB_FLAG;
1227 }
1228
1229 static inline void do_rte(DisasContext *dc)
1230 {
1231 TCGv t0, t1;
1232 t0 = tcg_temp_new();
1233 t1 = tcg_temp_new();
1234
1235 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1236 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1237 tcg_gen_shri_tl(t0, t1, 1);
1238 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1239
1240 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1241 tcg_gen_or_tl(t1, t1, t0);
1242 msr_write(dc, t1);
1243 tcg_temp_free(t1);
1244 tcg_temp_free(t0);
1245 dc->tb_flags &= ~DRTE_FLAG;
1246 }
1247
1248 static void dec_rts(DisasContext *dc)
1249 {
1250 unsigned int b_bit, i_bit, e_bit;
1251 int mem_index = cpu_mmu_index(dc->env);
1252
1253 i_bit = dc->ir & (1 << 21);
1254 b_bit = dc->ir & (1 << 22);
1255 e_bit = dc->ir & (1 << 23);
1256
1257 dc->delayed_branch = 2;
1258 dc->tb_flags |= D_FLAG;
1259 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1260 cpu_env, offsetof(CPUState, bimm));
1261
1262 if (i_bit) {
1263 LOG_DIS("rtid ir=%x\n", dc->ir);
1264 if ((dc->tb_flags & MSR_EE_FLAG)
1265 && mem_index == MMU_USER_IDX) {
1266 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1267 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1268 }
1269 dc->tb_flags |= DRTI_FLAG;
1270 } else if (b_bit) {
1271 LOG_DIS("rtbd ir=%x\n", dc->ir);
1272 if ((dc->tb_flags & MSR_EE_FLAG)
1273 && mem_index == MMU_USER_IDX) {
1274 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1275 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1276 }
1277 dc->tb_flags |= DRTB_FLAG;
1278 } else if (e_bit) {
1279 LOG_DIS("rted ir=%x\n", dc->ir);
1280 if ((dc->tb_flags & MSR_EE_FLAG)
1281 && mem_index == MMU_USER_IDX) {
1282 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1283 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1284 }
1285 dc->tb_flags |= DRTE_FLAG;
1286 } else
1287 LOG_DIS("rts ir=%x\n", dc->ir);
1288
1289 dc->jmp = JMP_INDIRECT;
1290 tcg_gen_movi_tl(env_btaken, 1);
1291 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1292 }
1293
1294 static int dec_check_fpuv2(DisasContext *dc)
1295 {
1296 int r;
1297
1298 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1299
1300 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1301 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1302 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1303 }
1304 return r;
1305 }
1306
1307 static void dec_fpu(DisasContext *dc)
1308 {
1309 unsigned int fpu_insn;
1310
1311 if ((dc->tb_flags & MSR_EE_FLAG)
1312 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1313 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1314 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1315 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1316 return;
1317 }
1318
1319 fpu_insn = (dc->ir >> 7) & 7;
1320
1321 switch (fpu_insn) {
1322 case 0:
1323 gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1324 break;
1325
1326 case 1:
1327 gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1328 break;
1329
1330 case 2:
1331 gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1332 break;
1333
1334 case 3:
1335 gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1336 break;
1337
1338 case 4:
1339 switch ((dc->ir >> 4) & 7) {
1340 case 0:
1341 gen_helper_fcmp_un(cpu_R[dc->rd],
1342 cpu_R[dc->ra], cpu_R[dc->rb]);
1343 break;
1344 case 1:
1345 gen_helper_fcmp_lt(cpu_R[dc->rd],
1346 cpu_R[dc->ra], cpu_R[dc->rb]);
1347 break;
1348 case 2:
1349 gen_helper_fcmp_eq(cpu_R[dc->rd],
1350 cpu_R[dc->ra], cpu_R[dc->rb]);
1351 break;
1352 case 3:
1353 gen_helper_fcmp_le(cpu_R[dc->rd],
1354 cpu_R[dc->ra], cpu_R[dc->rb]);
1355 break;
1356 case 4:
1357 gen_helper_fcmp_gt(cpu_R[dc->rd],
1358 cpu_R[dc->ra], cpu_R[dc->rb]);
1359 break;
1360 case 5:
1361 gen_helper_fcmp_ne(cpu_R[dc->rd],
1362 cpu_R[dc->ra], cpu_R[dc->rb]);
1363 break;
1364 case 6:
1365 gen_helper_fcmp_ge(cpu_R[dc->rd],
1366 cpu_R[dc->ra], cpu_R[dc->rb]);
1367 break;
1368 default:
1369 qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1370 fpu_insn, dc->pc, dc->opcode);
1371 dc->abort_at_next_insn = 1;
1372 break;
1373 }
1374 break;
1375
1376 case 5:
1377 if (!dec_check_fpuv2(dc)) {
1378 return;
1379 }
1380 gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
1381 break;
1382
1383 case 6:
1384 if (!dec_check_fpuv2(dc)) {
1385 return;
1386 }
1387 gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
1388 break;
1389
1390 case 7:
1391 if (!dec_check_fpuv2(dc)) {
1392 return;
1393 }
1394 gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
1395 break;
1396
1397 default:
1398 qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1399 fpu_insn, dc->pc, dc->opcode);
1400 dc->abort_at_next_insn = 1;
1401 break;
1402 }
1403 }
1404
1405 static void dec_null(DisasContext *dc)
1406 {
1407 if ((dc->tb_flags & MSR_EE_FLAG)
1408 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1409 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1410 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1411 return;
1412 }
1413 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1414 dc->abort_at_next_insn = 1;
1415 }
1416
1417 static struct decoder_info {
1418 struct {
1419 uint32_t bits;
1420 uint32_t mask;
1421 };
1422 void (*dec)(DisasContext *dc);
1423 } decinfo[] = {
1424 {DEC_ADD, dec_add},
1425 {DEC_SUB, dec_sub},
1426 {DEC_AND, dec_and},
1427 {DEC_XOR, dec_xor},
1428 {DEC_OR, dec_or},
1429 {DEC_BIT, dec_bit},
1430 {DEC_BARREL, dec_barrel},
1431 {DEC_LD, dec_load},
1432 {DEC_ST, dec_store},
1433 {DEC_IMM, dec_imm},
1434 {DEC_BR, dec_br},
1435 {DEC_BCC, dec_bcc},
1436 {DEC_RTS, dec_rts},
1437 {DEC_FPU, dec_fpu},
1438 {DEC_MUL, dec_mul},
1439 {DEC_DIV, dec_div},
1440 {DEC_MSR, dec_msr},
1441 {{0, 0}, dec_null}
1442 };
1443
1444 static inline void decode(DisasContext *dc)
1445 {
1446 uint32_t ir;
1447 int i;
1448
1449 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1450 tcg_gen_debug_insn_start(dc->pc);
1451
1452 dc->ir = ir = ldl_code(dc->pc);
1453 LOG_DIS("%8.8x\t", dc->ir);
1454
1455 if (dc->ir)
1456 dc->nr_nops = 0;
1457 else {
1458 if ((dc->tb_flags & MSR_EE_FLAG)
1459 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1460 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1461 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1462 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1463 return;
1464 }
1465
1466 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1467 dc->nr_nops++;
1468 if (dc->nr_nops > 4)
1469 cpu_abort(dc->env, "fetching nop sequence\n");
1470 }
1471 /* bit 2 seems to indicate insn type. */
1472 dc->type_b = ir & (1 << 29);
1473
1474 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1475 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1476 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1477 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1478 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1479
1480 /* Large switch for all insns. */
1481 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1482 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1483 decinfo[i].dec(dc);
1484 break;
1485 }
1486 }
1487 }
1488
1489 static void check_breakpoint(CPUState *env, DisasContext *dc)
1490 {
1491 CPUBreakpoint *bp;
1492
1493 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1494 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1495 if (bp->pc == dc->pc) {
1496 t_gen_raise_exception(dc, EXCP_DEBUG);
1497 dc->is_jmp = DISAS_UPDATE;
1498 }
1499 }
1500 }
1501 }
1502
1503 /* generate intermediate code for basic block 'tb'. */
1504 static void
1505 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1506 int search_pc)
1507 {
1508 uint16_t *gen_opc_end;
1509 uint32_t pc_start;
1510 int j, lj;
1511 struct DisasContext ctx;
1512 struct DisasContext *dc = &ctx;
1513 uint32_t next_page_start, org_flags;
1514 target_ulong npc;
1515 int num_insns;
1516 int max_insns;
1517
1518 qemu_log_try_set_file(stderr);
1519
1520 pc_start = tb->pc;
1521 dc->env = env;
1522 dc->tb = tb;
1523 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1524
1525 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1526
1527 dc->is_jmp = DISAS_NEXT;
1528 dc->jmp = 0;
1529 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1530 if (dc->delayed_branch) {
1531 dc->jmp = JMP_INDIRECT;
1532 }
1533 dc->pc = pc_start;
1534 dc->singlestep_enabled = env->singlestep_enabled;
1535 dc->cpustate_changed = 0;
1536 dc->abort_at_next_insn = 0;
1537 dc->nr_nops = 0;
1538
1539 if (pc_start & 3)
1540 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1541
1542 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1543 #if !SIM_COMPAT
1544 qemu_log("--------------\n");
1545 log_cpu_state(env, 0);
1546 #endif
1547 }
1548
1549 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1550 lj = -1;
1551 num_insns = 0;
1552 max_insns = tb->cflags & CF_COUNT_MASK;
1553 if (max_insns == 0)
1554 max_insns = CF_COUNT_MASK;
1555
1556 gen_icount_start();
1557 do
1558 {
1559 #if SIM_COMPAT
1560 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1561 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1562 gen_helper_debug();
1563 }
1564 #endif
1565 check_breakpoint(env, dc);
1566
1567 if (search_pc) {
1568 j = gen_opc_ptr - gen_opc_buf;
1569 if (lj < j) {
1570 lj++;
1571 while (lj < j)
1572 gen_opc_instr_start[lj++] = 0;
1573 }
1574 gen_opc_pc[lj] = dc->pc;
1575 gen_opc_instr_start[lj] = 1;
1576 gen_opc_icount[lj] = num_insns;
1577 }
1578
1579 /* Pretty disas. */
1580 LOG_DIS("%8.8x:\t", dc->pc);
1581
1582 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1583 gen_io_start();
1584
1585 dc->clear_imm = 1;
1586 decode(dc);
1587 if (dc->clear_imm)
1588 dc->tb_flags &= ~IMM_FLAG;
1589 dc->pc += 4;
1590 num_insns++;
1591
1592 if (dc->delayed_branch) {
1593 dc->delayed_branch--;
1594 if (!dc->delayed_branch) {
1595 if (dc->tb_flags & DRTI_FLAG)
1596 do_rti(dc);
1597 if (dc->tb_flags & DRTB_FLAG)
1598 do_rtb(dc);
1599 if (dc->tb_flags & DRTE_FLAG)
1600 do_rte(dc);
1601 /* Clear the delay slot flag. */
1602 dc->tb_flags &= ~D_FLAG;
1603 /* If it is a direct jump, try direct chaining. */
1604 if (dc->jmp == JMP_INDIRECT) {
1605 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1606 dc->is_jmp = DISAS_JUMP;
1607 } else if (dc->jmp == JMP_DIRECT) {
1608 t_sync_flags(dc);
1609 gen_goto_tb(dc, 0, dc->jmp_pc);
1610 dc->is_jmp = DISAS_TB_JUMP;
1611 } else if (dc->jmp == JMP_DIRECT_CC) {
1612 int l1;
1613
1614 t_sync_flags(dc);
1615 l1 = gen_new_label();
1616 /* Conditional jmp. */
1617 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1618 gen_goto_tb(dc, 1, dc->pc);
1619 gen_set_label(l1);
1620 gen_goto_tb(dc, 0, dc->jmp_pc);
1621
1622 dc->is_jmp = DISAS_TB_JUMP;
1623 }
1624 break;
1625 }
1626 }
1627 if (env->singlestep_enabled)
1628 break;
1629 } while (!dc->is_jmp && !dc->cpustate_changed
1630 && gen_opc_ptr < gen_opc_end
1631 && !singlestep
1632 && (dc->pc < next_page_start)
1633 && num_insns < max_insns);
1634
1635 npc = dc->pc;
1636 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1637 if (dc->tb_flags & D_FLAG) {
1638 dc->is_jmp = DISAS_UPDATE;
1639 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1640 sync_jmpstate(dc);
1641 } else
1642 npc = dc->jmp_pc;
1643 }
1644
1645 if (tb->cflags & CF_LAST_IO)
1646 gen_io_end();
1647 /* Force an update if the per-tb cpu state has changed. */
1648 if (dc->is_jmp == DISAS_NEXT
1649 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1650 dc->is_jmp = DISAS_UPDATE;
1651 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1652 }
1653 t_sync_flags(dc);
1654
1655 if (unlikely(env->singlestep_enabled)) {
1656 t_gen_raise_exception(dc, EXCP_DEBUG);
1657 if (dc->is_jmp == DISAS_NEXT)
1658 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1659 } else {
1660 switch(dc->is_jmp) {
1661 case DISAS_NEXT:
1662 gen_goto_tb(dc, 1, npc);
1663 break;
1664 default:
1665 case DISAS_JUMP:
1666 case DISAS_UPDATE:
1667 /* indicate that the hash table must be used
1668 to find the next TB */
1669 tcg_gen_exit_tb(0);
1670 break;
1671 case DISAS_TB_JUMP:
1672 /* nothing more to generate */
1673 break;
1674 }
1675 }
1676 gen_icount_end(tb, num_insns);
1677 *gen_opc_ptr = INDEX_op_end;
1678 if (search_pc) {
1679 j = gen_opc_ptr - gen_opc_buf;
1680 lj++;
1681 while (lj <= j)
1682 gen_opc_instr_start[lj++] = 0;
1683 } else {
1684 tb->size = dc->pc - pc_start;
1685 tb->icount = num_insns;
1686 }
1687
1688 #ifdef DEBUG_DISAS
1689 #if !SIM_COMPAT
1690 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1691 qemu_log("\n");
1692 #if DISAS_GNU
1693 log_target_disas(pc_start, dc->pc - pc_start, 0);
1694 #endif
1695 qemu_log("\nisize=%d osize=%td\n",
1696 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1697 }
1698 #endif
1699 #endif
1700 assert(!dc->abort_at_next_insn);
1701 }
1702
1703 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1704 {
1705 gen_intermediate_code_internal(env, tb, 0);
1706 }
1707
1708 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1709 {
1710 gen_intermediate_code_internal(env, tb, 1);
1711 }
1712
1713 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1714 int flags)
1715 {
1716 int i;
1717
1718 if (!env || !f)
1719 return;
1720
1721 cpu_fprintf(f, "IN: PC=%x %s\n",
1722 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1723 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1724 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1725 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
1726 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1727 env->btaken, env->btarget,
1728 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1729 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1730 (env->sregs[SR_MSR] & MSR_EIP),
1731 (env->sregs[SR_MSR] & MSR_IE));
1732
1733 for (i = 0; i < 32; i++) {
1734 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1735 if ((i + 1) % 4 == 0)
1736 cpu_fprintf(f, "\n");
1737 }
1738 cpu_fprintf(f, "\n\n");
1739 }
1740
1741 CPUState *cpu_mb_init (const char *cpu_model)
1742 {
1743 CPUState *env;
1744 static int tcg_initialized = 0;
1745 int i;
1746
1747 env = qemu_mallocz(sizeof(CPUState));
1748
1749 cpu_exec_init(env);
1750 cpu_reset(env);
1751 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1752
1753 if (tcg_initialized)
1754 return env;
1755
1756 tcg_initialized = 1;
1757
1758 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1759
1760 env_debug = tcg_global_mem_new(TCG_AREG0,
1761 offsetof(CPUState, debug),
1762 "debug0");
1763 env_iflags = tcg_global_mem_new(TCG_AREG0,
1764 offsetof(CPUState, iflags),
1765 "iflags");
1766 env_imm = tcg_global_mem_new(TCG_AREG0,
1767 offsetof(CPUState, imm),
1768 "imm");
1769 env_btarget = tcg_global_mem_new(TCG_AREG0,
1770 offsetof(CPUState, btarget),
1771 "btarget");
1772 env_btaken = tcg_global_mem_new(TCG_AREG0,
1773 offsetof(CPUState, btaken),
1774 "btaken");
1775 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1776 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1777 offsetof(CPUState, regs[i]),
1778 regnames[i]);
1779 }
1780 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1781 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1782 offsetof(CPUState, sregs[i]),
1783 special_regnames[i]);
1784 }
1785 #define GEN_HELPER 2
1786 #include "helper.h"
1787
1788 return env;
1789 }
1790
1791 void cpu_reset (CPUState *env)
1792 {
1793 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1794 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1795 log_cpu_state(env, 0);
1796 }
1797
1798 memset(env, 0, offsetof(CPUMBState, breakpoints));
1799 tlb_flush(env, 1);
1800
1801 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1802 | PVR0_USE_BARREL_MASK \
1803 | PVR0_USE_DIV_MASK \
1804 | PVR0_USE_HW_MUL_MASK \
1805 | PVR0_USE_EXC_MASK \
1806 | PVR0_USE_ICACHE_MASK \
1807 | PVR0_USE_DCACHE_MASK \
1808 | PVR0_USE_MMU \
1809 | (0xb << 8);
1810 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1811 | PVR2_D_LMB_MASK \
1812 | PVR2_I_OPB_MASK \
1813 | PVR2_I_LMB_MASK \
1814 | PVR2_USE_MSR_INSTR \
1815 | PVR2_USE_PCMP_INSTR \
1816 | PVR2_USE_BARREL_MASK \
1817 | PVR2_USE_DIV_MASK \
1818 | PVR2_USE_HW_MUL_MASK \
1819 | PVR2_USE_MUL64_MASK \
1820 | PVR2_USE_FPU_MASK \
1821 | PVR2_USE_FPU2_MASK \
1822 | PVR2_FPU_EXC_MASK \
1823 | 0;
1824 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1825 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1826
1827 #if defined(CONFIG_USER_ONLY)
1828 /* start in user mode with interrupts enabled. */
1829 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
1830 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1831 #else
1832 env->sregs[SR_MSR] = 0;
1833 mmu_init(&env->mmu);
1834 env->mmu.c_mmu = 3;
1835 env->mmu.c_mmu_tlb_access = 3;
1836 env->mmu.c_mmu_zones = 16;
1837 #endif
1838 }
1839
1840 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1841 unsigned long searched_pc, int pc_pos, void *puc)
1842 {
1843 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1844 }
Qemu copy for testing