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2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
4 * Copyright (c) 2009 Edgar E. Iglesias.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
32 #include "microblaze-decode.h"
33 #include "qemu-common.h"
41 #if DISAS_MB && !SIM_COMPAT
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
44 # define LOG_DIS(...) do { } while (0)
49 #define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
52 static TCGv env_debug
;
53 static TCGv_ptr cpu_env
;
54 static TCGv cpu_R
[32];
55 static TCGv cpu_SR
[18];
57 static TCGv env_btaken
;
58 static TCGv env_btarget
;
59 static TCGv env_iflags
;
61 #include "gen-icount.h"
63 /* This is the state at translation time. */
64 typedef struct DisasContext
{
67 target_ulong cache_pc
;
76 unsigned int cpustate_changed
;
77 unsigned int delayed_branch
;
78 unsigned int tb_flags
, synced_flags
; /* tb dependent flags. */
79 unsigned int clear_imm
;
84 #define JMP_INDIRECT 2
88 int abort_at_next_insn
;
90 struct TranslationBlock
*tb
;
91 int singlestep_enabled
;
94 static const char *regnames
[] =
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
102 static const char *special_regnames
[] =
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
109 /* Sign extend at translation time. */
110 static inline int sign_extend(unsigned int val
, unsigned int width
)
122 static inline void t_sync_flags(DisasContext
*dc
)
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc
->tb_flags
!= dc
->synced_flags
) {
126 tcg_gen_movi_tl(env_iflags
, dc
->tb_flags
);
127 dc
->synced_flags
= dc
->tb_flags
;
131 static inline void t_gen_raise_exception(DisasContext
*dc
, uint32_t index
)
133 TCGv_i32 tmp
= tcg_const_i32(index
);
136 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
137 gen_helper_raise_exception(tmp
);
138 tcg_temp_free_i32(tmp
);
139 dc
->is_jmp
= DISAS_UPDATE
;
142 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
144 TranslationBlock
*tb
;
146 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
148 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
149 tcg_gen_exit_tb((long)tb
+ n
);
151 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
156 static inline TCGv
*dec_alu_op_b(DisasContext
*dc
)
159 if (dc
->tb_flags
& IMM_FLAG
)
160 tcg_gen_ori_tl(env_imm
, env_imm
, dc
->imm
);
162 tcg_gen_movi_tl(env_imm
, (int32_t)((int16_t)dc
->imm
));
165 return &cpu_R
[dc
->rb
];
168 static void dec_add(DisasContext
*dc
)
175 LOG_DIS("add%s%s%s r%d r%d r%d\n",
176 dc
->type_b
? "i" : "", k
? "k" : "", c
? "c" : "",
177 dc
->rd
, dc
->ra
, dc
->rb
);
179 if (k
&& !c
&& dc
->rd
)
180 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
182 gen_helper_addkc(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)),
183 tcg_const_tl(k
), tcg_const_tl(c
));
185 TCGv d
= tcg_temp_new();
186 gen_helper_addkc(d
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)),
187 tcg_const_tl(k
), tcg_const_tl(c
));
192 static void dec_sub(DisasContext
*dc
)
194 unsigned int u
, cmp
, k
, c
;
199 cmp
= (dc
->imm
& 1) && (!dc
->type_b
) && k
;
202 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u
? "u" : "", dc
->rd
, dc
->ra
, dc
->ir
);
205 gen_helper_cmpu(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
207 gen_helper_cmp(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
210 LOG_DIS("sub%s%s r%d, r%d r%d\n",
211 k
? "k" : "", c
? "c" : "", dc
->rd
, dc
->ra
, dc
->rb
);
217 gen_helper_subkc(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)),
218 tcg_const_tl(k
), tcg_const_tl(c
));
220 gen_helper_subkc(t
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)),
221 tcg_const_tl(k
), tcg_const_tl(c
));
225 tcg_gen_sub_tl(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
229 static void dec_pattern(DisasContext
*dc
)
234 if ((dc
->tb_flags
& MSR_EE_FLAG
)
235 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
236 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
))) {
237 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
238 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
241 mode
= dc
->opcode
& 3;
245 LOG_DIS("pcmpbf r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
247 gen_helper_pcmpbf(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
250 LOG_DIS("pcmpeq r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
252 TCGv t0
= tcg_temp_local_new();
253 l1
= gen_new_label();
254 tcg_gen_movi_tl(t0
, 1);
255 tcg_gen_brcond_tl(TCG_COND_EQ
,
256 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
257 tcg_gen_movi_tl(t0
, 0);
259 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
264 LOG_DIS("pcmpne r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
265 l1
= gen_new_label();
267 TCGv t0
= tcg_temp_local_new();
268 tcg_gen_movi_tl(t0
, 1);
269 tcg_gen_brcond_tl(TCG_COND_NE
,
270 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
271 tcg_gen_movi_tl(t0
, 0);
273 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
279 "unsupported pattern insn opcode=%x\n", dc
->opcode
);
284 static void dec_and(DisasContext
*dc
)
288 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
293 not = dc
->opcode
& (1 << 1);
294 LOG_DIS("and%s\n", not ? "n" : "");
300 TCGv t
= tcg_temp_new();
301 tcg_gen_not_tl(t
, *(dec_alu_op_b(dc
)));
302 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t
);
305 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
308 static void dec_or(DisasContext
*dc
)
310 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
315 LOG_DIS("or r%d r%d r%d imm=%x\n", dc
->rd
, dc
->ra
, dc
->rb
, dc
->imm
);
317 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
320 static void dec_xor(DisasContext
*dc
)
322 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
327 LOG_DIS("xor r%d\n", dc
->rd
);
329 tcg_gen_xor_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
332 static void read_carry(DisasContext
*dc
, TCGv d
)
334 tcg_gen_shri_tl(d
, cpu_SR
[SR_MSR
], 31);
337 static void write_carry(DisasContext
*dc
, TCGv v
)
339 TCGv t0
= tcg_temp_new();
340 tcg_gen_shli_tl(t0
, v
, 31);
341 tcg_gen_sari_tl(t0
, t0
, 31);
342 tcg_gen_mov_tl(env_debug
, t0
);
343 tcg_gen_andi_tl(t0
, t0
, (MSR_C
| MSR_CC
));
344 tcg_gen_andi_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
],
346 tcg_gen_or_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], t0
);
351 static inline void msr_read(DisasContext
*dc
, TCGv d
)
353 tcg_gen_mov_tl(d
, cpu_SR
[SR_MSR
]);
356 static inline void msr_write(DisasContext
*dc
, TCGv v
)
358 dc
->cpustate_changed
= 1;
359 tcg_gen_mov_tl(cpu_SR
[SR_MSR
], v
);
360 /* PVR, we have a processor version register. */
361 tcg_gen_ori_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], (1 << 10));
364 static void dec_msr(DisasContext
*dc
)
367 unsigned int sr
, to
, rn
;
368 int mem_index
= cpu_mmu_index(dc
->env
);
370 sr
= dc
->imm
& ((1 << 14) - 1);
371 to
= dc
->imm
& (1 << 14);
374 dc
->cpustate_changed
= 1;
376 /* msrclr and msrset. */
377 if (!(dc
->imm
& (1 << 15))) {
378 unsigned int clr
= dc
->ir
& (1 << 16);
380 LOG_DIS("msr%s r%d imm=%x\n", clr
? "clr" : "set",
383 if (!(dc
->env
->pvr
.regs
[2] & PVR2_USE_MSR_INSTR
)) {
388 if ((dc
->tb_flags
& MSR_EE_FLAG
)
389 && mem_index
== MMU_USER_IDX
&& (dc
->imm
!= 4 && dc
->imm
!= 0)) {
390 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
391 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
396 msr_read(dc
, cpu_R
[dc
->rd
]);
401 tcg_gen_mov_tl(t1
, *(dec_alu_op_b(dc
)));
404 tcg_gen_not_tl(t1
, t1
);
405 tcg_gen_and_tl(t0
, t0
, t1
);
407 tcg_gen_or_tl(t0
, t0
, t1
);
411 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
+ 4);
412 dc
->is_jmp
= DISAS_UPDATE
;
417 if ((dc
->tb_flags
& MSR_EE_FLAG
)
418 && mem_index
== MMU_USER_IDX
) {
419 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
420 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
425 #if !defined(CONFIG_USER_ONLY)
426 /* Catch read/writes to the mmu block. */
427 if ((sr
& ~0xff) == 0x1000) {
429 LOG_DIS("m%ss sr%d r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
431 gen_helper_mmu_write(tcg_const_tl(sr
), cpu_R
[dc
->ra
]);
433 gen_helper_mmu_read(cpu_R
[dc
->rd
], tcg_const_tl(sr
));
439 LOG_DIS("m%ss sr%x r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
444 msr_write(dc
, cpu_R
[dc
->ra
]);
447 tcg_gen_mov_tl(cpu_SR
[SR_EAR
], cpu_R
[dc
->ra
]);
450 tcg_gen_mov_tl(cpu_SR
[SR_ESR
], cpu_R
[dc
->ra
]);
453 /* Ignored at the moment. */
456 cpu_abort(dc
->env
, "unknown mts reg %x\n", sr
);
460 LOG_DIS("m%ss r%d sr%x imm=%x\n", to
? "t" : "f", dc
->rd
, sr
, dc
->imm
);
464 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
467 msr_read(dc
, cpu_R
[dc
->rd
]);
470 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_EAR
]);
473 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_ESR
]);
476 tcg_gen_movi_tl(cpu_R
[dc
->rd
], 0);
479 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_BTR
]);
495 tcg_gen_ld_tl(cpu_R
[dc
->rd
],
496 cpu_env
, offsetof(CPUState
, pvr
.regs
[rn
]));
499 cpu_abort(dc
->env
, "unknown mfs reg %x\n", sr
);
505 tcg_gen_movi_tl(cpu_R
[0], 0);
509 /* 64-bit signed mul, lower result in d and upper in d2. */
510 static void t_gen_muls(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
514 t0
= tcg_temp_new_i64();
515 t1
= tcg_temp_new_i64();
517 tcg_gen_ext_i32_i64(t0
, a
);
518 tcg_gen_ext_i32_i64(t1
, b
);
519 tcg_gen_mul_i64(t0
, t0
, t1
);
521 tcg_gen_trunc_i64_i32(d
, t0
);
522 tcg_gen_shri_i64(t0
, t0
, 32);
523 tcg_gen_trunc_i64_i32(d2
, t0
);
525 tcg_temp_free_i64(t0
);
526 tcg_temp_free_i64(t1
);
529 /* 64-bit unsigned muls, lower result in d and upper in d2. */
530 static void t_gen_mulu(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
534 t0
= tcg_temp_new_i64();
535 t1
= tcg_temp_new_i64();
537 tcg_gen_extu_i32_i64(t0
, a
);
538 tcg_gen_extu_i32_i64(t1
, b
);
539 tcg_gen_mul_i64(t0
, t0
, t1
);
541 tcg_gen_trunc_i64_i32(d
, t0
);
542 tcg_gen_shri_i64(t0
, t0
, 32);
543 tcg_gen_trunc_i64_i32(d2
, t0
);
545 tcg_temp_free_i64(t0
);
546 tcg_temp_free_i64(t1
);
549 /* Multiplier unit. */
550 static void dec_mul(DisasContext
*dc
)
553 unsigned int subcode
;
555 if ((dc
->tb_flags
& MSR_EE_FLAG
)
556 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
557 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_HW_MUL_MASK
)) {
558 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
559 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
563 subcode
= dc
->imm
& 3;
564 d
[0] = tcg_temp_new();
565 d
[1] = tcg_temp_new();
568 LOG_DIS("muli r%d r%d %x\n", dc
->rd
, dc
->ra
, dc
->imm
);
569 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
573 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
574 if (subcode
>= 1 && subcode
<= 3
575 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_MUL64_MASK
))) {
581 LOG_DIS("mul r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
582 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
585 LOG_DIS("mulh r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
586 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
589 LOG_DIS("mulhsu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
590 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
593 LOG_DIS("mulhu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
594 t_gen_mulu(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
597 cpu_abort(dc
->env
, "unknown MUL insn %x\n", subcode
);
606 static void dec_div(DisasContext
*dc
)
613 if ((dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
614 && !((dc
->env
->pvr
.regs
[0] & PVR0_USE_DIV_MASK
))) {
615 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
616 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
620 gen_helper_divu(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
622 gen_helper_divs(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
624 tcg_gen_movi_tl(cpu_R
[dc
->rd
], 0);
627 static void dec_barrel(DisasContext
*dc
)
632 if ((dc
->tb_flags
& MSR_EE_FLAG
)
633 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
634 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_BARREL_MASK
)) {
635 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
636 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
640 s
= dc
->imm
& (1 << 10);
641 t
= dc
->imm
& (1 << 9);
643 LOG_DIS("bs%s%s r%d r%d r%d\n",
644 s
? "l" : "r", t
? "a" : "l", dc
->rd
, dc
->ra
, dc
->rb
);
648 tcg_gen_mov_tl(t0
, *(dec_alu_op_b(dc
)));
649 tcg_gen_andi_tl(t0
, t0
, 31);
652 tcg_gen_shl_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
655 tcg_gen_sar_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
657 tcg_gen_shr_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
661 static void dec_bit(DisasContext
*dc
)
665 int mem_index
= cpu_mmu_index(dc
->env
);
667 op
= dc
->ir
& ((1 << 8) - 1);
673 LOG_DIS("src r%d r%d\n", dc
->rd
, dc
->ra
);
674 tcg_gen_andi_tl(t0
, cpu_R
[dc
->ra
], 1);
678 tcg_gen_shli_tl(t1
, t1
, 31);
680 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
681 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], t1
);
694 LOG_DIS("srl r%d r%d\n", dc
->rd
, dc
->ra
);
697 tcg_gen_andi_tl(t0
, cpu_R
[dc
->ra
], 1);
702 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
704 tcg_gen_sari_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
708 LOG_DIS("ext8s r%d r%d\n", dc
->rd
, dc
->ra
);
709 tcg_gen_ext8s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
712 LOG_DIS("ext16s r%d r%d\n", dc
->rd
, dc
->ra
);
713 tcg_gen_ext16s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
717 LOG_DIS("wdc r%d\n", dc
->ra
);
718 if ((dc
->tb_flags
& MSR_EE_FLAG
)
719 && mem_index
== MMU_USER_IDX
) {
720 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
721 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
727 LOG_DIS("wic r%d\n", dc
->ra
);
728 if ((dc
->tb_flags
& MSR_EE_FLAG
)
729 && mem_index
== MMU_USER_IDX
) {
730 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
731 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
736 cpu_abort(dc
->env
, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
737 dc
->pc
, op
, dc
->rd
, dc
->ra
, dc
->rb
);
742 static inline void sync_jmpstate(DisasContext
*dc
)
744 if (dc
->jmp
== JMP_DIRECT
) {
745 dc
->jmp
= JMP_INDIRECT
;
746 tcg_gen_movi_tl(env_btaken
, 1);
747 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
751 static void dec_imm(DisasContext
*dc
)
753 LOG_DIS("imm %x\n", dc
->imm
<< 16);
754 tcg_gen_movi_tl(env_imm
, (dc
->imm
<< 16));
755 dc
->tb_flags
|= IMM_FLAG
;
759 static inline void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
762 int mem_index
= cpu_mmu_index(dc
->env
);
765 tcg_gen_qemu_ld8u(dst
, addr
, mem_index
);
766 } else if (size
== 2) {
767 tcg_gen_qemu_ld16u(dst
, addr
, mem_index
);
768 } else if (size
== 4) {
769 tcg_gen_qemu_ld32u(dst
, addr
, mem_index
);
771 cpu_abort(dc
->env
, "Incorrect load size %d\n", size
);
774 static inline TCGv
*compute_ldst_addr(DisasContext
*dc
, TCGv
*t
)
776 unsigned int extimm
= dc
->tb_flags
& IMM_FLAG
;
778 /* Treat the fast cases first. */
781 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
787 return &cpu_R
[dc
->ra
];
790 tcg_gen_movi_tl(*t
, (int32_t)((int16_t)dc
->imm
));
791 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *t
);
794 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
800 static void dec_load(DisasContext
*dc
)
805 size
= 1 << (dc
->opcode
& 3);
806 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
807 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
808 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
809 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
813 LOG_DIS("l %x %d\n", dc
->opcode
, size
);
815 addr
= compute_ldst_addr(dc
, &t
);
817 /* If we get a fault on a dslot, the jmpstate better be in sync. */
820 /* Verify alignment if needed. */
821 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
822 TCGv v
= tcg_temp_new();
825 * Microblaze gives MMU faults priority over faults due to
826 * unaligned addresses. That's why we speculatively do the load
827 * into v. If the load succeeds, we verify alignment of the
828 * address and if that succeeds we write into the destination reg.
830 gen_load(dc
, v
, *addr
, size
);
832 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
833 gen_helper_memalign(*addr
, tcg_const_tl(dc
->rd
),
834 tcg_const_tl(0), tcg_const_tl(size
- 1));
836 tcg_gen_mov_tl(cpu_R
[dc
->rd
], v
);
840 gen_load(dc
, cpu_R
[dc
->rd
], *addr
, size
);
842 gen_load(dc
, env_imm
, *addr
, size
);
850 static void gen_store(DisasContext
*dc
, TCGv addr
, TCGv val
,
853 int mem_index
= cpu_mmu_index(dc
->env
);
856 tcg_gen_qemu_st8(val
, addr
, mem_index
);
857 else if (size
== 2) {
858 tcg_gen_qemu_st16(val
, addr
, mem_index
);
859 } else if (size
== 4) {
860 tcg_gen_qemu_st32(val
, addr
, mem_index
);
862 cpu_abort(dc
->env
, "Incorrect store size %d\n", size
);
865 static void dec_store(DisasContext
*dc
)
870 size
= 1 << (dc
->opcode
& 3);
872 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
873 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
874 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
875 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
879 LOG_DIS("s%d%s\n", size
, dc
->type_b
? "i" : "");
881 /* If we get a fault on a dslot, the jmpstate better be in sync. */
883 addr
= compute_ldst_addr(dc
, &t
);
885 gen_store(dc
, *addr
, cpu_R
[dc
->rd
], size
);
887 /* Verify alignment if needed. */
888 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
889 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
890 /* FIXME: if the alignment is wrong, we should restore the value
893 gen_helper_memalign(*addr
, tcg_const_tl(dc
->rd
),
894 tcg_const_tl(1), tcg_const_tl(size
- 1));
901 static inline void eval_cc(DisasContext
*dc
, unsigned int cc
,
902 TCGv d
, TCGv a
, TCGv b
)
908 l1
= gen_new_label();
909 tcg_gen_movi_tl(env_btaken
, 1);
910 tcg_gen_brcond_tl(TCG_COND_EQ
, a
, b
, l1
);
911 tcg_gen_movi_tl(env_btaken
, 0);
915 l1
= gen_new_label();
916 tcg_gen_movi_tl(env_btaken
, 1);
917 tcg_gen_brcond_tl(TCG_COND_NE
, a
, b
, l1
);
918 tcg_gen_movi_tl(env_btaken
, 0);
922 l1
= gen_new_label();
923 tcg_gen_movi_tl(env_btaken
, 1);
924 tcg_gen_brcond_tl(TCG_COND_LT
, a
, b
, l1
);
925 tcg_gen_movi_tl(env_btaken
, 0);
929 l1
= gen_new_label();
930 tcg_gen_movi_tl(env_btaken
, 1);
931 tcg_gen_brcond_tl(TCG_COND_LE
, a
, b
, l1
);
932 tcg_gen_movi_tl(env_btaken
, 0);
936 l1
= gen_new_label();
937 tcg_gen_movi_tl(env_btaken
, 1);
938 tcg_gen_brcond_tl(TCG_COND_GE
, a
, b
, l1
);
939 tcg_gen_movi_tl(env_btaken
, 0);
943 l1
= gen_new_label();
944 tcg_gen_movi_tl(env_btaken
, 1);
945 tcg_gen_brcond_tl(TCG_COND_GT
, a
, b
, l1
);
946 tcg_gen_movi_tl(env_btaken
, 0);
950 cpu_abort(dc
->env
, "Unknown condition code %x.\n", cc
);
955 static void eval_cond_jmp(DisasContext
*dc
, TCGv pc_true
, TCGv pc_false
)
959 l1
= gen_new_label();
960 /* Conditional jmp. */
961 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_false
);
962 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
963 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_true
);
967 static void dec_bcc(DisasContext
*dc
)
972 cc
= EXTRACT_FIELD(dc
->ir
, 21, 23);
973 dslot
= dc
->ir
& (1 << 25);
974 LOG_DIS("bcc%s r%d %x\n", dslot
? "d" : "", dc
->ra
, dc
->imm
);
976 dc
->delayed_branch
= 1;
978 dc
->delayed_branch
= 2;
979 dc
->tb_flags
|= D_FLAG
;
980 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
981 cpu_env
, offsetof(CPUState
, bimm
));
984 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
985 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
986 eval_cc(dc
, cc
, env_btaken
, cpu_R
[dc
->ra
], tcg_const_tl(0));
987 dc
->jmp
= JMP_INDIRECT
;
990 static void dec_br(DisasContext
*dc
)
992 unsigned int dslot
, link
, abs
;
994 dslot
= dc
->ir
& (1 << 20);
995 abs
= dc
->ir
& (1 << 19);
996 link
= dc
->ir
& (1 << 18);
997 LOG_DIS("br%s%s%s%s imm=%x\n",
998 abs
? "a" : "", link
? "l" : "",
999 dc
->type_b
? "i" : "", dslot
? "d" : "",
1002 dc
->delayed_branch
= 1;
1004 dc
->delayed_branch
= 2;
1005 dc
->tb_flags
|= D_FLAG
;
1006 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1007 cpu_env
, offsetof(CPUState
, bimm
));
1010 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
1012 dc
->jmp
= JMP_INDIRECT
;
1014 tcg_gen_movi_tl(env_btaken
, 1);
1015 tcg_gen_mov_tl(env_btarget
, *(dec_alu_op_b(dc
)));
1016 if (link
&& !(dc
->tb_flags
& IMM_FLAG
)
1017 && (dc
->imm
== 8 || dc
->imm
== 0x18))
1018 t_gen_raise_exception(dc
, EXCP_BREAK
);
1020 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1022 if (dc
->tb_flags
& IMM_FLAG
) {
1023 tcg_gen_movi_tl(env_btaken
, 1);
1024 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
1025 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
1027 dc
->jmp
= JMP_DIRECT
;
1028 dc
->jmp_pc
= dc
->pc
+ (int32_t)((int16_t)dc
->imm
);
1033 static inline void do_rti(DisasContext
*dc
)
1036 t0
= tcg_temp_new();
1037 t1
= tcg_temp_new();
1038 tcg_gen_shri_tl(t0
, cpu_SR
[SR_MSR
], 1);
1039 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_IE
);
1040 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1042 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1043 tcg_gen_or_tl(t1
, t1
, t0
);
1047 dc
->tb_flags
&= ~DRTI_FLAG
;
1050 static inline void do_rtb(DisasContext
*dc
)
1053 t0
= tcg_temp_new();
1054 t1
= tcg_temp_new();
1055 tcg_gen_andi_tl(t1
, cpu_SR
[SR_MSR
], ~MSR_BIP
);
1056 tcg_gen_shri_tl(t0
, t1
, 1);
1057 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1059 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1060 tcg_gen_or_tl(t1
, t1
, t0
);
1064 dc
->tb_flags
&= ~DRTB_FLAG
;
1067 static inline void do_rte(DisasContext
*dc
)
1070 t0
= tcg_temp_new();
1071 t1
= tcg_temp_new();
1073 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_EE
);
1074 tcg_gen_andi_tl(t1
, t1
, ~MSR_EIP
);
1075 tcg_gen_shri_tl(t0
, t1
, 1);
1076 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1078 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1079 tcg_gen_or_tl(t1
, t1
, t0
);
1083 dc
->tb_flags
&= ~DRTE_FLAG
;
1086 static void dec_rts(DisasContext
*dc
)
1088 unsigned int b_bit
, i_bit
, e_bit
;
1089 int mem_index
= cpu_mmu_index(dc
->env
);
1091 i_bit
= dc
->ir
& (1 << 21);
1092 b_bit
= dc
->ir
& (1 << 22);
1093 e_bit
= dc
->ir
& (1 << 23);
1095 dc
->delayed_branch
= 2;
1096 dc
->tb_flags
|= D_FLAG
;
1097 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1098 cpu_env
, offsetof(CPUState
, bimm
));
1101 LOG_DIS("rtid ir=%x\n", dc
->ir
);
1102 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1103 && mem_index
== MMU_USER_IDX
) {
1104 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1105 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1107 dc
->tb_flags
|= DRTI_FLAG
;
1109 LOG_DIS("rtbd ir=%x\n", dc
->ir
);
1110 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1111 && mem_index
== MMU_USER_IDX
) {
1112 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1113 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1115 dc
->tb_flags
|= DRTB_FLAG
;
1117 LOG_DIS("rted ir=%x\n", dc
->ir
);
1118 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1119 && mem_index
== MMU_USER_IDX
) {
1120 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1121 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1123 dc
->tb_flags
|= DRTE_FLAG
;
1125 LOG_DIS("rts ir=%x\n", dc
->ir
);
1127 tcg_gen_movi_tl(env_btaken
, 1);
1128 tcg_gen_add_tl(env_btarget
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
1131 static void dec_fpu(DisasContext
*dc
)
1133 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1134 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1135 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_FPU_MASK
))) {
1136 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_FPU
);
1137 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1141 qemu_log ("unimplemented FPU insn pc=%x opc=%x\n", dc
->pc
, dc
->opcode
);
1142 dc
->abort_at_next_insn
= 1;
1145 static void dec_null(DisasContext
*dc
)
1147 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1148 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
1149 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1150 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1153 qemu_log ("unknown insn pc=%x opc=%x\n", dc
->pc
, dc
->opcode
);
1154 dc
->abort_at_next_insn
= 1;
1157 static struct decoder_info
{
1162 void (*dec
)(DisasContext
*dc
);
1170 {DEC_BARREL
, dec_barrel
},
1172 {DEC_ST
, dec_store
},
1184 static inline void decode(DisasContext
*dc
)
1189 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
1190 tcg_gen_debug_insn_start(dc
->pc
);
1192 dc
->ir
= ir
= ldl_code(dc
->pc
);
1193 LOG_DIS("%8.8x\t", dc
->ir
);
1198 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1199 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1200 && (dc
->env
->pvr
.regs
[2] & PVR2_OPCODE_0x0_ILL_MASK
)) {
1201 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1202 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1206 LOG_DIS("nr_nops=%d\t", dc
->nr_nops
);
1208 if (dc
->nr_nops
> 4)
1209 cpu_abort(dc
->env
, "fetching nop sequence\n");
1211 /* bit 2 seems to indicate insn type. */
1212 dc
->type_b
= ir
& (1 << 29);
1214 dc
->opcode
= EXTRACT_FIELD(ir
, 26, 31);
1215 dc
->rd
= EXTRACT_FIELD(ir
, 21, 25);
1216 dc
->ra
= EXTRACT_FIELD(ir
, 16, 20);
1217 dc
->rb
= EXTRACT_FIELD(ir
, 11, 15);
1218 dc
->imm
= EXTRACT_FIELD(ir
, 0, 15);
1220 /* Large switch for all insns. */
1221 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
1222 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
1229 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
1233 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1234 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1235 if (bp
->pc
== dc
->pc
) {
1236 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1237 dc
->is_jmp
= DISAS_UPDATE
;
1243 /* generate intermediate code for basic block 'tb'. */
1245 gen_intermediate_code_internal(CPUState
*env
, TranslationBlock
*tb
,
1248 uint16_t *gen_opc_end
;
1251 struct DisasContext ctx
;
1252 struct DisasContext
*dc
= &ctx
;
1253 uint32_t next_page_start
, org_flags
;
1258 qemu_log_try_set_file(stderr
);
1263 org_flags
= dc
->synced_flags
= dc
->tb_flags
= tb
->flags
;
1265 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1267 dc
->is_jmp
= DISAS_NEXT
;
1269 dc
->delayed_branch
= !!(dc
->tb_flags
& D_FLAG
);
1273 dc
->singlestep_enabled
= env
->singlestep_enabled
;
1274 dc
->cpustate_changed
= 0;
1275 dc
->abort_at_next_insn
= 0;
1279 cpu_abort(env
, "Microblaze: unaligned PC=%x\n", pc_start
);
1281 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1283 qemu_log("--------------\n");
1284 log_cpu_state(env
, 0);
1288 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1291 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1293 max_insns
= CF_COUNT_MASK
;
1299 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1300 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1304 check_breakpoint(env
, dc
);
1307 j
= gen_opc_ptr
- gen_opc_buf
;
1311 gen_opc_instr_start
[lj
++] = 0;
1313 gen_opc_pc
[lj
] = dc
->pc
;
1314 gen_opc_instr_start
[lj
] = 1;
1315 gen_opc_icount
[lj
] = num_insns
;
1319 LOG_DIS("%8.8x:\t", dc
->pc
);
1321 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
1327 dc
->tb_flags
&= ~IMM_FLAG
;
1332 if (dc
->delayed_branch
) {
1333 dc
->delayed_branch
--;
1334 if (!dc
->delayed_branch
) {
1335 if (dc
->tb_flags
& DRTI_FLAG
)
1337 if (dc
->tb_flags
& DRTB_FLAG
)
1339 if (dc
->tb_flags
& DRTE_FLAG
)
1341 /* Clear the delay slot flag. */
1342 dc
->tb_flags
&= ~D_FLAG
;
1343 /* If it is a direct jump, try direct chaining. */
1344 if (dc
->jmp
!= JMP_DIRECT
) {
1345 eval_cond_jmp(dc
, env_btarget
, tcg_const_tl(dc
->pc
));
1346 dc
->is_jmp
= DISAS_JUMP
;
1351 if (env
->singlestep_enabled
)
1353 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
1354 && gen_opc_ptr
< gen_opc_end
1356 && (dc
->pc
< next_page_start
)
1357 && num_insns
< max_insns
);
1360 if (dc
->jmp
== JMP_DIRECT
) {
1361 if (dc
->tb_flags
& D_FLAG
) {
1362 dc
->is_jmp
= DISAS_UPDATE
;
1363 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1369 if (tb
->cflags
& CF_LAST_IO
)
1371 /* Force an update if the per-tb cpu state has changed. */
1372 if (dc
->is_jmp
== DISAS_NEXT
1373 && (dc
->cpustate_changed
|| org_flags
!= dc
->tb_flags
)) {
1374 dc
->is_jmp
= DISAS_UPDATE
;
1375 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1379 if (unlikely(env
->singlestep_enabled
)) {
1380 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1381 if (dc
->is_jmp
== DISAS_NEXT
)
1382 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1384 switch(dc
->is_jmp
) {
1386 gen_goto_tb(dc
, 1, npc
);
1391 /* indicate that the hash table must be used
1392 to find the next TB */
1396 /* nothing more to generate */
1400 gen_icount_end(tb
, num_insns
);
1401 *gen_opc_ptr
= INDEX_op_end
;
1403 j
= gen_opc_ptr
- gen_opc_buf
;
1406 gen_opc_instr_start
[lj
++] = 0;
1408 tb
->size
= dc
->pc
- pc_start
;
1409 tb
->icount
= num_insns
;
1414 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1417 log_target_disas(pc_start
, dc
->pc
- pc_start
, 0);
1419 qemu_log("\nisize=%d osize=%zd\n",
1420 dc
->pc
- pc_start
, gen_opc_ptr
- gen_opc_buf
);
1424 assert(!dc
->abort_at_next_insn
);
1427 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
1429 gen_intermediate_code_internal(env
, tb
, 0);
1432 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
1434 gen_intermediate_code_internal(env
, tb
, 1);
1437 void cpu_dump_state (CPUState
*env
, FILE *f
,
1438 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1446 cpu_fprintf(f
, "IN: PC=%x %s\n",
1447 env
->sregs
[SR_PC
], lookup_symbol(env
->sregs
[SR_PC
]));
1448 cpu_fprintf(f
, "rmsr=%x resr=%x debug[%x] imm=%x iflags=%x\n",
1449 env
->sregs
[SR_MSR
], env
->sregs
[SR_ESR
],
1450 env
->debug
, env
->imm
, env
->iflags
);
1451 cpu_fprintf(f
, "btaken=%d btarget=%x mode=%s(saved=%s)\n",
1452 env
->btaken
, env
->btarget
,
1453 (env
->sregs
[SR_MSR
] & MSR_UM
) ? "user" : "kernel",
1454 (env
->sregs
[SR_MSR
] & MSR_UMS
) ? "user" : "kernel");
1455 for (i
= 0; i
< 32; i
++) {
1456 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
1457 if ((i
+ 1) % 4 == 0)
1458 cpu_fprintf(f
, "\n");
1460 cpu_fprintf(f
, "\n\n");
1463 CPUState
*cpu_mb_init (const char *cpu_model
)
1466 static int tcg_initialized
= 0;
1469 env
= qemu_mallocz(sizeof(CPUState
));
1474 env
->pvr
.regs
[0] = PVR0_PVR_FULL_MASK \
1475 | PVR0_USE_BARREL_MASK \
1476 | PVR0_USE_DIV_MASK \
1477 | PVR0_USE_HW_MUL_MASK \
1478 | PVR0_USE_EXC_MASK \
1479 | PVR0_USE_ICACHE_MASK \
1480 | PVR0_USE_DCACHE_MASK \
1483 env
->pvr
.regs
[2] = PVR2_D_OPB_MASK \
1487 | PVR2_USE_MSR_INSTR \
1488 | PVR2_USE_PCMP_INSTR \
1489 | PVR2_USE_BARREL_MASK \
1490 | PVR2_USE_DIV_MASK \
1491 | PVR2_USE_HW_MUL_MASK \
1492 | PVR2_USE_MUL64_MASK \
1494 env
->pvr
.regs
[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1495 env
->pvr
.regs
[11] = PVR11_USE_MMU
| (16 << 17);
1496 #if !defined(CONFIG_USER_ONLY)
1498 env
->mmu
.c_mmu_tlb_access
= 3;
1499 env
->mmu
.c_mmu_zones
= 16;
1502 if (tcg_initialized
)
1505 tcg_initialized
= 1;
1507 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
1509 env_debug
= tcg_global_mem_new(TCG_AREG0
,
1510 offsetof(CPUState
, debug
),
1512 env_iflags
= tcg_global_mem_new(TCG_AREG0
,
1513 offsetof(CPUState
, iflags
),
1515 env_imm
= tcg_global_mem_new(TCG_AREG0
,
1516 offsetof(CPUState
, imm
),
1518 env_btarget
= tcg_global_mem_new(TCG_AREG0
,
1519 offsetof(CPUState
, btarget
),
1521 env_btaken
= tcg_global_mem_new(TCG_AREG0
,
1522 offsetof(CPUState
, btaken
),
1524 for (i
= 0; i
< ARRAY_SIZE(cpu_R
); i
++) {
1525 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
1526 offsetof(CPUState
, regs
[i
]),
1529 for (i
= 0; i
< ARRAY_SIZE(cpu_SR
); i
++) {
1530 cpu_SR
[i
] = tcg_global_mem_new(TCG_AREG0
,
1531 offsetof(CPUState
, sregs
[i
]),
1532 special_regnames
[i
]);
1534 #define GEN_HELPER 2
1540 void cpu_reset (CPUState
*env
)
1542 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1543 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1544 log_cpu_state(env
, 0);
1547 memset(env
, 0, offsetof(CPUMBState
, breakpoints
));
1550 env
->sregs
[SR_MSR
] = 0;
1551 #if defined(CONFIG_USER_ONLY)
1552 /* start in user mode with interrupts enabled. */
1553 env
->pvr
.regs
[10] = 0x0c000000; /* Spartan 3a dsp. */
1555 mmu_init(&env
->mmu
);
1559 void gen_pc_load(CPUState
*env
, struct TranslationBlock
*tb
,
1560 unsigned long searched_pc
, int pc_pos
, void *puc
)
1562 env
->sregs
[SR_PC
] = gen_opc_pc
[pc_pos
];