2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
4 * Copyright (c) 2009 Edgar E. Iglesias.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
31 #include "microblaze-decode.h"
32 #include "qemu-common.h"
40 #if DISAS_MB && !SIM_COMPAT
41 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 # define LOG_DIS(...) do { } while (0)
48 #define EXTRACT_FIELD(src, start, end) \
49 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51 static TCGv env_debug
;
52 static TCGv_ptr cpu_env
;
53 static TCGv cpu_R
[32];
54 static TCGv cpu_SR
[18];
56 static TCGv env_btaken
;
57 static TCGv env_btarget
;
58 static TCGv env_iflags
;
60 #include "gen-icount.h"
62 /* This is the state at translation time. */
63 typedef struct DisasContext
{
74 unsigned int cpustate_changed
;
75 unsigned int delayed_branch
;
76 unsigned int tb_flags
, synced_flags
; /* tb dependent flags. */
77 unsigned int clear_imm
;
82 #define JMP_DIRECT_CC 2
83 #define JMP_INDIRECT 3
87 int abort_at_next_insn
;
89 struct TranslationBlock
*tb
;
90 int singlestep_enabled
;
93 static const char *regnames
[] =
95 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
96 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
97 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
98 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
101 static const char *special_regnames
[] =
103 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
104 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
105 "sr16", "sr17", "sr18"
108 /* Sign extend at translation time. */
109 static inline int sign_extend(unsigned int val
, unsigned int width
)
121 static inline void t_sync_flags(DisasContext
*dc
)
123 /* Synch the tb dependent flags between translator and runtime. */
124 if (dc
->tb_flags
!= dc
->synced_flags
) {
125 tcg_gen_movi_tl(env_iflags
, dc
->tb_flags
);
126 dc
->synced_flags
= dc
->tb_flags
;
130 static inline void t_gen_raise_exception(DisasContext
*dc
, uint32_t index
)
132 TCGv_i32 tmp
= tcg_const_i32(index
);
135 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
136 gen_helper_raise_exception(tmp
);
137 tcg_temp_free_i32(tmp
);
138 dc
->is_jmp
= DISAS_UPDATE
;
141 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
143 TranslationBlock
*tb
;
145 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
147 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
148 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
150 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
155 static void read_carry(DisasContext
*dc
, TCGv d
)
157 tcg_gen_shri_tl(d
, cpu_SR
[SR_MSR
], 31);
160 static void write_carry(DisasContext
*dc
, TCGv v
)
162 TCGv t0
= tcg_temp_new();
163 tcg_gen_shli_tl(t0
, v
, 31);
164 tcg_gen_sari_tl(t0
, t0
, 31);
165 tcg_gen_andi_tl(t0
, t0
, (MSR_C
| MSR_CC
));
166 tcg_gen_andi_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
],
168 tcg_gen_or_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], t0
);
172 /* True if ALU operand b is a small immediate that may deserve
174 static inline int dec_alu_op_b_is_small_imm(DisasContext
*dc
)
176 /* Immediate insn without the imm prefix ? */
177 return dc
->type_b
&& !(dc
->tb_flags
& IMM_FLAG
);
180 static inline TCGv
*dec_alu_op_b(DisasContext
*dc
)
183 if (dc
->tb_flags
& IMM_FLAG
)
184 tcg_gen_ori_tl(env_imm
, env_imm
, dc
->imm
);
186 tcg_gen_movi_tl(env_imm
, (int32_t)((int16_t)dc
->imm
));
189 return &cpu_R
[dc
->rb
];
192 static void dec_add(DisasContext
*dc
)
200 LOG_DIS("add%s%s%s r%d r%d r%d\n",
201 dc
->type_b
? "i" : "", k
? "k" : "", c
? "c" : "",
202 dc
->rd
, dc
->ra
, dc
->rb
);
204 /* Take care of the easy cases first. */
206 /* k - keep carry, no need to update MSR. */
207 /* If rd == r0, it's a nop. */
209 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
212 /* c - Add carry into the result. */
216 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
223 /* From now on, we can assume k is zero. So we need to update MSR. */
229 tcg_gen_movi_tl(cf
, 0);
233 TCGv ncf
= tcg_temp_new();
234 gen_helper_carry(ncf
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)), cf
);
235 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
236 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
237 write_carry(dc
, ncf
);
240 gen_helper_carry(cf
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)), cf
);
246 static void dec_sub(DisasContext
*dc
)
248 unsigned int u
, cmp
, k
, c
;
254 cmp
= (dc
->imm
& 1) && (!dc
->type_b
) && k
;
257 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u
? "u" : "", dc
->rd
, dc
->ra
, dc
->ir
);
260 gen_helper_cmpu(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
262 gen_helper_cmp(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
267 LOG_DIS("sub%s%s r%d, r%d r%d\n",
268 k
? "k" : "", c
? "c" : "", dc
->rd
, dc
->ra
, dc
->rb
);
270 /* Take care of the easy cases first. */
272 /* k - keep carry, no need to update MSR. */
273 /* If rd == r0, it's a nop. */
275 tcg_gen_sub_tl(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
278 /* c - Add carry into the result. */
282 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
289 /* From now on, we can assume k is zero. So we need to update MSR. */
290 /* Extract carry. And complement a into na. */
296 tcg_gen_movi_tl(cf
, 1);
299 /* d = b + ~a + c. carry defaults to 1. */
300 tcg_gen_not_tl(na
, cpu_R
[dc
->ra
]);
303 TCGv ncf
= tcg_temp_new();
304 gen_helper_carry(ncf
, na
, *(dec_alu_op_b(dc
)), cf
);
305 tcg_gen_add_tl(cpu_R
[dc
->rd
], na
, *(dec_alu_op_b(dc
)));
306 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
307 write_carry(dc
, ncf
);
310 gen_helper_carry(cf
, na
, *(dec_alu_op_b(dc
)), cf
);
317 static void dec_pattern(DisasContext
*dc
)
322 if ((dc
->tb_flags
& MSR_EE_FLAG
)
323 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
324 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
))) {
325 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
326 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
329 mode
= dc
->opcode
& 3;
333 LOG_DIS("pcmpbf r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
335 gen_helper_pcmpbf(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
338 LOG_DIS("pcmpeq r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
340 TCGv t0
= tcg_temp_local_new();
341 l1
= gen_new_label();
342 tcg_gen_movi_tl(t0
, 1);
343 tcg_gen_brcond_tl(TCG_COND_EQ
,
344 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
345 tcg_gen_movi_tl(t0
, 0);
347 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
352 LOG_DIS("pcmpne r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
353 l1
= gen_new_label();
355 TCGv t0
= tcg_temp_local_new();
356 tcg_gen_movi_tl(t0
, 1);
357 tcg_gen_brcond_tl(TCG_COND_NE
,
358 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
359 tcg_gen_movi_tl(t0
, 0);
361 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
367 "unsupported pattern insn opcode=%x\n", dc
->opcode
);
372 static void dec_and(DisasContext
*dc
)
376 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
381 not = dc
->opcode
& (1 << 1);
382 LOG_DIS("and%s\n", not ? "n" : "");
388 TCGv t
= tcg_temp_new();
389 tcg_gen_not_tl(t
, *(dec_alu_op_b(dc
)));
390 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t
);
393 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
396 static void dec_or(DisasContext
*dc
)
398 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
403 LOG_DIS("or r%d r%d r%d imm=%x\n", dc
->rd
, dc
->ra
, dc
->rb
, dc
->imm
);
405 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
408 static void dec_xor(DisasContext
*dc
)
410 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
415 LOG_DIS("xor r%d\n", dc
->rd
);
417 tcg_gen_xor_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
420 static inline void msr_read(DisasContext
*dc
, TCGv d
)
422 tcg_gen_mov_tl(d
, cpu_SR
[SR_MSR
]);
425 static inline void msr_write(DisasContext
*dc
, TCGv v
)
430 dc
->cpustate_changed
= 1;
431 /* PVR bit is not writable. */
432 tcg_gen_andi_tl(t
, v
, ~MSR_PVR
);
433 tcg_gen_andi_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], MSR_PVR
);
434 tcg_gen_or_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], v
);
438 static void dec_msr(DisasContext
*dc
)
441 unsigned int sr
, to
, rn
;
442 int mem_index
= cpu_mmu_index(dc
->env
);
444 sr
= dc
->imm
& ((1 << 14) - 1);
445 to
= dc
->imm
& (1 << 14);
448 dc
->cpustate_changed
= 1;
450 /* msrclr and msrset. */
451 if (!(dc
->imm
& (1 << 15))) {
452 unsigned int clr
= dc
->ir
& (1 << 16);
454 LOG_DIS("msr%s r%d imm=%x\n", clr
? "clr" : "set",
457 if (!(dc
->env
->pvr
.regs
[2] & PVR2_USE_MSR_INSTR
)) {
462 if ((dc
->tb_flags
& MSR_EE_FLAG
)
463 && mem_index
== MMU_USER_IDX
&& (dc
->imm
!= 4 && dc
->imm
!= 0)) {
464 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
465 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
470 msr_read(dc
, cpu_R
[dc
->rd
]);
475 tcg_gen_mov_tl(t1
, *(dec_alu_op_b(dc
)));
478 tcg_gen_not_tl(t1
, t1
);
479 tcg_gen_and_tl(t0
, t0
, t1
);
481 tcg_gen_or_tl(t0
, t0
, t1
);
485 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
+ 4);
486 dc
->is_jmp
= DISAS_UPDATE
;
491 if ((dc
->tb_flags
& MSR_EE_FLAG
)
492 && mem_index
== MMU_USER_IDX
) {
493 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
494 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
499 #if !defined(CONFIG_USER_ONLY)
500 /* Catch read/writes to the mmu block. */
501 if ((sr
& ~0xff) == 0x1000) {
503 LOG_DIS("m%ss sr%d r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
505 gen_helper_mmu_write(tcg_const_tl(sr
), cpu_R
[dc
->ra
]);
507 gen_helper_mmu_read(cpu_R
[dc
->rd
], tcg_const_tl(sr
));
513 LOG_DIS("m%ss sr%x r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
518 msr_write(dc
, cpu_R
[dc
->ra
]);
521 tcg_gen_mov_tl(cpu_SR
[SR_EAR
], cpu_R
[dc
->ra
]);
524 tcg_gen_mov_tl(cpu_SR
[SR_ESR
], cpu_R
[dc
->ra
]);
527 tcg_gen_andi_tl(cpu_SR
[SR_FSR
], cpu_R
[dc
->ra
], 31);
530 cpu_abort(dc
->env
, "unknown mts reg %x\n", sr
);
534 LOG_DIS("m%ss r%d sr%x imm=%x\n", to
? "t" : "f", dc
->rd
, sr
, dc
->imm
);
538 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
541 msr_read(dc
, cpu_R
[dc
->rd
]);
544 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_EAR
]);
547 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_ESR
]);
550 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_FSR
]);
553 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_BTR
]);
569 tcg_gen_ld_tl(cpu_R
[dc
->rd
],
570 cpu_env
, offsetof(CPUState
, pvr
.regs
[rn
]));
573 cpu_abort(dc
->env
, "unknown mfs reg %x\n", sr
);
579 tcg_gen_movi_tl(cpu_R
[0], 0);
583 /* 64-bit signed mul, lower result in d and upper in d2. */
584 static void t_gen_muls(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
588 t0
= tcg_temp_new_i64();
589 t1
= tcg_temp_new_i64();
591 tcg_gen_ext_i32_i64(t0
, a
);
592 tcg_gen_ext_i32_i64(t1
, b
);
593 tcg_gen_mul_i64(t0
, t0
, t1
);
595 tcg_gen_trunc_i64_i32(d
, t0
);
596 tcg_gen_shri_i64(t0
, t0
, 32);
597 tcg_gen_trunc_i64_i32(d2
, t0
);
599 tcg_temp_free_i64(t0
);
600 tcg_temp_free_i64(t1
);
603 /* 64-bit unsigned muls, lower result in d and upper in d2. */
604 static void t_gen_mulu(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
608 t0
= tcg_temp_new_i64();
609 t1
= tcg_temp_new_i64();
611 tcg_gen_extu_i32_i64(t0
, a
);
612 tcg_gen_extu_i32_i64(t1
, b
);
613 tcg_gen_mul_i64(t0
, t0
, t1
);
615 tcg_gen_trunc_i64_i32(d
, t0
);
616 tcg_gen_shri_i64(t0
, t0
, 32);
617 tcg_gen_trunc_i64_i32(d2
, t0
);
619 tcg_temp_free_i64(t0
);
620 tcg_temp_free_i64(t1
);
623 /* Multiplier unit. */
624 static void dec_mul(DisasContext
*dc
)
627 unsigned int subcode
;
629 if ((dc
->tb_flags
& MSR_EE_FLAG
)
630 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
631 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_HW_MUL_MASK
)) {
632 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
633 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
637 subcode
= dc
->imm
& 3;
638 d
[0] = tcg_temp_new();
639 d
[1] = tcg_temp_new();
642 LOG_DIS("muli r%d r%d %x\n", dc
->rd
, dc
->ra
, dc
->imm
);
643 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
647 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
648 if (subcode
>= 1 && subcode
<= 3
649 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_MUL64_MASK
))) {
655 LOG_DIS("mul r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
656 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
659 LOG_DIS("mulh r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
660 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
663 LOG_DIS("mulhsu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
664 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
667 LOG_DIS("mulhu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
668 t_gen_mulu(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
671 cpu_abort(dc
->env
, "unknown MUL insn %x\n", subcode
);
680 static void dec_div(DisasContext
*dc
)
687 if ((dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
688 && !((dc
->env
->pvr
.regs
[0] & PVR0_USE_DIV_MASK
))) {
689 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
690 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
694 gen_helper_divu(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
696 gen_helper_divs(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
698 tcg_gen_movi_tl(cpu_R
[dc
->rd
], 0);
701 static void dec_barrel(DisasContext
*dc
)
706 if ((dc
->tb_flags
& MSR_EE_FLAG
)
707 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
708 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_BARREL_MASK
)) {
709 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
710 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
714 s
= dc
->imm
& (1 << 10);
715 t
= dc
->imm
& (1 << 9);
717 LOG_DIS("bs%s%s r%d r%d r%d\n",
718 s
? "l" : "r", t
? "a" : "l", dc
->rd
, dc
->ra
, dc
->rb
);
722 tcg_gen_mov_tl(t0
, *(dec_alu_op_b(dc
)));
723 tcg_gen_andi_tl(t0
, t0
, 31);
726 tcg_gen_shl_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
729 tcg_gen_sar_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
731 tcg_gen_shr_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
735 static void dec_bit(DisasContext
*dc
)
739 int mem_index
= cpu_mmu_index(dc
->env
);
741 op
= dc
->ir
& ((1 << 8) - 1);
747 LOG_DIS("src r%d r%d\n", dc
->rd
, dc
->ra
);
748 tcg_gen_andi_tl(t0
, cpu_R
[dc
->ra
], 1);
752 tcg_gen_shli_tl(t1
, t1
, 31);
754 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
755 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], t1
);
768 LOG_DIS("srl r%d r%d\n", dc
->rd
, dc
->ra
);
771 tcg_gen_andi_tl(t0
, cpu_R
[dc
->ra
], 1);
776 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
778 tcg_gen_sari_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
782 LOG_DIS("ext8s r%d r%d\n", dc
->rd
, dc
->ra
);
783 tcg_gen_ext8s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
786 LOG_DIS("ext16s r%d r%d\n", dc
->rd
, dc
->ra
);
787 tcg_gen_ext16s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
794 LOG_DIS("wdc r%d\n", dc
->ra
);
795 if ((dc
->tb_flags
& MSR_EE_FLAG
)
796 && mem_index
== MMU_USER_IDX
) {
797 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
798 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
804 LOG_DIS("wic r%d\n", dc
->ra
);
805 if ((dc
->tb_flags
& MSR_EE_FLAG
)
806 && mem_index
== MMU_USER_IDX
) {
807 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
808 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
813 if ((dc
->tb_flags
& MSR_EE_FLAG
)
814 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
815 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
))) {
816 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
817 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
819 if (dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
) {
820 gen_helper_clz(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
824 cpu_abort(dc
->env
, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
825 dc
->pc
, op
, dc
->rd
, dc
->ra
, dc
->rb
);
830 static inline void sync_jmpstate(DisasContext
*dc
)
832 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
833 if (dc
->jmp
== JMP_DIRECT
) {
834 tcg_gen_movi_tl(env_btaken
, 1);
836 dc
->jmp
= JMP_INDIRECT
;
837 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
841 static void dec_imm(DisasContext
*dc
)
843 LOG_DIS("imm %x\n", dc
->imm
<< 16);
844 tcg_gen_movi_tl(env_imm
, (dc
->imm
<< 16));
845 dc
->tb_flags
|= IMM_FLAG
;
849 static inline void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
852 int mem_index
= cpu_mmu_index(dc
->env
);
855 tcg_gen_qemu_ld8u(dst
, addr
, mem_index
);
856 } else if (size
== 2) {
857 tcg_gen_qemu_ld16u(dst
, addr
, mem_index
);
858 } else if (size
== 4) {
859 tcg_gen_qemu_ld32u(dst
, addr
, mem_index
);
861 cpu_abort(dc
->env
, "Incorrect load size %d\n", size
);
864 static inline TCGv
*compute_ldst_addr(DisasContext
*dc
, TCGv
*t
)
866 unsigned int extimm
= dc
->tb_flags
& IMM_FLAG
;
868 /* Treat the common cases first. */
870 /* If any of the regs is r0, return a ptr to the other. */
872 return &cpu_R
[dc
->rb
];
873 } else if (dc
->rb
== 0) {
874 return &cpu_R
[dc
->ra
];
878 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
884 return &cpu_R
[dc
->ra
];
887 tcg_gen_movi_tl(*t
, (int32_t)((int16_t)dc
->imm
));
888 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *t
);
891 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
897 static inline void dec_byteswap(DisasContext
*dc
, TCGv dst
, TCGv src
, int size
)
900 tcg_gen_bswap32_tl(dst
, src
);
901 } else if (size
== 2) {
902 TCGv t
= tcg_temp_new();
904 /* bswap16 assumes the high bits are zero. */
905 tcg_gen_andi_tl(t
, src
, 0xffff);
906 tcg_gen_bswap16_tl(dst
, t
);
910 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
915 static void dec_load(DisasContext
*dc
)
918 unsigned int size
, rev
= 0;
920 size
= 1 << (dc
->opcode
& 3);
923 rev
= (dc
->ir
>> 9) & 1;
926 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
927 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
928 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
929 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
933 LOG_DIS("l%d%s%s\n", size
, dc
->type_b
? "i" : "", rev
? "r" : "");
936 addr
= compute_ldst_addr(dc
, &t
);
939 * When doing reverse accesses we need to do two things.
941 * 1. Reverse the address wrt endianness.
942 * 2. Byteswap the data lanes on the way back into the CPU core.
944 if (rev
&& size
!= 4) {
945 /* Endian reverse the address. t is addr. */
953 TCGv low
= tcg_temp_new();
955 /* Force addr into the temp. */
958 tcg_gen_mov_tl(t
, *addr
);
962 tcg_gen_andi_tl(low
, t
, 3);
963 tcg_gen_sub_tl(low
, tcg_const_tl(3), low
);
964 tcg_gen_andi_tl(t
, t
, ~3);
965 tcg_gen_or_tl(t
, t
, low
);
966 tcg_gen_mov_tl(env_imm
, t
);
974 /* Force addr into the temp. */
977 tcg_gen_xori_tl(t
, *addr
, 2);
980 tcg_gen_xori_tl(t
, t
, 2);
984 cpu_abort(dc
->env
, "Invalid reverse size\n");
989 /* If we get a fault on a dslot, the jmpstate better be in sync. */
992 /* Verify alignment if needed. */
993 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
994 TCGv v
= tcg_temp_new();
997 * Microblaze gives MMU faults priority over faults due to
998 * unaligned addresses. That's why we speculatively do the load
999 * into v. If the load succeeds, we verify alignment of the
1000 * address and if that succeeds we write into the destination reg.
1002 gen_load(dc
, v
, *addr
, size
);
1004 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1005 gen_helper_memalign(*addr
, tcg_const_tl(dc
->rd
),
1006 tcg_const_tl(0), tcg_const_tl(size
- 1));
1009 dec_byteswap(dc
, cpu_R
[dc
->rd
], v
, size
);
1011 tcg_gen_mov_tl(cpu_R
[dc
->rd
], v
);
1017 gen_load(dc
, cpu_R
[dc
->rd
], *addr
, size
);
1019 dec_byteswap(dc
, cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], size
);
1022 /* We are loading into r0, no need to reverse. */
1023 gen_load(dc
, env_imm
, *addr
, size
);
1031 static void gen_store(DisasContext
*dc
, TCGv addr
, TCGv val
,
1034 int mem_index
= cpu_mmu_index(dc
->env
);
1037 tcg_gen_qemu_st8(val
, addr
, mem_index
);
1038 else if (size
== 2) {
1039 tcg_gen_qemu_st16(val
, addr
, mem_index
);
1040 } else if (size
== 4) {
1041 tcg_gen_qemu_st32(val
, addr
, mem_index
);
1043 cpu_abort(dc
->env
, "Incorrect store size %d\n", size
);
1046 static void dec_store(DisasContext
*dc
)
1049 unsigned int size
, rev
= 0;
1051 size
= 1 << (dc
->opcode
& 3);
1053 rev
= (dc
->ir
>> 9) & 1;
1056 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
1057 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
1058 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1059 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1063 LOG_DIS("s%d%s%s\n", size
, dc
->type_b
? "i" : "", rev
? "r" : "");
1065 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1067 addr
= compute_ldst_addr(dc
, &t
);
1069 if (rev
&& size
!= 4) {
1070 /* Endian reverse the address. t is addr. */
1078 TCGv low
= tcg_temp_new();
1080 /* Force addr into the temp. */
1083 tcg_gen_mov_tl(t
, *addr
);
1087 tcg_gen_andi_tl(low
, t
, 3);
1088 tcg_gen_sub_tl(low
, tcg_const_tl(3), low
);
1089 tcg_gen_andi_tl(t
, t
, ~3);
1090 tcg_gen_or_tl(t
, t
, low
);
1091 tcg_gen_mov_tl(env_imm
, t
);
1099 /* Force addr into the temp. */
1102 tcg_gen_xori_tl(t
, *addr
, 2);
1105 tcg_gen_xori_tl(t
, t
, 2);
1109 cpu_abort(dc
->env
, "Invalid reverse size\n");
1114 TCGv bs_data
= tcg_temp_new();
1115 dec_byteswap(dc
, bs_data
, cpu_R
[dc
->rd
], size
);
1116 gen_store(dc
, *addr
, bs_data
, size
);
1117 tcg_temp_free(bs_data
);
1119 gen_store(dc
, *addr
, cpu_R
[dc
->rd
], size
);
1123 TCGv bs_data
= tcg_temp_new();
1124 dec_byteswap(dc
, bs_data
, cpu_R
[dc
->rd
], size
);
1125 gen_store(dc
, *addr
, bs_data
, size
);
1126 tcg_temp_free(bs_data
);
1128 gen_store(dc
, *addr
, cpu_R
[dc
->rd
], size
);
1132 /* Verify alignment if needed. */
1133 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
1134 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1135 /* FIXME: if the alignment is wrong, we should restore the value
1136 * in memory. One possible way to achieve this is to probe
1137 * the MMU prior to the memaccess, thay way we could put
1138 * the alignment checks in between the probe and the mem
1141 gen_helper_memalign(*addr
, tcg_const_tl(dc
->rd
),
1142 tcg_const_tl(1), tcg_const_tl(size
- 1));
1149 static inline void eval_cc(DisasContext
*dc
, unsigned int cc
,
1150 TCGv d
, TCGv a
, TCGv b
)
1154 tcg_gen_setcond_tl(TCG_COND_EQ
, d
, a
, b
);
1157 tcg_gen_setcond_tl(TCG_COND_NE
, d
, a
, b
);
1160 tcg_gen_setcond_tl(TCG_COND_LT
, d
, a
, b
);
1163 tcg_gen_setcond_tl(TCG_COND_LE
, d
, a
, b
);
1166 tcg_gen_setcond_tl(TCG_COND_GE
, d
, a
, b
);
1169 tcg_gen_setcond_tl(TCG_COND_GT
, d
, a
, b
);
1172 cpu_abort(dc
->env
, "Unknown condition code %x.\n", cc
);
1177 static void eval_cond_jmp(DisasContext
*dc
, TCGv pc_true
, TCGv pc_false
)
1181 l1
= gen_new_label();
1182 /* Conditional jmp. */
1183 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_false
);
1184 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
1185 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_true
);
1189 static void dec_bcc(DisasContext
*dc
)
1194 cc
= EXTRACT_FIELD(dc
->ir
, 21, 23);
1195 dslot
= dc
->ir
& (1 << 25);
1196 LOG_DIS("bcc%s r%d %x\n", dslot
? "d" : "", dc
->ra
, dc
->imm
);
1198 dc
->delayed_branch
= 1;
1200 dc
->delayed_branch
= 2;
1201 dc
->tb_flags
|= D_FLAG
;
1202 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1203 cpu_env
, offsetof(CPUState
, bimm
));
1206 if (dec_alu_op_b_is_small_imm(dc
)) {
1207 int32_t offset
= (int32_t)((int16_t)dc
->imm
); /* sign-extend. */
1209 tcg_gen_movi_tl(env_btarget
, dc
->pc
+ offset
);
1210 dc
->jmp
= JMP_DIRECT_CC
;
1211 dc
->jmp_pc
= dc
->pc
+ offset
;
1213 dc
->jmp
= JMP_INDIRECT
;
1214 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
1215 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
1217 eval_cc(dc
, cc
, env_btaken
, cpu_R
[dc
->ra
], tcg_const_tl(0));
1220 static void dec_br(DisasContext
*dc
)
1222 unsigned int dslot
, link
, abs
;
1223 int mem_index
= cpu_mmu_index(dc
->env
);
1225 dslot
= dc
->ir
& (1 << 20);
1226 abs
= dc
->ir
& (1 << 19);
1227 link
= dc
->ir
& (1 << 18);
1228 LOG_DIS("br%s%s%s%s imm=%x\n",
1229 abs
? "a" : "", link
? "l" : "",
1230 dc
->type_b
? "i" : "", dslot
? "d" : "",
1233 dc
->delayed_branch
= 1;
1235 dc
->delayed_branch
= 2;
1236 dc
->tb_flags
|= D_FLAG
;
1237 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1238 cpu_env
, offsetof(CPUState
, bimm
));
1241 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
1243 dc
->jmp
= JMP_INDIRECT
;
1245 tcg_gen_movi_tl(env_btaken
, 1);
1246 tcg_gen_mov_tl(env_btarget
, *(dec_alu_op_b(dc
)));
1247 if (link
&& !dslot
) {
1248 if (!(dc
->tb_flags
& IMM_FLAG
) && (dc
->imm
== 8 || dc
->imm
== 0x18))
1249 t_gen_raise_exception(dc
, EXCP_BREAK
);
1251 if ((dc
->tb_flags
& MSR_EE_FLAG
) && mem_index
== MMU_USER_IDX
) {
1252 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1253 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1257 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1261 if (dec_alu_op_b_is_small_imm(dc
)) {
1262 dc
->jmp
= JMP_DIRECT
;
1263 dc
->jmp_pc
= dc
->pc
+ (int32_t)((int16_t)dc
->imm
);
1265 tcg_gen_movi_tl(env_btaken
, 1);
1266 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
1267 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
1272 static inline void do_rti(DisasContext
*dc
)
1275 t0
= tcg_temp_new();
1276 t1
= tcg_temp_new();
1277 tcg_gen_shri_tl(t0
, cpu_SR
[SR_MSR
], 1);
1278 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_IE
);
1279 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1281 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1282 tcg_gen_or_tl(t1
, t1
, t0
);
1286 dc
->tb_flags
&= ~DRTI_FLAG
;
1289 static inline void do_rtb(DisasContext
*dc
)
1292 t0
= tcg_temp_new();
1293 t1
= tcg_temp_new();
1294 tcg_gen_andi_tl(t1
, cpu_SR
[SR_MSR
], ~MSR_BIP
);
1295 tcg_gen_shri_tl(t0
, t1
, 1);
1296 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1298 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1299 tcg_gen_or_tl(t1
, t1
, t0
);
1303 dc
->tb_flags
&= ~DRTB_FLAG
;
1306 static inline void do_rte(DisasContext
*dc
)
1309 t0
= tcg_temp_new();
1310 t1
= tcg_temp_new();
1312 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_EE
);
1313 tcg_gen_andi_tl(t1
, t1
, ~MSR_EIP
);
1314 tcg_gen_shri_tl(t0
, t1
, 1);
1315 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1317 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1318 tcg_gen_or_tl(t1
, t1
, t0
);
1322 dc
->tb_flags
&= ~DRTE_FLAG
;
1325 static void dec_rts(DisasContext
*dc
)
1327 unsigned int b_bit
, i_bit
, e_bit
;
1328 int mem_index
= cpu_mmu_index(dc
->env
);
1330 i_bit
= dc
->ir
& (1 << 21);
1331 b_bit
= dc
->ir
& (1 << 22);
1332 e_bit
= dc
->ir
& (1 << 23);
1334 dc
->delayed_branch
= 2;
1335 dc
->tb_flags
|= D_FLAG
;
1336 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1337 cpu_env
, offsetof(CPUState
, bimm
));
1340 LOG_DIS("rtid ir=%x\n", dc
->ir
);
1341 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1342 && mem_index
== MMU_USER_IDX
) {
1343 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1344 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1346 dc
->tb_flags
|= DRTI_FLAG
;
1348 LOG_DIS("rtbd ir=%x\n", dc
->ir
);
1349 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1350 && mem_index
== MMU_USER_IDX
) {
1351 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1352 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1354 dc
->tb_flags
|= DRTB_FLAG
;
1356 LOG_DIS("rted ir=%x\n", dc
->ir
);
1357 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1358 && mem_index
== MMU_USER_IDX
) {
1359 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1360 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1362 dc
->tb_flags
|= DRTE_FLAG
;
1364 LOG_DIS("rts ir=%x\n", dc
->ir
);
1366 dc
->jmp
= JMP_INDIRECT
;
1367 tcg_gen_movi_tl(env_btaken
, 1);
1368 tcg_gen_add_tl(env_btarget
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
1371 static int dec_check_fpuv2(DisasContext
*dc
)
1375 r
= dc
->env
->pvr
.regs
[2] & PVR2_USE_FPU2_MASK
;
1377 if (!r
&& (dc
->tb_flags
& MSR_EE_FLAG
)) {
1378 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_FPU
);
1379 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1384 static void dec_fpu(DisasContext
*dc
)
1386 unsigned int fpu_insn
;
1388 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1389 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1390 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_FPU_MASK
))) {
1391 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1392 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1396 fpu_insn
= (dc
->ir
>> 7) & 7;
1400 gen_helper_fadd(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1404 gen_helper_frsub(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1408 gen_helper_fmul(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1412 gen_helper_fdiv(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1416 switch ((dc
->ir
>> 4) & 7) {
1418 gen_helper_fcmp_un(cpu_R
[dc
->rd
],
1419 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1422 gen_helper_fcmp_lt(cpu_R
[dc
->rd
],
1423 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1426 gen_helper_fcmp_eq(cpu_R
[dc
->rd
],
1427 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1430 gen_helper_fcmp_le(cpu_R
[dc
->rd
],
1431 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1434 gen_helper_fcmp_gt(cpu_R
[dc
->rd
],
1435 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1438 gen_helper_fcmp_ne(cpu_R
[dc
->rd
],
1439 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1442 gen_helper_fcmp_ge(cpu_R
[dc
->rd
],
1443 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1446 qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1447 fpu_insn
, dc
->pc
, dc
->opcode
);
1448 dc
->abort_at_next_insn
= 1;
1454 if (!dec_check_fpuv2(dc
)) {
1457 gen_helper_flt(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
1461 if (!dec_check_fpuv2(dc
)) {
1464 gen_helper_fint(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
1468 if (!dec_check_fpuv2(dc
)) {
1471 gen_helper_fsqrt(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
1475 qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1476 fpu_insn
, dc
->pc
, dc
->opcode
);
1477 dc
->abort_at_next_insn
= 1;
1482 static void dec_null(DisasContext
*dc
)
1484 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1485 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
1486 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1487 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1490 qemu_log ("unknown insn pc=%x opc=%x\n", dc
->pc
, dc
->opcode
);
1491 dc
->abort_at_next_insn
= 1;
1494 /* Insns connected to FSL or AXI stream attached devices. */
1495 static void dec_stream(DisasContext
*dc
)
1497 int mem_index
= cpu_mmu_index(dc
->env
);
1498 TCGv_i32 t_id
, t_ctrl
;
1501 LOG_DIS("%s%s imm=%x\n", dc
->rd
? "get" : "put",
1502 dc
->type_b
? "" : "d", dc
->imm
);
1504 if ((dc
->tb_flags
& MSR_EE_FLAG
) && (mem_index
== MMU_USER_IDX
)) {
1505 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1506 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1510 t_id
= tcg_temp_new();
1512 tcg_gen_movi_tl(t_id
, dc
->imm
& 0xf);
1513 ctrl
= dc
->imm
>> 10;
1515 tcg_gen_andi_tl(t_id
, cpu_R
[dc
->rb
], 0xf);
1516 ctrl
= dc
->imm
>> 5;
1519 t_ctrl
= tcg_const_tl(ctrl
);
1522 gen_helper_put(t_id
, t_ctrl
, cpu_R
[dc
->ra
]);
1524 gen_helper_get(cpu_R
[dc
->rd
], t_id
, t_ctrl
);
1526 tcg_temp_free(t_id
);
1527 tcg_temp_free(t_ctrl
);
1530 static struct decoder_info
{
1535 void (*dec
)(DisasContext
*dc
);
1543 {DEC_BARREL
, dec_barrel
},
1545 {DEC_ST
, dec_store
},
1554 {DEC_STREAM
, dec_stream
},
1558 static inline void decode(DisasContext
*dc
)
1563 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
1564 tcg_gen_debug_insn_start(dc
->pc
);
1566 dc
->ir
= ir
= ldl_code(dc
->pc
);
1567 LOG_DIS("%8.8x\t", dc
->ir
);
1572 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1573 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1574 && (dc
->env
->pvr
.regs
[2] & PVR2_OPCODE_0x0_ILL_MASK
)) {
1575 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1576 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1580 LOG_DIS("nr_nops=%d\t", dc
->nr_nops
);
1582 if (dc
->nr_nops
> 4)
1583 cpu_abort(dc
->env
, "fetching nop sequence\n");
1585 /* bit 2 seems to indicate insn type. */
1586 dc
->type_b
= ir
& (1 << 29);
1588 dc
->opcode
= EXTRACT_FIELD(ir
, 26, 31);
1589 dc
->rd
= EXTRACT_FIELD(ir
, 21, 25);
1590 dc
->ra
= EXTRACT_FIELD(ir
, 16, 20);
1591 dc
->rb
= EXTRACT_FIELD(ir
, 11, 15);
1592 dc
->imm
= EXTRACT_FIELD(ir
, 0, 15);
1594 /* Large switch for all insns. */
1595 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
1596 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
1603 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
1607 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1608 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1609 if (bp
->pc
== dc
->pc
) {
1610 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1611 dc
->is_jmp
= DISAS_UPDATE
;
1617 /* generate intermediate code for basic block 'tb'. */
1619 gen_intermediate_code_internal(CPUState
*env
, TranslationBlock
*tb
,
1622 uint16_t *gen_opc_end
;
1625 struct DisasContext ctx
;
1626 struct DisasContext
*dc
= &ctx
;
1627 uint32_t next_page_start
, org_flags
;
1632 qemu_log_try_set_file(stderr
);
1637 org_flags
= dc
->synced_flags
= dc
->tb_flags
= tb
->flags
;
1639 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1641 dc
->is_jmp
= DISAS_NEXT
;
1643 dc
->delayed_branch
= !!(dc
->tb_flags
& D_FLAG
);
1644 if (dc
->delayed_branch
) {
1645 dc
->jmp
= JMP_INDIRECT
;
1648 dc
->singlestep_enabled
= env
->singlestep_enabled
;
1649 dc
->cpustate_changed
= 0;
1650 dc
->abort_at_next_insn
= 0;
1654 cpu_abort(env
, "Microblaze: unaligned PC=%x\n", pc_start
);
1656 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1658 qemu_log("--------------\n");
1659 log_cpu_state(env
, 0);
1663 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1666 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1668 max_insns
= CF_COUNT_MASK
;
1674 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1675 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1679 check_breakpoint(env
, dc
);
1682 j
= gen_opc_ptr
- gen_opc_buf
;
1686 gen_opc_instr_start
[lj
++] = 0;
1688 gen_opc_pc
[lj
] = dc
->pc
;
1689 gen_opc_instr_start
[lj
] = 1;
1690 gen_opc_icount
[lj
] = num_insns
;
1694 LOG_DIS("%8.8x:\t", dc
->pc
);
1696 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
1702 dc
->tb_flags
&= ~IMM_FLAG
;
1706 if (dc
->delayed_branch
) {
1707 dc
->delayed_branch
--;
1708 if (!dc
->delayed_branch
) {
1709 if (dc
->tb_flags
& DRTI_FLAG
)
1711 if (dc
->tb_flags
& DRTB_FLAG
)
1713 if (dc
->tb_flags
& DRTE_FLAG
)
1715 /* Clear the delay slot flag. */
1716 dc
->tb_flags
&= ~D_FLAG
;
1717 /* If it is a direct jump, try direct chaining. */
1718 if (dc
->jmp
== JMP_INDIRECT
) {
1719 eval_cond_jmp(dc
, env_btarget
, tcg_const_tl(dc
->pc
));
1720 dc
->is_jmp
= DISAS_JUMP
;
1721 } else if (dc
->jmp
== JMP_DIRECT
) {
1723 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
1724 dc
->is_jmp
= DISAS_TB_JUMP
;
1725 } else if (dc
->jmp
== JMP_DIRECT_CC
) {
1729 l1
= gen_new_label();
1730 /* Conditional jmp. */
1731 tcg_gen_brcondi_tl(TCG_COND_NE
, env_btaken
, 0, l1
);
1732 gen_goto_tb(dc
, 1, dc
->pc
);
1734 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
1736 dc
->is_jmp
= DISAS_TB_JUMP
;
1741 if (env
->singlestep_enabled
)
1743 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
1744 && gen_opc_ptr
< gen_opc_end
1746 && (dc
->pc
< next_page_start
)
1747 && num_insns
< max_insns
);
1750 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
1751 if (dc
->tb_flags
& D_FLAG
) {
1752 dc
->is_jmp
= DISAS_UPDATE
;
1753 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1759 if (tb
->cflags
& CF_LAST_IO
)
1761 /* Force an update if the per-tb cpu state has changed. */
1762 if (dc
->is_jmp
== DISAS_NEXT
1763 && (dc
->cpustate_changed
|| org_flags
!= dc
->tb_flags
)) {
1764 dc
->is_jmp
= DISAS_UPDATE
;
1765 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1769 if (unlikely(env
->singlestep_enabled
)) {
1770 TCGv_i32 tmp
= tcg_const_i32(EXCP_DEBUG
);
1772 if (dc
->is_jmp
!= DISAS_JUMP
) {
1773 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1775 gen_helper_raise_exception(tmp
);
1776 tcg_temp_free_i32(tmp
);
1778 switch(dc
->is_jmp
) {
1780 gen_goto_tb(dc
, 1, npc
);
1785 /* indicate that the hash table must be used
1786 to find the next TB */
1790 /* nothing more to generate */
1794 gen_icount_end(tb
, num_insns
);
1795 *gen_opc_ptr
= INDEX_op_end
;
1797 j
= gen_opc_ptr
- gen_opc_buf
;
1800 gen_opc_instr_start
[lj
++] = 0;
1802 tb
->size
= dc
->pc
- pc_start
;
1803 tb
->icount
= num_insns
;
1808 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1811 log_target_disas(pc_start
, dc
->pc
- pc_start
, 0);
1813 qemu_log("\nisize=%d osize=%td\n",
1814 dc
->pc
- pc_start
, gen_opc_ptr
- gen_opc_buf
);
1818 assert(!dc
->abort_at_next_insn
);
1821 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
1823 gen_intermediate_code_internal(env
, tb
, 0);
1826 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
1828 gen_intermediate_code_internal(env
, tb
, 1);
1831 void cpu_dump_state (CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
1839 cpu_fprintf(f
, "IN: PC=%x %s\n",
1840 env
->sregs
[SR_PC
], lookup_symbol(env
->sregs
[SR_PC
]));
1841 cpu_fprintf(f
, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1842 env
->sregs
[SR_MSR
], env
->sregs
[SR_ESR
], env
->sregs
[SR_EAR
],
1843 env
->debug
, env
->imm
, env
->iflags
, env
->sregs
[SR_FSR
]);
1844 cpu_fprintf(f
, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1845 env
->btaken
, env
->btarget
,
1846 (env
->sregs
[SR_MSR
] & MSR_UM
) ? "user" : "kernel",
1847 (env
->sregs
[SR_MSR
] & MSR_UMS
) ? "user" : "kernel",
1848 (env
->sregs
[SR_MSR
] & MSR_EIP
),
1849 (env
->sregs
[SR_MSR
] & MSR_IE
));
1851 for (i
= 0; i
< 32; i
++) {
1852 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
1853 if ((i
+ 1) % 4 == 0)
1854 cpu_fprintf(f
, "\n");
1856 cpu_fprintf(f
, "\n\n");
1859 CPUState
*cpu_mb_init (const char *cpu_model
)
1862 static int tcg_initialized
= 0;
1865 env
= g_malloc0(sizeof(CPUState
));
1869 qemu_init_vcpu(env
);
1870 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
1872 if (tcg_initialized
)
1875 tcg_initialized
= 1;
1877 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
1879 env_debug
= tcg_global_mem_new(TCG_AREG0
,
1880 offsetof(CPUState
, debug
),
1882 env_iflags
= tcg_global_mem_new(TCG_AREG0
,
1883 offsetof(CPUState
, iflags
),
1885 env_imm
= tcg_global_mem_new(TCG_AREG0
,
1886 offsetof(CPUState
, imm
),
1888 env_btarget
= tcg_global_mem_new(TCG_AREG0
,
1889 offsetof(CPUState
, btarget
),
1891 env_btaken
= tcg_global_mem_new(TCG_AREG0
,
1892 offsetof(CPUState
, btaken
),
1894 for (i
= 0; i
< ARRAY_SIZE(cpu_R
); i
++) {
1895 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
1896 offsetof(CPUState
, regs
[i
]),
1899 for (i
= 0; i
< ARRAY_SIZE(cpu_SR
); i
++) {
1900 cpu_SR
[i
] = tcg_global_mem_new(TCG_AREG0
,
1901 offsetof(CPUState
, sregs
[i
]),
1902 special_regnames
[i
]);
1904 #define GEN_HELPER 2
1910 void cpu_reset (CPUState
*env
)
1912 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1913 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1914 log_cpu_state(env
, 0);
1917 memset(env
, 0, offsetof(CPUMBState
, breakpoints
));
1920 env
->pvr
.regs
[0] = PVR0_PVR_FULL_MASK \
1921 | PVR0_USE_BARREL_MASK \
1922 | PVR0_USE_DIV_MASK \
1923 | PVR0_USE_HW_MUL_MASK \
1924 | PVR0_USE_EXC_MASK \
1925 | PVR0_USE_ICACHE_MASK \
1926 | PVR0_USE_DCACHE_MASK \
1929 env
->pvr
.regs
[2] = PVR2_D_OPB_MASK \
1933 | PVR2_USE_MSR_INSTR \
1934 | PVR2_USE_PCMP_INSTR \
1935 | PVR2_USE_BARREL_MASK \
1936 | PVR2_USE_DIV_MASK \
1937 | PVR2_USE_HW_MUL_MASK \
1938 | PVR2_USE_MUL64_MASK \
1939 | PVR2_USE_FPU_MASK \
1940 | PVR2_USE_FPU2_MASK \
1941 | PVR2_FPU_EXC_MASK \
1943 env
->pvr
.regs
[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1944 env
->pvr
.regs
[11] = PVR11_USE_MMU
| (16 << 17);
1946 #if defined(CONFIG_USER_ONLY)
1947 /* start in user mode with interrupts enabled. */
1948 env
->sregs
[SR_MSR
] = MSR_EE
| MSR_IE
| MSR_VM
| MSR_UM
;
1949 env
->pvr
.regs
[10] = 0x0c000000; /* Spartan 3a dsp. */
1951 env
->sregs
[SR_MSR
] = 0;
1952 mmu_init(&env
->mmu
);
1954 env
->mmu
.c_mmu_tlb_access
= 3;
1955 env
->mmu
.c_mmu_zones
= 16;
1959 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
1961 env
->sregs
[SR_PC
] = gen_opc_pc
[pc_pos
];