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microblaze: Emulate the hw stackprotector
[mirror_qemu.git] / target-microblaze / translate.c
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <assert.h>
26
27 #include "cpu.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "helper.h"
31 #include "microblaze-decode.h"
32 #include "qemu-common.h"
33
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 #define SIM_COMPAT 0
38 #define DISAS_GNU 1
39 #define DISAS_MB 1
40 #if DISAS_MB && !SIM_COMPAT
41 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
42 #else
43 # define LOG_DIS(...) do { } while (0)
44 #endif
45
46 #define D(x)
47
48 #define EXTRACT_FIELD(src, start, end) \
49 (((src) >> start) & ((1 << (end - start + 1)) - 1))
50
51 static TCGv env_debug;
52 static TCGv_ptr cpu_env;
53 static TCGv cpu_R[32];
54 static TCGv cpu_SR[18];
55 static TCGv env_imm;
56 static TCGv env_btaken;
57 static TCGv env_btarget;
58 static TCGv env_iflags;
59
60 #include "gen-icount.h"
61
62 /* This is the state at translation time. */
63 typedef struct DisasContext {
64 CPUState *env;
65 target_ulong pc;
66
67 /* Decoder. */
68 int type_b;
69 uint32_t ir;
70 uint8_t opcode;
71 uint8_t rd, ra, rb;
72 uint16_t imm;
73
74 unsigned int cpustate_changed;
75 unsigned int delayed_branch;
76 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
77 unsigned int clear_imm;
78 int is_jmp;
79
80 #define JMP_NOJMP 0
81 #define JMP_DIRECT 1
82 #define JMP_DIRECT_CC 2
83 #define JMP_INDIRECT 3
84 unsigned int jmp;
85 uint32_t jmp_pc;
86
87 int abort_at_next_insn;
88 int nr_nops;
89 struct TranslationBlock *tb;
90 int singlestep_enabled;
91 } DisasContext;
92
93 static const char *regnames[] =
94 {
95 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
96 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
97 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
98 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
99 };
100
101 static const char *special_regnames[] =
102 {
103 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
104 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
105 "sr16", "sr17", "sr18"
106 };
107
108 /* Sign extend at translation time. */
109 static inline int sign_extend(unsigned int val, unsigned int width)
110 {
111 int sval;
112
113 /* LSL. */
114 val <<= 31 - width;
115 sval = val;
116 /* ASR. */
117 sval >>= 31 - width;
118 return sval;
119 }
120
121 static inline void t_sync_flags(DisasContext *dc)
122 {
123 /* Synch the tb dependent flags between translator and runtime. */
124 if (dc->tb_flags != dc->synced_flags) {
125 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
126 dc->synced_flags = dc->tb_flags;
127 }
128 }
129
130 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
131 {
132 TCGv_i32 tmp = tcg_const_i32(index);
133
134 t_sync_flags(dc);
135 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
136 gen_helper_raise_exception(tmp);
137 tcg_temp_free_i32(tmp);
138 dc->is_jmp = DISAS_UPDATE;
139 }
140
141 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
142 {
143 TranslationBlock *tb;
144 tb = dc->tb;
145 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
146 tcg_gen_goto_tb(n);
147 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
148 tcg_gen_exit_tb((tcg_target_long)tb + n);
149 } else {
150 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
151 tcg_gen_exit_tb(0);
152 }
153 }
154
155 static void read_carry(DisasContext *dc, TCGv d)
156 {
157 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
158 }
159
160 static void write_carry(DisasContext *dc, TCGv v)
161 {
162 TCGv t0 = tcg_temp_new();
163 tcg_gen_shli_tl(t0, v, 31);
164 tcg_gen_sari_tl(t0, t0, 31);
165 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
166 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
167 ~(MSR_C | MSR_CC));
168 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
169 tcg_temp_free(t0);
170 }
171
172 /* True if ALU operand b is a small immediate that may deserve
173 faster treatment. */
174 static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
175 {
176 /* Immediate insn without the imm prefix ? */
177 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
178 }
179
180 static inline TCGv *dec_alu_op_b(DisasContext *dc)
181 {
182 if (dc->type_b) {
183 if (dc->tb_flags & IMM_FLAG)
184 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
185 else
186 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
187 return &env_imm;
188 } else
189 return &cpu_R[dc->rb];
190 }
191
192 static void dec_add(DisasContext *dc)
193 {
194 unsigned int k, c;
195 TCGv cf;
196
197 k = dc->opcode & 4;
198 c = dc->opcode & 2;
199
200 LOG_DIS("add%s%s%s r%d r%d r%d\n",
201 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
202 dc->rd, dc->ra, dc->rb);
203
204 /* Take care of the easy cases first. */
205 if (k) {
206 /* k - keep carry, no need to update MSR. */
207 /* If rd == r0, it's a nop. */
208 if (dc->rd) {
209 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
210
211 if (c) {
212 /* c - Add carry into the result. */
213 cf = tcg_temp_new();
214
215 read_carry(dc, cf);
216 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
217 tcg_temp_free(cf);
218 }
219 }
220 return;
221 }
222
223 /* From now on, we can assume k is zero. So we need to update MSR. */
224 /* Extract carry. */
225 cf = tcg_temp_new();
226 if (c) {
227 read_carry(dc, cf);
228 } else {
229 tcg_gen_movi_tl(cf, 0);
230 }
231
232 if (dc->rd) {
233 TCGv ncf = tcg_temp_new();
234 gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
235 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
236 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
237 write_carry(dc, ncf);
238 tcg_temp_free(ncf);
239 } else {
240 gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
241 write_carry(dc, cf);
242 }
243 tcg_temp_free(cf);
244 }
245
246 static void dec_sub(DisasContext *dc)
247 {
248 unsigned int u, cmp, k, c;
249 TCGv cf, na;
250
251 u = dc->imm & 2;
252 k = dc->opcode & 4;
253 c = dc->opcode & 2;
254 cmp = (dc->imm & 1) && (!dc->type_b) && k;
255
256 if (cmp) {
257 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
258 if (dc->rd) {
259 if (u)
260 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
261 else
262 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
263 }
264 return;
265 }
266
267 LOG_DIS("sub%s%s r%d, r%d r%d\n",
268 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
269
270 /* Take care of the easy cases first. */
271 if (k) {
272 /* k - keep carry, no need to update MSR. */
273 /* If rd == r0, it's a nop. */
274 if (dc->rd) {
275 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
276
277 if (c) {
278 /* c - Add carry into the result. */
279 cf = tcg_temp_new();
280
281 read_carry(dc, cf);
282 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
283 tcg_temp_free(cf);
284 }
285 }
286 return;
287 }
288
289 /* From now on, we can assume k is zero. So we need to update MSR. */
290 /* Extract carry. And complement a into na. */
291 cf = tcg_temp_new();
292 na = tcg_temp_new();
293 if (c) {
294 read_carry(dc, cf);
295 } else {
296 tcg_gen_movi_tl(cf, 1);
297 }
298
299 /* d = b + ~a + c. carry defaults to 1. */
300 tcg_gen_not_tl(na, cpu_R[dc->ra]);
301
302 if (dc->rd) {
303 TCGv ncf = tcg_temp_new();
304 gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
305 tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
306 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
307 write_carry(dc, ncf);
308 tcg_temp_free(ncf);
309 } else {
310 gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
311 write_carry(dc, cf);
312 }
313 tcg_temp_free(cf);
314 tcg_temp_free(na);
315 }
316
317 static void dec_pattern(DisasContext *dc)
318 {
319 unsigned int mode;
320 int l1;
321
322 if ((dc->tb_flags & MSR_EE_FLAG)
323 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
324 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
325 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
326 t_gen_raise_exception(dc, EXCP_HW_EXCP);
327 }
328
329 mode = dc->opcode & 3;
330 switch (mode) {
331 case 0:
332 /* pcmpbf. */
333 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
334 if (dc->rd)
335 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
336 break;
337 case 2:
338 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
339 if (dc->rd) {
340 TCGv t0 = tcg_temp_local_new();
341 l1 = gen_new_label();
342 tcg_gen_movi_tl(t0, 1);
343 tcg_gen_brcond_tl(TCG_COND_EQ,
344 cpu_R[dc->ra], cpu_R[dc->rb], l1);
345 tcg_gen_movi_tl(t0, 0);
346 gen_set_label(l1);
347 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
348 tcg_temp_free(t0);
349 }
350 break;
351 case 3:
352 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
353 l1 = gen_new_label();
354 if (dc->rd) {
355 TCGv t0 = tcg_temp_local_new();
356 tcg_gen_movi_tl(t0, 1);
357 tcg_gen_brcond_tl(TCG_COND_NE,
358 cpu_R[dc->ra], cpu_R[dc->rb], l1);
359 tcg_gen_movi_tl(t0, 0);
360 gen_set_label(l1);
361 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
362 tcg_temp_free(t0);
363 }
364 break;
365 default:
366 cpu_abort(dc->env,
367 "unsupported pattern insn opcode=%x\n", dc->opcode);
368 break;
369 }
370 }
371
372 static void dec_and(DisasContext *dc)
373 {
374 unsigned int not;
375
376 if (!dc->type_b && (dc->imm & (1 << 10))) {
377 dec_pattern(dc);
378 return;
379 }
380
381 not = dc->opcode & (1 << 1);
382 LOG_DIS("and%s\n", not ? "n" : "");
383
384 if (!dc->rd)
385 return;
386
387 if (not) {
388 TCGv t = tcg_temp_new();
389 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
390 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
391 tcg_temp_free(t);
392 } else
393 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
394 }
395
396 static void dec_or(DisasContext *dc)
397 {
398 if (!dc->type_b && (dc->imm & (1 << 10))) {
399 dec_pattern(dc);
400 return;
401 }
402
403 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
404 if (dc->rd)
405 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
406 }
407
408 static void dec_xor(DisasContext *dc)
409 {
410 if (!dc->type_b && (dc->imm & (1 << 10))) {
411 dec_pattern(dc);
412 return;
413 }
414
415 LOG_DIS("xor r%d\n", dc->rd);
416 if (dc->rd)
417 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
418 }
419
420 static inline void msr_read(DisasContext *dc, TCGv d)
421 {
422 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
423 }
424
425 static inline void msr_write(DisasContext *dc, TCGv v)
426 {
427 TCGv t;
428
429 t = tcg_temp_new();
430 dc->cpustate_changed = 1;
431 /* PVR bit is not writable. */
432 tcg_gen_andi_tl(t, v, ~MSR_PVR);
433 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
434 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
435 tcg_temp_free(t);
436 }
437
438 static void dec_msr(DisasContext *dc)
439 {
440 TCGv t0, t1;
441 unsigned int sr, to, rn;
442 int mem_index = cpu_mmu_index(dc->env);
443
444 sr = dc->imm & ((1 << 14) - 1);
445 to = dc->imm & (1 << 14);
446 dc->type_b = 1;
447 if (to)
448 dc->cpustate_changed = 1;
449
450 /* msrclr and msrset. */
451 if (!(dc->imm & (1 << 15))) {
452 unsigned int clr = dc->ir & (1 << 16);
453
454 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
455 dc->rd, dc->imm);
456
457 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
458 /* nop??? */
459 return;
460 }
461
462 if ((dc->tb_flags & MSR_EE_FLAG)
463 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
464 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
465 t_gen_raise_exception(dc, EXCP_HW_EXCP);
466 return;
467 }
468
469 if (dc->rd)
470 msr_read(dc, cpu_R[dc->rd]);
471
472 t0 = tcg_temp_new();
473 t1 = tcg_temp_new();
474 msr_read(dc, t0);
475 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
476
477 if (clr) {
478 tcg_gen_not_tl(t1, t1);
479 tcg_gen_and_tl(t0, t0, t1);
480 } else
481 tcg_gen_or_tl(t0, t0, t1);
482 msr_write(dc, t0);
483 tcg_temp_free(t0);
484 tcg_temp_free(t1);
485 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
486 dc->is_jmp = DISAS_UPDATE;
487 return;
488 }
489
490 if (to) {
491 if ((dc->tb_flags & MSR_EE_FLAG)
492 && mem_index == MMU_USER_IDX) {
493 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
494 t_gen_raise_exception(dc, EXCP_HW_EXCP);
495 return;
496 }
497 }
498
499 #if !defined(CONFIG_USER_ONLY)
500 /* Catch read/writes to the mmu block. */
501 if ((sr & ~0xff) == 0x1000) {
502 sr &= 7;
503 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
504 if (to)
505 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
506 else
507 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
508 return;
509 }
510 #endif
511
512 if (to) {
513 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
514 switch (sr) {
515 case 0:
516 break;
517 case 1:
518 msr_write(dc, cpu_R[dc->ra]);
519 break;
520 case 0x3:
521 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
522 break;
523 case 0x5:
524 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
525 break;
526 case 0x7:
527 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
528 break;
529 case 0x800:
530 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUState, slr));
531 break;
532 case 0x802:
533 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUState, shr));
534 break;
535 default:
536 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
537 break;
538 }
539 } else {
540 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
541
542 switch (sr) {
543 case 0:
544 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
545 break;
546 case 1:
547 msr_read(dc, cpu_R[dc->rd]);
548 break;
549 case 0x3:
550 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
551 break;
552 case 0x5:
553 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
554 break;
555 case 0x7:
556 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
557 break;
558 case 0xb:
559 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
560 break;
561 case 0x800:
562 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUState, slr));
563 break;
564 case 0x802:
565 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUState, shr));
566 break;
567 case 0x2000:
568 case 0x2001:
569 case 0x2002:
570 case 0x2003:
571 case 0x2004:
572 case 0x2005:
573 case 0x2006:
574 case 0x2007:
575 case 0x2008:
576 case 0x2009:
577 case 0x200a:
578 case 0x200b:
579 case 0x200c:
580 rn = sr & 0xf;
581 tcg_gen_ld_tl(cpu_R[dc->rd],
582 cpu_env, offsetof(CPUState, pvr.regs[rn]));
583 break;
584 default:
585 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
586 break;
587 }
588 }
589
590 if (dc->rd == 0) {
591 tcg_gen_movi_tl(cpu_R[0], 0);
592 }
593 }
594
595 /* 64-bit signed mul, lower result in d and upper in d2. */
596 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
597 {
598 TCGv_i64 t0, t1;
599
600 t0 = tcg_temp_new_i64();
601 t1 = tcg_temp_new_i64();
602
603 tcg_gen_ext_i32_i64(t0, a);
604 tcg_gen_ext_i32_i64(t1, b);
605 tcg_gen_mul_i64(t0, t0, t1);
606
607 tcg_gen_trunc_i64_i32(d, t0);
608 tcg_gen_shri_i64(t0, t0, 32);
609 tcg_gen_trunc_i64_i32(d2, t0);
610
611 tcg_temp_free_i64(t0);
612 tcg_temp_free_i64(t1);
613 }
614
615 /* 64-bit unsigned muls, lower result in d and upper in d2. */
616 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
617 {
618 TCGv_i64 t0, t1;
619
620 t0 = tcg_temp_new_i64();
621 t1 = tcg_temp_new_i64();
622
623 tcg_gen_extu_i32_i64(t0, a);
624 tcg_gen_extu_i32_i64(t1, b);
625 tcg_gen_mul_i64(t0, t0, t1);
626
627 tcg_gen_trunc_i64_i32(d, t0);
628 tcg_gen_shri_i64(t0, t0, 32);
629 tcg_gen_trunc_i64_i32(d2, t0);
630
631 tcg_temp_free_i64(t0);
632 tcg_temp_free_i64(t1);
633 }
634
635 /* Multiplier unit. */
636 static void dec_mul(DisasContext *dc)
637 {
638 TCGv d[2];
639 unsigned int subcode;
640
641 if ((dc->tb_flags & MSR_EE_FLAG)
642 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
643 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
644 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
645 t_gen_raise_exception(dc, EXCP_HW_EXCP);
646 return;
647 }
648
649 subcode = dc->imm & 3;
650 d[0] = tcg_temp_new();
651 d[1] = tcg_temp_new();
652
653 if (dc->type_b) {
654 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
655 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
656 goto done;
657 }
658
659 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
660 if (subcode >= 1 && subcode <= 3
661 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
662 /* nop??? */
663 }
664
665 switch (subcode) {
666 case 0:
667 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
668 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
669 break;
670 case 1:
671 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
672 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
673 break;
674 case 2:
675 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
676 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
677 break;
678 case 3:
679 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
680 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
681 break;
682 default:
683 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
684 break;
685 }
686 done:
687 tcg_temp_free(d[0]);
688 tcg_temp_free(d[1]);
689 }
690
691 /* Div unit. */
692 static void dec_div(DisasContext *dc)
693 {
694 unsigned int u;
695
696 u = dc->imm & 2;
697 LOG_DIS("div\n");
698
699 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
700 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
701 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
702 t_gen_raise_exception(dc, EXCP_HW_EXCP);
703 }
704
705 if (u)
706 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
707 else
708 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
709 if (!dc->rd)
710 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
711 }
712
713 static void dec_barrel(DisasContext *dc)
714 {
715 TCGv t0;
716 unsigned int s, t;
717
718 if ((dc->tb_flags & MSR_EE_FLAG)
719 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
720 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
721 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
722 t_gen_raise_exception(dc, EXCP_HW_EXCP);
723 return;
724 }
725
726 s = dc->imm & (1 << 10);
727 t = dc->imm & (1 << 9);
728
729 LOG_DIS("bs%s%s r%d r%d r%d\n",
730 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
731
732 t0 = tcg_temp_new();
733
734 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
735 tcg_gen_andi_tl(t0, t0, 31);
736
737 if (s)
738 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
739 else {
740 if (t)
741 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
742 else
743 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
744 }
745 }
746
747 static void dec_bit(DisasContext *dc)
748 {
749 TCGv t0, t1;
750 unsigned int op;
751 int mem_index = cpu_mmu_index(dc->env);
752
753 op = dc->ir & ((1 << 8) - 1);
754 switch (op) {
755 case 0x21:
756 /* src. */
757 t0 = tcg_temp_new();
758
759 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
760 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
761 if (dc->rd) {
762 t1 = tcg_temp_new();
763 read_carry(dc, t1);
764 tcg_gen_shli_tl(t1, t1, 31);
765
766 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
767 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
768 tcg_temp_free(t1);
769 }
770
771 /* Update carry. */
772 write_carry(dc, t0);
773 tcg_temp_free(t0);
774 break;
775
776 case 0x1:
777 case 0x41:
778 /* srl. */
779 t0 = tcg_temp_new();
780 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
781
782 /* Update carry. */
783 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
784 write_carry(dc, t0);
785 tcg_temp_free(t0);
786 if (dc->rd) {
787 if (op == 0x41)
788 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
789 else
790 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
791 }
792 break;
793 case 0x60:
794 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
795 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
796 break;
797 case 0x61:
798 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
799 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
800 break;
801 case 0x64:
802 case 0x66:
803 case 0x74:
804 case 0x76:
805 /* wdc. */
806 LOG_DIS("wdc r%d\n", dc->ra);
807 if ((dc->tb_flags & MSR_EE_FLAG)
808 && mem_index == MMU_USER_IDX) {
809 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
810 t_gen_raise_exception(dc, EXCP_HW_EXCP);
811 return;
812 }
813 break;
814 case 0x68:
815 /* wic. */
816 LOG_DIS("wic r%d\n", dc->ra);
817 if ((dc->tb_flags & MSR_EE_FLAG)
818 && mem_index == MMU_USER_IDX) {
819 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
820 t_gen_raise_exception(dc, EXCP_HW_EXCP);
821 return;
822 }
823 break;
824 case 0xe0:
825 if ((dc->tb_flags & MSR_EE_FLAG)
826 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
827 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
828 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
829 t_gen_raise_exception(dc, EXCP_HW_EXCP);
830 }
831 if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
832 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
833 }
834 break;
835 default:
836 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
837 dc->pc, op, dc->rd, dc->ra, dc->rb);
838 break;
839 }
840 }
841
842 static inline void sync_jmpstate(DisasContext *dc)
843 {
844 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
845 if (dc->jmp == JMP_DIRECT) {
846 tcg_gen_movi_tl(env_btaken, 1);
847 }
848 dc->jmp = JMP_INDIRECT;
849 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
850 }
851 }
852
853 static void dec_imm(DisasContext *dc)
854 {
855 LOG_DIS("imm %x\n", dc->imm << 16);
856 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
857 dc->tb_flags |= IMM_FLAG;
858 dc->clear_imm = 0;
859 }
860
861 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
862 unsigned int size)
863 {
864 int mem_index = cpu_mmu_index(dc->env);
865
866 if (size == 1) {
867 tcg_gen_qemu_ld8u(dst, addr, mem_index);
868 } else if (size == 2) {
869 tcg_gen_qemu_ld16u(dst, addr, mem_index);
870 } else if (size == 4) {
871 tcg_gen_qemu_ld32u(dst, addr, mem_index);
872 } else
873 cpu_abort(dc->env, "Incorrect load size %d\n", size);
874 }
875
876 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
877 {
878 unsigned int extimm = dc->tb_flags & IMM_FLAG;
879 /* Should be set to one if r1 is used by loadstores. */
880 int stackprot = 0;
881
882 /* All load/stores use ra. */
883 if (dc->ra == 1) {
884 stackprot = 1;
885 }
886
887 /* Treat the common cases first. */
888 if (!dc->type_b) {
889 /* If any of the regs is r0, return a ptr to the other. */
890 if (dc->ra == 0) {
891 return &cpu_R[dc->rb];
892 } else if (dc->rb == 0) {
893 return &cpu_R[dc->ra];
894 }
895
896 if (dc->rb == 1) {
897 stackprot = 1;
898 }
899
900 *t = tcg_temp_new();
901 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
902
903 if (stackprot) {
904 gen_helper_stackprot(*t);
905 }
906 return t;
907 }
908 /* Immediate. */
909 if (!extimm) {
910 if (dc->imm == 0) {
911 return &cpu_R[dc->ra];
912 }
913 *t = tcg_temp_new();
914 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
915 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
916 } else {
917 *t = tcg_temp_new();
918 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
919 }
920
921 if (stackprot) {
922 gen_helper_stackprot(*t);
923 }
924 return t;
925 }
926
927 static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
928 {
929 if (size == 4) {
930 tcg_gen_bswap32_tl(dst, src);
931 } else if (size == 2) {
932 TCGv t = tcg_temp_new();
933
934 /* bswap16 assumes the high bits are zero. */
935 tcg_gen_andi_tl(t, src, 0xffff);
936 tcg_gen_bswap16_tl(dst, t);
937 tcg_temp_free(t);
938 } else {
939 /* Ignore.
940 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
941 */
942 }
943 }
944
945 static void dec_load(DisasContext *dc)
946 {
947 TCGv t, *addr;
948 unsigned int size, rev = 0;
949
950 size = 1 << (dc->opcode & 3);
951
952 if (!dc->type_b) {
953 rev = (dc->ir >> 9) & 1;
954 }
955
956 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
957 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
958 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
959 t_gen_raise_exception(dc, EXCP_HW_EXCP);
960 return;
961 }
962
963 LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
964
965 t_sync_flags(dc);
966 addr = compute_ldst_addr(dc, &t);
967
968 /*
969 * When doing reverse accesses we need to do two things.
970 *
971 * 1. Reverse the address wrt endianness.
972 * 2. Byteswap the data lanes on the way back into the CPU core.
973 */
974 if (rev && size != 4) {
975 /* Endian reverse the address. t is addr. */
976 switch (size) {
977 case 1:
978 {
979 /* 00 -> 11
980 01 -> 10
981 10 -> 10
982 11 -> 00 */
983 TCGv low = tcg_temp_new();
984
985 /* Force addr into the temp. */
986 if (addr != &t) {
987 t = tcg_temp_new();
988 tcg_gen_mov_tl(t, *addr);
989 addr = &t;
990 }
991
992 tcg_gen_andi_tl(low, t, 3);
993 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
994 tcg_gen_andi_tl(t, t, ~3);
995 tcg_gen_or_tl(t, t, low);
996 tcg_gen_mov_tl(env_imm, t);
997 tcg_temp_free(low);
998 break;
999 }
1000
1001 case 2:
1002 /* 00 -> 10
1003 10 -> 00. */
1004 /* Force addr into the temp. */
1005 if (addr != &t) {
1006 t = tcg_temp_new();
1007 tcg_gen_xori_tl(t, *addr, 2);
1008 addr = &t;
1009 } else {
1010 tcg_gen_xori_tl(t, t, 2);
1011 }
1012 break;
1013 default:
1014 cpu_abort(dc->env, "Invalid reverse size\n");
1015 break;
1016 }
1017 }
1018
1019 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1020 sync_jmpstate(dc);
1021
1022 /* Verify alignment if needed. */
1023 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1024 TCGv v = tcg_temp_new();
1025
1026 /*
1027 * Microblaze gives MMU faults priority over faults due to
1028 * unaligned addresses. That's why we speculatively do the load
1029 * into v. If the load succeeds, we verify alignment of the
1030 * address and if that succeeds we write into the destination reg.
1031 */
1032 gen_load(dc, v, *addr, size);
1033
1034 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1035 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
1036 tcg_const_tl(0), tcg_const_tl(size - 1));
1037 if (dc->rd) {
1038 if (rev) {
1039 dec_byteswap(dc, cpu_R[dc->rd], v, size);
1040 } else {
1041 tcg_gen_mov_tl(cpu_R[dc->rd], v);
1042 }
1043 }
1044 tcg_temp_free(v);
1045 } else {
1046 if (dc->rd) {
1047 gen_load(dc, cpu_R[dc->rd], *addr, size);
1048 if (rev) {
1049 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1050 }
1051 } else {
1052 /* We are loading into r0, no need to reverse. */
1053 gen_load(dc, env_imm, *addr, size);
1054 }
1055 }
1056
1057 if (addr == &t)
1058 tcg_temp_free(t);
1059 }
1060
1061 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1062 unsigned int size)
1063 {
1064 int mem_index = cpu_mmu_index(dc->env);
1065
1066 if (size == 1)
1067 tcg_gen_qemu_st8(val, addr, mem_index);
1068 else if (size == 2) {
1069 tcg_gen_qemu_st16(val, addr, mem_index);
1070 } else if (size == 4) {
1071 tcg_gen_qemu_st32(val, addr, mem_index);
1072 } else
1073 cpu_abort(dc->env, "Incorrect store size %d\n", size);
1074 }
1075
1076 static void dec_store(DisasContext *dc)
1077 {
1078 TCGv t, *addr;
1079 unsigned int size, rev = 0;
1080
1081 size = 1 << (dc->opcode & 3);
1082 if (!dc->type_b) {
1083 rev = (dc->ir >> 9) & 1;
1084 }
1085
1086 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
1087 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1088 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1089 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1090 return;
1091 }
1092
1093 LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
1094 t_sync_flags(dc);
1095 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1096 sync_jmpstate(dc);
1097 addr = compute_ldst_addr(dc, &t);
1098
1099 if (rev && size != 4) {
1100 /* Endian reverse the address. t is addr. */
1101 switch (size) {
1102 case 1:
1103 {
1104 /* 00 -> 11
1105 01 -> 10
1106 10 -> 10
1107 11 -> 00 */
1108 TCGv low = tcg_temp_new();
1109
1110 /* Force addr into the temp. */
1111 if (addr != &t) {
1112 t = tcg_temp_new();
1113 tcg_gen_mov_tl(t, *addr);
1114 addr = &t;
1115 }
1116
1117 tcg_gen_andi_tl(low, t, 3);
1118 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1119 tcg_gen_andi_tl(t, t, ~3);
1120 tcg_gen_or_tl(t, t, low);
1121 tcg_gen_mov_tl(env_imm, t);
1122 tcg_temp_free(low);
1123 break;
1124 }
1125
1126 case 2:
1127 /* 00 -> 10
1128 10 -> 00. */
1129 /* Force addr into the temp. */
1130 if (addr != &t) {
1131 t = tcg_temp_new();
1132 tcg_gen_xori_tl(t, *addr, 2);
1133 addr = &t;
1134 } else {
1135 tcg_gen_xori_tl(t, t, 2);
1136 }
1137 break;
1138 default:
1139 cpu_abort(dc->env, "Invalid reverse size\n");
1140 break;
1141 }
1142
1143 if (size != 1) {
1144 TCGv bs_data = tcg_temp_new();
1145 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1146 gen_store(dc, *addr, bs_data, size);
1147 tcg_temp_free(bs_data);
1148 } else {
1149 gen_store(dc, *addr, cpu_R[dc->rd], size);
1150 }
1151 } else {
1152 if (rev) {
1153 TCGv bs_data = tcg_temp_new();
1154 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1155 gen_store(dc, *addr, bs_data, size);
1156 tcg_temp_free(bs_data);
1157 } else {
1158 gen_store(dc, *addr, cpu_R[dc->rd], size);
1159 }
1160 }
1161
1162 /* Verify alignment if needed. */
1163 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1164 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1165 /* FIXME: if the alignment is wrong, we should restore the value
1166 * in memory. One possible way to achieve this is to probe
1167 * the MMU prior to the memaccess, thay way we could put
1168 * the alignment checks in between the probe and the mem
1169 * access.
1170 */
1171 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
1172 tcg_const_tl(1), tcg_const_tl(size - 1));
1173 }
1174
1175 if (addr == &t)
1176 tcg_temp_free(t);
1177 }
1178
1179 static inline void eval_cc(DisasContext *dc, unsigned int cc,
1180 TCGv d, TCGv a, TCGv b)
1181 {
1182 switch (cc) {
1183 case CC_EQ:
1184 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
1185 break;
1186 case CC_NE:
1187 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
1188 break;
1189 case CC_LT:
1190 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
1191 break;
1192 case CC_LE:
1193 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
1194 break;
1195 case CC_GE:
1196 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
1197 break;
1198 case CC_GT:
1199 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
1200 break;
1201 default:
1202 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1203 break;
1204 }
1205 }
1206
1207 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1208 {
1209 int l1;
1210
1211 l1 = gen_new_label();
1212 /* Conditional jmp. */
1213 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1214 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1215 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1216 gen_set_label(l1);
1217 }
1218
1219 static void dec_bcc(DisasContext *dc)
1220 {
1221 unsigned int cc;
1222 unsigned int dslot;
1223
1224 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1225 dslot = dc->ir & (1 << 25);
1226 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1227
1228 dc->delayed_branch = 1;
1229 if (dslot) {
1230 dc->delayed_branch = 2;
1231 dc->tb_flags |= D_FLAG;
1232 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1233 cpu_env, offsetof(CPUState, bimm));
1234 }
1235
1236 if (dec_alu_op_b_is_small_imm(dc)) {
1237 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1238
1239 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
1240 dc->jmp = JMP_DIRECT_CC;
1241 dc->jmp_pc = dc->pc + offset;
1242 } else {
1243 dc->jmp = JMP_INDIRECT;
1244 tcg_gen_movi_tl(env_btarget, dc->pc);
1245 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1246 }
1247 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
1248 }
1249
1250 static void dec_br(DisasContext *dc)
1251 {
1252 unsigned int dslot, link, abs;
1253 int mem_index = cpu_mmu_index(dc->env);
1254
1255 dslot = dc->ir & (1 << 20);
1256 abs = dc->ir & (1 << 19);
1257 link = dc->ir & (1 << 18);
1258 LOG_DIS("br%s%s%s%s imm=%x\n",
1259 abs ? "a" : "", link ? "l" : "",
1260 dc->type_b ? "i" : "", dslot ? "d" : "",
1261 dc->imm);
1262
1263 dc->delayed_branch = 1;
1264 if (dslot) {
1265 dc->delayed_branch = 2;
1266 dc->tb_flags |= D_FLAG;
1267 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1268 cpu_env, offsetof(CPUState, bimm));
1269 }
1270 if (link && dc->rd)
1271 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1272
1273 dc->jmp = JMP_INDIRECT;
1274 if (abs) {
1275 tcg_gen_movi_tl(env_btaken, 1);
1276 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1277 if (link && !dslot) {
1278 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1279 t_gen_raise_exception(dc, EXCP_BREAK);
1280 if (dc->imm == 0) {
1281 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1282 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1283 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1284 return;
1285 }
1286
1287 t_gen_raise_exception(dc, EXCP_DEBUG);
1288 }
1289 }
1290 } else {
1291 if (dec_alu_op_b_is_small_imm(dc)) {
1292 dc->jmp = JMP_DIRECT;
1293 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1294 } else {
1295 tcg_gen_movi_tl(env_btaken, 1);
1296 tcg_gen_movi_tl(env_btarget, dc->pc);
1297 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1298 }
1299 }
1300 }
1301
1302 static inline void do_rti(DisasContext *dc)
1303 {
1304 TCGv t0, t1;
1305 t0 = tcg_temp_new();
1306 t1 = tcg_temp_new();
1307 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1308 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1309 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1310
1311 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1312 tcg_gen_or_tl(t1, t1, t0);
1313 msr_write(dc, t1);
1314 tcg_temp_free(t1);
1315 tcg_temp_free(t0);
1316 dc->tb_flags &= ~DRTI_FLAG;
1317 }
1318
1319 static inline void do_rtb(DisasContext *dc)
1320 {
1321 TCGv t0, t1;
1322 t0 = tcg_temp_new();
1323 t1 = tcg_temp_new();
1324 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1325 tcg_gen_shri_tl(t0, t1, 1);
1326 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1327
1328 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1329 tcg_gen_or_tl(t1, t1, t0);
1330 msr_write(dc, t1);
1331 tcg_temp_free(t1);
1332 tcg_temp_free(t0);
1333 dc->tb_flags &= ~DRTB_FLAG;
1334 }
1335
1336 static inline void do_rte(DisasContext *dc)
1337 {
1338 TCGv t0, t1;
1339 t0 = tcg_temp_new();
1340 t1 = tcg_temp_new();
1341
1342 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1343 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1344 tcg_gen_shri_tl(t0, t1, 1);
1345 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1346
1347 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1348 tcg_gen_or_tl(t1, t1, t0);
1349 msr_write(dc, t1);
1350 tcg_temp_free(t1);
1351 tcg_temp_free(t0);
1352 dc->tb_flags &= ~DRTE_FLAG;
1353 }
1354
1355 static void dec_rts(DisasContext *dc)
1356 {
1357 unsigned int b_bit, i_bit, e_bit;
1358 int mem_index = cpu_mmu_index(dc->env);
1359
1360 i_bit = dc->ir & (1 << 21);
1361 b_bit = dc->ir & (1 << 22);
1362 e_bit = dc->ir & (1 << 23);
1363
1364 dc->delayed_branch = 2;
1365 dc->tb_flags |= D_FLAG;
1366 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1367 cpu_env, offsetof(CPUState, bimm));
1368
1369 if (i_bit) {
1370 LOG_DIS("rtid ir=%x\n", dc->ir);
1371 if ((dc->tb_flags & MSR_EE_FLAG)
1372 && mem_index == MMU_USER_IDX) {
1373 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1374 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1375 }
1376 dc->tb_flags |= DRTI_FLAG;
1377 } else if (b_bit) {
1378 LOG_DIS("rtbd ir=%x\n", dc->ir);
1379 if ((dc->tb_flags & MSR_EE_FLAG)
1380 && mem_index == MMU_USER_IDX) {
1381 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1382 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1383 }
1384 dc->tb_flags |= DRTB_FLAG;
1385 } else if (e_bit) {
1386 LOG_DIS("rted ir=%x\n", dc->ir);
1387 if ((dc->tb_flags & MSR_EE_FLAG)
1388 && mem_index == MMU_USER_IDX) {
1389 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1390 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1391 }
1392 dc->tb_flags |= DRTE_FLAG;
1393 } else
1394 LOG_DIS("rts ir=%x\n", dc->ir);
1395
1396 dc->jmp = JMP_INDIRECT;
1397 tcg_gen_movi_tl(env_btaken, 1);
1398 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1399 }
1400
1401 static int dec_check_fpuv2(DisasContext *dc)
1402 {
1403 int r;
1404
1405 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1406
1407 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1408 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1409 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1410 }
1411 return r;
1412 }
1413
1414 static void dec_fpu(DisasContext *dc)
1415 {
1416 unsigned int fpu_insn;
1417
1418 if ((dc->tb_flags & MSR_EE_FLAG)
1419 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1420 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1421 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1422 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1423 return;
1424 }
1425
1426 fpu_insn = (dc->ir >> 7) & 7;
1427
1428 switch (fpu_insn) {
1429 case 0:
1430 gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1431 break;
1432
1433 case 1:
1434 gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1435 break;
1436
1437 case 2:
1438 gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1439 break;
1440
1441 case 3:
1442 gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1443 break;
1444
1445 case 4:
1446 switch ((dc->ir >> 4) & 7) {
1447 case 0:
1448 gen_helper_fcmp_un(cpu_R[dc->rd],
1449 cpu_R[dc->ra], cpu_R[dc->rb]);
1450 break;
1451 case 1:
1452 gen_helper_fcmp_lt(cpu_R[dc->rd],
1453 cpu_R[dc->ra], cpu_R[dc->rb]);
1454 break;
1455 case 2:
1456 gen_helper_fcmp_eq(cpu_R[dc->rd],
1457 cpu_R[dc->ra], cpu_R[dc->rb]);
1458 break;
1459 case 3:
1460 gen_helper_fcmp_le(cpu_R[dc->rd],
1461 cpu_R[dc->ra], cpu_R[dc->rb]);
1462 break;
1463 case 4:
1464 gen_helper_fcmp_gt(cpu_R[dc->rd],
1465 cpu_R[dc->ra], cpu_R[dc->rb]);
1466 break;
1467 case 5:
1468 gen_helper_fcmp_ne(cpu_R[dc->rd],
1469 cpu_R[dc->ra], cpu_R[dc->rb]);
1470 break;
1471 case 6:
1472 gen_helper_fcmp_ge(cpu_R[dc->rd],
1473 cpu_R[dc->ra], cpu_R[dc->rb]);
1474 break;
1475 default:
1476 qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1477 fpu_insn, dc->pc, dc->opcode);
1478 dc->abort_at_next_insn = 1;
1479 break;
1480 }
1481 break;
1482
1483 case 5:
1484 if (!dec_check_fpuv2(dc)) {
1485 return;
1486 }
1487 gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
1488 break;
1489
1490 case 6:
1491 if (!dec_check_fpuv2(dc)) {
1492 return;
1493 }
1494 gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
1495 break;
1496
1497 case 7:
1498 if (!dec_check_fpuv2(dc)) {
1499 return;
1500 }
1501 gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
1502 break;
1503
1504 default:
1505 qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1506 fpu_insn, dc->pc, dc->opcode);
1507 dc->abort_at_next_insn = 1;
1508 break;
1509 }
1510 }
1511
1512 static void dec_null(DisasContext *dc)
1513 {
1514 if ((dc->tb_flags & MSR_EE_FLAG)
1515 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1516 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1517 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1518 return;
1519 }
1520 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1521 dc->abort_at_next_insn = 1;
1522 }
1523
1524 /* Insns connected to FSL or AXI stream attached devices. */
1525 static void dec_stream(DisasContext *dc)
1526 {
1527 int mem_index = cpu_mmu_index(dc->env);
1528 TCGv_i32 t_id, t_ctrl;
1529 int ctrl;
1530
1531 LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1532 dc->type_b ? "" : "d", dc->imm);
1533
1534 if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1535 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1536 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1537 return;
1538 }
1539
1540 t_id = tcg_temp_new();
1541 if (dc->type_b) {
1542 tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1543 ctrl = dc->imm >> 10;
1544 } else {
1545 tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1546 ctrl = dc->imm >> 5;
1547 }
1548
1549 t_ctrl = tcg_const_tl(ctrl);
1550
1551 if (dc->rd == 0) {
1552 gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1553 } else {
1554 gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1555 }
1556 tcg_temp_free(t_id);
1557 tcg_temp_free(t_ctrl);
1558 }
1559
1560 static struct decoder_info {
1561 struct {
1562 uint32_t bits;
1563 uint32_t mask;
1564 };
1565 void (*dec)(DisasContext *dc);
1566 } decinfo[] = {
1567 {DEC_ADD, dec_add},
1568 {DEC_SUB, dec_sub},
1569 {DEC_AND, dec_and},
1570 {DEC_XOR, dec_xor},
1571 {DEC_OR, dec_or},
1572 {DEC_BIT, dec_bit},
1573 {DEC_BARREL, dec_barrel},
1574 {DEC_LD, dec_load},
1575 {DEC_ST, dec_store},
1576 {DEC_IMM, dec_imm},
1577 {DEC_BR, dec_br},
1578 {DEC_BCC, dec_bcc},
1579 {DEC_RTS, dec_rts},
1580 {DEC_FPU, dec_fpu},
1581 {DEC_MUL, dec_mul},
1582 {DEC_DIV, dec_div},
1583 {DEC_MSR, dec_msr},
1584 {DEC_STREAM, dec_stream},
1585 {{0, 0}, dec_null}
1586 };
1587
1588 static inline void decode(DisasContext *dc)
1589 {
1590 uint32_t ir;
1591 int i;
1592
1593 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1594 tcg_gen_debug_insn_start(dc->pc);
1595
1596 dc->ir = ir = ldl_code(dc->pc);
1597 LOG_DIS("%8.8x\t", dc->ir);
1598
1599 if (dc->ir)
1600 dc->nr_nops = 0;
1601 else {
1602 if ((dc->tb_flags & MSR_EE_FLAG)
1603 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1604 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1605 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1606 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1607 return;
1608 }
1609
1610 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1611 dc->nr_nops++;
1612 if (dc->nr_nops > 4)
1613 cpu_abort(dc->env, "fetching nop sequence\n");
1614 }
1615 /* bit 2 seems to indicate insn type. */
1616 dc->type_b = ir & (1 << 29);
1617
1618 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1619 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1620 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1621 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1622 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1623
1624 /* Large switch for all insns. */
1625 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1626 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1627 decinfo[i].dec(dc);
1628 break;
1629 }
1630 }
1631 }
1632
1633 static void check_breakpoint(CPUState *env, DisasContext *dc)
1634 {
1635 CPUBreakpoint *bp;
1636
1637 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1638 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1639 if (bp->pc == dc->pc) {
1640 t_gen_raise_exception(dc, EXCP_DEBUG);
1641 dc->is_jmp = DISAS_UPDATE;
1642 }
1643 }
1644 }
1645 }
1646
1647 /* generate intermediate code for basic block 'tb'. */
1648 static void
1649 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1650 int search_pc)
1651 {
1652 uint16_t *gen_opc_end;
1653 uint32_t pc_start;
1654 int j, lj;
1655 struct DisasContext ctx;
1656 struct DisasContext *dc = &ctx;
1657 uint32_t next_page_start, org_flags;
1658 target_ulong npc;
1659 int num_insns;
1660 int max_insns;
1661
1662 qemu_log_try_set_file(stderr);
1663
1664 pc_start = tb->pc;
1665 dc->env = env;
1666 dc->tb = tb;
1667 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1668
1669 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1670
1671 dc->is_jmp = DISAS_NEXT;
1672 dc->jmp = 0;
1673 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1674 if (dc->delayed_branch) {
1675 dc->jmp = JMP_INDIRECT;
1676 }
1677 dc->pc = pc_start;
1678 dc->singlestep_enabled = env->singlestep_enabled;
1679 dc->cpustate_changed = 0;
1680 dc->abort_at_next_insn = 0;
1681 dc->nr_nops = 0;
1682
1683 if (pc_start & 3)
1684 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1685
1686 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1687 #if !SIM_COMPAT
1688 qemu_log("--------------\n");
1689 log_cpu_state(env, 0);
1690 #endif
1691 }
1692
1693 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1694 lj = -1;
1695 num_insns = 0;
1696 max_insns = tb->cflags & CF_COUNT_MASK;
1697 if (max_insns == 0)
1698 max_insns = CF_COUNT_MASK;
1699
1700 gen_icount_start();
1701 do
1702 {
1703 #if SIM_COMPAT
1704 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1705 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1706 gen_helper_debug();
1707 }
1708 #endif
1709 check_breakpoint(env, dc);
1710
1711 if (search_pc) {
1712 j = gen_opc_ptr - gen_opc_buf;
1713 if (lj < j) {
1714 lj++;
1715 while (lj < j)
1716 gen_opc_instr_start[lj++] = 0;
1717 }
1718 gen_opc_pc[lj] = dc->pc;
1719 gen_opc_instr_start[lj] = 1;
1720 gen_opc_icount[lj] = num_insns;
1721 }
1722
1723 /* Pretty disas. */
1724 LOG_DIS("%8.8x:\t", dc->pc);
1725
1726 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1727 gen_io_start();
1728
1729 dc->clear_imm = 1;
1730 decode(dc);
1731 if (dc->clear_imm)
1732 dc->tb_flags &= ~IMM_FLAG;
1733 dc->pc += 4;
1734 num_insns++;
1735
1736 if (dc->delayed_branch) {
1737 dc->delayed_branch--;
1738 if (!dc->delayed_branch) {
1739 if (dc->tb_flags & DRTI_FLAG)
1740 do_rti(dc);
1741 if (dc->tb_flags & DRTB_FLAG)
1742 do_rtb(dc);
1743 if (dc->tb_flags & DRTE_FLAG)
1744 do_rte(dc);
1745 /* Clear the delay slot flag. */
1746 dc->tb_flags &= ~D_FLAG;
1747 /* If it is a direct jump, try direct chaining. */
1748 if (dc->jmp == JMP_INDIRECT) {
1749 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1750 dc->is_jmp = DISAS_JUMP;
1751 } else if (dc->jmp == JMP_DIRECT) {
1752 t_sync_flags(dc);
1753 gen_goto_tb(dc, 0, dc->jmp_pc);
1754 dc->is_jmp = DISAS_TB_JUMP;
1755 } else if (dc->jmp == JMP_DIRECT_CC) {
1756 int l1;
1757
1758 t_sync_flags(dc);
1759 l1 = gen_new_label();
1760 /* Conditional jmp. */
1761 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1762 gen_goto_tb(dc, 1, dc->pc);
1763 gen_set_label(l1);
1764 gen_goto_tb(dc, 0, dc->jmp_pc);
1765
1766 dc->is_jmp = DISAS_TB_JUMP;
1767 }
1768 break;
1769 }
1770 }
1771 if (env->singlestep_enabled)
1772 break;
1773 } while (!dc->is_jmp && !dc->cpustate_changed
1774 && gen_opc_ptr < gen_opc_end
1775 && !singlestep
1776 && (dc->pc < next_page_start)
1777 && num_insns < max_insns);
1778
1779 npc = dc->pc;
1780 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1781 if (dc->tb_flags & D_FLAG) {
1782 dc->is_jmp = DISAS_UPDATE;
1783 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1784 sync_jmpstate(dc);
1785 } else
1786 npc = dc->jmp_pc;
1787 }
1788
1789 if (tb->cflags & CF_LAST_IO)
1790 gen_io_end();
1791 /* Force an update if the per-tb cpu state has changed. */
1792 if (dc->is_jmp == DISAS_NEXT
1793 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1794 dc->is_jmp = DISAS_UPDATE;
1795 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1796 }
1797 t_sync_flags(dc);
1798
1799 if (unlikely(env->singlestep_enabled)) {
1800 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1801
1802 if (dc->is_jmp != DISAS_JUMP) {
1803 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1804 }
1805 gen_helper_raise_exception(tmp);
1806 tcg_temp_free_i32(tmp);
1807 } else {
1808 switch(dc->is_jmp) {
1809 case DISAS_NEXT:
1810 gen_goto_tb(dc, 1, npc);
1811 break;
1812 default:
1813 case DISAS_JUMP:
1814 case DISAS_UPDATE:
1815 /* indicate that the hash table must be used
1816 to find the next TB */
1817 tcg_gen_exit_tb(0);
1818 break;
1819 case DISAS_TB_JUMP:
1820 /* nothing more to generate */
1821 break;
1822 }
1823 }
1824 gen_icount_end(tb, num_insns);
1825 *gen_opc_ptr = INDEX_op_end;
1826 if (search_pc) {
1827 j = gen_opc_ptr - gen_opc_buf;
1828 lj++;
1829 while (lj <= j)
1830 gen_opc_instr_start[lj++] = 0;
1831 } else {
1832 tb->size = dc->pc - pc_start;
1833 tb->icount = num_insns;
1834 }
1835
1836 #ifdef DEBUG_DISAS
1837 #if !SIM_COMPAT
1838 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1839 qemu_log("\n");
1840 #if DISAS_GNU
1841 log_target_disas(pc_start, dc->pc - pc_start, 0);
1842 #endif
1843 qemu_log("\nisize=%d osize=%td\n",
1844 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1845 }
1846 #endif
1847 #endif
1848 assert(!dc->abort_at_next_insn);
1849 }
1850
1851 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1852 {
1853 gen_intermediate_code_internal(env, tb, 0);
1854 }
1855
1856 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1857 {
1858 gen_intermediate_code_internal(env, tb, 1);
1859 }
1860
1861 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1862 int flags)
1863 {
1864 int i;
1865
1866 if (!env || !f)
1867 return;
1868
1869 cpu_fprintf(f, "IN: PC=%x %s\n",
1870 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1871 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1872 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1873 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
1874 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1875 env->btaken, env->btarget,
1876 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1877 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1878 (env->sregs[SR_MSR] & MSR_EIP),
1879 (env->sregs[SR_MSR] & MSR_IE));
1880
1881 for (i = 0; i < 32; i++) {
1882 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1883 if ((i + 1) % 4 == 0)
1884 cpu_fprintf(f, "\n");
1885 }
1886 cpu_fprintf(f, "\n\n");
1887 }
1888
1889 CPUState *cpu_mb_init (const char *cpu_model)
1890 {
1891 CPUState *env;
1892 static int tcg_initialized = 0;
1893 int i;
1894
1895 env = g_malloc0(sizeof(CPUState));
1896
1897 cpu_exec_init(env);
1898 cpu_reset(env);
1899 qemu_init_vcpu(env);
1900 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1901
1902 if (tcg_initialized)
1903 return env;
1904
1905 tcg_initialized = 1;
1906
1907 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1908
1909 env_debug = tcg_global_mem_new(TCG_AREG0,
1910 offsetof(CPUState, debug),
1911 "debug0");
1912 env_iflags = tcg_global_mem_new(TCG_AREG0,
1913 offsetof(CPUState, iflags),
1914 "iflags");
1915 env_imm = tcg_global_mem_new(TCG_AREG0,
1916 offsetof(CPUState, imm),
1917 "imm");
1918 env_btarget = tcg_global_mem_new(TCG_AREG0,
1919 offsetof(CPUState, btarget),
1920 "btarget");
1921 env_btaken = tcg_global_mem_new(TCG_AREG0,
1922 offsetof(CPUState, btaken),
1923 "btaken");
1924 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1925 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1926 offsetof(CPUState, regs[i]),
1927 regnames[i]);
1928 }
1929 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1930 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1931 offsetof(CPUState, sregs[i]),
1932 special_regnames[i]);
1933 }
1934 #define GEN_HELPER 2
1935 #include "helper.h"
1936
1937 return env;
1938 }
1939
1940 void cpu_reset (CPUState *env)
1941 {
1942 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1943 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1944 log_cpu_state(env, 0);
1945 }
1946
1947 memset(env, 0, offsetof(CPUMBState, breakpoints));
1948 tlb_flush(env, 1);
1949
1950 /* Disable stack protector. */
1951 env->shr = ~0;
1952
1953 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1954 | PVR0_USE_BARREL_MASK \
1955 | PVR0_USE_DIV_MASK \
1956 | PVR0_USE_HW_MUL_MASK \
1957 | PVR0_USE_EXC_MASK \
1958 | PVR0_USE_ICACHE_MASK \
1959 | PVR0_USE_DCACHE_MASK \
1960 | PVR0_USE_MMU \
1961 | (0xb << 8);
1962 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1963 | PVR2_D_LMB_MASK \
1964 | PVR2_I_OPB_MASK \
1965 | PVR2_I_LMB_MASK \
1966 | PVR2_USE_MSR_INSTR \
1967 | PVR2_USE_PCMP_INSTR \
1968 | PVR2_USE_BARREL_MASK \
1969 | PVR2_USE_DIV_MASK \
1970 | PVR2_USE_HW_MUL_MASK \
1971 | PVR2_USE_MUL64_MASK \
1972 | PVR2_USE_FPU_MASK \
1973 | PVR2_USE_FPU2_MASK \
1974 | PVR2_FPU_EXC_MASK \
1975 | 0;
1976 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1977 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1978
1979 #if defined(CONFIG_USER_ONLY)
1980 /* start in user mode with interrupts enabled. */
1981 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
1982 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1983 #else
1984 env->sregs[SR_MSR] = 0;
1985 mmu_init(&env->mmu);
1986 env->mmu.c_mmu = 3;
1987 env->mmu.c_mmu_tlb_access = 3;
1988 env->mmu.c_mmu_zones = 16;
1989 #endif
1990 }
1991
1992 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
1993 {
1994 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1995 }
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