target-mips/TODO

   1 Unsolved issues/bugs in the mips/mipsel backend
   2 -----------------------------------------------
   3
   4 General
   5 -------
   6 - Unimplemented ASEs:
   7   - MIPS16
   8   - MDMX
   9   - SmartMIPS
  10   - DSP r1
  11   - DSP r2
  12 - MT ASE only partially implemented and not functional
  13 - Shadow register support only partially implemented,
  14   lacks set switching on interrupt/exception.
  15 - 34K ITC not implemented.
  16 - A general lack of documentation, especially for technical internals.
  17   Existing documentation is x86-centric.
  18 - Reverse endianness bit not implemented
  19 - The TLB emulation is very inefficient:
  20   Qemu's softmmu implements a x86-style MMU, with separate entries
  21   for read/write/execute, a TLB index which is just a modulo of the
  22   virtual address, and a set of TLBs for each user/kernel/supervisor
  23   MMU mode.
  24   MIPS has a single entry for read/write/execute and only one MMU mode.
  25   But it is fully associative with randomized entry indices, and uses
  26   up to 256 ASID tags as additional matching criterion (which roughly
  27   equates to 256 MMU modes). It also has a global flag which causes
  28   entries to match regardless of ASID.
  29   To cope with these differences, Qemu currently flushes the TLB at
  30   each ASID change. Using the MMU modes to implement ASIDs hinges on
  31   implementing the global bit efficiently.
  32 - save/restore of the CPU state is not implemented (see machine.c).
  33 - Improve cpu state handling:
  34   Step 1) Collect all the TC state in a single struct, so we need only
  35           a single global pointer per TC.
  36   Step 2) Use only a single TC context as working context, and copy the
  37           contexts on TC switch. Likewise for FPU contexts.
  38
  39 MIPS64
  40 ------
  41 - Userland emulation (both n32 and n64) not functional.
  42
  43 "Generic" 4Kc system emulation
  44 ------------------------------
  45 - Doesn't correspond to any real hardware.
  46
  47 PICA 61 system emulation
  48 ------------------------
  49 - No framebuffer support yet.
  50
  51 MALTA system emulation
  52 ----------------------
  53 - We fake firmware support instead of doing the real thing
  54 - Real firmware falls over when trying to init RAM, presumably due
  55   to lacking system controller emulation.
  56 - Bonito system controller not implemented
  57 - MSC1 system controller not implemented