target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 #define TARGET_HAS_ICE 1
   5
   6 #include "config.h"
   7 #include "mips-defs.h"
   8 #include "cpu-defs.h"
   9 #include "softfloat.h"
  10
  11 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
  12 // XXX: move that elsewhere
  13 #if defined(HOST_SOLARIS) && SOLARISREV < 10
  14 typedef unsigned char           uint_fast8_t;
  15 typedef unsigned int            uint_fast16_t;
  16 #endif
  17
  18 /* target_ulong size spec */
  19 #ifdef MIPS_HAS_MIPS64
  20 #define TLSZ "%016llx"
  21 #else
  22 #define TLSZ "%08x"
  23 #endif
  24
  25 typedef union fpr_t fpr_t;
  26 union fpr_t {
  27     float64  fd;   /* ieee double precision */
  28     float32  fs[2];/* ieee single precision */
  29     uint64_t d;    /* binary single fixed-point */
  30     uint32_t w[2]; /* binary single fixed-point */
  31 };
  32 /* define FP_ENDIAN_IDX to access the same location
  33  * in the fpr_t union regardless of the host endianess
  34  */
  35 #if defined(WORDS_BIGENDIAN)
  36 #  define FP_ENDIAN_IDX 1
  37 #else
  38 #  define FP_ENDIAN_IDX 0
  39 #endif
  40
  41 #if defined(MIPS_USES_R4K_TLB)
  42 typedef struct tlb_t tlb_t;
  43 struct tlb_t {
  44     target_ulong VPN;
  45     target_ulong end;
  46     target_ulong end2;
  47     uint_fast8_t ASID;
  48     uint_fast16_t G:1;
  49     uint_fast16_t C0:3;
  50     uint_fast16_t C1:3;
  51     uint_fast16_t V0:1;
  52     uint_fast16_t V1:1;
  53     uint_fast16_t D0:1;
  54     uint_fast16_t D1:1;
  55     target_ulong PFN[2];
  56 };
  57 #endif
  58
  59 typedef struct CPUMIPSState CPUMIPSState;
  60 struct CPUMIPSState {
  61     /* General integer registers */
  62     target_ulong gpr[32];
  63     /* Special registers */
  64     target_ulong PC;
  65 #if TARGET_LONG_BITS > HOST_LONG_BITS
  66     target_ulong t0;
  67     target_ulong t1;
  68     target_ulong t2;
  69 #endif
  70     target_ulong HI, LO;
  71     uint32_t DCR; /* ? */
  72 #if defined(MIPS_USES_FPU)
  73     /* Floating point registers */
  74     fpr_t fpr[16];
  75 #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
  76 #define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
  77 #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
  78 #define FPR_D(cpu, n)  (FPR(cpu, n)->d)
  79 #define FPR_W(cpu, n)  (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX])
  80
  81 #ifndef USE_HOST_FLOAT_REGS
  82     fpr_t ft0;
  83     fpr_t ft1;
  84     fpr_t ft2;
  85 #endif
  86     float_status fp_status;
  87     /* fpu implementation/revision register */
  88     uint32_t fcr0;
  89     /* fcsr */
  90     uint32_t fcr31;
  91 #define SET_FP_COND(reg)     do { (reg) |= (1<<23); } while(0)
  92 #define CLEAR_FP_COND(reg)   do { (reg) &= ~(1<<23); } while(0)
  93 #define IS_FP_COND_SET(reg)  (((reg) & (1<<23)) != 0)
  94 #define GET_FP_CAUSE(reg)    (((reg) >> 12) & 0x3f)
  95 #define GET_FP_ENABLE(reg)   (((reg) >>  7) & 0x1f)
  96 #define GET_FP_FLAGS(reg)    (((reg) >>  2) & 0x1f)
  97 #define SET_FP_CAUSE(reg,v)  do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0)
  98 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v) << 7); } while(0)
  99 #define SET_FP_FLAGS(reg,v)  do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v) << 2); } while(0)
 100 #define FP_INEXACT        1
 101 #define FP_UNDERFLOW      2
 102 #define FP_OVERFLOW       4
 103 #define FP_DIV0           8
 104 #define FP_INVALID        16
 105 #define FP_UNIMPLEMENTED  32
 106
 107 #endif
 108 #if defined(MIPS_USES_R4K_TLB)
 109     tlb_t tlb[MIPS_TLB_MAX];
 110     uint32_t tlb_in_use;
 111 #endif
 112     uint32_t CP0_index;
 113     uint32_t CP0_random;
 114     uint64_t CP0_EntryLo0;
 115     uint64_t CP0_EntryLo1;
 116     uint64_t CP0_Context;
 117     uint32_t CP0_PageMask;
 118     uint32_t CP0_PageGrain;
 119     uint32_t CP0_Wired;
 120     uint32_t CP0_HWREna;
 121     target_ulong CP0_BadVAddr;
 122     uint32_t CP0_Count;
 123     uint64_t CP0_EntryHi;
 124     uint32_t CP0_Compare;
 125     uint32_t CP0_Status;
 126 #define CP0St_CU3   31
 127 #define CP0St_CU2   30
 128 #define CP0St_CU1   29
 129 #define CP0St_CU0   28
 130 #define CP0St_RP    27
 131 #define CP0St_FR    26
 132 #define CP0St_RE    25
 133 #define CP0St_MX    24
 134 #define CP0St_PX    23
 135 #define CP0St_BEV   22
 136 #define CP0St_TS    21
 137 #define CP0St_SR    20
 138 #define CP0St_NMI   19
 139 #define CP0St_IM    8
 140 #define CP0St_KX    7
 141 #define CP0St_SX    6
 142 #define CP0St_UX    5
 143 #define CP0St_UM    4
 144 #define CP0St_R0    3
 145 #define CP0St_ERL   2
 146 #define CP0St_EXL   1
 147 #define CP0St_IE    0
 148     uint32_t CP0_IntCtl;
 149     uint32_t CP0_SRSCtl;
 150     uint32_t CP0_Cause;
 151 #define CP0Ca_BD   31
 152 #define CP0Ca_TI   30
 153 #define CP0Ca_CE   28
 154 #define CP0Ca_DC   27
 155 #define CP0Ca_PCI  26
 156 #define CP0Ca_IV   23
 157 #define CP0Ca_WP   22
 158 #define CP0Ca_IP    8
 159 #define CP0Ca_EC    2
 160     target_ulong CP0_EPC;
 161     uint32_t CP0_PRid;
 162     target_ulong CP0_EBase;
 163     uint32_t CP0_Config0;
 164 #define CP0C0_M    31
 165 #define CP0C0_K23  28
 166 #define CP0C0_KU   25
 167 #define CP0C0_MDU  20
 168 #define CP0C0_MM   17
 169 #define CP0C0_BM   16
 170 #define CP0C0_BE   15
 171 #define CP0C0_AT   13
 172 #define CP0C0_AR   10
 173 #define CP0C0_MT   7
 174 #define CP0C0_VI   3
 175 #define CP0C0_K0   0
 176     uint32_t CP0_Config1;
 177 #define CP0C1_M    31
 178 #define CP0C1_MMU  25
 179 #define CP0C1_IS   22
 180 #define CP0C1_IL   19
 181 #define CP0C1_IA   16
 182 #define CP0C1_DS   13
 183 #define CP0C1_DL   10
 184 #define CP0C1_DA   7
 185 #define CP0C1_C2   6
 186 #define CP0C1_MD   5
 187 #define CP0C1_PC   4
 188 #define CP0C1_WR   3
 189 #define CP0C1_CA   2
 190 #define CP0C1_EP   1
 191 #define CP0C1_FP   0
 192     uint32_t CP0_Config2;
 193 #define CP0C2_M    31
 194 #define CP0C2_TU   28
 195 #define CP0C2_TS   24
 196 #define CP0C2_TL   20
 197 #define CP0C2_TA   16
 198 #define CP0C2_SU   12
 199 #define CP0C2_SS   8
 200 #define CP0C2_SL   4
 201 #define CP0C2_SA   0
 202     uint32_t CP0_Config3;
 203 #define CP0C3_M    31
 204 #define CP0C3_DSPP 10
 205 #define CP0C3_LPA  7
 206 #define CP0C3_VEIC 6
 207 #define CP0C3_VInt 5
 208 #define CP0C3_SP   4
 209 #define CP0C3_MT   2
 210 #define CP0C3_SM   1
 211 #define CP0C3_TL   0
 212     target_ulong CP0_LLAddr;
 213     uint32_t CP0_WatchLo;
 214     uint32_t CP0_WatchHi;
 215     uint32_t CP0_XContext;
 216     uint32_t CP0_Framemask;
 217     uint32_t CP0_Debug;
 218 #define CPDB_DBD   31
 219 #define CP0DB_DM   30
 220 #define CP0DB_LSNM 28
 221 #define CP0DB_Doze 27
 222 #define CP0DB_Halt 26
 223 #define CP0DB_CNT  25
 224 #define CP0DB_IBEP 24
 225 #define CP0DB_DBEP 21
 226 #define CP0DB_IEXI 20
 227 #define CP0DB_VER  15
 228 #define CP0DB_DEC  10
 229 #define CP0DB_SSt  8
 230 #define CP0DB_DINT 5
 231 #define CP0DB_DIB  4
 232 #define CP0DB_DDBS 3
 233 #define CP0DB_DDBL 2
 234 #define CP0DB_DBp  1
 235 #define CP0DB_DSS  0
 236     target_ulong CP0_DEPC;
 237     uint32_t CP0_Performance0;
 238     uint32_t CP0_TagLo;
 239     uint32_t CP0_DataLo;
 240     uint32_t CP0_TagHi;
 241     uint32_t CP0_DataHi;
 242     target_ulong CP0_ErrorEPC;
 243     uint32_t CP0_DESAVE;
 244     /* Qemu */
 245     int interrupt_request;
 246     jmp_buf jmp_env;
 247     int exception_index;
 248     int error_code;
 249     int user_mode_only; /* user mode only simulation */
 250     uint32_t hflags;    /* CPU State */
 251     /* TMASK defines different execution modes */
 252 #define MIPS_HFLAG_TMASK  0x007F
 253 #define MIPS_HFLAG_MODE   0x001F /* execution modes                    */
 254 #define MIPS_HFLAG_UM     0x0001 /* user mode                          */
 255 #define MIPS_HFLAG_ERL    0x0002 /* Error mode                         */
 256 #define MIPS_HFLAG_EXL    0x0004 /* Exception mode                     */
 257 #define MIPS_HFLAG_DM     0x0008 /* Debug mode                         */
 258 #define MIPS_HFLAG_SM     0x0010 /* Supervisor mode                    */
 259 #define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */
 260     /* If translation is interrupted between the branch instruction and
 261      * the delay slot, record what type of branch it is so that we can
 262      * resume translation properly.  It might be possible to reduce
 263      * this from three bits to two.  */
 264 #define MIPS_HFLAG_BMASK  0x0380
 265 #define MIPS_HFLAG_B      0x0080 /* Unconditional branch               */
 266 #define MIPS_HFLAG_BC     0x0100 /* Conditional branch                 */
 267 #define MIPS_HFLAG_BL     0x0180 /* Likely branch                      */
 268 #define MIPS_HFLAG_BR     0x0200 /* branch to register (can't link TB) */
 269     target_ulong btarget;        /* Jump / branch target               */
 270     int bcond;                   /* Branch condition (if needed)       */
 271
 272     int halted; /* TRUE if the CPU is in suspend state */
 273
 274     int SYNCI_Step; /* Address step size for SYNCI */
 275     int CCRes; /* Cycle count resolution/divisor */
 276
 277     CPU_COMMON
 278
 279     int ram_size;
 280     const char *kernel_filename;
 281     const char *kernel_cmdline;
 282     const char *initrd_filename;
 283
 284     struct QEMUTimer *timer; /* Internal timer */
 285 };
 286
 287 #include "cpu-all.h"
 288
 289 /* Memory access type :
 290  * may be needed for precise access rights control and precise exceptions.
 291  */
 292 enum {
 293     /* 1 bit to define user level / supervisor access */
 294     ACCESS_USER  = 0x00,
 295     ACCESS_SUPER = 0x01,
 296     /* 1 bit to indicate direction */
 297     ACCESS_STORE = 0x02,
 298     /* Type of instruction that generated the access */
 299     ACCESS_CODE  = 0x10, /* Code fetch access                */
 300     ACCESS_INT   = 0x20, /* Integer load/store access        */
 301     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 302 };
 303
 304 /* Exceptions */
 305 enum {
 306     EXCP_NONE          = -1,
 307     EXCP_RESET         = 0,
 308     EXCP_SRESET,
 309     EXCP_DSS,
 310     EXCP_DINT,
 311     EXCP_NMI,
 312     EXCP_MCHECK,
 313     EXCP_EXT_INTERRUPT,
 314     EXCP_DFWATCH,
 315     EXCP_DIB, /* 8 */
 316     EXCP_IWATCH,
 317     EXCP_AdEL,
 318     EXCP_AdES,
 319     EXCP_TLBF,
 320     EXCP_IBE,
 321     EXCP_DBp,
 322     EXCP_SYSCALL,
 323     EXCP_BREAK, /* 16 */
 324     EXCP_CpU,
 325     EXCP_RI,
 326     EXCP_OVERFLOW,
 327     EXCP_TRAP,
 328     EXCP_DDBS,
 329     EXCP_DWATCH,
 330     EXCP_LAE,
 331     EXCP_SAE, /* 24 */
 332     EXCP_LTLBL,
 333     EXCP_TLBL,
 334     EXCP_TLBS,
 335     EXCP_DBE,
 336     EXCP_DDBL,
 337     EXCP_MTCP0         = 0x104, /* mtmsr instruction:               */
 338                                 /* may change privilege level       */
 339     EXCP_BRANCH        = 0x108, /* branch instruction               */
 340     EXCP_ERET          = 0x10C, /* return from interrupt            */
 341     EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
 342     EXCP_FLUSH         = 0x109,
 343 };
 344
 345 int cpu_mips_exec(CPUMIPSState *s);
 346 CPUMIPSState *cpu_mips_init(void);
 347 uint32_t cpu_mips_get_clock (void);
 348
 349 #endif /* !defined (__MIPS_CPU_H__) */