]>
git.proxmox.com Git - mirror_qemu.git/blob - target-mips/helper.c
2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
36 #if !defined(CONFIG_USER_ONLY)
38 /* no MMU emulation */
39 int no_mmu_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
40 target_ulong address
, int rw
, int access_type
)
43 *prot
= PAGE_READ
| PAGE_WRITE
;
47 /* fixed mapping MMU emulation */
48 int fixed_mmu_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
49 target_ulong address
, int rw
, int access_type
)
51 if (address
<= (int32_t)0x7FFFFFFFUL
) {
52 if (!(env
->CP0_Status
& (1 << CP0St_ERL
)))
53 *physical
= address
+ 0x40000000UL
;
56 } else if (address
<= (int32_t)0xBFFFFFFFUL
)
57 *physical
= address
& 0x1FFFFFFF;
61 *prot
= PAGE_READ
| PAGE_WRITE
;
65 /* MIPS32/MIPS64 R4000-style MMU emulation */
66 int r4k_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
67 target_ulong address
, int rw
, int access_type
)
69 uint8_t ASID
= env
->CP0_EntryHi
& 0xFF;
72 for (i
= 0; i
< env
->tlb
->tlb_in_use
; i
++) {
73 r4k_tlb_t
*tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
74 /* 1k pages are not supported. */
75 target_ulong mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
76 target_ulong tag
= address
& ~mask
;
77 target_ulong VPN
= tlb
->VPN
& ~mask
;
78 #if defined(TARGET_MIPS64)
82 /* Check ASID, virtual page number & size */
83 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
85 int n
= !!(address
& mask
& ~(mask
>> 1));
86 /* Check access rights */
87 if (!(n
? tlb
->V1
: tlb
->V0
))
88 return TLBRET_INVALID
;
89 if (rw
== 0 || (n
? tlb
->D1
: tlb
->D0
)) {
90 *physical
= tlb
->PFN
[n
] | (address
& (mask
>> 1));
92 if (n
? tlb
->D1
: tlb
->D0
)
99 return TLBRET_NOMATCH
;
102 static int get_physical_address (CPUMIPSState
*env
, hwaddr
*physical
,
103 int *prot
, target_ulong address
,
104 int rw
, int access_type
)
106 /* User mode can only access useg/xuseg */
107 int user_mode
= (env
->hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_UM
;
108 int supervisor_mode
= (env
->hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_SM
;
109 int kernel_mode
= !user_mode
&& !supervisor_mode
;
110 #if defined(TARGET_MIPS64)
111 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
112 int SX
= (env
->CP0_Status
& (1 << CP0St_SX
)) != 0;
113 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
115 int ret
= TLBRET_MATCH
;
118 qemu_log("user mode %d h %08x\n", user_mode
, env
->hflags
);
121 if (address
<= (int32_t)0x7FFFFFFFUL
) {
123 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
124 *physical
= address
& 0xFFFFFFFF;
125 *prot
= PAGE_READ
| PAGE_WRITE
;
127 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
129 #if defined(TARGET_MIPS64)
130 } else if (address
< 0x4000000000000000ULL
) {
132 if (UX
&& address
<= (0x3FFFFFFFFFFFFFFFULL
& env
->SEGMask
)) {
133 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
135 ret
= TLBRET_BADADDR
;
137 } else if (address
< 0x8000000000000000ULL
) {
139 if ((supervisor_mode
|| kernel_mode
) &&
140 SX
&& address
<= (0x7FFFFFFFFFFFFFFFULL
& env
->SEGMask
)) {
141 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
143 ret
= TLBRET_BADADDR
;
145 } else if (address
< 0xC000000000000000ULL
) {
147 if (kernel_mode
&& KX
&&
148 (address
& 0x07FFFFFFFFFFFFFFULL
) <= env
->PAMask
) {
149 *physical
= address
& env
->PAMask
;
150 *prot
= PAGE_READ
| PAGE_WRITE
;
152 ret
= TLBRET_BADADDR
;
154 } else if (address
< 0xFFFFFFFF80000000ULL
) {
156 if (kernel_mode
&& KX
&&
157 address
<= (0xFFFFFFFF7FFFFFFFULL
& env
->SEGMask
)) {
158 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
160 ret
= TLBRET_BADADDR
;
163 } else if (address
< (int32_t)0xA0000000UL
) {
166 *physical
= address
- (int32_t)0x80000000UL
;
167 *prot
= PAGE_READ
| PAGE_WRITE
;
169 ret
= TLBRET_BADADDR
;
171 } else if (address
< (int32_t)0xC0000000UL
) {
174 *physical
= address
- (int32_t)0xA0000000UL
;
175 *prot
= PAGE_READ
| PAGE_WRITE
;
177 ret
= TLBRET_BADADDR
;
179 } else if (address
< (int32_t)0xE0000000UL
) {
181 if (supervisor_mode
|| kernel_mode
) {
182 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
184 ret
= TLBRET_BADADDR
;
188 /* XXX: debug segment is not emulated */
190 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
192 ret
= TLBRET_BADADDR
;
196 qemu_log(TARGET_FMT_lx
" %d %d => %" HWADDR_PRIx
" %d (%d)\n",
197 address
, rw
, access_type
, *physical
, *prot
, ret
);
204 static void raise_mmu_exception(CPUMIPSState
*env
, target_ulong address
,
205 int rw
, int tlb_error
)
207 int exception
= 0, error_code
= 0;
212 /* Reference to kernel address from user mode or supervisor mode */
213 /* Reference to supervisor address from user mode */
215 exception
= EXCP_AdES
;
217 exception
= EXCP_AdEL
;
220 /* No TLB match for a mapped address */
222 exception
= EXCP_TLBS
;
224 exception
= EXCP_TLBL
;
228 /* TLB match with no valid bit */
230 exception
= EXCP_TLBS
;
232 exception
= EXCP_TLBL
;
235 /* TLB match but 'D' bit is cleared */
236 exception
= EXCP_LTLBL
;
240 /* Raise exception */
241 env
->CP0_BadVAddr
= address
;
242 env
->CP0_Context
= (env
->CP0_Context
& ~0x007fffff) |
243 ((address
>> 9) & 0x007ffff0);
245 (env
->CP0_EntryHi
& 0xFF) | (address
& (TARGET_PAGE_MASK
<< 1));
246 #if defined(TARGET_MIPS64)
247 env
->CP0_EntryHi
&= env
->SEGMask
;
248 env
->CP0_XContext
= (env
->CP0_XContext
& ((~0ULL) << (env
->SEGBITS
- 7))) |
249 ((address
& 0xC00000000000ULL
) >> (55 - env
->SEGBITS
)) |
250 ((address
& ((1ULL << env
->SEGBITS
) - 1) & 0xFFFFFFFFFFFFE000ULL
) >> 9);
252 env
->exception_index
= exception
;
253 env
->error_code
= error_code
;
256 #if !defined(CONFIG_USER_ONLY)
257 hwaddr
mips_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
259 MIPSCPU
*cpu
= MIPS_CPU(cs
);
263 if (get_physical_address(&cpu
->env
, &phys_addr
, &prot
, addr
, 0,
271 int mips_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
274 MIPSCPU
*cpu
= MIPS_CPU(cs
);
275 CPUMIPSState
*env
= &cpu
->env
;
276 #if !defined(CONFIG_USER_ONLY)
284 log_cpu_state(cs
, 0);
286 qemu_log("%s pc " TARGET_FMT_lx
" ad %" VADDR_PRIx
" rw %d mmu_idx %d\n",
287 __func__
, env
->active_tc
.PC
, address
, rw
, mmu_idx
);
292 #if !defined(CONFIG_USER_ONLY)
293 /* XXX: put correct access by using cpu_restore_state()
295 access_type
= ACCESS_INT
;
296 ret
= get_physical_address(env
, &physical
, &prot
,
297 address
, rw
, access_type
);
298 qemu_log("%s address=%" VADDR_PRIx
" ret %d physical " TARGET_FMT_plx
300 __func__
, address
, ret
, physical
, prot
);
301 if (ret
== TLBRET_MATCH
) {
302 tlb_set_page(env
, address
& TARGET_PAGE_MASK
,
303 physical
& TARGET_PAGE_MASK
, prot
| PAGE_EXEC
,
304 mmu_idx
, TARGET_PAGE_SIZE
);
309 raise_mmu_exception(env
, address
, rw
, ret
);
316 #if !defined(CONFIG_USER_ONLY)
317 hwaddr
cpu_mips_translate_address(CPUMIPSState
*env
, target_ulong address
, int rw
)
327 access_type
= ACCESS_INT
;
328 ret
= get_physical_address(env
, &physical
, &prot
,
329 address
, rw
, access_type
);
330 if (ret
!= TLBRET_MATCH
) {
331 raise_mmu_exception(env
, address
, rw
, ret
);
339 static const char * const excp_names
[EXCP_LAST
+ 1] = {
340 [EXCP_RESET
] = "reset",
341 [EXCP_SRESET
] = "soft reset",
342 [EXCP_DSS
] = "debug single step",
343 [EXCP_DINT
] = "debug interrupt",
344 [EXCP_NMI
] = "non-maskable interrupt",
345 [EXCP_MCHECK
] = "machine check",
346 [EXCP_EXT_INTERRUPT
] = "interrupt",
347 [EXCP_DFWATCH
] = "deferred watchpoint",
348 [EXCP_DIB
] = "debug instruction breakpoint",
349 [EXCP_IWATCH
] = "instruction fetch watchpoint",
350 [EXCP_AdEL
] = "address error load",
351 [EXCP_AdES
] = "address error store",
352 [EXCP_TLBF
] = "TLB refill",
353 [EXCP_IBE
] = "instruction bus error",
354 [EXCP_DBp
] = "debug breakpoint",
355 [EXCP_SYSCALL
] = "syscall",
356 [EXCP_BREAK
] = "break",
357 [EXCP_CpU
] = "coprocessor unusable",
358 [EXCP_RI
] = "reserved instruction",
359 [EXCP_OVERFLOW
] = "arithmetic overflow",
360 [EXCP_TRAP
] = "trap",
361 [EXCP_FPE
] = "floating point",
362 [EXCP_DDBS
] = "debug data break store",
363 [EXCP_DWATCH
] = "data watchpoint",
364 [EXCP_LTLBL
] = "TLB modify",
365 [EXCP_TLBL
] = "TLB load",
366 [EXCP_TLBS
] = "TLB store",
367 [EXCP_DBE
] = "data bus error",
368 [EXCP_DDBL
] = "debug data break load",
369 [EXCP_THREAD
] = "thread",
370 [EXCP_MDMX
] = "MDMX",
371 [EXCP_C2E
] = "precise coprocessor 2",
372 [EXCP_CACHE
] = "cache error",
375 target_ulong
exception_resume_pc (CPUMIPSState
*env
)
378 target_ulong isa_mode
;
380 isa_mode
= !!(env
->hflags
& MIPS_HFLAG_M16
);
381 bad_pc
= env
->active_tc
.PC
| isa_mode
;
382 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
383 /* If the exception was raised from a delay slot, come back to
385 bad_pc
-= (env
->hflags
& MIPS_HFLAG_B16
? 2 : 4);
391 #if !defined(CONFIG_USER_ONLY)
392 static void set_hflags_for_handler (CPUMIPSState
*env
)
394 /* Exception handlers are entered in 32-bit mode. */
395 env
->hflags
&= ~(MIPS_HFLAG_M16
);
396 /* ...except that microMIPS lets you choose. */
397 if (env
->insn_flags
& ASE_MICROMIPS
) {
398 env
->hflags
|= (!!(env
->CP0_Config3
399 & (1 << CP0C3_ISA_ON_EXC
))
400 << MIPS_HFLAG_M16_SHIFT
);
405 void mips_cpu_do_interrupt(CPUState
*cs
)
407 MIPSCPU
*cpu
= MIPS_CPU(cs
);
408 CPUMIPSState
*env
= &cpu
->env
;
409 #if !defined(CONFIG_USER_ONLY)
414 if (qemu_log_enabled() && env
->exception_index
!= EXCP_EXT_INTERRUPT
) {
415 if (env
->exception_index
< 0 || env
->exception_index
> EXCP_LAST
)
418 name
= excp_names
[env
->exception_index
];
420 qemu_log("%s enter: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
" %s exception\n",
421 __func__
, env
->active_tc
.PC
, env
->CP0_EPC
, name
);
423 if (env
->exception_index
== EXCP_EXT_INTERRUPT
&&
424 (env
->hflags
& MIPS_HFLAG_DM
))
425 env
->exception_index
= EXCP_DINT
;
427 switch (env
->exception_index
) {
429 env
->CP0_Debug
|= 1 << CP0DB_DSS
;
430 /* Debug single step cannot be raised inside a delay slot and
431 resume will always occur on the next instruction
432 (but we assume the pc has always been updated during
433 code translation). */
434 env
->CP0_DEPC
= env
->active_tc
.PC
| !!(env
->hflags
& MIPS_HFLAG_M16
);
435 goto enter_debug_mode
;
437 env
->CP0_Debug
|= 1 << CP0DB_DINT
;
440 env
->CP0_Debug
|= 1 << CP0DB_DIB
;
443 env
->CP0_Debug
|= 1 << CP0DB_DBp
;
446 env
->CP0_Debug
|= 1 << CP0DB_DDBS
;
449 env
->CP0_Debug
|= 1 << CP0DB_DDBL
;
451 env
->CP0_DEPC
= exception_resume_pc(env
);
452 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
454 env
->hflags
|= MIPS_HFLAG_DM
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
;
455 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
456 /* EJTAG probe trap enable is not implemented... */
457 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)))
458 env
->CP0_Cause
&= ~(1 << CP0Ca_BD
);
459 env
->active_tc
.PC
= (int32_t)0xBFC00480;
460 set_hflags_for_handler(env
);
466 env
->CP0_Status
|= (1 << CP0St_SR
);
467 memset(env
->CP0_WatchLo
, 0, sizeof(*env
->CP0_WatchLo
));
470 env
->CP0_Status
|= (1 << CP0St_NMI
);
472 env
->CP0_ErrorEPC
= exception_resume_pc(env
);
473 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
474 env
->CP0_Status
|= (1 << CP0St_ERL
) | (1 << CP0St_BEV
);
475 env
->hflags
|= MIPS_HFLAG_64
| MIPS_HFLAG_CP0
;
476 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
477 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)))
478 env
->CP0_Cause
&= ~(1 << CP0Ca_BD
);
479 env
->active_tc
.PC
= (int32_t)0xBFC00000;
480 set_hflags_for_handler(env
);
482 case EXCP_EXT_INTERRUPT
:
484 if (env
->CP0_Cause
& (1 << CP0Ca_IV
))
487 if (env
->CP0_Config3
& ((1 << CP0C3_VInt
) | (1 << CP0C3_VEIC
))) {
488 /* Vectored Interrupts. */
489 unsigned int spacing
;
491 unsigned int pending
= (env
->CP0_Cause
& CP0Ca_IP_mask
) >> 8;
493 pending
&= env
->CP0_Status
>> 8;
494 /* Compute the Vector Spacing. */
495 spacing
= (env
->CP0_IntCtl
>> CP0IntCtl_VS
) & ((1 << 6) - 1);
498 if (env
->CP0_Config3
& (1 << CP0C3_VInt
)) {
499 /* For VInt mode, the MIPS computes the vector internally. */
500 for (vector
= 7; vector
> 0; vector
--) {
501 if (pending
& (1 << vector
)) {
507 /* For VEIC mode, the external interrupt controller feeds the
508 vector through the CP0Cause IP lines. */
511 offset
= 0x200 + vector
* spacing
;
519 if (env
->error_code
== 1 && !(env
->CP0_Status
& (1 << CP0St_EXL
))) {
520 #if defined(TARGET_MIPS64)
521 int R
= env
->CP0_BadVAddr
>> 62;
522 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
523 int SX
= (env
->CP0_Status
& (1 << CP0St_SX
)) != 0;
524 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
526 if (((R
== 0 && UX
) || (R
== 1 && SX
) || (R
== 3 && KX
)) &&
527 (!(env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
))))
536 if (env
->error_code
== 1 && !(env
->CP0_Status
& (1 << CP0St_EXL
))) {
537 #if defined(TARGET_MIPS64)
538 int R
= env
->CP0_BadVAddr
>> 62;
539 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
540 int SX
= (env
->CP0_Status
& (1 << CP0St_SX
)) != 0;
541 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
543 if (((R
== 0 && UX
) || (R
== 1 && SX
) || (R
== 3 && KX
)) &&
544 (!(env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
))))
574 env
->CP0_Cause
= (env
->CP0_Cause
& ~(0x3 << CP0Ca_CE
)) |
575 (env
->error_code
<< CP0Ca_CE
);
594 /* XXX: TODO: manage defered watch exceptions */
607 if (env
->CP0_Status
& (1 << CP0St_BEV
)) {
613 if (!(env
->CP0_Status
& (1 << CP0St_EXL
))) {
614 env
->CP0_EPC
= exception_resume_pc(env
);
615 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
616 env
->CP0_Cause
|= (1 << CP0Ca_BD
);
618 env
->CP0_Cause
&= ~(1 << CP0Ca_BD
);
620 env
->CP0_Status
|= (1 << CP0St_EXL
);
621 env
->hflags
|= MIPS_HFLAG_64
| MIPS_HFLAG_CP0
;
622 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
624 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
625 if (env
->CP0_Status
& (1 << CP0St_BEV
)) {
626 env
->active_tc
.PC
= (int32_t)0xBFC00200;
628 env
->active_tc
.PC
= (int32_t)(env
->CP0_EBase
& ~0x3ff);
630 env
->active_tc
.PC
+= offset
;
631 set_hflags_for_handler(env
);
632 env
->CP0_Cause
= (env
->CP0_Cause
& ~(0x1f << CP0Ca_EC
)) | (cause
<< CP0Ca_EC
);
635 qemu_log("Invalid MIPS exception %d. Exiting\n", env
->exception_index
);
636 printf("Invalid MIPS exception %d. Exiting\n", env
->exception_index
);
639 if (qemu_log_enabled() && env
->exception_index
!= EXCP_EXT_INTERRUPT
) {
640 qemu_log("%s: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
" cause %d\n"
641 " S %08x C %08x A " TARGET_FMT_lx
" D " TARGET_FMT_lx
"\n",
642 __func__
, env
->active_tc
.PC
, env
->CP0_EPC
, cause
,
643 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_BadVAddr
,
647 env
->exception_index
= EXCP_NONE
;
650 #if !defined(CONFIG_USER_ONLY)
651 void r4k_invalidate_tlb (CPUMIPSState
*env
, int idx
, int use_extra
)
656 uint8_t ASID
= env
->CP0_EntryHi
& 0xFF;
659 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
660 /* The qemu TLB is flushed when the ASID changes, so no need to
661 flush these entries again. */
662 if (tlb
->G
== 0 && tlb
->ASID
!= ASID
) {
666 if (use_extra
&& env
->tlb
->tlb_in_use
< MIPS_TLB_MAX
) {
667 /* For tlbwr, we can shadow the discarded entry into
668 a new (fake) TLB entry, as long as the guest can not
669 tell that it's there. */
670 env
->tlb
->mmu
.r4k
.tlb
[env
->tlb
->tlb_in_use
] = *tlb
;
671 env
->tlb
->tlb_in_use
++;
675 /* 1k pages are not supported. */
676 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
678 addr
= tlb
->VPN
& ~mask
;
679 #if defined(TARGET_MIPS64)
680 if (addr
>= (0xFFFFFFFF80000000ULL
& env
->SEGMask
)) {
681 addr
|= 0x3FFFFF0000000000ULL
;
684 end
= addr
| (mask
>> 1);
686 tlb_flush_page (env
, addr
);
687 addr
+= TARGET_PAGE_SIZE
;
691 addr
= (tlb
->VPN
& ~mask
) | ((mask
>> 1) + 1);
692 #if defined(TARGET_MIPS64)
693 if (addr
>= (0xFFFFFFFF80000000ULL
& env
->SEGMask
)) {
694 addr
|= 0x3FFFFF0000000000ULL
;
698 while (addr
- 1 < end
) {
699 tlb_flush_page (env
, addr
);
700 addr
+= TARGET_PAGE_SIZE
;