target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "sysemu/kvm.h"
  28
  29 enum {
  30     TLBRET_XI = -6,
  31     TLBRET_RI = -5,
  32     TLBRET_DIRTY = -4,
  33     TLBRET_INVALID = -3,
  34     TLBRET_NOMATCH = -2,
  35     TLBRET_BADADDR = -1,
  36     TLBRET_MATCH = 0
  37 };
  38
  39 #if !defined(CONFIG_USER_ONLY)
  40
  41 /* no MMU emulation */
  42 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  43                         target_ulong address, int rw, int access_type)
  44 {
  45     *physical = address;
  46     *prot = PAGE_READ | PAGE_WRITE;
  47     return TLBRET_MATCH;
  48 }
  49
  50 /* fixed mapping MMU emulation */
  51 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  52                            target_ulong address, int rw, int access_type)
  53 {
  54     if (address <= (int32_t)0x7FFFFFFFUL) {
  55         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  56             *physical = address + 0x40000000UL;
  57         else
  58             *physical = address;
  59     } else if (address <= (int32_t)0xBFFFFFFFUL)
  60         *physical = address & 0x1FFFFFFF;
  61     else
  62         *physical = address;
  63
  64     *prot = PAGE_READ | PAGE_WRITE;
  65     return TLBRET_MATCH;
  66 }
  67
  68 /* MIPS32/MIPS64 R4000-style MMU emulation */
  69 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  70                      target_ulong address, int rw, int access_type)
  71 {
  72     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  73     int i;
  74
  75     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  76         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  77         /* 1k pages are not supported. */
  78         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  79         target_ulong tag = address & ~mask;
  80         target_ulong VPN = tlb->VPN & ~mask;
  81 #if defined(TARGET_MIPS64)
  82         tag &= env->SEGMask;
  83 #endif
  84
  85         /* Check ASID, virtual page number & size */
  86         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
  87             /* TLB match */
  88             int n = !!(address & mask & ~(mask >> 1));
  89             /* Check access rights */
  90             if (!(n ? tlb->V1 : tlb->V0)) {
  91                 return TLBRET_INVALID;
  92             }
  93             if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
  94                 return TLBRET_XI;
  95             }
  96             if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
  97                 return TLBRET_RI;
  98             }
  99             if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
 100                 *physical = tlb->PFN[n] | (address & (mask >> 1));
 101                 *prot = PAGE_READ;
 102                 if (n ? tlb->D1 : tlb->D0)
 103                     *prot |= PAGE_WRITE;
 104                 return TLBRET_MATCH;
 105             }
 106             return TLBRET_DIRTY;
 107         }
 108     }
 109     return TLBRET_NOMATCH;
 110 }
 111
 112 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 113                                 int *prot, target_ulong real_address,
 114                                 int rw, int access_type)
 115 {
 116     /* User mode can only access useg/xuseg */
 117     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 118     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 119     int kernel_mode = !user_mode && !supervisor_mode;
 120 #if defined(TARGET_MIPS64)
 121     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 122     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 123     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 124 #endif
 125     int ret = TLBRET_MATCH;
 126     /* effective address (modified for KVM T&E kernel segments) */
 127     target_ulong address = real_address;
 128
 129 #if 0
 130     qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 131 #endif
 132
 133 #define USEG_LIMIT      0x7FFFFFFFUL
 134 #define KSEG0_BASE      0x80000000UL
 135 #define KSEG1_BASE      0xA0000000UL
 136 #define KSEG2_BASE      0xC0000000UL
 137 #define KSEG3_BASE      0xE0000000UL
 138
 139 #define KVM_KSEG0_BASE  0x40000000UL
 140 #define KVM_KSEG2_BASE  0x60000000UL
 141
 142     if (kvm_enabled()) {
 143         /* KVM T&E adds guest kernel segments in useg */
 144         if (real_address >= KVM_KSEG0_BASE) {
 145             if (real_address < KVM_KSEG2_BASE) {
 146                 /* kseg0 */
 147                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 148             } else if (real_address <= USEG_LIMIT) {
 149                 /* kseg2/3 */
 150                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 151             }
 152         }
 153     }
 154
 155     if (address <= USEG_LIMIT) {
 156         /* useg */
 157         if (env->CP0_Status & (1 << CP0St_ERL)) {
 158             *physical = address & 0xFFFFFFFF;
 159             *prot = PAGE_READ | PAGE_WRITE;
 160         } else {
 161             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 162         }
 163 #if defined(TARGET_MIPS64)
 164     } else if (address < 0x4000000000000000ULL) {
 165         /* xuseg */
 166         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 167             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 168         } else {
 169             ret = TLBRET_BADADDR;
 170         }
 171     } else if (address < 0x8000000000000000ULL) {
 172         /* xsseg */
 173         if ((supervisor_mode || kernel_mode) &&
 174             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 175             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 176         } else {
 177             ret = TLBRET_BADADDR;
 178         }
 179     } else if (address < 0xC000000000000000ULL) {
 180         /* xkphys */
 181         if (kernel_mode && KX &&
 182             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 183             *physical = address & env->PAMask;
 184             *prot = PAGE_READ | PAGE_WRITE;
 185         } else {
 186             ret = TLBRET_BADADDR;
 187         }
 188     } else if (address < 0xFFFFFFFF80000000ULL) {
 189         /* xkseg */
 190         if (kernel_mode && KX &&
 191             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 192             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 193         } else {
 194             ret = TLBRET_BADADDR;
 195         }
 196 #endif
 197     } else if (address < (int32_t)KSEG1_BASE) {
 198         /* kseg0 */
 199         if (kernel_mode) {
 200             *physical = address - (int32_t)KSEG0_BASE;
 201             *prot = PAGE_READ | PAGE_WRITE;
 202         } else {
 203             ret = TLBRET_BADADDR;
 204         }
 205     } else if (address < (int32_t)KSEG2_BASE) {
 206         /* kseg1 */
 207         if (kernel_mode) {
 208             *physical = address - (int32_t)KSEG1_BASE;
 209             *prot = PAGE_READ | PAGE_WRITE;
 210         } else {
 211             ret = TLBRET_BADADDR;
 212         }
 213     } else if (address < (int32_t)KSEG3_BASE) {
 214         /* sseg (kseg2) */
 215         if (supervisor_mode || kernel_mode) {
 216             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 217         } else {
 218             ret = TLBRET_BADADDR;
 219         }
 220     } else {
 221         /* kseg3 */
 222         /* XXX: debug segment is not emulated */
 223         if (kernel_mode) {
 224             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 225         } else {
 226             ret = TLBRET_BADADDR;
 227         }
 228     }
 229 #if 0
 230     qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
 231             address, rw, access_type, *physical, *prot, ret);
 232 #endif
 233
 234     return ret;
 235 }
 236 #endif
 237
 238 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 239                                 int rw, int tlb_error)
 240 {
 241     CPUState *cs = CPU(mips_env_get_cpu(env));
 242     int exception = 0, error_code = 0;
 243
 244     switch (tlb_error) {
 245     default:
 246     case TLBRET_BADADDR:
 247         /* Reference to kernel address from user mode or supervisor mode */
 248         /* Reference to supervisor address from user mode */
 249         if (rw == MMU_DATA_STORE) {
 250             exception = EXCP_AdES;
 251         } else {
 252             exception = EXCP_AdEL;
 253         }
 254         break;
 255     case TLBRET_NOMATCH:
 256         /* No TLB match for a mapped address */
 257         if (rw == MMU_DATA_STORE) {
 258             exception = EXCP_TLBS;
 259         } else {
 260             exception = EXCP_TLBL;
 261         }
 262         error_code = 1;
 263         break;
 264     case TLBRET_INVALID:
 265         /* TLB match with no valid bit */
 266         if (rw == MMU_DATA_STORE) {
 267             exception = EXCP_TLBS;
 268         } else {
 269             exception = EXCP_TLBL;
 270         }
 271         break;
 272     case TLBRET_DIRTY:
 273         /* TLB match but 'D' bit is cleared */
 274         exception = EXCP_LTLBL;
 275         break;
 276     case TLBRET_XI:
 277         /* Execute-Inhibit Exception */
 278         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 279             exception = EXCP_TLBXI;
 280         } else {
 281             exception = EXCP_TLBL;
 282         }
 283         break;
 284     case TLBRET_RI:
 285         /* Read-Inhibit Exception */
 286         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 287             exception = EXCP_TLBRI;
 288         } else {
 289             exception = EXCP_TLBL;
 290         }
 291         break;
 292     }
 293     /* Raise exception */
 294     env->CP0_BadVAddr = address;
 295     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 296                        ((address >> 9) & 0x007ffff0);
 297     env->CP0_EntryHi =
 298         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 299 #if defined(TARGET_MIPS64)
 300     env->CP0_EntryHi &= env->SEGMask;
 301     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 302                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 303                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 304 #endif
 305     cs->exception_index = exception;
 306     env->error_code = error_code;
 307 }
 308
 309 #if !defined(CONFIG_USER_ONLY)
 310 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 311 {
 312     MIPSCPU *cpu = MIPS_CPU(cs);
 313     hwaddr phys_addr;
 314     int prot;
 315
 316     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 317                              ACCESS_INT) != 0) {
 318         return -1;
 319     }
 320     return phys_addr;
 321 }
 322 #endif
 323
 324 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 325                               int mmu_idx)
 326 {
 327     MIPSCPU *cpu = MIPS_CPU(cs);
 328     CPUMIPSState *env = &cpu->env;
 329 #if !defined(CONFIG_USER_ONLY)
 330     hwaddr physical;
 331     int prot;
 332     int access_type;
 333 #endif
 334     int ret = 0;
 335
 336 #if 0
 337     log_cpu_state(cs, 0);
 338 #endif
 339     qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 340               __func__, env->active_tc.PC, address, rw, mmu_idx);
 341
 342     /* data access */
 343 #if !defined(CONFIG_USER_ONLY)
 344     /* XXX: put correct access by using cpu_restore_state()
 345        correctly */
 346     access_type = ACCESS_INT;
 347     ret = get_physical_address(env, &physical, &prot,
 348                                address, rw, access_type);
 349     qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 350              " prot %d\n",
 351              __func__, address, ret, physical, prot);
 352     if (ret == TLBRET_MATCH) {
 353         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 354                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 355                      mmu_idx, TARGET_PAGE_SIZE);
 356         ret = 0;
 357     } else if (ret < 0)
 358 #endif
 359     {
 360         raise_mmu_exception(env, address, rw, ret);
 361         ret = 1;
 362     }
 363
 364     return ret;
 365 }
 366
 367 #if !defined(CONFIG_USER_ONLY)
 368 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 369 {
 370     hwaddr physical;
 371     int prot;
 372     int access_type;
 373     int ret = 0;
 374
 375     /* data access */
 376     access_type = ACCESS_INT;
 377     ret = get_physical_address(env, &physical, &prot,
 378                                address, rw, access_type);
 379     if (ret != TLBRET_MATCH) {
 380         raise_mmu_exception(env, address, rw, ret);
 381         return -1LL;
 382     } else {
 383         return physical;
 384     }
 385 }
 386 #endif
 387
 388 static const char * const excp_names[EXCP_LAST + 1] = {
 389     [EXCP_RESET] = "reset",
 390     [EXCP_SRESET] = "soft reset",
 391     [EXCP_DSS] = "debug single step",
 392     [EXCP_DINT] = "debug interrupt",
 393     [EXCP_NMI] = "non-maskable interrupt",
 394     [EXCP_MCHECK] = "machine check",
 395     [EXCP_EXT_INTERRUPT] = "interrupt",
 396     [EXCP_DFWATCH] = "deferred watchpoint",
 397     [EXCP_DIB] = "debug instruction breakpoint",
 398     [EXCP_IWATCH] = "instruction fetch watchpoint",
 399     [EXCP_AdEL] = "address error load",
 400     [EXCP_AdES] = "address error store",
 401     [EXCP_TLBF] = "TLB refill",
 402     [EXCP_IBE] = "instruction bus error",
 403     [EXCP_DBp] = "debug breakpoint",
 404     [EXCP_SYSCALL] = "syscall",
 405     [EXCP_BREAK] = "break",
 406     [EXCP_CpU] = "coprocessor unusable",
 407     [EXCP_RI] = "reserved instruction",
 408     [EXCP_OVERFLOW] = "arithmetic overflow",
 409     [EXCP_TRAP] = "trap",
 410     [EXCP_FPE] = "floating point",
 411     [EXCP_DDBS] = "debug data break store",
 412     [EXCP_DWATCH] = "data watchpoint",
 413     [EXCP_LTLBL] = "TLB modify",
 414     [EXCP_TLBL] = "TLB load",
 415     [EXCP_TLBS] = "TLB store",
 416     [EXCP_DBE] = "data bus error",
 417     [EXCP_DDBL] = "debug data break load",
 418     [EXCP_THREAD] = "thread",
 419     [EXCP_MDMX] = "MDMX",
 420     [EXCP_C2E] = "precise coprocessor 2",
 421     [EXCP_CACHE] = "cache error",
 422     [EXCP_TLBXI] = "TLB execute-inhibit",
 423     [EXCP_TLBRI] = "TLB read-inhibit",
 424 };
 425
 426 target_ulong exception_resume_pc (CPUMIPSState *env)
 427 {
 428     target_ulong bad_pc;
 429     target_ulong isa_mode;
 430
 431     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 432     bad_pc = env->active_tc.PC | isa_mode;
 433     if (env->hflags & MIPS_HFLAG_BMASK) {
 434         /* If the exception was raised from a delay slot, come back to
 435            the jump.  */
 436         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 437     }
 438
 439     return bad_pc;
 440 }
 441
 442 #if !defined(CONFIG_USER_ONLY)
 443 static void set_hflags_for_handler (CPUMIPSState *env)
 444 {
 445     /* Exception handlers are entered in 32-bit mode.  */
 446     env->hflags &= ~(MIPS_HFLAG_M16);
 447     /* ...except that microMIPS lets you choose.  */
 448     if (env->insn_flags & ASE_MICROMIPS) {
 449         env->hflags |= (!!(env->CP0_Config3
 450                            & (1 << CP0C3_ISA_ON_EXC))
 451                         << MIPS_HFLAG_M16_SHIFT);
 452     }
 453 }
 454 #endif
 455
 456 void mips_cpu_do_interrupt(CPUState *cs)
 457 {
 458 #if !defined(CONFIG_USER_ONLY)
 459     MIPSCPU *cpu = MIPS_CPU(cs);
 460     CPUMIPSState *env = &cpu->env;
 461     target_ulong offset;
 462     int cause = -1;
 463     const char *name;
 464
 465     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 466         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 467             name = "unknown";
 468         } else {
 469             name = excp_names[cs->exception_index];
 470         }
 471
 472         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 473                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 474     }
 475     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 476         (env->hflags & MIPS_HFLAG_DM)) {
 477         cs->exception_index = EXCP_DINT;
 478     }
 479     offset = 0x180;
 480     switch (cs->exception_index) {
 481     case EXCP_DSS:
 482         env->CP0_Debug |= 1 << CP0DB_DSS;
 483         /* Debug single step cannot be raised inside a delay slot and
 484            resume will always occur on the next instruction
 485            (but we assume the pc has always been updated during
 486            code translation). */
 487         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 488         goto enter_debug_mode;
 489     case EXCP_DINT:
 490         env->CP0_Debug |= 1 << CP0DB_DINT;
 491         goto set_DEPC;
 492     case EXCP_DIB:
 493         env->CP0_Debug |= 1 << CP0DB_DIB;
 494         goto set_DEPC;
 495     case EXCP_DBp:
 496         env->CP0_Debug |= 1 << CP0DB_DBp;
 497         goto set_DEPC;
 498     case EXCP_DDBS:
 499         env->CP0_Debug |= 1 << CP0DB_DDBS;
 500         goto set_DEPC;
 501     case EXCP_DDBL:
 502         env->CP0_Debug |= 1 << CP0DB_DDBL;
 503     set_DEPC:
 504         env->CP0_DEPC = exception_resume_pc(env);
 505         env->hflags &= ~MIPS_HFLAG_BMASK;
 506  enter_debug_mode:
 507         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 508         env->hflags &= ~(MIPS_HFLAG_KSU);
 509         /* EJTAG probe trap enable is not implemented... */
 510         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 511             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 512         env->active_tc.PC = (int32_t)0xBFC00480;
 513         set_hflags_for_handler(env);
 514         break;
 515     case EXCP_RESET:
 516         cpu_reset(CPU(cpu));
 517         break;
 518     case EXCP_SRESET:
 519         env->CP0_Status |= (1 << CP0St_SR);
 520         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 521         goto set_error_EPC;
 522     case EXCP_NMI:
 523         env->CP0_Status |= (1 << CP0St_NMI);
 524  set_error_EPC:
 525         env->CP0_ErrorEPC = exception_resume_pc(env);
 526         env->hflags &= ~MIPS_HFLAG_BMASK;
 527         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 528         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 529         env->hflags &= ~(MIPS_HFLAG_KSU);
 530         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 531             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 532         env->active_tc.PC = (int32_t)0xBFC00000;
 533         set_hflags_for_handler(env);
 534         break;
 535     case EXCP_EXT_INTERRUPT:
 536         cause = 0;
 537         if (env->CP0_Cause & (1 << CP0Ca_IV))
 538             offset = 0x200;
 539
 540         if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
 541             /* Vectored Interrupts.  */
 542             unsigned int spacing;
 543             unsigned int vector;
 544             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 545
 546             pending &= env->CP0_Status >> 8;
 547             /* Compute the Vector Spacing.  */
 548             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
 549             spacing <<= 5;
 550
 551             if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
 552                 /* For VInt mode, the MIPS computes the vector internally.  */
 553                 for (vector = 7; vector > 0; vector--) {
 554                     if (pending & (1 << vector)) {
 555                         /* Found it.  */
 556                         break;
 557                     }
 558                 }
 559             } else {
 560                 /* For VEIC mode, the external interrupt controller feeds the
 561                    vector through the CP0Cause IP lines.  */
 562                 vector = pending;
 563             }
 564             offset = 0x200 + vector * spacing;
 565         }
 566         goto set_EPC;
 567     case EXCP_LTLBL:
 568         cause = 1;
 569         goto set_EPC;
 570     case EXCP_TLBL:
 571         cause = 2;
 572         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 573 #if defined(TARGET_MIPS64)
 574             int R = env->CP0_BadVAddr >> 62;
 575             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 576             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 577             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 578
 579             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 580                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 581                 offset = 0x080;
 582             else
 583 #endif
 584                 offset = 0x000;
 585         }
 586         goto set_EPC;
 587     case EXCP_TLBS:
 588         cause = 3;
 589         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 590 #if defined(TARGET_MIPS64)
 591             int R = env->CP0_BadVAddr >> 62;
 592             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 593             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 594             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 595
 596             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 597                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 598                 offset = 0x080;
 599             else
 600 #endif
 601                 offset = 0x000;
 602         }
 603         goto set_EPC;
 604     case EXCP_AdEL:
 605         cause = 4;
 606         goto set_EPC;
 607     case EXCP_AdES:
 608         cause = 5;
 609         goto set_EPC;
 610     case EXCP_IBE:
 611         cause = 6;
 612         goto set_EPC;
 613     case EXCP_DBE:
 614         cause = 7;
 615         goto set_EPC;
 616     case EXCP_SYSCALL:
 617         cause = 8;
 618         goto set_EPC;
 619     case EXCP_BREAK:
 620         cause = 9;
 621         goto set_EPC;
 622     case EXCP_RI:
 623         cause = 10;
 624         goto set_EPC;
 625     case EXCP_CpU:
 626         cause = 11;
 627         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 628                          (env->error_code << CP0Ca_CE);
 629         goto set_EPC;
 630     case EXCP_OVERFLOW:
 631         cause = 12;
 632         goto set_EPC;
 633     case EXCP_TRAP:
 634         cause = 13;
 635         goto set_EPC;
 636     case EXCP_FPE:
 637         cause = 15;
 638         goto set_EPC;
 639     case EXCP_C2E:
 640         cause = 18;
 641         goto set_EPC;
 642     case EXCP_TLBRI:
 643         cause = 19;
 644         goto set_EPC;
 645     case EXCP_TLBXI:
 646         cause = 20;
 647         goto set_EPC;
 648     case EXCP_MDMX:
 649         cause = 22;
 650         goto set_EPC;
 651     case EXCP_DWATCH:
 652         cause = 23;
 653         /* XXX: TODO: manage defered watch exceptions */
 654         goto set_EPC;
 655     case EXCP_MCHECK:
 656         cause = 24;
 657         goto set_EPC;
 658     case EXCP_THREAD:
 659         cause = 25;
 660         goto set_EPC;
 661     case EXCP_DSPDIS:
 662         cause = 26;
 663         goto set_EPC;
 664     case EXCP_CACHE:
 665         cause = 30;
 666         if (env->CP0_Status & (1 << CP0St_BEV)) {
 667             offset = 0x100;
 668         } else {
 669             offset = 0x20000100;
 670         }
 671  set_EPC:
 672         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 673             env->CP0_EPC = exception_resume_pc(env);
 674             if (env->hflags & MIPS_HFLAG_BMASK) {
 675                 env->CP0_Cause |= (1U << CP0Ca_BD);
 676             } else {
 677                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 678             }
 679             env->CP0_Status |= (1 << CP0St_EXL);
 680             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 681             env->hflags &= ~(MIPS_HFLAG_KSU);
 682         }
 683         env->hflags &= ~MIPS_HFLAG_BMASK;
 684         if (env->CP0_Status & (1 << CP0St_BEV)) {
 685             env->active_tc.PC = (int32_t)0xBFC00200;
 686         } else {
 687             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 688         }
 689         env->active_tc.PC += offset;
 690         set_hflags_for_handler(env);
 691         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 692         break;
 693     default:
 694         qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 695         printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 696         exit(1);
 697     }
 698     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 699         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 700                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 701                 __func__, env->active_tc.PC, env->CP0_EPC, cause,
 702                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 703                 env->CP0_DEPC);
 704     }
 705 #endif
 706     cs->exception_index = EXCP_NONE;
 707 }
 708
 709 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 710 {
 711     if (interrupt_request & CPU_INTERRUPT_HARD) {
 712         MIPSCPU *cpu = MIPS_CPU(cs);
 713         CPUMIPSState *env = &cpu->env;
 714
 715         if (cpu_mips_hw_interrupts_pending(env)) {
 716             /* Raise it */
 717             cs->exception_index = EXCP_EXT_INTERRUPT;
 718             env->error_code = 0;
 719             mips_cpu_do_interrupt(cs);
 720             return true;
 721         }
 722     }
 723     return false;
 724 }
 725
 726 #if !defined(CONFIG_USER_ONLY)
 727 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 728 {
 729     MIPSCPU *cpu = mips_env_get_cpu(env);
 730     CPUState *cs;
 731     r4k_tlb_t *tlb;
 732     target_ulong addr;
 733     target_ulong end;
 734     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 735     target_ulong mask;
 736
 737     tlb = &env->tlb->mmu.r4k.tlb[idx];
 738     /* The qemu TLB is flushed when the ASID changes, so no need to
 739        flush these entries again.  */
 740     if (tlb->G == 0 && tlb->ASID != ASID) {
 741         return;
 742     }
 743
 744     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 745         /* For tlbwr, we can shadow the discarded entry into
 746            a new (fake) TLB entry, as long as the guest can not
 747            tell that it's there.  */
 748         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 749         env->tlb->tlb_in_use++;
 750         return;
 751     }
 752
 753     /* 1k pages are not supported. */
 754     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 755     if (tlb->V0) {
 756         cs = CPU(cpu);
 757         addr = tlb->VPN & ~mask;
 758 #if defined(TARGET_MIPS64)
 759         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 760             addr |= 0x3FFFFF0000000000ULL;
 761         }
 762 #endif
 763         end = addr | (mask >> 1);
 764         while (addr < end) {
 765             tlb_flush_page(cs, addr);
 766             addr += TARGET_PAGE_SIZE;
 767         }
 768     }
 769     if (tlb->V1) {
 770         cs = CPU(cpu);
 771         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 772 #if defined(TARGET_MIPS64)
 773         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 774             addr |= 0x3FFFFF0000000000ULL;
 775         }
 776 #endif
 777         end = addr | mask;
 778         while (addr - 1 < end) {
 779             tlb_flush_page(cs, addr);
 780             addr += TARGET_PAGE_SIZE;
 781         }
 782     }
 783 }
 784 #endif