target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "sysemu/kvm.h"
  28
  29 enum {
  30     TLBRET_DIRTY = -4,
  31     TLBRET_INVALID = -3,
  32     TLBRET_NOMATCH = -2,
  33     TLBRET_BADADDR = -1,
  34     TLBRET_MATCH = 0
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ | PAGE_WRITE;
  45     return TLBRET_MATCH;
  46 }
  47
  48 /* fixed mapping MMU emulation */
  49 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  50                            target_ulong address, int rw, int access_type)
  51 {
  52     if (address <= (int32_t)0x7FFFFFFFUL) {
  53         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  54             *physical = address + 0x40000000UL;
  55         else
  56             *physical = address;
  57     } else if (address <= (int32_t)0xBFFFFFFFUL)
  58         *physical = address & 0x1FFFFFFF;
  59     else
  60         *physical = address;
  61
  62     *prot = PAGE_READ | PAGE_WRITE;
  63     return TLBRET_MATCH;
  64 }
  65
  66 /* MIPS32/MIPS64 R4000-style MMU emulation */
  67 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  68                      target_ulong address, int rw, int access_type)
  69 {
  70     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  71     int i;
  72
  73     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  74         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  75         /* 1k pages are not supported. */
  76         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  77         target_ulong tag = address & ~mask;
  78         target_ulong VPN = tlb->VPN & ~mask;
  79 #if defined(TARGET_MIPS64)
  80         tag &= env->SEGMask;
  81 #endif
  82
  83         /* Check ASID, virtual page number & size */
  84         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  85             /* TLB match */
  86             int n = !!(address & mask & ~(mask >> 1));
  87             /* Check access rights */
  88             if (!(n ? tlb->V1 : tlb->V0))
  89                 return TLBRET_INVALID;
  90             if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
  91                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  92                 *prot = PAGE_READ;
  93                 if (n ? tlb->D1 : tlb->D0)
  94                     *prot |= PAGE_WRITE;
  95                 return TLBRET_MATCH;
  96             }
  97             return TLBRET_DIRTY;
  98         }
  99     }
 100     return TLBRET_NOMATCH;
 101 }
 102
 103 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 104                                 int *prot, target_ulong real_address,
 105                                 int rw, int access_type)
 106 {
 107     /* User mode can only access useg/xuseg */
 108     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 109     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 110     int kernel_mode = !user_mode && !supervisor_mode;
 111 #if defined(TARGET_MIPS64)
 112     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 113     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 114     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 115 #endif
 116     int ret = TLBRET_MATCH;
 117     /* effective address (modified for KVM T&E kernel segments) */
 118     target_ulong address = real_address;
 119
 120 #if 0
 121     qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 122 #endif
 123
 124 #define USEG_LIMIT      0x7FFFFFFFUL
 125 #define KSEG0_BASE      0x80000000UL
 126 #define KSEG1_BASE      0xA0000000UL
 127 #define KSEG2_BASE      0xC0000000UL
 128 #define KSEG3_BASE      0xE0000000UL
 129
 130 #define KVM_KSEG0_BASE  0x40000000UL
 131 #define KVM_KSEG2_BASE  0x60000000UL
 132
 133     if (kvm_enabled()) {
 134         /* KVM T&E adds guest kernel segments in useg */
 135         if (real_address >= KVM_KSEG0_BASE) {
 136             if (real_address < KVM_KSEG2_BASE) {
 137                 /* kseg0 */
 138                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 139             } else if (real_address <= USEG_LIMIT) {
 140                 /* kseg2/3 */
 141                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 142             }
 143         }
 144     }
 145
 146     if (address <= USEG_LIMIT) {
 147         /* useg */
 148         if (env->CP0_Status & (1 << CP0St_ERL)) {
 149             *physical = address & 0xFFFFFFFF;
 150             *prot = PAGE_READ | PAGE_WRITE;
 151         } else {
 152             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 153         }
 154 #if defined(TARGET_MIPS64)
 155     } else if (address < 0x4000000000000000ULL) {
 156         /* xuseg */
 157         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 158             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 159         } else {
 160             ret = TLBRET_BADADDR;
 161         }
 162     } else if (address < 0x8000000000000000ULL) {
 163         /* xsseg */
 164         if ((supervisor_mode || kernel_mode) &&
 165             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 166             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 167         } else {
 168             ret = TLBRET_BADADDR;
 169         }
 170     } else if (address < 0xC000000000000000ULL) {
 171         /* xkphys */
 172         if (kernel_mode && KX &&
 173             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 174             *physical = address & env->PAMask;
 175             *prot = PAGE_READ | PAGE_WRITE;
 176         } else {
 177             ret = TLBRET_BADADDR;
 178         }
 179     } else if (address < 0xFFFFFFFF80000000ULL) {
 180         /* xkseg */
 181         if (kernel_mode && KX &&
 182             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 183             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 184         } else {
 185             ret = TLBRET_BADADDR;
 186         }
 187 #endif
 188     } else if (address < (int32_t)KSEG1_BASE) {
 189         /* kseg0 */
 190         if (kernel_mode) {
 191             *physical = address - (int32_t)KSEG0_BASE;
 192             *prot = PAGE_READ | PAGE_WRITE;
 193         } else {
 194             ret = TLBRET_BADADDR;
 195         }
 196     } else if (address < (int32_t)KSEG2_BASE) {
 197         /* kseg1 */
 198         if (kernel_mode) {
 199             *physical = address - (int32_t)KSEG1_BASE;
 200             *prot = PAGE_READ | PAGE_WRITE;
 201         } else {
 202             ret = TLBRET_BADADDR;
 203         }
 204     } else if (address < (int32_t)KSEG3_BASE) {
 205         /* sseg (kseg2) */
 206         if (supervisor_mode || kernel_mode) {
 207             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 208         } else {
 209             ret = TLBRET_BADADDR;
 210         }
 211     } else {
 212         /* kseg3 */
 213         /* XXX: debug segment is not emulated */
 214         if (kernel_mode) {
 215             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 216         } else {
 217             ret = TLBRET_BADADDR;
 218         }
 219     }
 220 #if 0
 221     qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
 222             address, rw, access_type, *physical, *prot, ret);
 223 #endif
 224
 225     return ret;
 226 }
 227 #endif
 228
 229 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 230                                 int rw, int tlb_error)
 231 {
 232     CPUState *cs = CPU(mips_env_get_cpu(env));
 233     int exception = 0, error_code = 0;
 234
 235     switch (tlb_error) {
 236     default:
 237     case TLBRET_BADADDR:
 238         /* Reference to kernel address from user mode or supervisor mode */
 239         /* Reference to supervisor address from user mode */
 240         if (rw == MMU_DATA_STORE) {
 241             exception = EXCP_AdES;
 242         } else {
 243             exception = EXCP_AdEL;
 244         }
 245         break;
 246     case TLBRET_NOMATCH:
 247         /* No TLB match for a mapped address */
 248         if (rw == MMU_DATA_STORE) {
 249             exception = EXCP_TLBS;
 250         } else {
 251             exception = EXCP_TLBL;
 252         }
 253         error_code = 1;
 254         break;
 255     case TLBRET_INVALID:
 256         /* TLB match with no valid bit */
 257         if (rw == MMU_DATA_STORE) {
 258             exception = EXCP_TLBS;
 259         } else {
 260             exception = EXCP_TLBL;
 261         }
 262         break;
 263     case TLBRET_DIRTY:
 264         /* TLB match but 'D' bit is cleared */
 265         exception = EXCP_LTLBL;
 266         break;
 267
 268     }
 269     /* Raise exception */
 270     env->CP0_BadVAddr = address;
 271     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 272                        ((address >> 9) & 0x007ffff0);
 273     env->CP0_EntryHi =
 274         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 275 #if defined(TARGET_MIPS64)
 276     env->CP0_EntryHi &= env->SEGMask;
 277     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 278                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 279                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 280 #endif
 281     cs->exception_index = exception;
 282     env->error_code = error_code;
 283 }
 284
 285 #if !defined(CONFIG_USER_ONLY)
 286 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 287 {
 288     MIPSCPU *cpu = MIPS_CPU(cs);
 289     hwaddr phys_addr;
 290     int prot;
 291
 292     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 293                              ACCESS_INT) != 0) {
 294         return -1;
 295     }
 296     return phys_addr;
 297 }
 298 #endif
 299
 300 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 301                               int mmu_idx)
 302 {
 303     MIPSCPU *cpu = MIPS_CPU(cs);
 304     CPUMIPSState *env = &cpu->env;
 305 #if !defined(CONFIG_USER_ONLY)
 306     hwaddr physical;
 307     int prot;
 308     int access_type;
 309 #endif
 310     int ret = 0;
 311
 312 #if 0
 313     log_cpu_state(cs, 0);
 314 #endif
 315     qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 316               __func__, env->active_tc.PC, address, rw, mmu_idx);
 317
 318     /* data access */
 319 #if !defined(CONFIG_USER_ONLY)
 320     /* XXX: put correct access by using cpu_restore_state()
 321        correctly */
 322     access_type = ACCESS_INT;
 323     ret = get_physical_address(env, &physical, &prot,
 324                                address, rw, access_type);
 325     qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 326              " prot %d\n",
 327              __func__, address, ret, physical, prot);
 328     if (ret == TLBRET_MATCH) {
 329         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 330                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 331                      mmu_idx, TARGET_PAGE_SIZE);
 332         ret = 0;
 333     } else if (ret < 0)
 334 #endif
 335     {
 336         raise_mmu_exception(env, address, rw, ret);
 337         ret = 1;
 338     }
 339
 340     return ret;
 341 }
 342
 343 #if !defined(CONFIG_USER_ONLY)
 344 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 345 {
 346     hwaddr physical;
 347     int prot;
 348     int access_type;
 349     int ret = 0;
 350
 351     /* data access */
 352     access_type = ACCESS_INT;
 353     ret = get_physical_address(env, &physical, &prot,
 354                                address, rw, access_type);
 355     if (ret != TLBRET_MATCH) {
 356         raise_mmu_exception(env, address, rw, ret);
 357         return -1LL;
 358     } else {
 359         return physical;
 360     }
 361 }
 362 #endif
 363
 364 static const char * const excp_names[EXCP_LAST + 1] = {
 365     [EXCP_RESET] = "reset",
 366     [EXCP_SRESET] = "soft reset",
 367     [EXCP_DSS] = "debug single step",
 368     [EXCP_DINT] = "debug interrupt",
 369     [EXCP_NMI] = "non-maskable interrupt",
 370     [EXCP_MCHECK] = "machine check",
 371     [EXCP_EXT_INTERRUPT] = "interrupt",
 372     [EXCP_DFWATCH] = "deferred watchpoint",
 373     [EXCP_DIB] = "debug instruction breakpoint",
 374     [EXCP_IWATCH] = "instruction fetch watchpoint",
 375     [EXCP_AdEL] = "address error load",
 376     [EXCP_AdES] = "address error store",
 377     [EXCP_TLBF] = "TLB refill",
 378     [EXCP_IBE] = "instruction bus error",
 379     [EXCP_DBp] = "debug breakpoint",
 380     [EXCP_SYSCALL] = "syscall",
 381     [EXCP_BREAK] = "break",
 382     [EXCP_CpU] = "coprocessor unusable",
 383     [EXCP_RI] = "reserved instruction",
 384     [EXCP_OVERFLOW] = "arithmetic overflow",
 385     [EXCP_TRAP] = "trap",
 386     [EXCP_FPE] = "floating point",
 387     [EXCP_DDBS] = "debug data break store",
 388     [EXCP_DWATCH] = "data watchpoint",
 389     [EXCP_LTLBL] = "TLB modify",
 390     [EXCP_TLBL] = "TLB load",
 391     [EXCP_TLBS] = "TLB store",
 392     [EXCP_DBE] = "data bus error",
 393     [EXCP_DDBL] = "debug data break load",
 394     [EXCP_THREAD] = "thread",
 395     [EXCP_MDMX] = "MDMX",
 396     [EXCP_C2E] = "precise coprocessor 2",
 397     [EXCP_CACHE] = "cache error",
 398 };
 399
 400 target_ulong exception_resume_pc (CPUMIPSState *env)
 401 {
 402     target_ulong bad_pc;
 403     target_ulong isa_mode;
 404
 405     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 406     bad_pc = env->active_tc.PC | isa_mode;
 407     if (env->hflags & MIPS_HFLAG_BMASK) {
 408         /* If the exception was raised from a delay slot, come back to
 409            the jump.  */
 410         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 411     }
 412
 413     return bad_pc;
 414 }
 415
 416 #if !defined(CONFIG_USER_ONLY)
 417 static void set_hflags_for_handler (CPUMIPSState *env)
 418 {
 419     /* Exception handlers are entered in 32-bit mode.  */
 420     env->hflags &= ~(MIPS_HFLAG_M16);
 421     /* ...except that microMIPS lets you choose.  */
 422     if (env->insn_flags & ASE_MICROMIPS) {
 423         env->hflags |= (!!(env->CP0_Config3
 424                            & (1 << CP0C3_ISA_ON_EXC))
 425                         << MIPS_HFLAG_M16_SHIFT);
 426     }
 427 }
 428 #endif
 429
 430 void mips_cpu_do_interrupt(CPUState *cs)
 431 {
 432 #if !defined(CONFIG_USER_ONLY)
 433     MIPSCPU *cpu = MIPS_CPU(cs);
 434     CPUMIPSState *env = &cpu->env;
 435     target_ulong offset;
 436     int cause = -1;
 437     const char *name;
 438
 439     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 440         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 441             name = "unknown";
 442         } else {
 443             name = excp_names[cs->exception_index];
 444         }
 445
 446         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 447                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 448     }
 449     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 450         (env->hflags & MIPS_HFLAG_DM)) {
 451         cs->exception_index = EXCP_DINT;
 452     }
 453     offset = 0x180;
 454     switch (cs->exception_index) {
 455     case EXCP_DSS:
 456         env->CP0_Debug |= 1 << CP0DB_DSS;
 457         /* Debug single step cannot be raised inside a delay slot and
 458            resume will always occur on the next instruction
 459            (but we assume the pc has always been updated during
 460            code translation). */
 461         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 462         goto enter_debug_mode;
 463     case EXCP_DINT:
 464         env->CP0_Debug |= 1 << CP0DB_DINT;
 465         goto set_DEPC;
 466     case EXCP_DIB:
 467         env->CP0_Debug |= 1 << CP0DB_DIB;
 468         goto set_DEPC;
 469     case EXCP_DBp:
 470         env->CP0_Debug |= 1 << CP0DB_DBp;
 471         goto set_DEPC;
 472     case EXCP_DDBS:
 473         env->CP0_Debug |= 1 << CP0DB_DDBS;
 474         goto set_DEPC;
 475     case EXCP_DDBL:
 476         env->CP0_Debug |= 1 << CP0DB_DDBL;
 477     set_DEPC:
 478         env->CP0_DEPC = exception_resume_pc(env);
 479         env->hflags &= ~MIPS_HFLAG_BMASK;
 480  enter_debug_mode:
 481         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 482         env->hflags &= ~(MIPS_HFLAG_KSU);
 483         /* EJTAG probe trap enable is not implemented... */
 484         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 485             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 486         env->active_tc.PC = (int32_t)0xBFC00480;
 487         set_hflags_for_handler(env);
 488         break;
 489     case EXCP_RESET:
 490         cpu_reset(CPU(cpu));
 491         break;
 492     case EXCP_SRESET:
 493         env->CP0_Status |= (1 << CP0St_SR);
 494         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 495         goto set_error_EPC;
 496     case EXCP_NMI:
 497         env->CP0_Status |= (1 << CP0St_NMI);
 498  set_error_EPC:
 499         env->CP0_ErrorEPC = exception_resume_pc(env);
 500         env->hflags &= ~MIPS_HFLAG_BMASK;
 501         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 502         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 503         env->hflags &= ~(MIPS_HFLAG_KSU);
 504         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 505             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 506         env->active_tc.PC = (int32_t)0xBFC00000;
 507         set_hflags_for_handler(env);
 508         break;
 509     case EXCP_EXT_INTERRUPT:
 510         cause = 0;
 511         if (env->CP0_Cause & (1 << CP0Ca_IV))
 512             offset = 0x200;
 513
 514         if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
 515             /* Vectored Interrupts.  */
 516             unsigned int spacing;
 517             unsigned int vector;
 518             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 519
 520             pending &= env->CP0_Status >> 8;
 521             /* Compute the Vector Spacing.  */
 522             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
 523             spacing <<= 5;
 524
 525             if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
 526                 /* For VInt mode, the MIPS computes the vector internally.  */
 527                 for (vector = 7; vector > 0; vector--) {
 528                     if (pending & (1 << vector)) {
 529                         /* Found it.  */
 530                         break;
 531                     }
 532                 }
 533             } else {
 534                 /* For VEIC mode, the external interrupt controller feeds the
 535                    vector through the CP0Cause IP lines.  */
 536                 vector = pending;
 537             }
 538             offset = 0x200 + vector * spacing;
 539         }
 540         goto set_EPC;
 541     case EXCP_LTLBL:
 542         cause = 1;
 543         goto set_EPC;
 544     case EXCP_TLBL:
 545         cause = 2;
 546         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 547 #if defined(TARGET_MIPS64)
 548             int R = env->CP0_BadVAddr >> 62;
 549             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 550             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 551             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 552
 553             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 554                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 555                 offset = 0x080;
 556             else
 557 #endif
 558                 offset = 0x000;
 559         }
 560         goto set_EPC;
 561     case EXCP_TLBS:
 562         cause = 3;
 563         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 564 #if defined(TARGET_MIPS64)
 565             int R = env->CP0_BadVAddr >> 62;
 566             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 567             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 568             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 569
 570             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 571                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 572                 offset = 0x080;
 573             else
 574 #endif
 575                 offset = 0x000;
 576         }
 577         goto set_EPC;
 578     case EXCP_AdEL:
 579         cause = 4;
 580         goto set_EPC;
 581     case EXCP_AdES:
 582         cause = 5;
 583         goto set_EPC;
 584     case EXCP_IBE:
 585         cause = 6;
 586         goto set_EPC;
 587     case EXCP_DBE:
 588         cause = 7;
 589         goto set_EPC;
 590     case EXCP_SYSCALL:
 591         cause = 8;
 592         goto set_EPC;
 593     case EXCP_BREAK:
 594         cause = 9;
 595         goto set_EPC;
 596     case EXCP_RI:
 597         cause = 10;
 598         goto set_EPC;
 599     case EXCP_CpU:
 600         cause = 11;
 601         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 602                          (env->error_code << CP0Ca_CE);
 603         goto set_EPC;
 604     case EXCP_OVERFLOW:
 605         cause = 12;
 606         goto set_EPC;
 607     case EXCP_TRAP:
 608         cause = 13;
 609         goto set_EPC;
 610     case EXCP_FPE:
 611         cause = 15;
 612         goto set_EPC;
 613     case EXCP_C2E:
 614         cause = 18;
 615         goto set_EPC;
 616     case EXCP_MDMX:
 617         cause = 22;
 618         goto set_EPC;
 619     case EXCP_DWATCH:
 620         cause = 23;
 621         /* XXX: TODO: manage defered watch exceptions */
 622         goto set_EPC;
 623     case EXCP_MCHECK:
 624         cause = 24;
 625         goto set_EPC;
 626     case EXCP_THREAD:
 627         cause = 25;
 628         goto set_EPC;
 629     case EXCP_DSPDIS:
 630         cause = 26;
 631         goto set_EPC;
 632     case EXCP_CACHE:
 633         cause = 30;
 634         if (env->CP0_Status & (1 << CP0St_BEV)) {
 635             offset = 0x100;
 636         } else {
 637             offset = 0x20000100;
 638         }
 639  set_EPC:
 640         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 641             env->CP0_EPC = exception_resume_pc(env);
 642             if (env->hflags & MIPS_HFLAG_BMASK) {
 643                 env->CP0_Cause |= (1U << CP0Ca_BD);
 644             } else {
 645                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 646             }
 647             env->CP0_Status |= (1 << CP0St_EXL);
 648             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 649             env->hflags &= ~(MIPS_HFLAG_KSU);
 650         }
 651         env->hflags &= ~MIPS_HFLAG_BMASK;
 652         if (env->CP0_Status & (1 << CP0St_BEV)) {
 653             env->active_tc.PC = (int32_t)0xBFC00200;
 654         } else {
 655             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 656         }
 657         env->active_tc.PC += offset;
 658         set_hflags_for_handler(env);
 659         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 660         break;
 661     default:
 662         qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 663         printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 664         exit(1);
 665     }
 666     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 667         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 668                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 669                 __func__, env->active_tc.PC, env->CP0_EPC, cause,
 670                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 671                 env->CP0_DEPC);
 672     }
 673 #endif
 674     cs->exception_index = EXCP_NONE;
 675 }
 676
 677 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 678 {
 679     if (interrupt_request & CPU_INTERRUPT_HARD) {
 680         MIPSCPU *cpu = MIPS_CPU(cs);
 681         CPUMIPSState *env = &cpu->env;
 682
 683         if (cpu_mips_hw_interrupts_pending(env)) {
 684             /* Raise it */
 685             cs->exception_index = EXCP_EXT_INTERRUPT;
 686             env->error_code = 0;
 687             mips_cpu_do_interrupt(cs);
 688             return true;
 689         }
 690     }
 691     return false;
 692 }
 693
 694 #if !defined(CONFIG_USER_ONLY)
 695 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 696 {
 697     MIPSCPU *cpu = mips_env_get_cpu(env);
 698     CPUState *cs;
 699     r4k_tlb_t *tlb;
 700     target_ulong addr;
 701     target_ulong end;
 702     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 703     target_ulong mask;
 704
 705     tlb = &env->tlb->mmu.r4k.tlb[idx];
 706     /* The qemu TLB is flushed when the ASID changes, so no need to
 707        flush these entries again.  */
 708     if (tlb->G == 0 && tlb->ASID != ASID) {
 709         return;
 710     }
 711
 712     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 713         /* For tlbwr, we can shadow the discarded entry into
 714            a new (fake) TLB entry, as long as the guest can not
 715            tell that it's there.  */
 716         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 717         env->tlb->tlb_in_use++;
 718         return;
 719     }
 720
 721     /* 1k pages are not supported. */
 722     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 723     if (tlb->V0) {
 724         cs = CPU(cpu);
 725         addr = tlb->VPN & ~mask;
 726 #if defined(TARGET_MIPS64)
 727         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 728             addr |= 0x3FFFFF0000000000ULL;
 729         }
 730 #endif
 731         end = addr | (mask >> 1);
 732         while (addr < end) {
 733             tlb_flush_page(cs, addr);
 734             addr += TARGET_PAGE_SIZE;
 735         }
 736     }
 737     if (tlb->V1) {
 738         cs = CPU(cpu);
 739         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 740 #if defined(TARGET_MIPS64)
 741         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 742             addr |= 0x3FFFFF0000000000ULL;
 743         }
 744 #endif
 745         end = addr | mask;
 746         while (addr - 1 < end) {
 747             tlb_flush_page(cs, addr);
 748             addr += TARGET_PAGE_SIZE;
 749         }
 750     }
 751 }
 752 #endif