target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30
  31 enum {
  32     TLBRET_DIRTY = -4,
  33     TLBRET_INVALID = -3,
  34     TLBRET_NOMATCH = -2,
  35     TLBRET_BADADDR = -1,
  36     TLBRET_MATCH = 0
  37 };
  38
  39 /* MIPS32 4K MMU emulation */
  40 #ifdef MIPS_USES_R4K_TLB
  41 static int map_address (CPUState *env, target_ulong *physical, int *prot,
  42                         target_ulong address, int rw, int access_type)
  43 {
  44     target_ulong tag = address & (TARGET_PAGE_MASK << 1);
  45     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  46     tlb_t *tlb;
  47     int i, n;
  48
  49     for (i = 0; i < env->tlb_in_use; i++) {
  50         tlb = &env->tlb[i];
  51         /* Check ASID, virtual page number & size */
  52         if ((tlb->G == 1 || tlb->ASID == ASID) &&
  53             tlb->VPN == tag) {
  54             /* TLB match */
  55             n = (address >> TARGET_PAGE_BITS) & 1;
  56             /* Check access rights */
  57            if (!(n ? tlb->V1 : tlb->V0))
  58                 return TLBRET_INVALID;
  59            if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  60                 *physical = tlb->PFN[n] | (address & ~TARGET_PAGE_MASK);
  61                 *prot = PAGE_READ;
  62                 if (n ? tlb->D1 : tlb->D0)
  63                     *prot |= PAGE_WRITE;
  64                 return TLBRET_MATCH;
  65             }
  66             return TLBRET_DIRTY;
  67         }
  68     }
  69     return TLBRET_NOMATCH;
  70 }
  71 #endif
  72
  73 static int get_physical_address (CPUState *env, target_ulong *physical,
  74                                 int *prot, target_ulong address,
  75                                 int rw, int access_type)
  76 {
  77     /* User mode can only access useg */
  78     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
  79     int ret = TLBRET_MATCH;
  80
  81 #if 0
  82     if (logfile) {
  83         fprintf(logfile, "user mode %d h %08x\n",
  84                 user_mode, env->hflags);
  85     }
  86 #endif
  87     if (user_mode && address > 0x7FFFFFFFUL)
  88         return TLBRET_BADADDR;
  89     if (address < (int32_t)0x80000000UL) {
  90         if (!(env->hflags & MIPS_HFLAG_ERL)) {
  91 #ifdef MIPS_USES_R4K_TLB
  92             ret = map_address(env, physical, prot, address, rw, access_type);
  93 #else
  94             *physical = address + 0x40000000UL;
  95             *prot = PAGE_READ | PAGE_WRITE;
  96 #endif
  97         } else {
  98             *physical = address;
  99             *prot = PAGE_READ | PAGE_WRITE;
 100         }
 101     } else if (address < (int32_t)0xA0000000UL) {
 102         /* kseg0 */
 103         /* XXX: check supervisor mode */
 104         *physical = address - (int32_t)0x80000000UL;
 105         *prot = PAGE_READ | PAGE_WRITE;
 106     } else if (address < (int32_t)0xC0000000UL) {
 107         /* kseg1 */
 108         /* XXX: check supervisor mode */
 109         *physical = address - (int32_t)0xA0000000UL;
 110         *prot = PAGE_READ | PAGE_WRITE;
 111     } else if (address < (int32_t)0xE0000000UL) {
 112         /* kseg2 */
 113 #ifdef MIPS_USES_R4K_TLB
 114         ret = map_address(env, physical, prot, address, rw, access_type);
 115 #else
 116         *physical = address;
 117         *prot = PAGE_READ | PAGE_WRITE;
 118 #endif
 119     } else {
 120         /* kseg3 */
 121         /* XXX: check supervisor mode */
 122         /* XXX: debug segment is not emulated */
 123 #ifdef MIPS_USES_R4K_TLB
 124         ret = map_address(env, physical, prot, address, rw, access_type);
 125 #else
 126         *physical = address;
 127         *prot = PAGE_READ | PAGE_WRITE;
 128 #endif
 129     }
 130 #if 0
 131     if (logfile) {
 132         fprintf(logfile, TLSZ " %d %d => " TLSZ " %d (%d)\n",
 133                 address, rw, access_type, *physical, *prot, ret);
 134     }
 135 #endif
 136
 137     return ret;
 138 }
 139
 140 #if defined(CONFIG_USER_ONLY)
 141 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 142 {
 143     return addr;
 144 }
 145 #else
 146 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 147 {
 148     target_ulong phys_addr;
 149     int prot;
 150
 151     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 152         return -1;
 153     return phys_addr;
 154 }
 155
 156 void cpu_mips_init_mmu (CPUState *env)
 157 {
 158 }
 159 #endif /* !defined(CONFIG_USER_ONLY) */
 160
 161 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 162                                int is_user, int is_softmmu)
 163 {
 164     target_ulong physical;
 165     int prot;
 166     int exception = 0, error_code = 0;
 167     int access_type;
 168     int ret = 0;
 169
 170     if (logfile) {
 171 #if 0
 172         cpu_dump_state(env, logfile, fprintf, 0);
 173 #endif
 174         fprintf(logfile, "%s pc " TLSZ " ad " TLSZ " rw %d is_user %d smmu %d\n",
 175                 __func__, env->PC, address, rw, is_user, is_softmmu);
 176     }
 177
 178     rw &= 1;
 179
 180     /* data access */
 181     /* XXX: put correct access by using cpu_restore_state()
 182        correctly */
 183     access_type = ACCESS_INT;
 184     if (env->user_mode_only) {
 185         /* user mode only emulation */
 186         ret = TLBRET_NOMATCH;
 187         goto do_fault;
 188     }
 189     ret = get_physical_address(env, &physical, &prot,
 190                                address, rw, access_type);
 191     if (logfile) {
 192         fprintf(logfile, "%s address=" TLSZ " ret %d physical " TLSZ " prot %d\n",
 193                 __func__, address, ret, physical, prot);
 194     }
 195     if (ret == TLBRET_MATCH) {
 196        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
 197                           physical & TARGET_PAGE_MASK, prot,
 198                           is_user, is_softmmu);
 199     } else if (ret < 0) {
 200     do_fault:
 201         switch (ret) {
 202         default:
 203         case TLBRET_BADADDR:
 204             /* Reference to kernel address from user mode or supervisor mode */
 205             /* Reference to supervisor address from user mode */
 206             if (rw)
 207                 exception = EXCP_AdES;
 208             else
 209                 exception = EXCP_AdEL;
 210             break;
 211         case TLBRET_NOMATCH:
 212             /* No TLB match for a mapped address */
 213             if (rw)
 214                 exception = EXCP_TLBS;
 215             else
 216                 exception = EXCP_TLBL;
 217             error_code = 1;
 218             break;
 219         case TLBRET_INVALID:
 220             /* TLB match with no valid bit */
 221             if (rw)
 222                 exception = EXCP_TLBS;
 223             else
 224                 exception = EXCP_TLBL;
 225             break;
 226         case TLBRET_DIRTY:
 227             /* TLB match but 'D' bit is cleared */
 228             exception = EXCP_LTLBL;
 229             break;
 230
 231         }
 232         /* Raise exception */
 233         env->CP0_BadVAddr = address;
 234         env->CP0_Context = (env->CP0_Context & 0xff800000) |
 235                            ((address >> 9) &   0x007ffff0);
 236         env->CP0_EntryHi =
 237             (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 238         env->exception_index = exception;
 239         env->error_code = error_code;
 240         ret = 1;
 241     }
 242
 243     return ret;
 244 }
 245
 246 #if defined(CONFIG_USER_ONLY)
 247 void do_interrupt (CPUState *env)
 248 {
 249     env->exception_index = EXCP_NONE;
 250 }
 251 #else
 252 void do_interrupt (CPUState *env)
 253 {
 254     target_ulong offset;
 255     int cause = -1;
 256
 257     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 258         fprintf(logfile, "%s enter: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n",
 259                 __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
 260     }
 261     if (env->exception_index == EXCP_EXT_INTERRUPT &&
 262         (env->hflags & MIPS_HFLAG_DM))
 263         env->exception_index = EXCP_DINT;
 264     offset = 0x180;
 265     switch (env->exception_index) {
 266     case EXCP_DSS:
 267         env->CP0_Debug |= 1 << CP0DB_DSS;
 268         /* Debug single step cannot be raised inside a delay slot and
 269          * resume will always occur on the next instruction
 270          * (but we assume the pc has always been updated during
 271          *  code translation).
 272          */
 273         env->CP0_DEPC = env->PC;
 274         goto enter_debug_mode;
 275     case EXCP_DINT:
 276         env->CP0_Debug |= 1 << CP0DB_DINT;
 277         goto set_DEPC;
 278     case EXCP_DIB:
 279         env->CP0_Debug |= 1 << CP0DB_DIB;
 280         goto set_DEPC;
 281     case EXCP_DBp:
 282         env->CP0_Debug |= 1 << CP0DB_DBp;
 283         goto set_DEPC;
 284     case EXCP_DDBS:
 285         env->CP0_Debug |= 1 << CP0DB_DDBS;
 286         goto set_DEPC;
 287     case EXCP_DDBL:
 288         env->CP0_Debug |= 1 << CP0DB_DDBL;
 289         goto set_DEPC;
 290     set_DEPC:
 291         if (env->hflags & MIPS_HFLAG_BMASK) {
 292             /* If the exception was raised from a delay slot,
 293                come back to the jump.  */
 294             env->CP0_DEPC = env->PC - 4;
 295             env->hflags &= ~MIPS_HFLAG_BMASK;
 296         } else {
 297             env->CP0_DEPC = env->PC;
 298         }
 299     enter_debug_mode:
 300         env->hflags |= MIPS_HFLAG_DM;
 301         /* EJTAG probe trap enable is not implemented... */
 302         env->PC = (int32_t)0xBFC00480;
 303         break;
 304     case EXCP_RESET:
 305         cpu_reset(env);
 306         break;
 307     case EXCP_SRESET:
 308         env->CP0_Status = (1 << CP0St_SR);
 309         env->CP0_WatchLo = 0;
 310         goto set_error_EPC;
 311     case EXCP_NMI:
 312         env->CP0_Status = (1 << CP0St_NMI);
 313     set_error_EPC:
 314         if (env->hflags & MIPS_HFLAG_BMASK) {
 315             /* If the exception was raised from a delay slot,
 316                come back to the jump.  */
 317             env->CP0_ErrorEPC = env->PC - 4;
 318             env->hflags &= ~MIPS_HFLAG_BMASK;
 319         } else {
 320             env->CP0_ErrorEPC = env->PC;
 321         }
 322         env->hflags |= MIPS_HFLAG_ERL;
 323         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 324         env->PC = (int32_t)0xBFC00000;
 325         break;
 326     case EXCP_MCHECK:
 327         cause = 24;
 328         goto set_EPC;
 329     case EXCP_EXT_INTERRUPT:
 330         cause = 0;
 331         if (env->CP0_Cause & (1 << CP0Ca_IV))
 332             offset = 0x200;
 333         goto set_EPC;
 334     case EXCP_DWATCH:
 335         cause = 23;
 336         /* XXX: TODO: manage defered watch exceptions */
 337         goto set_EPC;
 338     case EXCP_AdEL:
 339     case EXCP_AdES:
 340         cause = 4;
 341         goto set_EPC;
 342     case EXCP_TLBL:
 343         cause = 2;
 344         if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
 345             offset = 0x000;
 346         goto set_EPC;
 347     case EXCP_IBE:
 348         cause = 6;
 349         goto set_EPC;
 350     case EXCP_DBE:
 351         cause = 7;
 352         goto set_EPC;
 353     case EXCP_SYSCALL:
 354         cause = 8;
 355         goto set_EPC;
 356     case EXCP_BREAK:
 357         cause = 9;
 358         goto set_EPC;
 359     case EXCP_RI:
 360         cause = 10;
 361         goto set_EPC;
 362     case EXCP_CpU:
 363         cause = 11;
 364         env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
 365         goto set_EPC;
 366     case EXCP_OVERFLOW:
 367         cause = 12;
 368         goto set_EPC;
 369     case EXCP_TRAP:
 370         cause = 13;
 371         goto set_EPC;
 372     case EXCP_LTLBL:
 373         cause = 1;
 374         goto set_EPC;
 375     case EXCP_TLBS:
 376         cause = 3;
 377         if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
 378             offset = 0x000;
 379         goto set_EPC;
 380     set_EPC:
 381         if (env->hflags & MIPS_HFLAG_BMASK) {
 382             /* If the exception was raised from a delay slot,
 383                come back to the jump.  */
 384             env->CP0_EPC = env->PC - 4;
 385             env->CP0_Cause |= 0x80000000;
 386             env->hflags &= ~MIPS_HFLAG_BMASK;
 387         } else {
 388             env->CP0_EPC = env->PC;
 389             env->CP0_Cause &= ~0x80000000;
 390         }
 391         if (env->CP0_Status & (1 << CP0St_BEV)) {
 392             env->PC = (int32_t)0xBFC00200;
 393         } else {
 394             env->PC = (int32_t)0x80000000;
 395         }
 396         env->hflags |= MIPS_HFLAG_EXL;
 397         env->CP0_Status |= (1 << CP0St_EXL);
 398         env->PC += offset;
 399         env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
 400         break;
 401     default:
 402         if (logfile) {
 403             fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
 404                     env->exception_index);
 405         }
 406         printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 407         exit(1);
 408     }
 409     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 410         fprintf(logfile, "%s: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n"
 411                 "    S %08x C %08x A " TLSZ " D " TLSZ "\n",
 412                 __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
 413                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 414                 env->CP0_DEPC);
 415     }
 416     env->exception_index = EXCP_NONE;
 417 }
 418 #endif /* !defined(CONFIG_USER_ONLY) */
 419
 420 void invalidate_tlb (CPUState *env, int idx, int use_extra)
 421 {
 422     tlb_t *tlb;
 423     uint8_t ASID;
 424
 425     ASID = env->CP0_EntryHi & 0xFF;
 426
 427     tlb = &env->tlb[idx];
 428     /* The qemu TLB is flushed then the ASID changes, so no need to
 429        flush these entries again.  */
 430     if (tlb->G == 0 && tlb->ASID != ASID) {
 431         return;
 432     }
 433
 434     if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
 435         /* For tlbwr, we can shadow the discarded entry into
 436            a new (fake) TLB entry, as long as the guest can not
 437            tell that it's there.  */
 438         env->tlb[env->tlb_in_use] = *tlb;
 439         env->tlb_in_use++;
 440         return;
 441     }
 442
 443     if (tlb->V0)
 444             tlb_flush_page (env, tlb->VPN);
 445     if (tlb->V1)
 446             tlb_flush_page (env, tlb->VPN + TARGET_PAGE_SIZE);
 447 }