target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "exec.h"
  21
  22 /* MIPS32 4K MMU emulation */
  23 #ifdef MIPS_USES_R4K_TLB
  24 static int map_address (CPUState *env, target_ulong *physical, int *prot,
  25                         target_ulong address, int rw, int access_type)
  26 {
  27     tlb_t *tlb;
  28     target_ulong tag;
  29     uint8_t ASID;
  30     int i, n;
  31     int ret;
  32
  33     ret = -2;
  34     tag = (address & 0xFFFFE000);
  35     ASID = env->CP0_EntryHi & 0x000000FF;
  36     for (i = 0; i < 16; i++) {
  37         tlb = &env->tlb[i];
  38         /* Check ASID, virtual page number & size */
  39         if ((tlb->G == 1 || tlb->ASID == ASID) &&
  40             tlb->VPN == tag && address < tlb->end) {
  41             /* TLB match */
  42             n = (address >> 12) & 1;
  43             /* Check access rights */
  44             if ((tlb->V[n] & 2) && (rw == 0 || (tlb->D[n] & 4))) {
  45                 *physical = tlb->PFN[n] | (address & 0xFFF);
  46                 *prot = PAGE_READ;
  47                 if (tlb->D[n])
  48                     *prot |= PAGE_WRITE;
  49                 return 0;
  50             } else if (!(tlb->V[n] & 2)) {
  51                 return -3;
  52             } else {
  53                 return -4;
  54             }
  55         }
  56     }
  57
  58     return ret;
  59 }
  60 #endif
  61
  62 int get_physical_address (CPUState *env, target_ulong *physical, int *prot,
  63                           target_ulong address, int rw, int access_type)
  64 {
  65     int user_mode;
  66     int ret;
  67
  68     /* User mode can only access useg */
  69     user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0;
  70 #if 0
  71     if (logfile) {
  72         fprintf(logfile, "user mode %d h %08x\n",
  73                 user_mode, env->hflags);
  74     }
  75 #endif
  76     if (user_mode && address > 0x7FFFFFFFUL)
  77         return -1;
  78     ret = 0;
  79     if (address < 0x80000000UL) {
  80         if (!(env->hflags & MIPS_HFLAG_ERL)) {
  81 #ifdef MIPS_USES_R4K_TLB
  82             ret = map_address(env, physical, prot, address, rw, access_type);
  83 #else
  84             *physical = address + 0x40000000UL;
  85             *prot = PAGE_READ | PAGE_WRITE;
  86 #endif
  87         } else {
  88             *physical = address;
  89             *prot = PAGE_READ | PAGE_WRITE;
  90         }
  91     } else if (address < 0xA0000000UL) {
  92         /* kseg0 */
  93         /* XXX: check supervisor mode */
  94         *physical = address - 0x80000000UL;
  95         *prot = PAGE_READ | PAGE_WRITE;
  96     } else if (address < 0xC0000000UL) {
  97         /* kseg1 */
  98         /* XXX: check supervisor mode */
  99         *physical = address - 0xA0000000UL;
 100         *prot = PAGE_READ | PAGE_WRITE;
 101     } else if (address < 0xE0000000UL) {
 102         /* kseg2 */
 103 #ifdef MIPS_USES_R4K_TLB
 104         ret = map_address(env, physical, prot, address, rw, access_type);
 105 #else
 106         *physical = address;
 107         *prot = PAGE_READ | PAGE_WRITE;
 108 #endif
 109     } else {
 110         /* kseg3 */
 111         /* XXX: check supervisor mode */
 112         /* XXX: debug segment is not emulated */
 113 #ifdef MIPS_USES_R4K_TLB
 114         ret = map_address(env, physical, prot, address, rw, access_type);
 115 #else
 116         *physical = address;
 117         *prot = PAGE_READ | PAGE_WRITE;
 118 #endif
 119     }
 120 #if 0
 121     if (logfile) {
 122         fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
 123                 access_type, *physical, *prot, ret);
 124     }
 125 #endif
 126
 127     return ret;
 128 }
 129
 130 #if defined(CONFIG_USER_ONLY)
 131 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 132 {
 133     return addr;
 134 }
 135 #else
 136 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 137 {
 138     target_ulong phys_addr;
 139     int prot;
 140
 141     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 142         return -1;
 143     return phys_addr;
 144 }
 145 #endif
 146
 147 #if !defined(CONFIG_USER_ONLY)
 148
 149 #define MMUSUFFIX _mmu
 150 #define GETPC() (__builtin_return_address(0))
 151
 152 #define SHIFT 0
 153 #include "softmmu_template.h"
 154
 155 #define SHIFT 1
 156 #include "softmmu_template.h"
 157
 158 #define SHIFT 2
 159 #include "softmmu_template.h"
 160
 161 #define SHIFT 3
 162 #include "softmmu_template.h"
 163
 164 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
 165 {
 166     TranslationBlock *tb;
 167     CPUState *saved_env;
 168     unsigned long pc;
 169     int ret;
 170
 171     /* XXX: hack to restore env in all cases, even if not called from
 172        generated code */
 173     saved_env = env;
 174     env = cpu_single_env;
 175     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
 176     if (ret) {
 177         if (retaddr) {
 178             /* now we have a real cpu fault */
 179             pc = (unsigned long)retaddr;
 180             tb = tb_find_pc(pc);
 181             if (tb) {
 182                 /* the PC is inside the translated code. It means that we have
 183                    a virtual CPU fault */
 184                 cpu_restore_state(tb, env, pc, NULL);
 185             }
 186         }
 187         do_raise_exception_err(env->exception_index, env->error_code);
 188     }
 189     env = saved_env;
 190 }
 191
 192 void cpu_mips_init_mmu (CPUState *env)
 193 {
 194 }
 195
 196 #endif /* !defined(CONFIG_USER_ONLY) */
 197
 198 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 199                                int is_user, int is_softmmu)
 200 {
 201     target_ulong physical;
 202     int prot;
 203     int exception = 0, error_code = 0;
 204     int access_type;
 205     int ret = 0;
 206
 207     if (logfile) {
 208         cpu_dump_state(env, logfile, fprintf, 0);
 209         fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
 210                 __func__, env->PC, address, rw, is_user, is_softmmu);
 211     }
 212     /* data access */
 213     /* XXX: put correct access by using cpu_restore_state()
 214        correctly */
 215     access_type = ACCESS_INT;
 216     if (env->user_mode_only) {
 217         /* user mode only emulation */
 218         ret = -2;
 219         goto do_fault;
 220     }
 221     ret = get_physical_address(env, &physical, &prot,
 222                                address, rw, access_type);
 223     if (logfile) {
 224         fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
 225                 __func__, address, ret, physical, prot);
 226     }
 227     if (ret == 0) {
 228         ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
 229                            is_user, is_softmmu);
 230     } else if (ret < 0) {
 231     do_fault:
 232         switch (ret) {
 233         default:
 234         case -1:
 235             /* Reference to kernel address from user mode or supervisor mode */
 236             /* Reference to supervisor address from user mode */
 237             if (rw)
 238                 exception = EXCP_AdES;
 239             else
 240                 exception = EXCP_AdEL;
 241             break;
 242         case -2:
 243             /* No TLB match for a mapped address */
 244             if (rw)
 245                 exception = EXCP_TLBS;
 246             else
 247                 exception = EXCP_TLBL;
 248             error_code = 1;
 249             break;
 250         case -3:
 251             /* TLB match with no valid bit */
 252             if (rw)
 253                 exception = EXCP_TLBS;
 254             else
 255                 exception = EXCP_TLBL;
 256             error_code = 0;
 257             break;
 258         case -4:
 259             /* TLB match but 'D' bit is cleared */
 260             exception = EXCP_LTLBL;
 261             break;
 262
 263         }
 264         /* Raise exception */
 265         env->CP0_BadVAddr = address;
 266         env->CP0_Context =
 267             (env->CP0_Context & 0x00000FFF) | (address & 0xFFFFF000);
 268         env->CP0_EntryHi =
 269             (env->CP0_EntryHi & 0x00000FFF) | (address & 0xFFFFF000);
 270         env->exception_index = exception;
 271         env->error_code = error_code;
 272         ret = 1;
 273     }
 274
 275     return ret;
 276 }
 277
 278 void do_interrupt (CPUState *env)
 279 {
 280     target_ulong pc, offset;
 281     int cause = -1;
 282
 283     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 284         fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
 285                 __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
 286     }
 287     if (env->exception_index == EXCP_EXT_INTERRUPT &&
 288         (env->hflags & MIPS_HFLAG_DM))
 289         env->exception_index = EXCP_DINT;
 290     offset = 0x180;
 291     switch (env->exception_index) {
 292     case EXCP_DSS:
 293         env->CP0_Debug |= 1 << CP0DB_DSS;
 294         /* Debug single step cannot be raised inside a delay slot and
 295          * resume will always occur on the next instruction
 296          * (but we assume the pc has always been updated during
 297          *  code translation).
 298          */
 299         env->CP0_DEPC = env->PC;
 300         goto enter_debug_mode;
 301     case EXCP_DINT:
 302         env->CP0_Debug |= 1 << CP0DB_DINT;
 303         goto set_DEPC;
 304     case EXCP_DIB:
 305         env->CP0_Debug |= 1 << CP0DB_DIB;
 306         goto set_DEPC;
 307     case EXCP_DBp:
 308         env->CP0_Debug |= 1 << CP0DB_DBp;
 309         goto set_DEPC;
 310     case EXCP_DDBS:
 311         env->CP0_Debug |= 1 << CP0DB_DDBS;
 312         goto set_DEPC;
 313     case EXCP_DDBL:
 314         env->CP0_Debug |= 1 << CP0DB_DDBL;
 315         goto set_DEPC;
 316     set_DEPC:
 317         if (env->hflags & MIPS_HFLAG_DS) {
 318             /* If the exception was raised from a delay slot,
 319              * come back to the jump
 320              */
 321             env->CP0_DEPC = env->PC - 4;
 322         } else {
 323             env->CP0_DEPC = env->PC;
 324         }
 325     enter_debug_mode:
 326         env->hflags |= MIPS_HFLAG_DM;
 327         /* EJTAG probe trap enable is not implemented... */
 328         pc = 0xBFC00480;
 329         break;
 330     case EXCP_RESET:
 331 #ifdef MIPS_USES_R4K_TLB
 332         env->CP0_random = MIPS_TLB_NB - 1;
 333 #endif
 334         env->CP0_Wired = 0;
 335         env->CP0_Config0 = MIPS_CONFIG0;
 336 #if defined (MIPS_CONFIG1)
 337         env->CP0_Config1 = MIPS_CONFIG1;
 338 #endif
 339 #if defined (MIPS_CONFIG2)
 340         env->CP0_Config2 = MIPS_CONFIG2;
 341 #endif
 342 #if defined (MIPS_CONFIG3)
 343         env->CP0_Config3 = MIPS_CONFIG3;
 344 #endif
 345         env->CP0_WatchLo = 0;
 346         env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
 347         goto set_error_EPC;
 348     case EXCP_SRESET:
 349         env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
 350             (1 << CP0St_SR);
 351         env->CP0_WatchLo = 0;
 352         goto set_error_EPC;
 353     case EXCP_NMI:
 354         env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
 355             (1 << CP0St_NMI);
 356     set_error_EPC:
 357         env->hflags = MIPS_HFLAG_ERL;
 358         if (env->hflags & MIPS_HFLAG_DS) {
 359             /* If the exception was raised from a delay slot,
 360              * come back to the jump
 361              */
 362             env->CP0_ErrorEPC = env->PC - 4;
 363         } else {
 364             env->CP0_ErrorEPC = env->PC;
 365         }
 366         pc = 0xBFC00000;
 367         break;
 368     case EXCP_MCHECK:
 369         cause = 24;
 370         goto set_EPC;
 371     case EXCP_EXT_INTERRUPT:
 372         cause = 0;
 373         if (env->CP0_Cause & (1 << CP0Ca_IV))
 374             offset = 0x200;
 375         goto set_EPC;
 376     case EXCP_DWATCH:
 377         cause = 23;
 378         /* XXX: TODO: manage defered watch exceptions */
 379         goto set_EPC;
 380     case EXCP_AdEL:
 381     case EXCP_AdES:
 382         cause = 4;
 383         goto set_EPC;
 384     case EXCP_TLBL:
 385     case EXCP_TLBF:
 386         cause = 2;
 387         if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
 388             offset = 0x000;
 389         goto set_EPC;
 390     case EXCP_IBE:
 391         cause = 6;
 392         goto set_EPC;
 393     case EXCP_DBE:
 394         cause = 7;
 395         goto set_EPC;
 396     case EXCP_SYSCALL:
 397         cause = 8;
 398         goto set_EPC;
 399     case EXCP_BREAK:
 400         cause = 9;
 401         goto set_EPC;
 402     case EXCP_RI:
 403         cause = 10;
 404         goto set_EPC;
 405     case EXCP_CpU:
 406         cause = 11;
 407         /* XXX: fill in the faulty unit number */
 408         goto set_EPC;
 409     case EXCP_OVERFLOW:
 410         cause = 12;
 411         goto set_EPC;
 412     case EXCP_TRAP:
 413         cause = 13;
 414         goto set_EPC;
 415     case EXCP_LTLBL:
 416         cause = 1;
 417         goto set_EPC;
 418     case EXCP_TLBS:
 419         cause = 3;
 420     set_EPC:
 421         if (env->CP0_Status & (1 << CP0St_BEV)) {
 422             pc = 0xBFC00200;
 423         } else {
 424             pc = 0x80000000;
 425         }
 426         env->hflags |= MIPS_HFLAG_EXL;
 427         pc += offset;
 428         env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
 429         if (env->hflags & MIPS_HFLAG_DS) {
 430             /* If the exception was raised from a delay slot,
 431              * come back to the jump
 432              */
 433             env->CP0_EPC = env->PC - 4;
 434             env->CP0_Cause |= 0x80000000;
 435         } else {
 436             env->CP0_EPC = env->PC;
 437             env->CP0_Cause &= ~0x80000000;
 438         }
 439         break;
 440     default:
 441         if (logfile) {
 442             fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
 443                     env->exception_index);
 444         }
 445         printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 446         exit(1);
 447     }
 448     env->PC = pc;
 449     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 450         fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
 451                 "    S %08x C %08x A %08x D %08x\n",
 452                 __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
 453                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 454                 env->CP0_DEPC);
 455     }
 456     env->exception_index = EXCP_NONE;
 457 }