target-mips/kvm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012-2014 Imagination Technologies Ltd.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10 */
  11
  12 #include "qemu/osdep.h"
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/error-report.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/kvm.h"
  23 #include "cpu.h"
  24 #include "sysemu/cpus.h"
  25 #include "kvm_mips.h"
  26 #include "exec/memattrs.h"
  27
  28 #define DEBUG_KVM 0
  29
  30 #define DPRINTF(fmt, ...) \
  31     do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
  32
  33 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  34     KVM_CAP_LAST_INFO
  35 };
  36
  37 static void kvm_mips_update_state(void *opaque, int running, RunState state);
  38
  39 unsigned long kvm_arch_vcpu_id(CPUState *cs)
  40 {
  41     return cs->cpu_index;
  42 }
  43
  44 int kvm_arch_init(MachineState *ms, KVMState *s)
  45 {
  46     /* MIPS has 128 signals */
  47     kvm_set_sigmask_len(s, 16);
  48
  49     DPRINTF("%s\n", __func__);
  50     return 0;
  51 }
  52
  53 int kvm_arch_init_vcpu(CPUState *cs)
  54 {
  55     int ret = 0;
  56
  57     qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
  58
  59     DPRINTF("%s\n", __func__);
  60     return ret;
  61 }
  62
  63 void kvm_mips_reset_vcpu(MIPSCPU *cpu)
  64 {
  65     CPUMIPSState *env = &cpu->env;
  66
  67     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
  68         fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n");
  69         env->CP0_Config1 &= ~(1 << CP0C1_FP);
  70     }
  71
  72     DPRINTF("%s\n", __func__);
  73 }
  74
  75 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  76 {
  77     DPRINTF("%s\n", __func__);
  78     return 0;
  79 }
  80
  81 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  82 {
  83     DPRINTF("%s\n", __func__);
  84     return 0;
  85 }
  86
  87 static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
  88 {
  89     CPUMIPSState *env = &cpu->env;
  90
  91     return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
  92 }
  93
  94
  95 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
  96 {
  97     MIPSCPU *cpu = MIPS_CPU(cs);
  98     int r;
  99     struct kvm_mips_interrupt intr;
 100
 101     qemu_mutex_lock_iothread();
 102
 103     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 104             cpu_mips_io_interrupts_pending(cpu)) {
 105         intr.cpu = -1;
 106         intr.irq = 2;
 107         r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 108         if (r < 0) {
 109             error_report("%s: cpu %d: failed to inject IRQ %x",
 110                          __func__, cs->cpu_index, intr.irq);
 111         }
 112     }
 113
 114     qemu_mutex_unlock_iothread();
 115 }
 116
 117 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 118 {
 119     return MEMTXATTRS_UNSPECIFIED;
 120 }
 121
 122 int kvm_arch_process_async_events(CPUState *cs)
 123 {
 124     return cs->halted;
 125 }
 126
 127 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 128 {
 129     int ret;
 130
 131     DPRINTF("%s\n", __func__);
 132     switch (run->exit_reason) {
 133     default:
 134         error_report("%s: unknown exit reason %d",
 135                      __func__, run->exit_reason);
 136         ret = -1;
 137         break;
 138     }
 139
 140     return ret;
 141 }
 142
 143 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 144 {
 145     DPRINTF("%s\n", __func__);
 146     return true;
 147 }
 148
 149 int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
 150 {
 151     DPRINTF("%s\n", __func__);
 152     return 1;
 153 }
 154
 155 int kvm_arch_on_sigbus(int code, void *addr)
 156 {
 157     DPRINTF("%s\n", __func__);
 158     return 1;
 159 }
 160
 161 void kvm_arch_init_irq_routing(KVMState *s)
 162 {
 163 }
 164
 165 int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
 166 {
 167     CPUState *cs = CPU(cpu);
 168     struct kvm_mips_interrupt intr;
 169
 170     if (!kvm_enabled()) {
 171         return 0;
 172     }
 173
 174     intr.cpu = -1;
 175
 176     if (level) {
 177         intr.irq = irq;
 178     } else {
 179         intr.irq = -irq;
 180     }
 181
 182     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 183
 184     return 0;
 185 }
 186
 187 int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
 188 {
 189     CPUState *cs = current_cpu;
 190     CPUState *dest_cs = CPU(cpu);
 191     struct kvm_mips_interrupt intr;
 192
 193     if (!kvm_enabled()) {
 194         return 0;
 195     }
 196
 197     intr.cpu = dest_cs->cpu_index;
 198
 199     if (level) {
 200         intr.irq = irq;
 201     } else {
 202         intr.irq = -irq;
 203     }
 204
 205     DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
 206
 207     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 208
 209     return 0;
 210 }
 211
 212 #define MIPS_CP0_32(_R, _S)                                     \
 213     (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
 214
 215 #define MIPS_CP0_64(_R, _S)                                     \
 216     (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
 217
 218 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
 219 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
 220 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
 221 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
 222 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
 223 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
 224 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
 225 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
 226 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
 227 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
 228 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
 229 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
 230 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
 231 #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
 232 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
 233 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
 234 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
 235 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
 236 #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
 237 #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
 238 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 239
 240 static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
 241                                        int32_t *addr)
 242 {
 243     struct kvm_one_reg cp0reg = {
 244         .id = reg_id,
 245         .addr = (uintptr_t)addr
 246     };
 247
 248     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 249 }
 250
 251 static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id,
 252                                         uint32_t *addr)
 253 {
 254     struct kvm_one_reg cp0reg = {
 255         .id = reg_id,
 256         .addr = (uintptr_t)addr
 257     };
 258
 259     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 260 }
 261
 262 static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
 263                                          target_ulong *addr)
 264 {
 265     uint64_t val64 = *addr;
 266     struct kvm_one_reg cp0reg = {
 267         .id = reg_id,
 268         .addr = (uintptr_t)&val64
 269     };
 270
 271     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 272 }
 273
 274 static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
 275                                          uint64_t *addr)
 276 {
 277     struct kvm_one_reg cp0reg = {
 278         .id = reg_id,
 279         .addr = (uintptr_t)addr
 280     };
 281
 282     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 283 }
 284
 285 static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
 286                                        int32_t *addr)
 287 {
 288     struct kvm_one_reg cp0reg = {
 289         .id = reg_id,
 290         .addr = (uintptr_t)addr
 291     };
 292
 293     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 294 }
 295
 296 static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id,
 297                                         uint32_t *addr)
 298 {
 299     struct kvm_one_reg cp0reg = {
 300         .id = reg_id,
 301         .addr = (uintptr_t)addr
 302     };
 303
 304     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 305 }
 306
 307 static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id,
 308                                          target_ulong *addr)
 309 {
 310     int ret;
 311     uint64_t val64 = 0;
 312     struct kvm_one_reg cp0reg = {
 313         .id = reg_id,
 314         .addr = (uintptr_t)&val64
 315     };
 316
 317     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 318     if (ret >= 0) {
 319         *addr = val64;
 320     }
 321     return ret;
 322 }
 323
 324 static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id,
 325                                          uint64_t *addr)
 326 {
 327     struct kvm_one_reg cp0reg = {
 328         .id = reg_id,
 329         .addr = (uintptr_t)addr
 330     };
 331
 332     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 333 }
 334
 335 #define KVM_REG_MIPS_CP0_CONFIG_MASK    (1U << CP0C0_M)
 336 #define KVM_REG_MIPS_CP0_CONFIG1_MASK   (1U << CP0C1_M)
 337 #define KVM_REG_MIPS_CP0_CONFIG2_MASK   (1U << CP0C2_M)
 338 #define KVM_REG_MIPS_CP0_CONFIG3_MASK   (1U << CP0C3_M)
 339 #define KVM_REG_MIPS_CP0_CONFIG4_MASK   (1U << CP0C4_M)
 340 #define KVM_REG_MIPS_CP0_CONFIG5_MASK   0
 341
 342 static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id,
 343                                           int32_t *addr, int32_t mask)
 344 {
 345     int err;
 346     int32_t tmp, change;
 347
 348     err = kvm_mips_get_one_reg(cs, reg_id, &tmp);
 349     if (err < 0) {
 350         return err;
 351     }
 352
 353     /* only change bits in mask */
 354     change = (*addr ^ tmp) & mask;
 355     if (!change) {
 356         return 0;
 357     }
 358
 359     tmp = tmp ^ change;
 360     return kvm_mips_put_one_reg(cs, reg_id, &tmp);
 361 }
 362
 363 /*
 364  * We freeze the KVM timer when either the VM clock is stopped or the state is
 365  * saved (the state is dirty).
 366  */
 367
 368 /*
 369  * Save the state of the KVM timer when VM clock is stopped or state is synced
 370  * to QEMU.
 371  */
 372 static int kvm_mips_save_count(CPUState *cs)
 373 {
 374     MIPSCPU *cpu = MIPS_CPU(cs);
 375     CPUMIPSState *env = &cpu->env;
 376     uint64_t count_ctl;
 377     int err, ret = 0;
 378
 379     /* freeze KVM timer */
 380     err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 381     if (err < 0) {
 382         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
 383         ret = err;
 384     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 385         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 386         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 387         if (err < 0) {
 388             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 389             ret = err;
 390         }
 391     }
 392
 393     /* read CP0_Cause */
 394     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 395     if (err < 0) {
 396         DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
 397         ret = err;
 398     }
 399
 400     /* read CP0_Count */
 401     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 402     if (err < 0) {
 403         DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
 404         ret = err;
 405     }
 406
 407     return ret;
 408 }
 409
 410 /*
 411  * Restore the state of the KVM timer when VM clock is restarted or state is
 412  * synced to KVM.
 413  */
 414 static int kvm_mips_restore_count(CPUState *cs)
 415 {
 416     MIPSCPU *cpu = MIPS_CPU(cs);
 417     CPUMIPSState *env = &cpu->env;
 418     uint64_t count_ctl;
 419     int err_dc, err, ret = 0;
 420
 421     /* check the timer is frozen */
 422     err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 423     if (err_dc < 0) {
 424         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
 425         ret = err_dc;
 426     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 427         /* freeze timer (sets COUNT_RESUME for us) */
 428         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 429         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 430         if (err < 0) {
 431             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 432             ret = err;
 433         }
 434     }
 435
 436     /* load CP0_Cause */
 437     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 438     if (err < 0) {
 439         DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
 440         ret = err;
 441     }
 442
 443     /* load CP0_Count */
 444     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 445     if (err < 0) {
 446         DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
 447         ret = err;
 448     }
 449
 450     /* resume KVM timer */
 451     if (err_dc >= 0) {
 452         count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
 453         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 454         if (err < 0) {
 455             DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
 456             ret = err;
 457         }
 458     }
 459
 460     return ret;
 461 }
 462
 463 /*
 464  * Handle the VM clock being started or stopped
 465  */
 466 static void kvm_mips_update_state(void *opaque, int running, RunState state)
 467 {
 468     CPUState *cs = opaque;
 469     int ret;
 470     uint64_t count_resume;
 471
 472     /*
 473      * If state is already dirty (synced to QEMU) then the KVM timer state is
 474      * already saved and can be restored when it is synced back to KVM.
 475      */
 476     if (!running) {
 477         if (!cs->kvm_vcpu_dirty) {
 478             ret = kvm_mips_save_count(cs);
 479             if (ret < 0) {
 480                 fprintf(stderr, "Failed saving count\n");
 481             }
 482         }
 483     } else {
 484         /* Set clock restore time to now */
 485         count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
 486         ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
 487                                      &count_resume);
 488         if (ret < 0) {
 489             fprintf(stderr, "Failed setting COUNT_RESUME\n");
 490             return;
 491         }
 492
 493         if (!cs->kvm_vcpu_dirty) {
 494             ret = kvm_mips_restore_count(cs);
 495             if (ret < 0) {
 496                 fprintf(stderr, "Failed restoring count\n");
 497             }
 498         }
 499     }
 500 }
 501
 502 static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
 503 {
 504     MIPSCPU *cpu = MIPS_CPU(cs);
 505     CPUMIPSState *env = &cpu->env;
 506     int err, ret = 0;
 507
 508     (void)level;
 509
 510     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 511     if (err < 0) {
 512         DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
 513         ret = err;
 514     }
 515     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 516                                  &env->CP0_Context);
 517     if (err < 0) {
 518         DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
 519         ret = err;
 520     }
 521     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 522                                  &env->active_tc.CP0_UserLocal);
 523     if (err < 0) {
 524         DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
 525         ret = err;
 526     }
 527     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 528                                &env->CP0_PageMask);
 529     if (err < 0) {
 530         DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
 531         ret = err;
 532     }
 533     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 534     if (err < 0) {
 535         DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
 536         ret = err;
 537     }
 538     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 539     if (err < 0) {
 540         DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
 541         ret = err;
 542     }
 543     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 544                                  &env->CP0_BadVAddr);
 545     if (err < 0) {
 546         DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
 547         ret = err;
 548     }
 549
 550     /* If VM clock stopped then state will be restored when it is restarted */
 551     if (runstate_is_running()) {
 552         err = kvm_mips_restore_count(cs);
 553         if (err < 0) {
 554             ret = err;
 555         }
 556     }
 557
 558     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 559                                  &env->CP0_EntryHi);
 560     if (err < 0) {
 561         DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
 562         ret = err;
 563     }
 564     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 565                                &env->CP0_Compare);
 566     if (err < 0) {
 567         DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
 568         ret = err;
 569     }
 570     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 571     if (err < 0) {
 572         DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
 573         ret = err;
 574     }
 575     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 576     if (err < 0) {
 577         DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
 578         ret = err;
 579     }
 580     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
 581     if (err < 0) {
 582         DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err);
 583         ret = err;
 584     }
 585     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG,
 586                                   &env->CP0_Config0,
 587                                   KVM_REG_MIPS_CP0_CONFIG_MASK);
 588     if (err < 0) {
 589         DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err);
 590         ret = err;
 591     }
 592     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1,
 593                                   &env->CP0_Config1,
 594                                   KVM_REG_MIPS_CP0_CONFIG1_MASK);
 595     if (err < 0) {
 596         DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err);
 597         ret = err;
 598     }
 599     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2,
 600                                   &env->CP0_Config2,
 601                                   KVM_REG_MIPS_CP0_CONFIG2_MASK);
 602     if (err < 0) {
 603         DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err);
 604         ret = err;
 605     }
 606     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3,
 607                                   &env->CP0_Config3,
 608                                   KVM_REG_MIPS_CP0_CONFIG3_MASK);
 609     if (err < 0) {
 610         DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err);
 611         ret = err;
 612     }
 613     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4,
 614                                   &env->CP0_Config4,
 615                                   KVM_REG_MIPS_CP0_CONFIG4_MASK);
 616     if (err < 0) {
 617         DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err);
 618         ret = err;
 619     }
 620     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5,
 621                                   &env->CP0_Config5,
 622                                   KVM_REG_MIPS_CP0_CONFIG5_MASK);
 623     if (err < 0) {
 624         DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err);
 625         ret = err;
 626     }
 627     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 628                                  &env->CP0_ErrorEPC);
 629     if (err < 0) {
 630         DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
 631         ret = err;
 632     }
 633
 634     return ret;
 635 }
 636
 637 static int kvm_mips_get_cp0_registers(CPUState *cs)
 638 {
 639     MIPSCPU *cpu = MIPS_CPU(cs);
 640     CPUMIPSState *env = &cpu->env;
 641     int err, ret = 0;
 642
 643     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 644     if (err < 0) {
 645         DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
 646         ret = err;
 647     }
 648     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 649                                  &env->CP0_Context);
 650     if (err < 0) {
 651         DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
 652         ret = err;
 653     }
 654     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 655                                  &env->active_tc.CP0_UserLocal);
 656     if (err < 0) {
 657         DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
 658         ret = err;
 659     }
 660     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 661                                &env->CP0_PageMask);
 662     if (err < 0) {
 663         DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
 664         ret = err;
 665     }
 666     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 667     if (err < 0) {
 668         DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
 669         ret = err;
 670     }
 671     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 672     if (err < 0) {
 673         DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
 674         ret = err;
 675     }
 676     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 677                                  &env->CP0_BadVAddr);
 678     if (err < 0) {
 679         DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
 680         ret = err;
 681     }
 682     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 683                                  &env->CP0_EntryHi);
 684     if (err < 0) {
 685         DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
 686         ret = err;
 687     }
 688     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 689                                &env->CP0_Compare);
 690     if (err < 0) {
 691         DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
 692         ret = err;
 693     }
 694     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 695     if (err < 0) {
 696         DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
 697         ret = err;
 698     }
 699
 700     /* If VM clock stopped then state was already saved when it was stopped */
 701     if (runstate_is_running()) {
 702         err = kvm_mips_save_count(cs);
 703         if (err < 0) {
 704             ret = err;
 705         }
 706     }
 707
 708     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 709     if (err < 0) {
 710         DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
 711         ret = err;
 712     }
 713     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
 714     if (err < 0) {
 715         DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err);
 716         ret = err;
 717     }
 718     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0);
 719     if (err < 0) {
 720         DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err);
 721         ret = err;
 722     }
 723     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1);
 724     if (err < 0) {
 725         DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err);
 726         ret = err;
 727     }
 728     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2);
 729     if (err < 0) {
 730         DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err);
 731         ret = err;
 732     }
 733     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3);
 734     if (err < 0) {
 735         DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err);
 736         ret = err;
 737     }
 738     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4);
 739     if (err < 0) {
 740         DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err);
 741         ret = err;
 742     }
 743     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5);
 744     if (err < 0) {
 745         DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err);
 746         ret = err;
 747     }
 748     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 749                                  &env->CP0_ErrorEPC);
 750     if (err < 0) {
 751         DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
 752         ret = err;
 753     }
 754
 755     return ret;
 756 }
 757
 758 int kvm_arch_put_registers(CPUState *cs, int level)
 759 {
 760     MIPSCPU *cpu = MIPS_CPU(cs);
 761     CPUMIPSState *env = &cpu->env;
 762     struct kvm_regs regs;
 763     int ret;
 764     int i;
 765
 766     /* Set the registers based on QEMU's view of things */
 767     for (i = 0; i < 32; i++) {
 768         regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i];
 769     }
 770
 771     regs.hi = (int64_t)(target_long)env->active_tc.HI[0];
 772     regs.lo = (int64_t)(target_long)env->active_tc.LO[0];
 773     regs.pc = (int64_t)(target_long)env->active_tc.PC;
 774
 775     ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
 776
 777     if (ret < 0) {
 778         return ret;
 779     }
 780
 781     ret = kvm_mips_put_cp0_registers(cs, level);
 782     if (ret < 0) {
 783         return ret;
 784     }
 785
 786     return ret;
 787 }
 788
 789 int kvm_arch_get_registers(CPUState *cs)
 790 {
 791     MIPSCPU *cpu = MIPS_CPU(cs);
 792     CPUMIPSState *env = &cpu->env;
 793     int ret = 0;
 794     struct kvm_regs regs;
 795     int i;
 796
 797     /* Get the current register set as KVM seems it */
 798     ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
 799
 800     if (ret < 0) {
 801         return ret;
 802     }
 803
 804     for (i = 0; i < 32; i++) {
 805         env->active_tc.gpr[i] = regs.gpr[i];
 806     }
 807
 808     env->active_tc.HI[0] = regs.hi;
 809     env->active_tc.LO[0] = regs.lo;
 810     env->active_tc.PC = regs.pc;
 811
 812     kvm_mips_get_cp0_registers(cs);
 813
 814     return ret;
 815 }
 816
 817 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 818                              uint64_t address, uint32_t data, PCIDevice *dev)
 819 {
 820     return 0;
 821 }
 822
 823 int kvm_arch_msi_data_to_gsi(uint32_t data)
 824 {
 825     abort();
 826 }