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[qemu.git] / target-mips / op.c
1 /*
2 * MIPS emulation micro-operations for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include "config.h"
23 #include "exec.h"
24
25 #ifndef CALL_FROM_TB0
26 #define CALL_FROM_TB0(func) func();
27 #endif
28 #ifndef CALL_FROM_TB1
29 #define CALL_FROM_TB1(func, arg0) func(arg0);
30 #endif
31 #ifndef CALL_FROM_TB1_CONST16
32 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
33 #endif
34 #ifndef CALL_FROM_TB2
35 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
36 #endif
37 #ifndef CALL_FROM_TB2_CONST16
38 #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
39 CALL_FROM_TB2(func, arg0, arg1);
40 #endif
41 #ifndef CALL_FROM_TB3
42 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
43 #endif
44 #ifndef CALL_FROM_TB4
45 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
46 func(arg0, arg1, arg2, arg3);
47 #endif
48
49 #define REG 1
50 #include "op_template.c"
51 #undef REG
52 #define REG 2
53 #include "op_template.c"
54 #undef REG
55 #define REG 3
56 #include "op_template.c"
57 #undef REG
58 #define REG 4
59 #include "op_template.c"
60 #undef REG
61 #define REG 5
62 #include "op_template.c"
63 #undef REG
64 #define REG 6
65 #include "op_template.c"
66 #undef REG
67 #define REG 7
68 #include "op_template.c"
69 #undef REG
70 #define REG 8
71 #include "op_template.c"
72 #undef REG
73 #define REG 9
74 #include "op_template.c"
75 #undef REG
76 #define REG 10
77 #include "op_template.c"
78 #undef REG
79 #define REG 11
80 #include "op_template.c"
81 #undef REG
82 #define REG 12
83 #include "op_template.c"
84 #undef REG
85 #define REG 13
86 #include "op_template.c"
87 #undef REG
88 #define REG 14
89 #include "op_template.c"
90 #undef REG
91 #define REG 15
92 #include "op_template.c"
93 #undef REG
94 #define REG 16
95 #include "op_template.c"
96 #undef REG
97 #define REG 17
98 #include "op_template.c"
99 #undef REG
100 #define REG 18
101 #include "op_template.c"
102 #undef REG
103 #define REG 19
104 #include "op_template.c"
105 #undef REG
106 #define REG 20
107 #include "op_template.c"
108 #undef REG
109 #define REG 21
110 #include "op_template.c"
111 #undef REG
112 #define REG 22
113 #include "op_template.c"
114 #undef REG
115 #define REG 23
116 #include "op_template.c"
117 #undef REG
118 #define REG 24
119 #include "op_template.c"
120 #undef REG
121 #define REG 25
122 #include "op_template.c"
123 #undef REG
124 #define REG 26
125 #include "op_template.c"
126 #undef REG
127 #define REG 27
128 #include "op_template.c"
129 #undef REG
130 #define REG 28
131 #include "op_template.c"
132 #undef REG
133 #define REG 29
134 #include "op_template.c"
135 #undef REG
136 #define REG 30
137 #include "op_template.c"
138 #undef REG
139 #define REG 31
140 #include "op_template.c"
141 #undef REG
142
143 #define TN
144 #include "op_template.c"
145 #undef TN
146
147 #define SFREG 0
148 #define DFREG 0
149 #include "fop_template.c"
150 #undef SFREG
151 #undef DFREG
152 #define SFREG 1
153 #include "fop_template.c"
154 #undef SFREG
155 #define SFREG 2
156 #define DFREG 2
157 #include "fop_template.c"
158 #undef SFREG
159 #undef DFREG
160 #define SFREG 3
161 #include "fop_template.c"
162 #undef SFREG
163 #define SFREG 4
164 #define DFREG 4
165 #include "fop_template.c"
166 #undef SFREG
167 #undef DFREG
168 #define SFREG 5
169 #include "fop_template.c"
170 #undef SFREG
171 #define SFREG 6
172 #define DFREG 6
173 #include "fop_template.c"
174 #undef SFREG
175 #undef DFREG
176 #define SFREG 7
177 #include "fop_template.c"
178 #undef SFREG
179 #define SFREG 8
180 #define DFREG 8
181 #include "fop_template.c"
182 #undef SFREG
183 #undef DFREG
184 #define SFREG 9
185 #include "fop_template.c"
186 #undef SFREG
187 #define SFREG 10
188 #define DFREG 10
189 #include "fop_template.c"
190 #undef SFREG
191 #undef DFREG
192 #define SFREG 11
193 #include "fop_template.c"
194 #undef SFREG
195 #define SFREG 12
196 #define DFREG 12
197 #include "fop_template.c"
198 #undef SFREG
199 #undef DFREG
200 #define SFREG 13
201 #include "fop_template.c"
202 #undef SFREG
203 #define SFREG 14
204 #define DFREG 14
205 #include "fop_template.c"
206 #undef SFREG
207 #undef DFREG
208 #define SFREG 15
209 #include "fop_template.c"
210 #undef SFREG
211 #define SFREG 16
212 #define DFREG 16
213 #include "fop_template.c"
214 #undef SFREG
215 #undef DFREG
216 #define SFREG 17
217 #include "fop_template.c"
218 #undef SFREG
219 #define SFREG 18
220 #define DFREG 18
221 #include "fop_template.c"
222 #undef SFREG
223 #undef DFREG
224 #define SFREG 19
225 #include "fop_template.c"
226 #undef SFREG
227 #define SFREG 20
228 #define DFREG 20
229 #include "fop_template.c"
230 #undef SFREG
231 #undef DFREG
232 #define SFREG 21
233 #include "fop_template.c"
234 #undef SFREG
235 #define SFREG 22
236 #define DFREG 22
237 #include "fop_template.c"
238 #undef SFREG
239 #undef DFREG
240 #define SFREG 23
241 #include "fop_template.c"
242 #undef SFREG
243 #define SFREG 24
244 #define DFREG 24
245 #include "fop_template.c"
246 #undef SFREG
247 #undef DFREG
248 #define SFREG 25
249 #include "fop_template.c"
250 #undef SFREG
251 #define SFREG 26
252 #define DFREG 26
253 #include "fop_template.c"
254 #undef SFREG
255 #undef DFREG
256 #define SFREG 27
257 #include "fop_template.c"
258 #undef SFREG
259 #define SFREG 28
260 #define DFREG 28
261 #include "fop_template.c"
262 #undef SFREG
263 #undef DFREG
264 #define SFREG 29
265 #include "fop_template.c"
266 #undef SFREG
267 #define SFREG 30
268 #define DFREG 30
269 #include "fop_template.c"
270 #undef SFREG
271 #undef DFREG
272 #define SFREG 31
273 #include "fop_template.c"
274 #undef SFREG
275
276 #define FTN
277 #include "fop_template.c"
278 #undef FTN
279
280 void op_dup_T0 (void)
281 {
282 T2 = T0;
283 RETURN();
284 }
285
286 void op_load_HI (void)
287 {
288 T0 = env->HI;
289 RETURN();
290 }
291
292 void op_store_HI (void)
293 {
294 env->HI = T0;
295 RETURN();
296 }
297
298 void op_load_LO (void)
299 {
300 T0 = env->LO;
301 RETURN();
302 }
303
304 void op_store_LO (void)
305 {
306 env->LO = T0;
307 RETURN();
308 }
309
310 /* Load and store */
311 #define MEMSUFFIX _raw
312 #include "op_mem.c"
313 #undef MEMSUFFIX
314 #if !defined(CONFIG_USER_ONLY)
315 #define MEMSUFFIX _user
316 #include "op_mem.c"
317 #undef MEMSUFFIX
318
319 #define MEMSUFFIX _kernel
320 #include "op_mem.c"
321 #undef MEMSUFFIX
322 #endif
323
324 /* Arithmetic */
325 void op_add (void)
326 {
327 T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
328 RETURN();
329 }
330
331 void op_addo (void)
332 {
333 target_ulong tmp;
334
335 tmp = (int32_t)T0;
336 T0 = (int32_t)T0 + (int32_t)T1;
337 if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
338 /* operands of same sign, result different sign */
339 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
340 }
341 T0 = (int32_t)T0;
342 RETURN();
343 }
344
345 void op_sub (void)
346 {
347 T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
348 RETURN();
349 }
350
351 void op_subo (void)
352 {
353 target_ulong tmp;
354
355 tmp = (int32_t)T0;
356 T0 = (int32_t)T0 - (int32_t)T1;
357 if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
358 /* operands of different sign, first operand and result different sign */
359 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
360 }
361 T0 = (int32_t)T0;
362 RETURN();
363 }
364
365 void op_mul (void)
366 {
367 T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
368 RETURN();
369 }
370
371 void op_div (void)
372 {
373 if (T1 != 0) {
374 env->LO = (int32_t)((int32_t)T0 / (int32_t)T1);
375 env->HI = (int32_t)((int32_t)T0 % (int32_t)T1);
376 }
377 RETURN();
378 }
379
380 void op_divu (void)
381 {
382 if (T1 != 0) {
383 env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
384 env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
385 }
386 RETURN();
387 }
388
389 #ifdef MIPS_HAS_MIPS64
390 /* Arithmetic */
391 void op_dadd (void)
392 {
393 T0 += T1;
394 RETURN();
395 }
396
397 void op_daddo (void)
398 {
399 target_long tmp;
400
401 tmp = T0;
402 T0 += T1;
403 if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
404 /* operands of same sign, result different sign */
405 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
406 }
407 RETURN();
408 }
409
410 void op_dsub (void)
411 {
412 T0 -= T1;
413 RETURN();
414 }
415
416 void op_dsubo (void)
417 {
418 target_long tmp;
419
420 tmp = T0;
421 T0 = (int64_t)T0 - (int64_t)T1;
422 if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
423 /* operands of different sign, first operand and result different sign */
424 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
425 }
426 RETURN();
427 }
428
429 void op_dmul (void)
430 {
431 T0 = (int64_t)T0 * (int64_t)T1;
432 RETURN();
433 }
434
435 #if TARGET_LONG_BITS > HOST_LONG_BITS
436 /* Those might call libgcc functions. */
437 void op_ddiv (void)
438 {
439 do_ddiv();
440 RETURN();
441 }
442
443 void op_ddivu (void)
444 {
445 do_ddivu();
446 RETURN();
447 }
448 #else
449 void op_ddiv (void)
450 {
451 if (T1 != 0) {
452 env->LO = (int64_t)T0 / (int64_t)T1;
453 env->HI = (int64_t)T0 % (int64_t)T1;
454 }
455 RETURN();
456 }
457
458 void op_ddivu (void)
459 {
460 if (T1 != 0) {
461 env->LO = T0 / T1;
462 env->HI = T0 % T1;
463 }
464 RETURN();
465 }
466 #endif
467 #endif /* MIPS_HAS_MIPS64 */
468
469 /* Logical */
470 void op_and (void)
471 {
472 T0 &= T1;
473 RETURN();
474 }
475
476 void op_nor (void)
477 {
478 T0 = ~(T0 | T1);
479 RETURN();
480 }
481
482 void op_or (void)
483 {
484 T0 |= T1;
485 RETURN();
486 }
487
488 void op_xor (void)
489 {
490 T0 ^= T1;
491 RETURN();
492 }
493
494 void op_sll (void)
495 {
496 T0 = (int32_t)((uint32_t)T0 << (uint32_t)T1);
497 RETURN();
498 }
499
500 void op_sra (void)
501 {
502 T0 = (int32_t)((int32_t)T0 >> (uint32_t)T1);
503 RETURN();
504 }
505
506 void op_srl (void)
507 {
508 T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1);
509 RETURN();
510 }
511
512 void op_rotr (void)
513 {
514 target_ulong tmp;
515
516 if (T1) {
517 tmp = (int32_t)((uint32_t)T0 << (0x20 - (uint32_t)T1));
518 T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1) | tmp;
519 } else
520 T0 = T1;
521 RETURN();
522 }
523
524 void op_sllv (void)
525 {
526 T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
527 RETURN();
528 }
529
530 void op_srav (void)
531 {
532 T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
533 RETURN();
534 }
535
536 void op_srlv (void)
537 {
538 T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
539 RETURN();
540 }
541
542 void op_rotrv (void)
543 {
544 target_ulong tmp;
545
546 T0 &= 0x1F;
547 if (T0) {
548 tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
549 T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
550 } else
551 T0 = T1;
552 RETURN();
553 }
554
555 void op_clo (void)
556 {
557 int n;
558
559 if (T0 == ~((target_ulong)0)) {
560 T0 = 32;
561 } else {
562 for (n = 0; n < 32; n++) {
563 if (!(T0 & (1 << 31)))
564 break;
565 T0 = T0 << 1;
566 }
567 T0 = n;
568 }
569 RETURN();
570 }
571
572 void op_clz (void)
573 {
574 int n;
575
576 if (T0 == 0) {
577 T0 = 32;
578 } else {
579 for (n = 0; n < 32; n++) {
580 if (T0 & (1 << 31))
581 break;
582 T0 = T0 << 1;
583 }
584 T0 = n;
585 }
586 RETURN();
587 }
588
589 #ifdef MIPS_HAS_MIPS64
590
591 #if TARGET_LONG_BITS > HOST_LONG_BITS
592 /* Those might call libgcc functions. */
593 void op_dsll (void)
594 {
595 CALL_FROM_TB0(do_dsll);
596 RETURN();
597 }
598
599 void op_dsll32 (void)
600 {
601 CALL_FROM_TB0(do_dsll32);
602 RETURN();
603 }
604
605 void op_dsra (void)
606 {
607 CALL_FROM_TB0(do_dsra);
608 RETURN();
609 }
610
611 void op_dsra32 (void)
612 {
613 CALL_FROM_TB0(do_dsra32);
614 RETURN();
615 }
616
617 void op_dsrl (void)
618 {
619 CALL_FROM_TB0(do_dsrl);
620 RETURN();
621 }
622
623 void op_dsrl32 (void)
624 {
625 CALL_FROM_TB0(do_dsrl32);
626 RETURN();
627 }
628
629 void op_drotr (void)
630 {
631 CALL_FROM_TB0(do_drotr);
632 RETURN();
633 }
634
635 void op_drotr32 (void)
636 {
637 CALL_FROM_TB0(do_drotr32);
638 RETURN();
639 }
640
641 void op_dsllv (void)
642 {
643 CALL_FROM_TB0(do_dsllv);
644 RETURN();
645 }
646
647 void op_dsrav (void)
648 {
649 CALL_FROM_TB0(do_dsrav);
650 RETURN();
651 }
652
653 void op_dsrlv (void)
654 {
655 CALL_FROM_TB0(do_dsrlv);
656 RETURN();
657 }
658
659 void op_drotrv (void)
660 {
661 CALL_FROM_TB0(do_drotrv);
662 RETURN();
663 }
664
665 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
666
667 void op_dsll (void)
668 {
669 T0 = T0 << T1;
670 RETURN();
671 }
672
673 void op_dsll32 (void)
674 {
675 T0 = T0 << (T1 + 32);
676 RETURN();
677 }
678
679 void op_dsra (void)
680 {
681 T0 = (int64_t)T0 >> T1;
682 RETURN();
683 }
684
685 void op_dsra32 (void)
686 {
687 T0 = (int64_t)T0 >> (T1 + 32);
688 RETURN();
689 }
690
691 void op_dsrl (void)
692 {
693 T0 = T0 >> T1;
694 RETURN();
695 }
696
697 void op_dsrl32 (void)
698 {
699 T0 = T0 >> (T1 + 32);
700 RETURN();
701 }
702
703 void op_drotr (void)
704 {
705 target_ulong tmp;
706
707 if (T1) {
708 tmp = T0 << (0x40 - T1);
709 T0 = (T0 >> T1) | tmp;
710 } else
711 T0 = T1;
712 RETURN();
713 }
714
715 void op_drotr32 (void)
716 {
717 target_ulong tmp;
718
719 if (T1) {
720 tmp = T0 << (0x40 - (32 + T1));
721 T0 = (T0 >> (32 + T1)) | tmp;
722 } else
723 T0 = T1;
724 RETURN();
725 }
726
727 void op_dsllv (void)
728 {
729 T0 = T1 << (T0 & 0x3F);
730 RETURN();
731 }
732
733 void op_dsrav (void)
734 {
735 T0 = (int64_t)T1 >> (T0 & 0x3F);
736 RETURN();
737 }
738
739 void op_dsrlv (void)
740 {
741 T0 = T1 >> (T0 & 0x3F);
742 RETURN();
743 }
744
745 void op_drotrv (void)
746 {
747 target_ulong tmp;
748
749 T0 &= 0x3F;
750 if (T0) {
751 tmp = T1 << (0x40 - T0);
752 T0 = (T1 >> T0) | tmp;
753 } else
754 T0 = T1;
755 RETURN();
756 }
757 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
758
759 void op_dclo (void)
760 {
761 int n;
762
763 if (T0 == ~((target_ulong)0)) {
764 T0 = 64;
765 } else {
766 for (n = 0; n < 64; n++) {
767 if (!(T0 & (1ULL << 63)))
768 break;
769 T0 = T0 << 1;
770 }
771 T0 = n;
772 }
773 RETURN();
774 }
775
776 void op_dclz (void)
777 {
778 int n;
779
780 if (T0 == 0) {
781 T0 = 64;
782 } else {
783 for (n = 0; n < 64; n++) {
784 if (T0 & (1ULL << 63))
785 break;
786 T0 = T0 << 1;
787 }
788 T0 = n;
789 }
790 RETURN();
791 }
792 #endif
793
794 /* 64 bits arithmetic */
795 #if TARGET_LONG_BITS > HOST_LONG_BITS
796 void op_mult (void)
797 {
798 CALL_FROM_TB0(do_mult);
799 RETURN();
800 }
801
802 void op_multu (void)
803 {
804 CALL_FROM_TB0(do_multu);
805 RETURN();
806 }
807
808 void op_madd (void)
809 {
810 CALL_FROM_TB0(do_madd);
811 RETURN();
812 }
813
814 void op_maddu (void)
815 {
816 CALL_FROM_TB0(do_maddu);
817 RETURN();
818 }
819
820 void op_msub (void)
821 {
822 CALL_FROM_TB0(do_msub);
823 RETURN();
824 }
825
826 void op_msubu (void)
827 {
828 CALL_FROM_TB0(do_msubu);
829 RETURN();
830 }
831
832 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
833
834 static inline uint64_t get_HILO (void)
835 {
836 return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
837 }
838
839 static inline void set_HILO (uint64_t HILO)
840 {
841 env->LO = (int32_t)(HILO & 0xFFFFFFFF);
842 env->HI = (int32_t)(HILO >> 32);
843 }
844
845 void op_mult (void)
846 {
847 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
848 RETURN();
849 }
850
851 void op_multu (void)
852 {
853 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
854 RETURN();
855 }
856
857 void op_madd (void)
858 {
859 int64_t tmp;
860
861 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
862 set_HILO((int64_t)get_HILO() + tmp);
863 RETURN();
864 }
865
866 void op_maddu (void)
867 {
868 uint64_t tmp;
869
870 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
871 set_HILO(get_HILO() + tmp);
872 RETURN();
873 }
874
875 void op_msub (void)
876 {
877 int64_t tmp;
878
879 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
880 set_HILO((int64_t)get_HILO() - tmp);
881 RETURN();
882 }
883
884 void op_msubu (void)
885 {
886 uint64_t tmp;
887
888 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
889 set_HILO(get_HILO() - tmp);
890 RETURN();
891 }
892 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
893
894 #ifdef MIPS_HAS_MIPS64
895 void op_dmult (void)
896 {
897 CALL_FROM_TB0(do_dmult);
898 RETURN();
899 }
900
901 void op_dmultu (void)
902 {
903 CALL_FROM_TB0(do_dmultu);
904 RETURN();
905 }
906 #endif
907
908 /* Conditional moves */
909 void op_movn (void)
910 {
911 if (T1 != 0)
912 env->gpr[PARAM1] = T0;
913 RETURN();
914 }
915
916 void op_movz (void)
917 {
918 if (T1 == 0)
919 env->gpr[PARAM1] = T0;
920 RETURN();
921 }
922
923 void op_movf (void)
924 {
925 if (!(env->fcr31 & PARAM1))
926 env->gpr[PARAM2] = env->gpr[PARAM3];
927 RETURN();
928 }
929
930 void op_movt (void)
931 {
932 if (env->fcr31 & PARAM1)
933 env->gpr[PARAM2] = env->gpr[PARAM3];
934 RETURN();
935 }
936
937 /* Tests */
938 #define OP_COND(name, cond) \
939 void glue(op_, name) (void) \
940 { \
941 if (cond) { \
942 T0 = 1; \
943 } else { \
944 T0 = 0; \
945 } \
946 RETURN(); \
947 }
948
949 OP_COND(eq, T0 == T1);
950 OP_COND(ne, T0 != T1);
951 OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
952 OP_COND(geu, T0 >= T1);
953 OP_COND(lt, (int32_t)T0 < (int32_t)T1);
954 OP_COND(ltu, T0 < T1);
955 OP_COND(gez, (int32_t)T0 >= 0);
956 OP_COND(gtz, (int32_t)T0 > 0);
957 OP_COND(lez, (int32_t)T0 <= 0);
958 OP_COND(ltz, (int32_t)T0 < 0);
959
960 /* Branches */
961 //#undef USE_DIRECT_JUMP
962
963 void OPPROTO op_goto_tb0(void)
964 {
965 GOTO_TB(op_goto_tb0, PARAM1, 0);
966 RETURN();
967 }
968
969 void OPPROTO op_goto_tb1(void)
970 {
971 GOTO_TB(op_goto_tb1, PARAM1, 1);
972 RETURN();
973 }
974
975 /* Branch to register */
976 void op_save_breg_target (void)
977 {
978 env->btarget = T2;
979 RETURN();
980 }
981
982 void op_restore_breg_target (void)
983 {
984 T2 = env->btarget;
985 RETURN();
986 }
987
988 void op_breg (void)
989 {
990 env->PC = T2;
991 RETURN();
992 }
993
994 void op_save_btarget (void)
995 {
996 env->btarget = PARAM1;
997 RETURN();
998 }
999
1000 /* Conditional branch */
1001 void op_set_bcond (void)
1002 {
1003 T2 = T0;
1004 RETURN();
1005 }
1006
1007 void op_save_bcond (void)
1008 {
1009 env->bcond = T2;
1010 RETURN();
1011 }
1012
1013 void op_restore_bcond (void)
1014 {
1015 T2 = env->bcond;
1016 RETURN();
1017 }
1018
1019 void op_jnz_T2 (void)
1020 {
1021 if (T2)
1022 GOTO_LABEL_PARAM(1);
1023 RETURN();
1024 }
1025
1026 /* CP0 functions */
1027 void op_mfc0_index (void)
1028 {
1029 T0 = env->CP0_Index;
1030 RETURN();
1031 }
1032
1033 void op_mfc0_random (void)
1034 {
1035 CALL_FROM_TB0(do_mfc0_random);
1036 RETURN();
1037 }
1038
1039 void op_mfc0_entrylo0 (void)
1040 {
1041 T0 = (int32_t)env->CP0_EntryLo0;
1042 RETURN();
1043 }
1044
1045 void op_mfc0_entrylo1 (void)
1046 {
1047 T0 = (int32_t)env->CP0_EntryLo1;
1048 RETURN();
1049 }
1050
1051 void op_mfc0_context (void)
1052 {
1053 T0 = (int32_t)env->CP0_Context;
1054 RETURN();
1055 }
1056
1057 void op_mfc0_pagemask (void)
1058 {
1059 T0 = env->CP0_PageMask;
1060 RETURN();
1061 }
1062
1063 void op_mfc0_pagegrain (void)
1064 {
1065 T0 = env->CP0_PageGrain;
1066 RETURN();
1067 }
1068
1069 void op_mfc0_wired (void)
1070 {
1071 T0 = env->CP0_Wired;
1072 RETURN();
1073 }
1074
1075 void op_mfc0_hwrena (void)
1076 {
1077 T0 = env->CP0_HWREna;
1078 RETURN();
1079 }
1080
1081 void op_mfc0_badvaddr (void)
1082 {
1083 T0 = (int32_t)env->CP0_BadVAddr;
1084 RETURN();
1085 }
1086
1087 void op_mfc0_count (void)
1088 {
1089 CALL_FROM_TB0(do_mfc0_count);
1090 RETURN();
1091 }
1092
1093 void op_mfc0_entryhi (void)
1094 {
1095 T0 = (int32_t)env->CP0_EntryHi;
1096 RETURN();
1097 }
1098
1099 void op_mfc0_compare (void)
1100 {
1101 T0 = env->CP0_Compare;
1102 RETURN();
1103 }
1104
1105 void op_mfc0_status (void)
1106 {
1107 T0 = env->CP0_Status;
1108 if (env->hflags & MIPS_HFLAG_UM)
1109 T0 |= (1 << CP0St_UM);
1110 if (env->hflags & MIPS_HFLAG_ERL)
1111 T0 |= (1 << CP0St_ERL);
1112 if (env->hflags & MIPS_HFLAG_EXL)
1113 T0 |= (1 << CP0St_EXL);
1114 RETURN();
1115 }
1116
1117 void op_mfc0_intctl (void)
1118 {
1119 T0 = env->CP0_IntCtl;
1120 RETURN();
1121 }
1122
1123 void op_mfc0_srsctl (void)
1124 {
1125 T0 = env->CP0_SRSCtl;
1126 RETURN();
1127 }
1128
1129 void op_mfc0_srsmap (void)
1130 {
1131 T0 = env->CP0_SRSMap;
1132 RETURN();
1133 }
1134
1135 void op_mfc0_cause (void)
1136 {
1137 T0 = env->CP0_Cause;
1138 RETURN();
1139 }
1140
1141 void op_mfc0_epc (void)
1142 {
1143 T0 = (int32_t)env->CP0_EPC;
1144 RETURN();
1145 }
1146
1147 void op_mfc0_prid (void)
1148 {
1149 T0 = env->CP0_PRid;
1150 RETURN();
1151 }
1152
1153 void op_mfc0_ebase (void)
1154 {
1155 T0 = env->CP0_EBase;
1156 RETURN();
1157 }
1158
1159 void op_mfc0_config0 (void)
1160 {
1161 T0 = env->CP0_Config0;
1162 RETURN();
1163 }
1164
1165 void op_mfc0_config1 (void)
1166 {
1167 T0 = env->CP0_Config1;
1168 RETURN();
1169 }
1170
1171 void op_mfc0_config2 (void)
1172 {
1173 T0 = env->CP0_Config2;
1174 RETURN();
1175 }
1176
1177 void op_mfc0_config3 (void)
1178 {
1179 T0 = env->CP0_Config3;
1180 RETURN();
1181 }
1182
1183 void op_mfc0_config6 (void)
1184 {
1185 T0 = env->CP0_Config6;
1186 RETURN();
1187 }
1188
1189 void op_mfc0_config7 (void)
1190 {
1191 T0 = env->CP0_Config7;
1192 RETURN();
1193 }
1194
1195 void op_mfc0_lladdr (void)
1196 {
1197 T0 = (int32_t)env->CP0_LLAddr >> 4;
1198 RETURN();
1199 }
1200
1201 void op_mfc0_watchlo0 (void)
1202 {
1203 T0 = (int32_t)env->CP0_WatchLo;
1204 RETURN();
1205 }
1206
1207 void op_mfc0_watchhi0 (void)
1208 {
1209 T0 = env->CP0_WatchHi;
1210 RETURN();
1211 }
1212
1213 void op_mfc0_xcontext (void)
1214 {
1215 T0 = (int32_t)env->CP0_XContext;
1216 RETURN();
1217 }
1218
1219 void op_mfc0_framemask (void)
1220 {
1221 T0 = env->CP0_Framemask;
1222 RETURN();
1223 }
1224
1225 void op_mfc0_debug (void)
1226 {
1227 T0 = env->CP0_Debug;
1228 if (env->hflags & MIPS_HFLAG_DM)
1229 T0 |= 1 << CP0DB_DM;
1230 RETURN();
1231 }
1232
1233 void op_mfc0_depc (void)
1234 {
1235 T0 = (int32_t)env->CP0_DEPC;
1236 RETURN();
1237 }
1238
1239 void op_mfc0_performance0 (void)
1240 {
1241 T0 = env->CP0_Performance0;
1242 RETURN();
1243 }
1244
1245 void op_mfc0_taglo (void)
1246 {
1247 T0 = env->CP0_TagLo;
1248 RETURN();
1249 }
1250
1251 void op_mfc0_datalo (void)
1252 {
1253 T0 = env->CP0_DataLo;
1254 RETURN();
1255 }
1256
1257 void op_mfc0_taghi (void)
1258 {
1259 T0 = env->CP0_TagHi;
1260 RETURN();
1261 }
1262
1263 void op_mfc0_datahi (void)
1264 {
1265 T0 = env->CP0_DataHi;
1266 RETURN();
1267 }
1268
1269 void op_mfc0_errorepc (void)
1270 {
1271 T0 = (int32_t)env->CP0_ErrorEPC;
1272 RETURN();
1273 }
1274
1275 void op_mfc0_desave (void)
1276 {
1277 T0 = env->CP0_DESAVE;
1278 RETURN();
1279 }
1280
1281 void op_mtc0_index (void)
1282 {
1283 env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
1284 RETURN();
1285 }
1286
1287 void op_mtc0_entrylo0 (void)
1288 {
1289 /* Large physaddr not implemented */
1290 /* 1k pages not implemented */
1291 env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
1292 RETURN();
1293 }
1294
1295 void op_mtc0_entrylo1 (void)
1296 {
1297 /* Large physaddr not implemented */
1298 /* 1k pages not implemented */
1299 env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
1300 RETURN();
1301 }
1302
1303 void op_mtc0_context (void)
1304 {
1305 env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1306 RETURN();
1307 }
1308
1309 void op_mtc0_pagemask (void)
1310 {
1311 /* 1k pages not implemented */
1312 env->CP0_PageMask = T0 & 0x1FFFE000;
1313 RETURN();
1314 }
1315
1316 void op_mtc0_pagegrain (void)
1317 {
1318 /* SmartMIPS not implemented */
1319 /* Large physaddr not implemented */
1320 /* 1k pages not implemented */
1321 env->CP0_PageGrain = 0;
1322 RETURN();
1323 }
1324
1325 void op_mtc0_wired (void)
1326 {
1327 env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
1328 RETURN();
1329 }
1330
1331 void op_mtc0_hwrena (void)
1332 {
1333 env->CP0_HWREna = T0 & 0x0000000F;
1334 RETURN();
1335 }
1336
1337 void op_mtc0_count (void)
1338 {
1339 CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1340 RETURN();
1341 }
1342
1343 void op_mtc0_entryhi (void)
1344 {
1345 target_ulong old, val;
1346
1347 /* 1k pages not implemented */
1348 /* Ignore MIPS64 TLB for now */
1349 val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
1350 old = env->CP0_EntryHi;
1351 env->CP0_EntryHi = val;
1352 /* If the ASID changes, flush qemu's TLB. */
1353 if ((old & 0xFF) != (val & 0xFF))
1354 CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1355 RETURN();
1356 }
1357
1358 void op_mtc0_compare (void)
1359 {
1360 CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1361 RETURN();
1362 }
1363
1364 void op_mtc0_status (void)
1365 {
1366 uint32_t val, old;
1367
1368 val = (int32_t)T0 & 0xFA78FF01;
1369 old = env->CP0_Status;
1370 if (T0 & (1 << CP0St_UM))
1371 env->hflags |= MIPS_HFLAG_UM;
1372 else
1373 env->hflags &= ~MIPS_HFLAG_UM;
1374 if (T0 & (1 << CP0St_ERL))
1375 env->hflags |= MIPS_HFLAG_ERL;
1376 else
1377 env->hflags &= ~MIPS_HFLAG_ERL;
1378 if (T0 & (1 << CP0St_EXL))
1379 env->hflags |= MIPS_HFLAG_EXL;
1380 else
1381 env->hflags &= ~MIPS_HFLAG_EXL;
1382 env->CP0_Status = val;
1383 if (loglevel & CPU_LOG_TB_IN_ASM)
1384 CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1385 CALL_FROM_TB1(cpu_mips_update_irq, env);
1386 RETURN();
1387 }
1388
1389 void op_mtc0_intctl (void)
1390 {
1391 /* vectored interrupts not implemented */
1392 env->CP0_IntCtl = 0;
1393 RETURN();
1394 }
1395
1396 void op_mtc0_srsctl (void)
1397 {
1398 /* shadow registers not implemented */
1399 env->CP0_SRSCtl = 0;
1400 RETURN();
1401 }
1402
1403 void op_mtc0_srsmap (void)
1404 {
1405 /* shadow registers not implemented */
1406 env->CP0_SRSMap = 0;
1407 RETURN();
1408 }
1409
1410 void op_mtc0_cause (void)
1411 {
1412 uint32_t mask = 0x00C00300;
1413
1414 if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1415 mask |= 1 << CP0Ca_DC;
1416
1417 env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);
1418
1419 /* Handle the software interrupt as an hardware one, as they
1420 are very similar */
1421 if (T0 & CP0Ca_IP_mask) {
1422 CALL_FROM_TB1(cpu_mips_update_irq, env);
1423 }
1424 RETURN();
1425 }
1426
1427 void op_mtc0_epc (void)
1428 {
1429 env->CP0_EPC = (int32_t)T0;
1430 RETURN();
1431 }
1432
1433 void op_mtc0_ebase (void)
1434 {
1435 /* vectored interrupts not implemented */
1436 /* Multi-CPU not implemented */
1437 env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1438 RETURN();
1439 }
1440
1441 void op_mtc0_config0 (void)
1442 {
1443 #if defined(MIPS_USES_R4K_TLB)
1444 /* Fixed mapping MMU not implemented */
1445 env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
1446 #else
1447 env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
1448 #endif
1449 RETURN();
1450 }
1451
1452 void op_mtc0_config2 (void)
1453 {
1454 /* tertiary/secondary caches not implemented */
1455 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1456 RETURN();
1457 }
1458
1459 void op_mtc0_watchlo0 (void)
1460 {
1461 env->CP0_WatchLo = (int32_t)T0;
1462 RETURN();
1463 }
1464
1465 void op_mtc0_watchhi0 (void)
1466 {
1467 env->CP0_WatchHi = T0 & 0x40FF0FF8;
1468 RETURN();
1469 }
1470
1471 void op_mtc0_xcontext (void)
1472 {
1473 env->CP0_XContext = (int32_t)T0; /* XXX */
1474 RETURN();
1475 }
1476
1477 void op_mtc0_framemask (void)
1478 {
1479 env->CP0_Framemask = T0; /* XXX */
1480 RETURN();
1481 }
1482
1483 void op_mtc0_debug (void)
1484 {
1485 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1486 if (T0 & (1 << CP0DB_DM))
1487 env->hflags |= MIPS_HFLAG_DM;
1488 else
1489 env->hflags &= ~MIPS_HFLAG_DM;
1490 RETURN();
1491 }
1492
1493 void op_mtc0_depc (void)
1494 {
1495 env->CP0_DEPC = (int32_t)T0;
1496 RETURN();
1497 }
1498
1499 void op_mtc0_performance0 (void)
1500 {
1501 env->CP0_Performance0 = T0; /* XXX */
1502 RETURN();
1503 }
1504
1505 void op_mtc0_taglo (void)
1506 {
1507 env->CP0_TagLo = T0 & 0xFFFFFCF6;
1508 RETURN();
1509 }
1510
1511 void op_mtc0_datalo (void)
1512 {
1513 env->CP0_DataLo = T0; /* XXX */
1514 RETURN();
1515 }
1516
1517 void op_mtc0_taghi (void)
1518 {
1519 env->CP0_TagHi = T0; /* XXX */
1520 RETURN();
1521 }
1522
1523 void op_mtc0_datahi (void)
1524 {
1525 env->CP0_DataHi = T0; /* XXX */
1526 RETURN();
1527 }
1528
1529 void op_mtc0_errorepc (void)
1530 {
1531 env->CP0_ErrorEPC = (int32_t)T0;
1532 RETURN();
1533 }
1534
1535 void op_mtc0_desave (void)
1536 {
1537 env->CP0_DESAVE = T0;
1538 RETURN();
1539 }
1540
1541 void op_dmfc0_entrylo0 (void)
1542 {
1543 T0 = env->CP0_EntryLo0;
1544 RETURN();
1545 }
1546
1547 void op_dmfc0_entrylo1 (void)
1548 {
1549 T0 = env->CP0_EntryLo1;
1550 RETURN();
1551 }
1552
1553 void op_dmfc0_context (void)
1554 {
1555 T0 = env->CP0_Context;
1556 RETURN();
1557 }
1558
1559 void op_dmfc0_badvaddr (void)
1560 {
1561 T0 = env->CP0_BadVAddr;
1562 RETURN();
1563 }
1564
1565 void op_dmfc0_entryhi (void)
1566 {
1567 T0 = env->CP0_EntryHi;
1568 RETURN();
1569 }
1570
1571 void op_dmfc0_epc (void)
1572 {
1573 T0 = env->CP0_EPC;
1574 RETURN();
1575 }
1576
1577 void op_dmfc0_lladdr (void)
1578 {
1579 T0 = env->CP0_LLAddr >> 4;
1580 RETURN();
1581 }
1582
1583 void op_dmfc0_watchlo0 (void)
1584 {
1585 T0 = env->CP0_WatchLo;
1586 RETURN();
1587 }
1588
1589 void op_dmfc0_xcontext (void)
1590 {
1591 T0 = env->CP0_XContext;
1592 RETURN();
1593 }
1594
1595 void op_dmfc0_depc (void)
1596 {
1597 T0 = env->CP0_DEPC;
1598 RETURN();
1599 }
1600
1601 void op_dmfc0_errorepc (void)
1602 {
1603 T0 = env->CP0_ErrorEPC;
1604 RETURN();
1605 }
1606
1607 void op_dmtc0_entrylo0 (void)
1608 {
1609 /* Large physaddr not implemented */
1610 /* 1k pages not implemented */
1611 env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1612 RETURN();
1613 }
1614
1615 void op_dmtc0_entrylo1 (void)
1616 {
1617 /* Large physaddr not implemented */
1618 /* 1k pages not implemented */
1619 env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1620 RETURN();
1621 }
1622
1623 void op_dmtc0_context (void)
1624 {
1625 env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1626 RETURN();
1627 }
1628
1629 void op_dmtc0_epc (void)
1630 {
1631 env->CP0_EPC = T0;
1632 RETURN();
1633 }
1634
1635 void op_dmtc0_watchlo0 (void)
1636 {
1637 env->CP0_WatchLo = T0;
1638 RETURN();
1639 }
1640
1641 void op_dmtc0_xcontext (void)
1642 {
1643 env->CP0_XContext = T0; /* XXX */
1644 RETURN();
1645 }
1646
1647 void op_dmtc0_depc (void)
1648 {
1649 env->CP0_DEPC = T0;
1650 RETURN();
1651 }
1652
1653 void op_dmtc0_errorepc (void)
1654 {
1655 env->CP0_ErrorEPC = T0;
1656 RETURN();
1657 }
1658
1659 #if 0
1660 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1661 #else
1662 # define DEBUG_FPU_STATE() do { } while(0)
1663 #endif
1664
1665 void op_cp1_enabled(void)
1666 {
1667 if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1668 CALL_FROM_TB2(do_raise_exception_direct_err, EXCP_CpU, 1);
1669 }
1670 RETURN();
1671 }
1672
1673 /* CP1 functions */
1674 void op_cfc1 (void)
1675 {
1676 if (T1 == 0) {
1677 T0 = env->fcr0;
1678 }
1679 else {
1680 /* fetch fcr31, masking unused bits */
1681 T0 = env->fcr31 & 0x0183FFFF;
1682 }
1683 DEBUG_FPU_STATE();
1684 RETURN();
1685 }
1686
1687 /* convert MIPS rounding mode in FCR31 to IEEE library */
1688 unsigned int ieee_rm[] = {
1689 float_round_nearest_even,
1690 float_round_to_zero,
1691 float_round_up,
1692 float_round_down
1693 };
1694
1695 #define RESTORE_ROUNDING_MODE \
1696 set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1697
1698 void op_ctc1 (void)
1699 {
1700 if (T1 == 0) {
1701 /* XXX should this throw an exception?
1702 * don't write to FCR0.
1703 * env->fcr0 = T0;
1704 */
1705 }
1706 else {
1707 /* store new fcr31, masking unused bits */
1708 env->fcr31 = T0 & 0x0183FFFF;
1709
1710 /* set rounding mode */
1711 RESTORE_ROUNDING_MODE;
1712
1713 #ifndef CONFIG_SOFTFLOAT
1714 /* no floating point exception for native float */
1715 SET_FP_ENABLE(env->fcr31, 0);
1716 #endif
1717 }
1718 DEBUG_FPU_STATE();
1719 RETURN();
1720 }
1721
1722 void op_mfc1 (void)
1723 {
1724 T0 = WT0;
1725 DEBUG_FPU_STATE();
1726 RETURN();
1727 }
1728
1729 void op_mtc1 (void)
1730 {
1731 WT0 = T0;
1732 DEBUG_FPU_STATE();
1733 RETURN();
1734 }
1735
1736 /* Float support.
1737 Single precition routines have a "s" suffix, double precision a
1738 "d" suffix. */
1739
1740 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1741
1742 FLOAT_OP(cvtd, s)
1743 {
1744 FDT2 = float32_to_float64(FST0, &env->fp_status);
1745 DEBUG_FPU_STATE();
1746 RETURN();
1747 }
1748 FLOAT_OP(cvtd, w)
1749 {
1750 FDT2 = int32_to_float64(WT0, &env->fp_status);
1751 DEBUG_FPU_STATE();
1752 RETURN();
1753 }
1754 FLOAT_OP(cvts, d)
1755 {
1756 FST2 = float64_to_float32(FDT0, &env->fp_status);
1757 DEBUG_FPU_STATE();
1758 RETURN();
1759 }
1760 FLOAT_OP(cvts, w)
1761 {
1762 FST2 = int32_to_float32(WT0, &env->fp_status);
1763 DEBUG_FPU_STATE();
1764 RETURN();
1765 }
1766 FLOAT_OP(cvtw, s)
1767 {
1768 WT2 = float32_to_int32(FST0, &env->fp_status);
1769 DEBUG_FPU_STATE();
1770 RETURN();
1771 }
1772 FLOAT_OP(cvtw, d)
1773 {
1774 WT2 = float64_to_int32(FDT0, &env->fp_status);
1775 DEBUG_FPU_STATE();
1776 RETURN();
1777 }
1778
1779 FLOAT_OP(roundw, d)
1780 {
1781 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1782 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1783 RESTORE_ROUNDING_MODE;
1784
1785 DEBUG_FPU_STATE();
1786 RETURN();
1787 }
1788 FLOAT_OP(roundw, s)
1789 {
1790 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1791 WT2 = float32_round_to_int(FST0, &env->fp_status);
1792 RESTORE_ROUNDING_MODE;
1793 DEBUG_FPU_STATE();
1794 RETURN();
1795 }
1796
1797 FLOAT_OP(truncw, d)
1798 {
1799 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1800 DEBUG_FPU_STATE();
1801 RETURN();
1802 }
1803 FLOAT_OP(truncw, s)
1804 {
1805 WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1806 DEBUG_FPU_STATE();
1807 RETURN();
1808 }
1809
1810 FLOAT_OP(ceilw, d)
1811 {
1812 set_float_rounding_mode(float_round_up, &env->fp_status);
1813 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1814 RESTORE_ROUNDING_MODE;
1815
1816 DEBUG_FPU_STATE();
1817 RETURN();
1818 }
1819 FLOAT_OP(ceilw, s)
1820 {
1821 set_float_rounding_mode(float_round_up, &env->fp_status);
1822 WT2 = float32_round_to_int(FST0, &env->fp_status);
1823 RESTORE_ROUNDING_MODE;
1824 DEBUG_FPU_STATE();
1825 RETURN();
1826 }
1827
1828 FLOAT_OP(floorw, d)
1829 {
1830 set_float_rounding_mode(float_round_down, &env->fp_status);
1831 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1832 RESTORE_ROUNDING_MODE;
1833
1834 DEBUG_FPU_STATE();
1835 RETURN();
1836 }
1837 FLOAT_OP(floorw, s)
1838 {
1839 set_float_rounding_mode(float_round_down, &env->fp_status);
1840 WT2 = float32_round_to_int(FST0, &env->fp_status);
1841 RESTORE_ROUNDING_MODE;
1842 DEBUG_FPU_STATE();
1843 RETURN();
1844 }
1845
1846 /* binary operations */
1847 #define FLOAT_BINOP(name) \
1848 FLOAT_OP(name, d) \
1849 { \
1850 FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \
1851 DEBUG_FPU_STATE(); \
1852 } \
1853 FLOAT_OP(name, s) \
1854 { \
1855 FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \
1856 DEBUG_FPU_STATE(); \
1857 }
1858 FLOAT_BINOP(add)
1859 FLOAT_BINOP(sub)
1860 FLOAT_BINOP(mul)
1861 FLOAT_BINOP(div)
1862 #undef FLOAT_BINOP
1863
1864 /* unary operations, modifying fp status */
1865 #define FLOAT_UNOP(name) \
1866 FLOAT_OP(name, d) \
1867 { \
1868 FDT2 = float64_ ## name(FDT0, &env->fp_status); \
1869 DEBUG_FPU_STATE(); \
1870 } \
1871 FLOAT_OP(name, s) \
1872 { \
1873 FST2 = float32_ ## name(FST0, &env->fp_status); \
1874 DEBUG_FPU_STATE(); \
1875 }
1876 FLOAT_UNOP(sqrt)
1877 #undef FLOAT_UNOP
1878
1879 /* unary operations, not modifying fp status */
1880 #define FLOAT_UNOP(name) \
1881 FLOAT_OP(name, d) \
1882 { \
1883 FDT2 = float64_ ## name(FDT0); \
1884 DEBUG_FPU_STATE(); \
1885 } \
1886 FLOAT_OP(name, s) \
1887 { \
1888 FST2 = float32_ ## name(FST0); \
1889 DEBUG_FPU_STATE(); \
1890 }
1891 FLOAT_UNOP(abs)
1892 FLOAT_UNOP(chs)
1893 #undef FLOAT_UNOP
1894
1895 FLOAT_OP(mov, d)
1896 {
1897 FDT2 = FDT0;
1898 DEBUG_FPU_STATE();
1899 RETURN();
1900 }
1901 FLOAT_OP(mov, s)
1902 {
1903 FST2 = FST0;
1904 DEBUG_FPU_STATE();
1905 RETURN();
1906 }
1907
1908 #ifdef CONFIG_SOFTFLOAT
1909 #define clear_invalid() do { \
1910 int flags = get_float_exception_flags(&env->fp_status); \
1911 flags &= ~float_flag_invalid; \
1912 set_float_exception_flags(flags, &env->fp_status); \
1913 } while(0)
1914 #else
1915 #define clear_invalid() do { } while(0)
1916 #endif
1917
1918 extern void dump_fpu_s(CPUState *env);
1919
1920 #define FOP_COND(fmt, op, sig, cond) \
1921 void op_cmp_ ## fmt ## _ ## op (void) \
1922 { \
1923 if (cond) \
1924 SET_FP_COND(env->fcr31); \
1925 else \
1926 CLEAR_FP_COND(env->fcr31); \
1927 if (!sig) \
1928 clear_invalid(); \
1929 /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1930 DEBUG_FPU_STATE(); \
1931 RETURN(); \
1932 }
1933
1934 int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
1935 {
1936 if (float64_is_nan(a) || float64_is_nan(b)) {
1937 float_raise(float_flag_invalid, status);
1938 return 1;
1939 }
1940 else {
1941 return 0;
1942 }
1943 }
1944
1945 FOP_COND(d, f, 0, 0)
1946 FOP_COND(d, un, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1947 FOP_COND(d, eq, 0, float64_eq(FDT0, FDT1, &env->fp_status))
1948 FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1949 FOP_COND(d, olt, 0, float64_lt(FDT0, FDT1, &env->fp_status))
1950 FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1951 FOP_COND(d, ole, 0, float64_le(FDT0, FDT1, &env->fp_status))
1952 FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1953 /* NOTE: the comma operator will make "cond" to eval to false,
1954 * but float*_is_unordered() is still called
1955 */
1956 FOP_COND(d, sf, 1, (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0))
1957 FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1958 FOP_COND(d, seq, 1, float64_eq(FDT0, FDT1, &env->fp_status))
1959 FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1960 FOP_COND(d, lt, 1, float64_lt(FDT0, FDT1, &env->fp_status))
1961 FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1962 FOP_COND(d, le, 1, float64_le(FDT0, FDT1, &env->fp_status))
1963 FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1964
1965 flag float32_is_unordered(float32 a, float32 b STATUS_PARAM)
1966 {
1967 extern flag float32_is_nan( float32 a );
1968 if (float32_is_nan(a) || float32_is_nan(b)) {
1969 float_raise(float_flag_invalid, status);
1970 return 1;
1971 }
1972 else {
1973 return 0;
1974 }
1975 }
1976
1977 /* NOTE: the comma operator will make "cond" to eval to false,
1978 * but float*_is_unordered() is still called
1979 */
1980 FOP_COND(s, f, 0, 0)
1981 FOP_COND(s, un, 0, float32_is_unordered(FST1, FST0, &env->fp_status))
1982 FOP_COND(s, eq, 0, float32_eq(FST0, FST1, &env->fp_status))
1983 FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1984 FOP_COND(s, olt, 0, float32_lt(FST0, FST1, &env->fp_status))
1985 FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1986 FOP_COND(s, ole, 0, float32_le(FST0, FST1, &env->fp_status))
1987 FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1988 /* NOTE: the comma operator will make "cond" to eval to false,
1989 * but float*_is_unordered() is still called
1990 */
1991 FOP_COND(s, sf, 1, (float32_is_unordered(FST0, FST1, &env->fp_status), 0))
1992 FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
1993 FOP_COND(s, seq, 1, float32_eq(FST0, FST1, &env->fp_status))
1994 FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1995 FOP_COND(s, lt, 1, float32_lt(FST0, FST1, &env->fp_status))
1996 FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1997 FOP_COND(s, le, 1, float32_le(FST0, FST1, &env->fp_status))
1998 FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1999
2000 void op_bc1f (void)
2001 {
2002 T0 = ! IS_FP_COND_SET(env->fcr31);
2003 DEBUG_FPU_STATE();
2004 RETURN();
2005 }
2006
2007 void op_bc1t (void)
2008 {
2009 T0 = IS_FP_COND_SET(env->fcr31);
2010 DEBUG_FPU_STATE();
2011 RETURN();
2012 }
2013
2014 #if defined(MIPS_USES_R4K_TLB)
2015 void op_tlbwi (void)
2016 {
2017 CALL_FROM_TB0(do_tlbwi);
2018 RETURN();
2019 }
2020
2021 void op_tlbwr (void)
2022 {
2023 CALL_FROM_TB0(do_tlbwr);
2024 RETURN();
2025 }
2026
2027 void op_tlbp (void)
2028 {
2029 CALL_FROM_TB0(do_tlbp);
2030 RETURN();
2031 }
2032
2033 void op_tlbr (void)
2034 {
2035 CALL_FROM_TB0(do_tlbr);
2036 RETURN();
2037 }
2038 #endif
2039
2040 /* Specials */
2041 #if defined (CONFIG_USER_ONLY)
2042 void op_tls_value (void)
2043 {
2044 T0 = env->tls_value;
2045 }
2046 #endif
2047
2048 void op_pmon (void)
2049 {
2050 CALL_FROM_TB1(do_pmon, PARAM1);
2051 RETURN();
2052 }
2053
2054 void op_di (void)
2055 {
2056 T0 = env->CP0_Status;
2057 env->CP0_Status = T0 & ~(1 << CP0St_IE);
2058 CALL_FROM_TB1(cpu_mips_update_irq, env);
2059 RETURN();
2060 }
2061
2062 void op_ei (void)
2063 {
2064 T0 = env->CP0_Status;
2065 env->CP0_Status = T0 | (1 << CP0St_IE);
2066 CALL_FROM_TB1(cpu_mips_update_irq, env);
2067 RETURN();
2068 }
2069
2070 void op_trap (void)
2071 {
2072 if (T0) {
2073 CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP);
2074 }
2075 RETURN();
2076 }
2077
2078 void op_debug (void)
2079 {
2080 CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2081 RETURN();
2082 }
2083
2084 void op_set_lladdr (void)
2085 {
2086 env->CP0_LLAddr = T2;
2087 RETURN();
2088 }
2089
2090 void debug_eret (void);
2091 void op_eret (void)
2092 {
2093 CALL_FROM_TB0(debug_eret);
2094 if (env->hflags & MIPS_HFLAG_ERL) {
2095 env->PC = env->CP0_ErrorEPC;
2096 env->hflags &= ~MIPS_HFLAG_ERL;
2097 env->CP0_Status &= ~(1 << CP0St_ERL);
2098 } else {
2099 env->PC = env->CP0_EPC;
2100 env->hflags &= ~MIPS_HFLAG_EXL;
2101 env->CP0_Status &= ~(1 << CP0St_EXL);
2102 }
2103 env->CP0_LLAddr = 1;
2104 RETURN();
2105 }
2106
2107 void op_deret (void)
2108 {
2109 CALL_FROM_TB0(debug_eret);
2110 env->PC = env->CP0_DEPC;
2111 RETURN();
2112 }
2113
2114 void op_rdhwr_cpunum(void)
2115 {
2116 if (env->CP0_HWREna & (1 << 0))
2117 T0 = env->CP0_EBase & 0x2ff;
2118 else
2119 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2120 RETURN();
2121 }
2122
2123 void op_rdhwr_synci_step(void)
2124 {
2125 if (env->CP0_HWREna & (1 << 1))
2126 T0 = env->SYNCI_Step;
2127 else
2128 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2129 RETURN();
2130 }
2131
2132 void op_rdhwr_cc(void)
2133 {
2134 if (env->CP0_HWREna & (1 << 2))
2135 T0 = env->CP0_Count;
2136 else
2137 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2138 RETURN();
2139 }
2140
2141 void op_rdhwr_ccres(void)
2142 {
2143 if (env->CP0_HWREna & (1 << 3))
2144 T0 = env->CCRes;
2145 else
2146 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2147 RETURN();
2148 }
2149
2150 void op_save_state (void)
2151 {
2152 env->hflags = PARAM1;
2153 RETURN();
2154 }
2155
2156 void op_save_pc (void)
2157 {
2158 env->PC = PARAM1;
2159 RETURN();
2160 }
2161
2162 void op_raise_exception (void)
2163 {
2164 CALL_FROM_TB1(do_raise_exception, PARAM1);
2165 RETURN();
2166 }
2167
2168 void op_raise_exception_err (void)
2169 {
2170 CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2171 RETURN();
2172 }
2173
2174 void op_exit_tb (void)
2175 {
2176 EXIT_TB();
2177 RETURN();
2178 }
2179
2180 void op_wait (void)
2181 {
2182 env->halted = 1;
2183 CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2184 RETURN();
2185 }
2186
2187 /* Bitfield operations. */
2188 void op_ext(void)
2189 {
2190 unsigned int pos = PARAM1;
2191 unsigned int size = PARAM2;
2192
2193 T0 = ((uint32_t)T1 >> pos) & ((1 << size) - 1);
2194 RETURN();
2195 }
2196
2197 void op_ins(void)
2198 {
2199 unsigned int pos = PARAM1;
2200 unsigned int size = PARAM2;
2201 target_ulong mask = ((1 << size) - 1) << pos;
2202
2203 T0 = (T2 & ~mask) | (((uint32_t)T1 << pos) & mask);
2204 RETURN();
2205 }
2206
2207 void op_wsbh(void)
2208 {
2209 T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2210 RETURN();
2211 }
2212
2213 #ifdef MIPS_HAS_MIPS64
2214 void op_dext(void)
2215 {
2216 unsigned int pos = PARAM1;
2217 unsigned int size = PARAM2;
2218
2219 T0 = (T1 >> pos) & ((1 << size) - 1);
2220 RETURN();
2221 }
2222
2223 void op_dins(void)
2224 {
2225 unsigned int pos = PARAM1;
2226 unsigned int size = PARAM2;
2227 target_ulong mask = ((1 << size) - 1) << pos;
2228
2229 T0 = (T2 & ~mask) | ((T1 << pos) & mask);
2230 RETURN();
2231 }
2232
2233 void op_dsbh(void)
2234 {
2235 T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2236 RETURN();
2237 }
2238
2239 void op_dshd(void)
2240 {
2241 T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2242 RETURN();
2243 }
2244 #endif
2245
2246 void op_seb(void)
2247 {
2248 T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2249 RETURN();
2250 }
2251
2252 void op_seh(void)
2253 {
2254 T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
2255 RETURN();
2256 }
Qemu copy for testing