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git.proxmox.com Git - mirror_qemu.git/blob - target-mips/op_helper.c
be207b9bb92aaab00917767bf223e5510dc7dac3
2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define MIPS_DEBUG_DISAS
25 #define GETPC() (__builtin_return_address(0))
27 /*****************************************************************************/
28 /* Exceptions processing helpers */
29 void cpu_loop_exit(void)
31 longjmp(env
->jmp_env
, 1);
34 void do_raise_exception_err (uint32_t exception
, int error_code
)
37 if (logfile
&& exception
< 0x100)
38 fprintf(logfile
, "%s: %d %d\n", __func__
, exception
, error_code
);
40 env
->exception_index
= exception
;
41 env
->error_code
= error_code
;
46 void do_raise_exception (uint32_t exception
)
48 do_raise_exception_err(exception
, 0);
51 void do_restore_state (void *pc_ptr
)
54 unsigned long pc
= (unsigned long) pc_ptr
;
57 cpu_restore_state (tb
, env
, pc
, NULL
);
60 void do_raise_exception_direct (uint32_t exception
)
62 do_restore_state (GETPC ());
63 do_raise_exception_err (exception
, 0);
66 #define MEMSUFFIX _raw
67 #include "op_helper_mem.c"
69 #if !defined(CONFIG_USER_ONLY)
70 #define MEMSUFFIX _user
71 #include "op_helper_mem.c"
73 #define MEMSUFFIX _kernel
74 #include "op_helper_mem.c"
78 /* 64 bits arithmetic for 32 bits hosts */
79 #if (HOST_LONG_BITS == 32)
80 static inline uint64_t get_HILO (void)
82 return ((uint64_t)env
->HI
<< 32) | (uint64_t)env
->LO
;
85 static inline void set_HILO (uint64_t HILO
)
87 env
->LO
= HILO
& 0xFFFFFFFF;
93 set_HILO((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
98 set_HILO((uint64_t)T0
* (uint64_t)T1
);
105 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
106 set_HILO((int64_t)get_HILO() + tmp
);
113 tmp
= ((uint64_t)T0
* (uint64_t)T1
);
114 set_HILO(get_HILO() + tmp
);
121 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
122 set_HILO((int64_t)get_HILO() - tmp
);
129 tmp
= ((uint64_t)T0
* (uint64_t)T1
);
130 set_HILO(get_HILO() - tmp
);
134 #if defined(CONFIG_USER_ONLY)
135 void do_mfc0 (int reg
, int sel
)
137 cpu_abort(env
, "mfc0 reg=%d sel=%d\n", reg
, sel
);
139 void do_mtc0 (int reg
, int sel
)
141 cpu_abort(env
, "mtc0 reg=%d sel=%d\n", reg
, sel
);
146 cpu_abort(env
, "tlbwi\n");
151 cpu_abort(env
, "tlbwr\n");
156 cpu_abort(env
, "tlbp\n");
161 cpu_abort(env
, "tlbr\n");
166 void do_mfc0 (int reg
, int sel
)
168 const unsigned char *rn
;
170 if (sel
!= 0 && reg
!= 16 && reg
!= 28) {
180 T0
= cpu_mips_get_random(env
);
184 T0
= env
->CP0_EntryLo0
;
188 T0
= env
->CP0_EntryLo1
;
192 T0
= env
->CP0_Context
;
196 T0
= env
->CP0_PageMask
;
204 T0
= env
->CP0_BadVAddr
;
208 T0
= cpu_mips_get_count(env
);
212 T0
= env
->CP0_EntryHi
;
216 T0
= env
->CP0_Compare
;
220 T0
= env
->CP0_Status
;
221 if (env
->hflags
& MIPS_HFLAG_UM
)
222 T0
|= (1 << CP0St_UM
);
223 if (env
->hflags
& MIPS_HFLAG_ERL
)
224 T0
|= (1 << CP0St_ERL
);
225 if (env
->hflags
& MIPS_HFLAG_EXL
)
226 T0
|= (1 << CP0St_EXL
);
244 T0
= env
->CP0_Config0
;
248 T0
= env
->CP0_Config1
;
252 rn
= "Unknown config register";
257 T0
= env
->CP0_LLAddr
>> 4;
261 T0
= env
->CP0_WatchLo
;
265 T0
= env
->CP0_WatchHi
;
270 if (env
->hflags
& MIPS_HFLAG_DM
)
285 T0
= env
->CP0_DataLo
;
294 T0
= env
->CP0_ErrorEPC
;
298 T0
= env
->CP0_DESAVE
;
306 #if defined MIPS_DEBUG_DISAS
307 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
308 fprintf(logfile
, "%08x mfc0 %s => %08x (%d %d)\n",
309 env
->PC
, rn
, T0
, reg
, sel
);
315 void do_mtc0 (int reg
, int sel
)
317 const unsigned char *rn
;
318 uint32_t val
, old
, mask
;
320 if (sel
!= 0 && reg
!= 16 && reg
!= 28) {
328 val
= (env
->CP0_index
& 0x80000000) | (T0
& 0x0000000F);
329 old
= env
->CP0_index
;
330 env
->CP0_index
= val
;
334 val
= T0
& 0x03FFFFFFF;
335 old
= env
->CP0_EntryLo0
;
336 env
->CP0_EntryLo0
= val
;
340 val
= T0
& 0x03FFFFFFF;
341 old
= env
->CP0_EntryLo1
;
342 env
->CP0_EntryLo1
= val
;
346 val
= (env
->CP0_Context
& 0xFF000000) | (T0
& 0x00FFFFF0);
347 old
= env
->CP0_Context
;
348 env
->CP0_Context
= val
;
352 val
= T0
& 0x01FFE000;
353 old
= env
->CP0_PageMask
;
354 env
->CP0_PageMask
= val
;
358 val
= T0
& 0x0000000F;
359 old
= env
->CP0_Wired
;
360 env
->CP0_Wired
= val
;
365 old
= cpu_mips_get_count(env
);
366 cpu_mips_store_count(env
, val
);
370 val
= T0
& 0xFFFFF0FF;
371 old
= env
->CP0_EntryHi
;
372 env
->CP0_EntryHi
= val
;
373 /* If the ASID changes, flush qemu's TLB. */
374 if ((old
& 0xFF) != (val
& 0xFF))
380 old
= env
->CP0_Compare
;
381 cpu_mips_store_compare(env
, val
);
385 val
= T0
& 0xFA78FF01;
386 if (T0
& (1 << CP0St_UM
))
387 env
->hflags
|= MIPS_HFLAG_UM
;
389 env
->hflags
&= ~MIPS_HFLAG_UM
;
390 if (T0
& (1 << CP0St_ERL
))
391 env
->hflags
|= MIPS_HFLAG_ERL
;
393 env
->hflags
&= ~MIPS_HFLAG_ERL
;
394 if (T0
& (1 << CP0St_EXL
))
395 env
->hflags
|= MIPS_HFLAG_EXL
;
397 env
->hflags
&= ~MIPS_HFLAG_EXL
;
398 old
= env
->CP0_Status
;
399 env
->CP0_Status
= val
;
400 /* If we unmasked an asserted IRQ, raise it */
402 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
403 fprintf(logfile
, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
404 old
, val
, env
->CP0_Cause
, old
& mask
, val
& mask
,
405 env
->CP0_Cause
& mask
);
408 if ((val
& (1 << CP0St_IE
)) && !(old
& (1 << CP0St_IE
)) &&
409 !(env
->hflags
& MIPS_HFLAG_EXL
) &&
410 !(env
->hflags
& MIPS_HFLAG_ERL
) &&
411 !(env
->hflags
& MIPS_HFLAG_DM
) &&
412 (env
->CP0_Status
& env
->CP0_Cause
& mask
)) {
414 fprintf(logfile
, "Raise pending IRQs\n");
415 env
->interrupt_request
|= CPU_INTERRUPT_HARD
;
416 do_raise_exception(EXCP_EXT_INTERRUPT
);
417 } else if (!(val
& 0x00000001) && (old
& 0x00000001)) {
418 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
424 val
= (env
->CP0_Cause
& 0xB000F87C) | (T0
& 0x000C00300);
425 old
= env
->CP0_Cause
;
426 env
->CP0_Cause
= val
;
430 /* Check if we ever asserted a software IRQ */
431 for (i
= 0; i
< 2; i
++) {
433 if ((val
& mask
) & !(old
& mask
))
449 #if defined(MIPS_USES_R4K_TLB)
450 val
= (env
->CP0_Config0
& 0x8017FF80) | (T0
& 0x7E000001);
452 val
= (env
->CP0_Config0
& 0xFE17FF80) | (T0
& 0x00000001);
454 old
= env
->CP0_Config0
;
455 env
->CP0_Config0
= val
;
461 rn
= "bad config selector";
467 old
= env
->CP0_WatchLo
;
468 env
->CP0_WatchLo
= val
;
472 val
= T0
& 0x40FF0FF8;
473 old
= env
->CP0_WatchHi
;
474 env
->CP0_WatchHi
= val
;
478 val
= (env
->CP0_Debug
& 0x8C03FC1F) | (T0
& 0x13300120);
479 if (T0
& (1 << CP0DB_DM
))
480 env
->hflags
|= MIPS_HFLAG_DM
;
482 env
->hflags
&= ~MIPS_HFLAG_DM
;
483 old
= env
->CP0_Debug
;
484 env
->CP0_Debug
= val
;
496 val
= T0
& 0xFFFFFCF6;
497 old
= env
->CP0_TagLo
;
498 env
->CP0_TagLo
= val
;
510 old
= env
->CP0_ErrorEPC
;
511 env
->CP0_ErrorEPC
= val
;
516 old
= env
->CP0_DESAVE
;
517 env
->CP0_DESAVE
= val
;
527 #if defined MIPS_DEBUG_DISAS
528 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
529 fprintf(logfile
, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n",
530 env
->PC
, rn
, T0
, val
, reg
, sel
, old
);
537 #if defined(MIPS_USES_R4K_TLB)
538 static void invalidate_tb (int idx
)
541 target_ulong addr
, end
;
543 tlb
= &env
->tlb
[idx
];
546 end
= addr
+ (tlb
->end
- tlb
->VPN
);
547 tb_invalidate_page_range(addr
, end
);
548 /* FIXME: Might be faster to just invalidate the whole "tlb" here
549 and refill it on demand from our simulated TLB. */
551 while (addr
< tlb
->end
) {
552 tlb_flush_page (env
, addr
);
553 addr
+= TARGET_PAGE_SIZE
;
558 end
= addr
+ (tlb
->end
- tlb
->VPN
);
559 tb_invalidate_page_range(addr
, end
);
560 /* FIXME: Might be faster to just invalidate the whole "tlb" here
561 and refill it on demand from our simulated TLB. */
563 while (addr
< tlb
->end2
) {
564 tlb_flush_page (env
, addr
);
565 addr
+= TARGET_PAGE_SIZE
;
570 static void fill_tb (int idx
)
575 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
576 tlb
= &env
->tlb
[idx
];
577 tlb
->VPN
= env
->CP0_EntryHi
& 0xFFFFE000;
578 tlb
->ASID
= env
->CP0_EntryHi
& 0x000000FF;
579 size
= env
->CP0_PageMask
>> 13;
580 size
= 4 * (size
+ 1);
581 tlb
->end
= tlb
->VPN
+ (1 << (8 + size
));
582 tlb
->end2
= tlb
->end
+ (1 << (8 + size
));
583 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
584 tlb
->V
[0] = env
->CP0_EntryLo0
& 2;
585 tlb
->D
[0] = env
->CP0_EntryLo0
& 4;
586 tlb
->C
[0] = (env
->CP0_EntryLo0
>> 3) & 0x7;
587 tlb
->PFN
[0] = (env
->CP0_EntryLo0
>> 6) << 12;
588 tlb
->V
[1] = env
->CP0_EntryLo1
& 2;
589 tlb
->D
[1] = env
->CP0_EntryLo1
& 4;
590 tlb
->C
[1] = (env
->CP0_EntryLo1
>> 3) & 0x7;
591 tlb
->PFN
[1] = (env
->CP0_EntryLo1
>> 6) << 12;
596 /* Wildly undefined effects for CP0_index containing a too high value and
597 MIPS_TLB_NB not being a power of two. But so does real silicon. */
598 invalidate_tb(env
->CP0_index
& (MIPS_TLB_NB
- 1));
599 fill_tb(env
->CP0_index
& (MIPS_TLB_NB
- 1));
604 int r
= cpu_mips_get_random(env
);
617 tag
= (env
->CP0_EntryHi
& 0xFFFFE000);
618 ASID
= env
->CP0_EntryHi
& 0x000000FF;
619 for (i
= 0; i
< MIPS_TLB_NB
; i
++) {
621 /* Check ASID, virtual page number & size */
622 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && tlb
->VPN
== tag
) {
628 if (i
== MIPS_TLB_NB
) {
629 env
->CP0_index
|= 0x80000000;
638 tlb
= &env
->tlb
[env
->CP0_index
& (MIPS_TLB_NB
- 1)];
640 /* If this will change the current ASID, flush qemu's TLB. */
641 /* FIXME: Could avoid flushing things which match global entries... */
642 if ((env
->CP0_EntryHi
& 0xFF) != tlb
->ASID
)
645 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
646 size
= (tlb
->end
- tlb
->VPN
) >> 12;
647 env
->CP0_PageMask
= (size
- 1) << 13;
648 env
->CP0_EntryLo0
= tlb
->V
[0] | tlb
->D
[0] | (tlb
->C
[0] << 3) |
650 env
->CP0_EntryLo1
= tlb
->V
[1] | tlb
->D
[1] | (tlb
->C
[1] << 3) |
655 #endif /* !CONFIG_USER_ONLY */
657 void op_dump_ldst (const unsigned char *func
)
660 fprintf(logfile
, "%s => %08x %08x\n", __func__
, T0
, T1
);
666 fprintf(logfile
, "%s %08x at %08x (%08x)\n", __func__
,
667 T1
, T0
, env
->CP0_LLAddr
);
671 void debug_eret (void)
674 fprintf(logfile
, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n",
675 env
->PC
, env
->CP0_EPC
, env
->CP0_ErrorEPC
,
676 env
->hflags
& MIPS_HFLAG_ERL
? 1 : 0);
680 void do_pmon (int function
)
684 case 2: /* TODO: char inbyte(int waitflag); */
685 if (env
->gpr
[4] == 0)
688 case 11: /* TODO: char inbyte (void); */
693 printf("%c", env
->gpr
[4] & 0xFF);
699 unsigned char *fmt
= (void *)env
->gpr
[4];
706 #if !defined(CONFIG_USER_ONLY)
708 static void do_unaligned_access (target_ulong addr
, int is_write
, int is_user
, void *retaddr
);
710 #define MMUSUFFIX _mmu
714 #include "softmmu_template.h"
717 #include "softmmu_template.h"
720 #include "softmmu_template.h"
723 #include "softmmu_template.h"
725 static void do_unaligned_access (target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
727 env
->CP0_BadVAddr
= addr
;
728 do_restore_state (retaddr
);
729 do_raise_exception ((is_write
== 1) ? EXCP_AdES
: EXCP_AdEL
);
732 void tlb_fill (target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
734 TranslationBlock
*tb
;
739 /* XXX: hack to restore env in all cases, even if not called from
742 env
= cpu_single_env
;
743 ret
= cpu_mips_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
746 /* now we have a real cpu fault */
747 pc
= (unsigned long)retaddr
;
750 /* the PC is inside the translated code. It means that we have
751 a virtual CPU fault */
752 cpu_restore_state(tb
, env
, pc
, NULL
);
755 do_raise_exception_err(env
->exception_index
, env
->error_code
);