target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "exec.h"
  21
  22 #include "host-utils.h"
  23
  24 #include "helper.h"
  25 /*****************************************************************************/
  26 /* Exceptions processing helpers */
  27
  28 void helper_raise_exception_err (uint32_t exception, int error_code)
  29 {
  30 #if 1
  31     if (exception < 0x100)
  32         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  33 #endif
  34     env->exception_index = exception;
  35     env->error_code = error_code;
  36     cpu_loop_exit();
  37 }
  38
  39 void helper_raise_exception (uint32_t exception)
  40 {
  41     helper_raise_exception_err(exception, 0);
  42 }
  43
  44 void helper_interrupt_restart (void)
  45 {
  46     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
  47         !(env->CP0_Status & (1 << CP0St_ERL)) &&
  48         !(env->hflags & MIPS_HFLAG_DM) &&
  49         (env->CP0_Status & (1 << CP0St_IE)) &&
  50         (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
  51         env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
  52         helper_raise_exception(EXCP_EXT_INTERRUPT);
  53     }
  54 }
  55
  56 #if !defined(CONFIG_USER_ONLY)
  57 static void do_restore_state (void *pc_ptr)
  58 {
  59     TranslationBlock *tb;
  60     unsigned long pc = (unsigned long) pc_ptr;
  61
  62     tb = tb_find_pc (pc);
  63     if (tb) {
  64         cpu_restore_state (tb, env, pc, NULL);
  65     }
  66 }
  67 #endif
  68
  69 #if defined(CONFIG_USER_ONLY)
  70 #define HELPER_LD(name, insn, type)                                     \
  71 static inline type do_##name(target_ulong addr, int mem_idx)            \
  72 {                                                                       \
  73     return (type) insn##_raw(addr);                                     \
  74 }
  75 #else
  76 #define HELPER_LD(name, insn, type)                                     \
  77 static inline type do_##name(target_ulong addr, int mem_idx)            \
  78 {                                                                       \
  79     switch (mem_idx)                                                    \
  80     {                                                                   \
  81     case 0: return (type) insn##_kernel(addr); break;                   \
  82     case 1: return (type) insn##_super(addr); break;                    \
  83     default:                                                            \
  84     case 2: return (type) insn##_user(addr); break;                     \
  85     }                                                                   \
  86 }
  87 #endif
  88 HELPER_LD(lbu, ldub, uint8_t)
  89 HELPER_LD(lw, ldl, int32_t)
  90 #ifdef TARGET_MIPS64
  91 HELPER_LD(ld, ldq, int64_t)
  92 #endif
  93 #undef HELPER_LD
  94
  95 #if defined(CONFIG_USER_ONLY)
  96 #define HELPER_ST(name, insn, type)                                     \
  97 static inline void do_##name(target_ulong addr, type val, int mem_idx)  \
  98 {                                                                       \
  99     insn##_raw(addr, val);                                              \
 100 }
 101 #else
 102 #define HELPER_ST(name, insn, type)                                     \
 103 static inline void do_##name(target_ulong addr, type val, int mem_idx)  \
 104 {                                                                       \
 105     switch (mem_idx)                                                    \
 106     {                                                                   \
 107     case 0: insn##_kernel(addr, val); break;                            \
 108     case 1: insn##_super(addr, val); break;                             \
 109     default:                                                            \
 110     case 2: insn##_user(addr, val); break;                              \
 111     }                                                                   \
 112 }
 113 #endif
 114 HELPER_ST(sb, stb, uint8_t)
 115 HELPER_ST(sw, stl, uint32_t)
 116 #ifdef TARGET_MIPS64
 117 HELPER_ST(sd, stq, uint64_t)
 118 #endif
 119 #undef HELPER_ST
 120
 121 target_ulong helper_clo (target_ulong arg1)
 122 {
 123     return clo32(arg1);
 124 }
 125
 126 target_ulong helper_clz (target_ulong arg1)
 127 {
 128     return clz32(arg1);
 129 }
 130
 131 #if defined(TARGET_MIPS64)
 132 target_ulong helper_dclo (target_ulong arg1)
 133 {
 134     return clo64(arg1);
 135 }
 136
 137 target_ulong helper_dclz (target_ulong arg1)
 138 {
 139     return clz64(arg1);
 140 }
 141 #endif /* TARGET_MIPS64 */
 142
 143 /* 64 bits arithmetic for 32 bits hosts */
 144 static inline uint64_t get_HILO (void)
 145 {
 146     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 147 }
 148
 149 static inline void set_HILO (uint64_t HILO)
 150 {
 151     env->active_tc.LO[0] = (int32_t)HILO;
 152     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 153 }
 154
 155 static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
 156 {
 157     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 158     arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 159 }
 160
 161 static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
 162 {
 163     arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 164     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 165 }
 166
 167 /* Multiplication variants of the vr54xx. */
 168 target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
 169 {
 170     set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 171
 172     return arg1;
 173 }
 174
 175 target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
 176 {
 177     set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 178
 179     return arg1;
 180 }
 181
 182 target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
 183 {
 184     set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 185
 186     return arg1;
 187 }
 188
 189 target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
 190 {
 191     set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 192
 193     return arg1;
 194 }
 195
 196 target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
 197 {
 198     set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 199
 200     return arg1;
 201 }
 202
 203 target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
 204 {
 205     set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 206
 207     return arg1;
 208 }
 209
 210 target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
 211 {
 212     set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 213
 214     return arg1;
 215 }
 216
 217 target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
 218 {
 219     set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 220
 221     return arg1;
 222 }
 223
 224 target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
 225 {
 226     set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 227
 228     return arg1;
 229 }
 230
 231 target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
 232 {
 233     set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 234
 235     return arg1;
 236 }
 237
 238 target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
 239 {
 240     set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 241
 242     return arg1;
 243 }
 244
 245 target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
 246 {
 247     set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 248
 249     return arg1;
 250 }
 251
 252 target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
 253 {
 254     set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 255
 256     return arg1;
 257 }
 258
 259 target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
 260 {
 261     set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 262
 263     return arg1;
 264 }
 265
 266 #ifdef TARGET_MIPS64
 267 void helper_dmult (target_ulong arg1, target_ulong arg2)
 268 {
 269     muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 270 }
 271
 272 void helper_dmultu (target_ulong arg1, target_ulong arg2)
 273 {
 274     mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 275 }
 276 #endif
 277
 278 #ifndef CONFIG_USER_ONLY
 279
 280 static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
 281 {
 282     target_phys_addr_t lladdr;
 283
 284     lladdr = cpu_mips_translate_address(env, address, rw);
 285
 286     if (lladdr == -1LL) {
 287         cpu_loop_exit();
 288     } else {
 289         return lladdr;
 290     }
 291 }
 292
 293 #define HELPER_LD_ATOMIC(name, insn)                                          \
 294 target_ulong helper_##name(target_ulong arg, int mem_idx)                     \
 295 {                                                                             \
 296     env->lladdr = do_translate_address(arg, 0);                               \
 297     env->llval = do_##insn(arg, mem_idx);                                     \
 298     return env->llval;                                                        \
 299 }
 300 HELPER_LD_ATOMIC(ll, lw)
 301 #ifdef TARGET_MIPS64
 302 HELPER_LD_ATOMIC(lld, ld)
 303 #endif
 304 #undef HELPER_LD_ATOMIC
 305
 306 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 307 target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
 308 {                                                                             \
 309     target_long tmp;                                                          \
 310                                                                               \
 311     if (arg2 & almask) {                                                      \
 312         env->CP0_BadVAddr = arg2;                                             \
 313         helper_raise_exception(EXCP_AdES);                                    \
 314     }                                                                         \
 315     if (do_translate_address(arg2, 1) == env->lladdr) {                       \
 316         tmp = do_##ld_insn(arg2, mem_idx);                                    \
 317         if (tmp == env->llval) {                                              \
 318             do_##st_insn(arg2, arg1, mem_idx);                                \
 319             return 1;                                                         \
 320         }                                                                     \
 321     }                                                                         \
 322     return 0;                                                                 \
 323 }
 324 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 325 #ifdef TARGET_MIPS64
 326 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 327 #endif
 328 #undef HELPER_ST_ATOMIC
 329 #endif
 330
 331 #ifdef TARGET_WORDS_BIGENDIAN
 332 #define GET_LMASK(v) ((v) & 3)
 333 #define GET_OFFSET(addr, offset) (addr + (offset))
 334 #else
 335 #define GET_LMASK(v) (((v) & 3) ^ 3)
 336 #define GET_OFFSET(addr, offset) (addr - (offset))
 337 #endif
 338
 339 target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
 340 {
 341     target_ulong tmp;
 342
 343     tmp = do_lbu(arg2, mem_idx);
 344     arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
 345
 346     if (GET_LMASK(arg2) <= 2) {
 347         tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
 348         arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
 349     }
 350
 351     if (GET_LMASK(arg2) <= 1) {
 352         tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
 353         arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
 354     }
 355
 356     if (GET_LMASK(arg2) == 0) {
 357         tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
 358         arg1 = (arg1 & 0xFFFFFF00) | tmp;
 359     }
 360     return (int32_t)arg1;
 361 }
 362
 363 target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
 364 {
 365     target_ulong tmp;
 366
 367     tmp = do_lbu(arg2, mem_idx);
 368     arg1 = (arg1 & 0xFFFFFF00) | tmp;
 369
 370     if (GET_LMASK(arg2) >= 1) {
 371         tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
 372         arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
 373     }
 374
 375     if (GET_LMASK(arg2) >= 2) {
 376         tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
 377         arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
 378     }
 379
 380     if (GET_LMASK(arg2) == 3) {
 381         tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
 382         arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
 383     }
 384     return (int32_t)arg1;
 385 }
 386
 387 void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
 388 {
 389     do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
 390
 391     if (GET_LMASK(arg2) <= 2)
 392         do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 393
 394     if (GET_LMASK(arg2) <= 1)
 395         do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 396
 397     if (GET_LMASK(arg2) == 0)
 398         do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 399 }
 400
 401 void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
 402 {
 403     do_sb(arg2, (uint8_t)arg1, mem_idx);
 404
 405     if (GET_LMASK(arg2) >= 1)
 406         do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 407
 408     if (GET_LMASK(arg2) >= 2)
 409         do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 410
 411     if (GET_LMASK(arg2) == 3)
 412         do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 413 }
 414
 415 #if defined(TARGET_MIPS64)
 416 /* "half" load and stores.  We must do the memory access inline,
 417    or fault handling won't work.  */
 418
 419 #ifdef TARGET_WORDS_BIGENDIAN
 420 #define GET_LMASK64(v) ((v) & 7)
 421 #else
 422 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 423 #endif
 424
 425 target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
 426 {
 427     uint64_t tmp;
 428
 429     tmp = do_lbu(arg2, mem_idx);
 430     arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 431
 432     if (GET_LMASK64(arg2) <= 6) {
 433         tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
 434         arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
 435     }
 436
 437     if (GET_LMASK64(arg2) <= 5) {
 438         tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
 439         arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
 440     }
 441
 442     if (GET_LMASK64(arg2) <= 4) {
 443         tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
 444         arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
 445     }
 446
 447     if (GET_LMASK64(arg2) <= 3) {
 448         tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
 449         arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
 450     }
 451
 452     if (GET_LMASK64(arg2) <= 2) {
 453         tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
 454         arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
 455     }
 456
 457     if (GET_LMASK64(arg2) <= 1) {
 458         tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
 459         arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
 460     }
 461
 462     if (GET_LMASK64(arg2) == 0) {
 463         tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
 464         arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 465     }
 466
 467     return arg1;
 468 }
 469
 470 target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
 471 {
 472     uint64_t tmp;
 473
 474     tmp = do_lbu(arg2, mem_idx);
 475     arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 476
 477     if (GET_LMASK64(arg2) >= 1) {
 478         tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
 479         arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
 480     }
 481
 482     if (GET_LMASK64(arg2) >= 2) {
 483         tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
 484         arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
 485     }
 486
 487     if (GET_LMASK64(arg2) >= 3) {
 488         tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
 489         arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
 490     }
 491
 492     if (GET_LMASK64(arg2) >= 4) {
 493         tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
 494         arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
 495     }
 496
 497     if (GET_LMASK64(arg2) >= 5) {
 498         tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
 499         arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
 500     }
 501
 502     if (GET_LMASK64(arg2) >= 6) {
 503         tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
 504         arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
 505     }
 506
 507     if (GET_LMASK64(arg2) == 7) {
 508         tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
 509         arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 510     }
 511
 512     return arg1;
 513 }
 514
 515 void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
 516 {
 517     do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
 518
 519     if (GET_LMASK64(arg2) <= 6)
 520         do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 521
 522     if (GET_LMASK64(arg2) <= 5)
 523         do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 524
 525     if (GET_LMASK64(arg2) <= 4)
 526         do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 527
 528     if (GET_LMASK64(arg2) <= 3)
 529         do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 530
 531     if (GET_LMASK64(arg2) <= 2)
 532         do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 533
 534     if (GET_LMASK64(arg2) <= 1)
 535         do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 536
 537     if (GET_LMASK64(arg2) <= 0)
 538         do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 539 }
 540
 541 void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
 542 {
 543     do_sb(arg2, (uint8_t)arg1, mem_idx);
 544
 545     if (GET_LMASK64(arg2) >= 1)
 546         do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 547
 548     if (GET_LMASK64(arg2) >= 2)
 549         do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 550
 551     if (GET_LMASK64(arg2) >= 3)
 552         do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 553
 554     if (GET_LMASK64(arg2) >= 4)
 555         do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 556
 557     if (GET_LMASK64(arg2) >= 5)
 558         do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 559
 560     if (GET_LMASK64(arg2) >= 6)
 561         do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 562
 563     if (GET_LMASK64(arg2) == 7)
 564         do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 565 }
 566 #endif /* TARGET_MIPS64 */
 567
 568 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 569
 570 void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
 571 {
 572     target_ulong base_reglist = reglist & 0xf;
 573     target_ulong do_r31 = reglist & 0x10;
 574 #ifdef CONFIG_USER_ONLY
 575 #undef ldfun
 576 #define ldfun ldl_raw
 577 #else
 578     uint32_t (*ldfun)(target_ulong);
 579
 580     switch (mem_idx)
 581     {
 582     case 0: ldfun = ldl_kernel; break;
 583     case 1: ldfun = ldl_super; break;
 584     default:
 585     case 2: ldfun = ldl_user; break;
 586     }
 587 #endif
 588
 589     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 590         target_ulong i;
 591
 592         for (i = 0; i < base_reglist; i++) {
 593             env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr);
 594             addr += 4;
 595         }
 596     }
 597
 598     if (do_r31) {
 599         env->active_tc.gpr[31] = (target_long) ldfun(addr);
 600     }
 601 }
 602
 603 void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
 604 {
 605     target_ulong base_reglist = reglist & 0xf;
 606     target_ulong do_r31 = reglist & 0x10;
 607 #ifdef CONFIG_USER_ONLY
 608 #undef stfun
 609 #define stfun stl_raw
 610 #else
 611     void (*stfun)(target_ulong, uint32_t);
 612
 613     switch (mem_idx)
 614     {
 615     case 0: stfun = stl_kernel; break;
 616     case 1: stfun = stl_super; break;
 617      default:
 618     case 2: stfun = stl_user; break;
 619     }
 620 #endif
 621
 622     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 623         target_ulong i;
 624
 625         for (i = 0; i < base_reglist; i++) {
 626             stfun(addr, env->active_tc.gpr[multiple_regs[i]]);
 627             addr += 4;
 628         }
 629     }
 630
 631     if (do_r31) {
 632         stfun(addr, env->active_tc.gpr[31]);
 633     }
 634 }
 635
 636 #if defined(TARGET_MIPS64)
 637 void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
 638 {
 639     target_ulong base_reglist = reglist & 0xf;
 640     target_ulong do_r31 = reglist & 0x10;
 641 #ifdef CONFIG_USER_ONLY
 642 #undef ldfun
 643 #define ldfun ldq_raw
 644 #else
 645     uint64_t (*ldfun)(target_ulong);
 646
 647     switch (mem_idx)
 648     {
 649     case 0: ldfun = ldq_kernel; break;
 650     case 1: ldfun = ldq_super; break;
 651     default:
 652     case 2: ldfun = ldq_user; break;
 653     }
 654 #endif
 655
 656     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 657         target_ulong i;
 658
 659         for (i = 0; i < base_reglist; i++) {
 660             env->active_tc.gpr[multiple_regs[i]] = ldfun(addr);
 661             addr += 8;
 662         }
 663     }
 664
 665     if (do_r31) {
 666         env->active_tc.gpr[31] = ldfun(addr);
 667     }
 668 }
 669
 670 void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
 671 {
 672     target_ulong base_reglist = reglist & 0xf;
 673     target_ulong do_r31 = reglist & 0x10;
 674 #ifdef CONFIG_USER_ONLY
 675 #undef stfun
 676 #define stfun stq_raw
 677 #else
 678     void (*stfun)(target_ulong, uint64_t);
 679
 680     switch (mem_idx)
 681     {
 682     case 0: stfun = stq_kernel; break;
 683     case 1: stfun = stq_super; break;
 684      default:
 685     case 2: stfun = stq_user; break;
 686     }
 687 #endif
 688
 689     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 690         target_ulong i;
 691
 692         for (i = 0; i < base_reglist; i++) {
 693             stfun(addr, env->active_tc.gpr[multiple_regs[i]]);
 694             addr += 8;
 695         }
 696     }
 697
 698     if (do_r31) {
 699         stfun(addr, env->active_tc.gpr[31]);
 700     }
 701 }
 702 #endif
 703
 704 #ifndef CONFIG_USER_ONLY
 705 /* CP0 helpers */
 706 target_ulong helper_mfc0_mvpcontrol (void)
 707 {
 708     return env->mvp->CP0_MVPControl;
 709 }
 710
 711 target_ulong helper_mfc0_mvpconf0 (void)
 712 {
 713     return env->mvp->CP0_MVPConf0;
 714 }
 715
 716 target_ulong helper_mfc0_mvpconf1 (void)
 717 {
 718     return env->mvp->CP0_MVPConf1;
 719 }
 720
 721 target_ulong helper_mfc0_random (void)
 722 {
 723     return (int32_t)cpu_mips_get_random(env);
 724 }
 725
 726 target_ulong helper_mfc0_tcstatus (void)
 727 {
 728     return env->active_tc.CP0_TCStatus;
 729 }
 730
 731 target_ulong helper_mftc0_tcstatus(void)
 732 {
 733     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 734
 735     if (other_tc == env->current_tc)
 736         return env->active_tc.CP0_TCStatus;
 737     else
 738         return env->tcs[other_tc].CP0_TCStatus;
 739 }
 740
 741 target_ulong helper_mfc0_tcbind (void)
 742 {
 743     return env->active_tc.CP0_TCBind;
 744 }
 745
 746 target_ulong helper_mftc0_tcbind(void)
 747 {
 748     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 749
 750     if (other_tc == env->current_tc)
 751         return env->active_tc.CP0_TCBind;
 752     else
 753         return env->tcs[other_tc].CP0_TCBind;
 754 }
 755
 756 target_ulong helper_mfc0_tcrestart (void)
 757 {
 758     return env->active_tc.PC;
 759 }
 760
 761 target_ulong helper_mftc0_tcrestart(void)
 762 {
 763     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 764
 765     if (other_tc == env->current_tc)
 766         return env->active_tc.PC;
 767     else
 768         return env->tcs[other_tc].PC;
 769 }
 770
 771 target_ulong helper_mfc0_tchalt (void)
 772 {
 773     return env->active_tc.CP0_TCHalt;
 774 }
 775
 776 target_ulong helper_mftc0_tchalt(void)
 777 {
 778     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 779
 780     if (other_tc == env->current_tc)
 781         return env->active_tc.CP0_TCHalt;
 782     else
 783         return env->tcs[other_tc].CP0_TCHalt;
 784 }
 785
 786 target_ulong helper_mfc0_tccontext (void)
 787 {
 788     return env->active_tc.CP0_TCContext;
 789 }
 790
 791 target_ulong helper_mftc0_tccontext(void)
 792 {
 793     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 794
 795     if (other_tc == env->current_tc)
 796         return env->active_tc.CP0_TCContext;
 797     else
 798         return env->tcs[other_tc].CP0_TCContext;
 799 }
 800
 801 target_ulong helper_mfc0_tcschedule (void)
 802 {
 803     return env->active_tc.CP0_TCSchedule;
 804 }
 805
 806 target_ulong helper_mftc0_tcschedule(void)
 807 {
 808     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 809
 810     if (other_tc == env->current_tc)
 811         return env->active_tc.CP0_TCSchedule;
 812     else
 813         return env->tcs[other_tc].CP0_TCSchedule;
 814 }
 815
 816 target_ulong helper_mfc0_tcschefback (void)
 817 {
 818     return env->active_tc.CP0_TCScheFBack;
 819 }
 820
 821 target_ulong helper_mftc0_tcschefback(void)
 822 {
 823     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 824
 825     if (other_tc == env->current_tc)
 826         return env->active_tc.CP0_TCScheFBack;
 827     else
 828         return env->tcs[other_tc].CP0_TCScheFBack;
 829 }
 830
 831 target_ulong helper_mfc0_count (void)
 832 {
 833     return (int32_t)cpu_mips_get_count(env);
 834 }
 835
 836 target_ulong helper_mftc0_entryhi(void)
 837 {
 838     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 839     int32_t tcstatus;
 840
 841     if (other_tc == env->current_tc)
 842         tcstatus = env->active_tc.CP0_TCStatus;
 843     else
 844         tcstatus = env->tcs[other_tc].CP0_TCStatus;
 845
 846     return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
 847 }
 848
 849 target_ulong helper_mftc0_status(void)
 850 {
 851     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 852     target_ulong t0;
 853     int32_t tcstatus;
 854
 855     if (other_tc == env->current_tc)
 856         tcstatus = env->active_tc.CP0_TCStatus;
 857     else
 858         tcstatus = env->tcs[other_tc].CP0_TCStatus;
 859
 860     t0 = env->CP0_Status & ~0xf1000018;
 861     t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
 862     t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
 863     t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
 864
 865     return t0;
 866 }
 867
 868 target_ulong helper_mfc0_lladdr (void)
 869 {
 870     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 871 }
 872
 873 target_ulong helper_mfc0_watchlo (uint32_t sel)
 874 {
 875     return (int32_t)env->CP0_WatchLo[sel];
 876 }
 877
 878 target_ulong helper_mfc0_watchhi (uint32_t sel)
 879 {
 880     return env->CP0_WatchHi[sel];
 881 }
 882
 883 target_ulong helper_mfc0_debug (void)
 884 {
 885     target_ulong t0 = env->CP0_Debug;
 886     if (env->hflags & MIPS_HFLAG_DM)
 887         t0 |= 1 << CP0DB_DM;
 888
 889     return t0;
 890 }
 891
 892 target_ulong helper_mftc0_debug(void)
 893 {
 894     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 895     int32_t tcstatus;
 896
 897     if (other_tc == env->current_tc)
 898         tcstatus = env->active_tc.CP0_Debug_tcstatus;
 899     else
 900         tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
 901
 902     /* XXX: Might be wrong, check with EJTAG spec. */
 903     return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 904             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 905 }
 906
 907 #if defined(TARGET_MIPS64)
 908 target_ulong helper_dmfc0_tcrestart (void)
 909 {
 910     return env->active_tc.PC;
 911 }
 912
 913 target_ulong helper_dmfc0_tchalt (void)
 914 {
 915     return env->active_tc.CP0_TCHalt;
 916 }
 917
 918 target_ulong helper_dmfc0_tccontext (void)
 919 {
 920     return env->active_tc.CP0_TCContext;
 921 }
 922
 923 target_ulong helper_dmfc0_tcschedule (void)
 924 {
 925     return env->active_tc.CP0_TCSchedule;
 926 }
 927
 928 target_ulong helper_dmfc0_tcschefback (void)
 929 {
 930     return env->active_tc.CP0_TCScheFBack;
 931 }
 932
 933 target_ulong helper_dmfc0_lladdr (void)
 934 {
 935     return env->lladdr >> env->CP0_LLAddr_shift;
 936 }
 937
 938 target_ulong helper_dmfc0_watchlo (uint32_t sel)
 939 {
 940     return env->CP0_WatchLo[sel];
 941 }
 942 #endif /* TARGET_MIPS64 */
 943
 944 void helper_mtc0_index (target_ulong arg1)
 945 {
 946     int num = 1;
 947     unsigned int tmp = env->tlb->nb_tlb;
 948
 949     do {
 950         tmp >>= 1;
 951         num <<= 1;
 952     } while (tmp);
 953     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 954 }
 955
 956 void helper_mtc0_mvpcontrol (target_ulong arg1)
 957 {
 958     uint32_t mask = 0;
 959     uint32_t newval;
 960
 961     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 962         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 963                 (1 << CP0MVPCo_EVP);
 964     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 965         mask |= (1 << CP0MVPCo_STLB);
 966     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 967
 968     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 969
 970     env->mvp->CP0_MVPControl = newval;
 971 }
 972
 973 void helper_mtc0_vpecontrol (target_ulong arg1)
 974 {
 975     uint32_t mask;
 976     uint32_t newval;
 977
 978     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 979            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 980     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 981
 982     /* Yield scheduler intercept not implemented. */
 983     /* Gating storage scheduler intercept not implemented. */
 984
 985     // TODO: Enable/disable TCs.
 986
 987     env->CP0_VPEControl = newval;
 988 }
 989
 990 void helper_mtc0_vpeconf0 (target_ulong arg1)
 991 {
 992     uint32_t mask = 0;
 993     uint32_t newval;
 994
 995     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
 996         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
 997             mask |= (0xff << CP0VPEC0_XTC);
 998         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 999     }
1000     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1001
1002     // TODO: TC exclusive handling due to ERL/EXL.
1003
1004     env->CP0_VPEConf0 = newval;
1005 }
1006
1007 void helper_mtc0_vpeconf1 (target_ulong arg1)
1008 {
1009     uint32_t mask = 0;
1010     uint32_t newval;
1011
1012     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1013         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1014                 (0xff << CP0VPEC1_NCP1);
1015     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1016
1017     /* UDI not implemented. */
1018     /* CP2 not implemented. */
1019
1020     // TODO: Handle FPU (CP1) binding.
1021
1022     env->CP0_VPEConf1 = newval;
1023 }
1024
1025 void helper_mtc0_yqmask (target_ulong arg1)
1026 {
1027     /* Yield qualifier inputs not implemented. */
1028     env->CP0_YQMask = 0x00000000;
1029 }
1030
1031 void helper_mtc0_vpeopt (target_ulong arg1)
1032 {
1033     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1034 }
1035
1036 void helper_mtc0_entrylo0 (target_ulong arg1)
1037 {
1038     /* Large physaddr (PABITS) not implemented */
1039     /* 1k pages not implemented */
1040     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1041 }
1042
1043 void helper_mtc0_tcstatus (target_ulong arg1)
1044 {
1045     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1046     uint32_t newval;
1047
1048     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1049
1050     // TODO: Sync with CP0_Status.
1051
1052     env->active_tc.CP0_TCStatus = newval;
1053 }
1054
1055 void helper_mttc0_tcstatus (target_ulong arg1)
1056 {
1057     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1058
1059     // TODO: Sync with CP0_Status.
1060
1061     if (other_tc == env->current_tc)
1062         env->active_tc.CP0_TCStatus = arg1;
1063     else
1064         env->tcs[other_tc].CP0_TCStatus = arg1;
1065 }
1066
1067 void helper_mtc0_tcbind (target_ulong arg1)
1068 {
1069     uint32_t mask = (1 << CP0TCBd_TBE);
1070     uint32_t newval;
1071
1072     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1073         mask |= (1 << CP0TCBd_CurVPE);
1074     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1075     env->active_tc.CP0_TCBind = newval;
1076 }
1077
1078 void helper_mttc0_tcbind (target_ulong arg1)
1079 {
1080     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1081     uint32_t mask = (1 << CP0TCBd_TBE);
1082     uint32_t newval;
1083
1084     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1085         mask |= (1 << CP0TCBd_CurVPE);
1086     if (other_tc == env->current_tc) {
1087         newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1088         env->active_tc.CP0_TCBind = newval;
1089     } else {
1090         newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1091         env->tcs[other_tc].CP0_TCBind = newval;
1092     }
1093 }
1094
1095 void helper_mtc0_tcrestart (target_ulong arg1)
1096 {
1097     env->active_tc.PC = arg1;
1098     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1099     env->lladdr = 0ULL;
1100     /* MIPS16 not implemented. */
1101 }
1102
1103 void helper_mttc0_tcrestart (target_ulong arg1)
1104 {
1105     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1106
1107     if (other_tc == env->current_tc) {
1108         env->active_tc.PC = arg1;
1109         env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1110         env->lladdr = 0ULL;
1111         /* MIPS16 not implemented. */
1112     } else {
1113         env->tcs[other_tc].PC = arg1;
1114         env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1115         env->lladdr = 0ULL;
1116         /* MIPS16 not implemented. */
1117     }
1118 }
1119
1120 void helper_mtc0_tchalt (target_ulong arg1)
1121 {
1122     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1123
1124     // TODO: Halt TC / Restart (if allocated+active) TC.
1125 }
1126
1127 void helper_mttc0_tchalt (target_ulong arg1)
1128 {
1129     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1130
1131     // TODO: Halt TC / Restart (if allocated+active) TC.
1132
1133     if (other_tc == env->current_tc)
1134         env->active_tc.CP0_TCHalt = arg1;
1135     else
1136         env->tcs[other_tc].CP0_TCHalt = arg1;
1137 }
1138
1139 void helper_mtc0_tccontext (target_ulong arg1)
1140 {
1141     env->active_tc.CP0_TCContext = arg1;
1142 }
1143
1144 void helper_mttc0_tccontext (target_ulong arg1)
1145 {
1146     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1147
1148     if (other_tc == env->current_tc)
1149         env->active_tc.CP0_TCContext = arg1;
1150     else
1151         env->tcs[other_tc].CP0_TCContext = arg1;
1152 }
1153
1154 void helper_mtc0_tcschedule (target_ulong arg1)
1155 {
1156     env->active_tc.CP0_TCSchedule = arg1;
1157 }
1158
1159 void helper_mttc0_tcschedule (target_ulong arg1)
1160 {
1161     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1162
1163     if (other_tc == env->current_tc)
1164         env->active_tc.CP0_TCSchedule = arg1;
1165     else
1166         env->tcs[other_tc].CP0_TCSchedule = arg1;
1167 }
1168
1169 void helper_mtc0_tcschefback (target_ulong arg1)
1170 {
1171     env->active_tc.CP0_TCScheFBack = arg1;
1172 }
1173
1174 void helper_mttc0_tcschefback (target_ulong arg1)
1175 {
1176     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1177
1178     if (other_tc == env->current_tc)
1179         env->active_tc.CP0_TCScheFBack = arg1;
1180     else
1181         env->tcs[other_tc].CP0_TCScheFBack = arg1;
1182 }
1183
1184 void helper_mtc0_entrylo1 (target_ulong arg1)
1185 {
1186     /* Large physaddr (PABITS) not implemented */
1187     /* 1k pages not implemented */
1188     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1189 }
1190
1191 void helper_mtc0_context (target_ulong arg1)
1192 {
1193     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1194 }
1195
1196 void helper_mtc0_pagemask (target_ulong arg1)
1197 {
1198     /* 1k pages not implemented */
1199     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1200 }
1201
1202 void helper_mtc0_pagegrain (target_ulong arg1)
1203 {
1204     /* SmartMIPS not implemented */
1205     /* Large physaddr (PABITS) not implemented */
1206     /* 1k pages not implemented */
1207     env->CP0_PageGrain = 0;
1208 }
1209
1210 void helper_mtc0_wired (target_ulong arg1)
1211 {
1212     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1213 }
1214
1215 void helper_mtc0_srsconf0 (target_ulong arg1)
1216 {
1217     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1218 }
1219
1220 void helper_mtc0_srsconf1 (target_ulong arg1)
1221 {
1222     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1223 }
1224
1225 void helper_mtc0_srsconf2 (target_ulong arg1)
1226 {
1227     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1228 }
1229
1230 void helper_mtc0_srsconf3 (target_ulong arg1)
1231 {
1232     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1233 }
1234
1235 void helper_mtc0_srsconf4 (target_ulong arg1)
1236 {
1237     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1238 }
1239
1240 void helper_mtc0_hwrena (target_ulong arg1)
1241 {
1242     env->CP0_HWREna = arg1 & 0x0000000F;
1243 }
1244
1245 void helper_mtc0_count (target_ulong arg1)
1246 {
1247     cpu_mips_store_count(env, arg1);
1248 }
1249
1250 void helper_mtc0_entryhi (target_ulong arg1)
1251 {
1252     target_ulong old, val;
1253
1254     /* 1k pages not implemented */
1255     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1256 #if defined(TARGET_MIPS64)
1257     val &= env->SEGMask;
1258 #endif
1259     old = env->CP0_EntryHi;
1260     env->CP0_EntryHi = val;
1261     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1262         uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1263         env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
1264     }
1265     /* If the ASID changes, flush qemu's TLB.  */
1266     if ((old & 0xFF) != (val & 0xFF))
1267         cpu_mips_tlb_flush(env, 1);
1268 }
1269
1270 void helper_mttc0_entryhi(target_ulong arg1)
1271 {
1272     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1273     int32_t tcstatus;
1274
1275     env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
1276     if (other_tc == env->current_tc) {
1277         tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1278         env->active_tc.CP0_TCStatus = tcstatus;
1279     } else {
1280         tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1281         env->tcs[other_tc].CP0_TCStatus = tcstatus;
1282     }
1283 }
1284
1285 void helper_mtc0_compare (target_ulong arg1)
1286 {
1287     cpu_mips_store_compare(env, arg1);
1288 }
1289
1290 void helper_mtc0_status (target_ulong arg1)
1291 {
1292     uint32_t val, old;
1293     uint32_t mask = env->CP0_Status_rw_bitmask;
1294
1295     val = arg1 & mask;
1296     old = env->CP0_Status;
1297     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1298     compute_hflags(env);
1299     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1300         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1301                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1302                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1303                 env->CP0_Cause);
1304         switch (env->hflags & MIPS_HFLAG_KSU) {
1305         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1306         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1307         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1308         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1309         }
1310     }
1311     cpu_mips_update_irq(env);
1312 }
1313
1314 void helper_mttc0_status(target_ulong arg1)
1315 {
1316     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1317     int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
1318
1319     env->CP0_Status = arg1 & ~0xf1000018;
1320     tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
1321     tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1322     tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1323     if (other_tc == env->current_tc)
1324         env->active_tc.CP0_TCStatus = tcstatus;
1325     else
1326         env->tcs[other_tc].CP0_TCStatus = tcstatus;
1327 }
1328
1329 void helper_mtc0_intctl (target_ulong arg1)
1330 {
1331     /* vectored interrupts not implemented, no performance counters. */
1332     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
1333 }
1334
1335 void helper_mtc0_srsctl (target_ulong arg1)
1336 {
1337     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1338     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1339 }
1340
1341 void helper_mtc0_cause (target_ulong arg1)
1342 {
1343     uint32_t mask = 0x00C00300;
1344     uint32_t old = env->CP0_Cause;
1345
1346     if (env->insn_flags & ISA_MIPS32R2)
1347         mask |= 1 << CP0Ca_DC;
1348
1349     env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
1350
1351     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1352         if (env->CP0_Cause & (1 << CP0Ca_DC))
1353             cpu_mips_stop_count(env);
1354         else
1355             cpu_mips_start_count(env);
1356     }
1357
1358     /* Handle the software interrupt as an hardware one, as they
1359        are very similar */
1360     if (arg1 & CP0Ca_IP_mask) {
1361         cpu_mips_update_irq(env);
1362     }
1363 }
1364
1365 void helper_mtc0_ebase (target_ulong arg1)
1366 {
1367     /* vectored interrupts not implemented */
1368     /* Multi-CPU not implemented */
1369     env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
1370 }
1371
1372 void helper_mtc0_config0 (target_ulong arg1)
1373 {
1374     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1375 }
1376
1377 void helper_mtc0_config2 (target_ulong arg1)
1378 {
1379     /* tertiary/secondary caches not implemented */
1380     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1381 }
1382
1383 void helper_mtc0_lladdr (target_ulong arg1)
1384 {
1385     target_long mask = env->CP0_LLAddr_rw_bitmask;
1386     arg1 = arg1 << env->CP0_LLAddr_shift;
1387     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1388 }
1389
1390 void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
1391 {
1392     /* Watch exceptions for instructions, data loads, data stores
1393        not implemented. */
1394     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1395 }
1396
1397 void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
1398 {
1399     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1400     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1401 }
1402
1403 void helper_mtc0_xcontext (target_ulong arg1)
1404 {
1405     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1406     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1407 }
1408
1409 void helper_mtc0_framemask (target_ulong arg1)
1410 {
1411     env->CP0_Framemask = arg1; /* XXX */
1412 }
1413
1414 void helper_mtc0_debug (target_ulong arg1)
1415 {
1416     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1417     if (arg1 & (1 << CP0DB_DM))
1418         env->hflags |= MIPS_HFLAG_DM;
1419     else
1420         env->hflags &= ~MIPS_HFLAG_DM;
1421 }
1422
1423 void helper_mttc0_debug(target_ulong arg1)
1424 {
1425     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1426     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1427
1428     /* XXX: Might be wrong, check with EJTAG spec. */
1429     if (other_tc == env->current_tc)
1430         env->active_tc.CP0_Debug_tcstatus = val;
1431     else
1432         env->tcs[other_tc].CP0_Debug_tcstatus = val;
1433     env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1434                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1435 }
1436
1437 void helper_mtc0_performance0 (target_ulong arg1)
1438 {
1439     env->CP0_Performance0 = arg1 & 0x000007ff;
1440 }
1441
1442 void helper_mtc0_taglo (target_ulong arg1)
1443 {
1444     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1445 }
1446
1447 void helper_mtc0_datalo (target_ulong arg1)
1448 {
1449     env->CP0_DataLo = arg1; /* XXX */
1450 }
1451
1452 void helper_mtc0_taghi (target_ulong arg1)
1453 {
1454     env->CP0_TagHi = arg1; /* XXX */
1455 }
1456
1457 void helper_mtc0_datahi (target_ulong arg1)
1458 {
1459     env->CP0_DataHi = arg1; /* XXX */
1460 }
1461
1462 /* MIPS MT functions */
1463 target_ulong helper_mftgpr(uint32_t sel)
1464 {
1465     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1466
1467     if (other_tc == env->current_tc)
1468         return env->active_tc.gpr[sel];
1469     else
1470         return env->tcs[other_tc].gpr[sel];
1471 }
1472
1473 target_ulong helper_mftlo(uint32_t sel)
1474 {
1475     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1476
1477     if (other_tc == env->current_tc)
1478         return env->active_tc.LO[sel];
1479     else
1480         return env->tcs[other_tc].LO[sel];
1481 }
1482
1483 target_ulong helper_mfthi(uint32_t sel)
1484 {
1485     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1486
1487     if (other_tc == env->current_tc)
1488         return env->active_tc.HI[sel];
1489     else
1490         return env->tcs[other_tc].HI[sel];
1491 }
1492
1493 target_ulong helper_mftacx(uint32_t sel)
1494 {
1495     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1496
1497     if (other_tc == env->current_tc)
1498         return env->active_tc.ACX[sel];
1499     else
1500         return env->tcs[other_tc].ACX[sel];
1501 }
1502
1503 target_ulong helper_mftdsp(void)
1504 {
1505     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1506
1507     if (other_tc == env->current_tc)
1508         return env->active_tc.DSPControl;
1509     else
1510         return env->tcs[other_tc].DSPControl;
1511 }
1512
1513 void helper_mttgpr(target_ulong arg1, uint32_t sel)
1514 {
1515     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1516
1517     if (other_tc == env->current_tc)
1518         env->active_tc.gpr[sel] = arg1;
1519     else
1520         env->tcs[other_tc].gpr[sel] = arg1;
1521 }
1522
1523 void helper_mttlo(target_ulong arg1, uint32_t sel)
1524 {
1525     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1526
1527     if (other_tc == env->current_tc)
1528         env->active_tc.LO[sel] = arg1;
1529     else
1530         env->tcs[other_tc].LO[sel] = arg1;
1531 }
1532
1533 void helper_mtthi(target_ulong arg1, uint32_t sel)
1534 {
1535     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1536
1537     if (other_tc == env->current_tc)
1538         env->active_tc.HI[sel] = arg1;
1539     else
1540         env->tcs[other_tc].HI[sel] = arg1;
1541 }
1542
1543 void helper_mttacx(target_ulong arg1, uint32_t sel)
1544 {
1545     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1546
1547     if (other_tc == env->current_tc)
1548         env->active_tc.ACX[sel] = arg1;
1549     else
1550         env->tcs[other_tc].ACX[sel] = arg1;
1551 }
1552
1553 void helper_mttdsp(target_ulong arg1)
1554 {
1555     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1556
1557     if (other_tc == env->current_tc)
1558         env->active_tc.DSPControl = arg1;
1559     else
1560         env->tcs[other_tc].DSPControl = arg1;
1561 }
1562
1563 /* MIPS MT functions */
1564 target_ulong helper_dmt(target_ulong arg1)
1565 {
1566     // TODO
1567     arg1 = 0;
1568     // rt = arg1
1569
1570     return arg1;
1571 }
1572
1573 target_ulong helper_emt(target_ulong arg1)
1574 {
1575     // TODO
1576     arg1 = 0;
1577     // rt = arg1
1578
1579     return arg1;
1580 }
1581
1582 target_ulong helper_dvpe(target_ulong arg1)
1583 {
1584     // TODO
1585     arg1 = 0;
1586     // rt = arg1
1587
1588     return arg1;
1589 }
1590
1591 target_ulong helper_evpe(target_ulong arg1)
1592 {
1593     // TODO
1594     arg1 = 0;
1595     // rt = arg1
1596
1597     return arg1;
1598 }
1599 #endif /* !CONFIG_USER_ONLY */
1600
1601 void helper_fork(target_ulong arg1, target_ulong arg2)
1602 {
1603     // arg1 = rt, arg2 = rs
1604     arg1 = 0;
1605     // TODO: store to TC register
1606 }
1607
1608 target_ulong helper_yield(target_ulong arg1)
1609 {
1610     if (arg1 < 0) {
1611         /* No scheduling policy implemented. */
1612         if (arg1 != -2) {
1613             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1614                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1615                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1616                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1617                 helper_raise_exception(EXCP_THREAD);
1618             }
1619         }
1620     } else if (arg1 == 0) {
1621         if (0 /* TODO: TC underflow */) {
1622             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1623             helper_raise_exception(EXCP_THREAD);
1624         } else {
1625             // TODO: Deallocate TC
1626         }
1627     } else if (arg1 > 0) {
1628         /* Yield qualifier inputs not implemented. */
1629         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1630         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1631         helper_raise_exception(EXCP_THREAD);
1632     }
1633     return env->CP0_YQMask;
1634 }
1635
1636 #ifndef CONFIG_USER_ONLY
1637 /* TLB management */
1638 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1639 {
1640     /* Flush qemu's TLB and discard all shadowed entries.  */
1641     tlb_flush (env, flush_global);
1642     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1643 }
1644
1645 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
1646 {
1647     /* Discard entries from env->tlb[first] onwards.  */
1648     while (env->tlb->tlb_in_use > first) {
1649         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1650     }
1651 }
1652
1653 static void r4k_fill_tlb (int idx)
1654 {
1655     r4k_tlb_t *tlb;
1656
1657     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1658     tlb = &env->tlb->mmu.r4k.tlb[idx];
1659     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1660 #if defined(TARGET_MIPS64)
1661     tlb->VPN &= env->SEGMask;
1662 #endif
1663     tlb->ASID = env->CP0_EntryHi & 0xFF;
1664     tlb->PageMask = env->CP0_PageMask;
1665     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1666     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1667     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1668     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1669     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1670     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1671     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1672     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1673     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1674 }
1675
1676 void r4k_helper_tlbwi (void)
1677 {
1678     int idx;
1679
1680     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1681
1682     /* Discard cached TLB entries.  We could avoid doing this if the
1683        tlbwi is just upgrading access permissions on the current entry;
1684        that might be a further win.  */
1685     r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
1686
1687     r4k_invalidate_tlb(env, idx, 0);
1688     r4k_fill_tlb(idx);
1689 }
1690
1691 void r4k_helper_tlbwr (void)
1692 {
1693     int r = cpu_mips_get_random(env);
1694
1695     r4k_invalidate_tlb(env, r, 1);
1696     r4k_fill_tlb(r);
1697 }
1698
1699 void r4k_helper_tlbp (void)
1700 {
1701     r4k_tlb_t *tlb;
1702     target_ulong mask;
1703     target_ulong tag;
1704     target_ulong VPN;
1705     uint8_t ASID;
1706     int i;
1707
1708     ASID = env->CP0_EntryHi & 0xFF;
1709     for (i = 0; i < env->tlb->nb_tlb; i++) {
1710         tlb = &env->tlb->mmu.r4k.tlb[i];
1711         /* 1k pages are not supported. */
1712         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1713         tag = env->CP0_EntryHi & ~mask;
1714         VPN = tlb->VPN & ~mask;
1715         /* Check ASID, virtual page number & size */
1716         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1717             /* TLB match */
1718             env->CP0_Index = i;
1719             break;
1720         }
1721     }
1722     if (i == env->tlb->nb_tlb) {
1723         /* No match.  Discard any shadow entries, if any of them match.  */
1724         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1725             tlb = &env->tlb->mmu.r4k.tlb[i];
1726             /* 1k pages are not supported. */
1727             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1728             tag = env->CP0_EntryHi & ~mask;
1729             VPN = tlb->VPN & ~mask;
1730             /* Check ASID, virtual page number & size */
1731             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1732                 r4k_mips_tlb_flush_extra (env, i);
1733                 break;
1734             }
1735         }
1736
1737         env->CP0_Index |= 0x80000000;
1738     }
1739 }
1740
1741 void r4k_helper_tlbr (void)
1742 {
1743     r4k_tlb_t *tlb;
1744     uint8_t ASID;
1745     int idx;
1746
1747     ASID = env->CP0_EntryHi & 0xFF;
1748     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1749     tlb = &env->tlb->mmu.r4k.tlb[idx];
1750
1751     /* If this will change the current ASID, flush qemu's TLB.  */
1752     if (ASID != tlb->ASID)
1753         cpu_mips_tlb_flush (env, 1);
1754
1755     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1756
1757     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1758     env->CP0_PageMask = tlb->PageMask;
1759     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1760                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1761     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1762                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1763 }
1764
1765 void helper_tlbwi(void)
1766 {
1767     env->tlb->helper_tlbwi();
1768 }
1769
1770 void helper_tlbwr(void)
1771 {
1772     env->tlb->helper_tlbwr();
1773 }
1774
1775 void helper_tlbp(void)
1776 {
1777     env->tlb->helper_tlbp();
1778 }
1779
1780 void helper_tlbr(void)
1781 {
1782     env->tlb->helper_tlbr();
1783 }
1784
1785 /* Specials */
1786 target_ulong helper_di (void)
1787 {
1788     target_ulong t0 = env->CP0_Status;
1789
1790     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1791     cpu_mips_update_irq(env);
1792
1793     return t0;
1794 }
1795
1796 target_ulong helper_ei (void)
1797 {
1798     target_ulong t0 = env->CP0_Status;
1799
1800     env->CP0_Status = t0 | (1 << CP0St_IE);
1801     cpu_mips_update_irq(env);
1802
1803     return t0;
1804 }
1805
1806 static void debug_pre_eret (void)
1807 {
1808     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1809         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1810                 env->active_tc.PC, env->CP0_EPC);
1811         if (env->CP0_Status & (1 << CP0St_ERL))
1812             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1813         if (env->hflags & MIPS_HFLAG_DM)
1814             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1815         qemu_log("\n");
1816     }
1817 }
1818
1819 static void debug_post_eret (void)
1820 {
1821     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1822         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1823                 env->active_tc.PC, env->CP0_EPC);
1824         if (env->CP0_Status & (1 << CP0St_ERL))
1825             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1826         if (env->hflags & MIPS_HFLAG_DM)
1827             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1828         switch (env->hflags & MIPS_HFLAG_KSU) {
1829         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1830         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1831         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1832         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1833         }
1834     }
1835 }
1836
1837 static void set_pc (target_ulong error_pc)
1838 {
1839     env->active_tc.PC = error_pc & ~(target_ulong)1;
1840     if (error_pc & 1) {
1841         env->hflags |= MIPS_HFLAG_M16;
1842     } else {
1843         env->hflags &= ~(MIPS_HFLAG_M16);
1844     }
1845 }
1846
1847 void helper_eret (void)
1848 {
1849     debug_pre_eret();
1850     if (env->CP0_Status & (1 << CP0St_ERL)) {
1851         set_pc(env->CP0_ErrorEPC);
1852         env->CP0_Status &= ~(1 << CP0St_ERL);
1853     } else {
1854         set_pc(env->CP0_EPC);
1855         env->CP0_Status &= ~(1 << CP0St_EXL);
1856     }
1857     compute_hflags(env);
1858     debug_post_eret();
1859     env->lladdr = 1;
1860 }
1861
1862 void helper_deret (void)
1863 {
1864     debug_pre_eret();
1865     set_pc(env->CP0_DEPC);
1866
1867     env->hflags &= MIPS_HFLAG_DM;
1868     compute_hflags(env);
1869     debug_post_eret();
1870     env->lladdr = 1;
1871 }
1872 #endif /* !CONFIG_USER_ONLY */
1873
1874 target_ulong helper_rdhwr_cpunum(void)
1875 {
1876     if ((env->hflags & MIPS_HFLAG_CP0) ||
1877         (env->CP0_HWREna & (1 << 0)))
1878         return env->CP0_EBase & 0x3ff;
1879     else
1880         helper_raise_exception(EXCP_RI);
1881
1882     return 0;
1883 }
1884
1885 target_ulong helper_rdhwr_synci_step(void)
1886 {
1887     if ((env->hflags & MIPS_HFLAG_CP0) ||
1888         (env->CP0_HWREna & (1 << 1)))
1889         return env->SYNCI_Step;
1890     else
1891         helper_raise_exception(EXCP_RI);
1892
1893     return 0;
1894 }
1895
1896 target_ulong helper_rdhwr_cc(void)
1897 {
1898     if ((env->hflags & MIPS_HFLAG_CP0) ||
1899         (env->CP0_HWREna & (1 << 2)))
1900         return env->CP0_Count;
1901     else
1902         helper_raise_exception(EXCP_RI);
1903
1904     return 0;
1905 }
1906
1907 target_ulong helper_rdhwr_ccres(void)
1908 {
1909     if ((env->hflags & MIPS_HFLAG_CP0) ||
1910         (env->CP0_HWREna & (1 << 3)))
1911         return env->CCRes;
1912     else
1913         helper_raise_exception(EXCP_RI);
1914
1915     return 0;
1916 }
1917
1918 void helper_pmon (int function)
1919 {
1920     function /= 2;
1921     switch (function) {
1922     case 2: /* TODO: char inbyte(int waitflag); */
1923         if (env->active_tc.gpr[4] == 0)
1924             env->active_tc.gpr[2] = -1;
1925         /* Fall through */
1926     case 11: /* TODO: char inbyte (void); */
1927         env->active_tc.gpr[2] = -1;
1928         break;
1929     case 3:
1930     case 12:
1931         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
1932         break;
1933     case 17:
1934         break;
1935     case 158:
1936         {
1937             unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
1938             printf("%s", fmt);
1939         }
1940         break;
1941     }
1942 }
1943
1944 void helper_wait (void)
1945 {
1946     env->halted = 1;
1947     helper_raise_exception(EXCP_HLT);
1948 }
1949
1950 #if !defined(CONFIG_USER_ONLY)
1951
1952 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1953
1954 #define MMUSUFFIX _mmu
1955 #define ALIGNED_ONLY
1956
1957 #define SHIFT 0
1958 #include "softmmu_template.h"
1959
1960 #define SHIFT 1
1961 #include "softmmu_template.h"
1962
1963 #define SHIFT 2
1964 #include "softmmu_template.h"
1965
1966 #define SHIFT 3
1967 #include "softmmu_template.h"
1968
1969 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1970 {
1971     env->CP0_BadVAddr = addr;
1972     do_restore_state (retaddr);
1973     helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1974 }
1975
1976 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1977 {
1978     TranslationBlock *tb;
1979     CPUState *saved_env;
1980     unsigned long pc;
1981     int ret;
1982
1983     /* XXX: hack to restore env in all cases, even if not called from
1984        generated code */
1985     saved_env = env;
1986     env = cpu_single_env;
1987     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1988     if (ret) {
1989         if (retaddr) {
1990             /* now we have a real cpu fault */
1991             pc = (unsigned long)retaddr;
1992             tb = tb_find_pc(pc);
1993             if (tb) {
1994                 /* the PC is inside the translated code. It means that we have
1995                    a virtual CPU fault */
1996                 cpu_restore_state(tb, env, pc, NULL);
1997             }
1998         }
1999         helper_raise_exception_err(env->exception_index, env->error_code);
2000     }
2001     env = saved_env;
2002 }
2003
2004 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
2005                           int unused, int size)
2006 {
2007     if (is_exec)
2008         helper_raise_exception(EXCP_IBE);
2009     else
2010         helper_raise_exception(EXCP_DBE);
2011 }
2012 #endif /* !CONFIG_USER_ONLY */
2013
2014 /* Complex FPU operations which may need stack space. */
2015
2016 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
2017 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
2018 #define FLOAT_TWO32 make_float32(1 << 30)
2019 #define FLOAT_TWO64 make_float64(1ULL << 62)
2020 #define FLOAT_QNAN32 0x7fbfffff
2021 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
2022 #define FLOAT_SNAN32 0x7fffffff
2023 #define FLOAT_SNAN64 0x7fffffffffffffffULL
2024
2025 /* convert MIPS rounding mode in FCR31 to IEEE library */
2026 static unsigned int ieee_rm[] = {
2027     float_round_nearest_even,
2028     float_round_to_zero,
2029     float_round_up,
2030     float_round_down
2031 };
2032
2033 #define RESTORE_ROUNDING_MODE \
2034     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
2035
2036 #define RESTORE_FLUSH_MODE \
2037     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2038
2039 target_ulong helper_cfc1 (uint32_t reg)
2040 {
2041     target_ulong arg1;
2042
2043     switch (reg) {
2044     case 0:
2045         arg1 = (int32_t)env->active_fpu.fcr0;
2046         break;
2047     case 25:
2048         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2049         break;
2050     case 26:
2051         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2052         break;
2053     case 28:
2054         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2055         break;
2056     default:
2057         arg1 = (int32_t)env->active_fpu.fcr31;
2058         break;
2059     }
2060
2061     return arg1;
2062 }
2063
2064 void helper_ctc1 (target_ulong arg1, uint32_t reg)
2065 {
2066     switch(reg) {
2067     case 25:
2068         if (arg1 & 0xffffff00)
2069             return;
2070         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2071                      ((arg1 & 0x1) << 23);
2072         break;
2073     case 26:
2074         if (arg1 & 0x007c0000)
2075             return;
2076         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2077         break;
2078     case 28:
2079         if (arg1 & 0x007c0000)
2080             return;
2081         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2082                      ((arg1 & 0x4) << 22);
2083         break;
2084     case 31:
2085         if (arg1 & 0x007c0000)
2086             return;
2087         env->active_fpu.fcr31 = arg1;
2088         break;
2089     default:
2090         return;
2091     }
2092     /* set rounding mode */
2093     RESTORE_ROUNDING_MODE;
2094     /* set flush-to-zero mode */
2095     RESTORE_FLUSH_MODE;
2096     set_float_exception_flags(0, &env->active_fpu.fp_status);
2097     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2098         helper_raise_exception(EXCP_FPE);
2099 }
2100
2101 static inline char ieee_ex_to_mips(char xcpt)
2102 {
2103     return (xcpt & float_flag_inexact) >> 5 |
2104            (xcpt & float_flag_underflow) >> 3 |
2105            (xcpt & float_flag_overflow) >> 1 |
2106            (xcpt & float_flag_divbyzero) << 1 |
2107            (xcpt & float_flag_invalid) << 4;
2108 }
2109
2110 static inline char mips_ex_to_ieee(char xcpt)
2111 {
2112     return (xcpt & FP_INEXACT) << 5 |
2113            (xcpt & FP_UNDERFLOW) << 3 |
2114            (xcpt & FP_OVERFLOW) << 1 |
2115            (xcpt & FP_DIV0) >> 1 |
2116            (xcpt & FP_INVALID) >> 4;
2117 }
2118
2119 static inline void update_fcr31(void)
2120 {
2121     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2122
2123     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2124     if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
2125         helper_raise_exception(EXCP_FPE);
2126     else
2127         UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2128 }
2129
2130 /* Float support.
2131    Single precition routines have a "s" suffix, double precision a
2132    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2133    paired single lower "pl", paired single upper "pu".  */
2134
2135 /* unary operations, modifying fp status  */
2136 uint64_t helper_float_sqrt_d(uint64_t fdt0)
2137 {
2138     return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2139 }
2140
2141 uint32_t helper_float_sqrt_s(uint32_t fst0)
2142 {
2143     return float32_sqrt(fst0, &env->active_fpu.fp_status);
2144 }
2145
2146 uint64_t helper_float_cvtd_s(uint32_t fst0)
2147 {
2148     uint64_t fdt2;
2149
2150     set_float_exception_flags(0, &env->active_fpu.fp_status);
2151     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2152     update_fcr31();
2153     return fdt2;
2154 }
2155
2156 uint64_t helper_float_cvtd_w(uint32_t wt0)
2157 {
2158     uint64_t fdt2;
2159
2160     set_float_exception_flags(0, &env->active_fpu.fp_status);
2161     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2162     update_fcr31();
2163     return fdt2;
2164 }
2165
2166 uint64_t helper_float_cvtd_l(uint64_t dt0)
2167 {
2168     uint64_t fdt2;
2169
2170     set_float_exception_flags(0, &env->active_fpu.fp_status);
2171     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2172     update_fcr31();
2173     return fdt2;
2174 }
2175
2176 uint64_t helper_float_cvtl_d(uint64_t fdt0)
2177 {
2178     uint64_t dt2;
2179
2180     set_float_exception_flags(0, &env->active_fpu.fp_status);
2181     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2182     update_fcr31();
2183     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2184         dt2 = FLOAT_SNAN64;
2185     return dt2;
2186 }
2187
2188 uint64_t helper_float_cvtl_s(uint32_t fst0)
2189 {
2190     uint64_t dt2;
2191
2192     set_float_exception_flags(0, &env->active_fpu.fp_status);
2193     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2194     update_fcr31();
2195     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2196         dt2 = FLOAT_SNAN64;
2197     return dt2;
2198 }
2199
2200 uint64_t helper_float_cvtps_pw(uint64_t dt0)
2201 {
2202     uint32_t fst2;
2203     uint32_t fsth2;
2204
2205     set_float_exception_flags(0, &env->active_fpu.fp_status);
2206     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2207     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2208     update_fcr31();
2209     return ((uint64_t)fsth2 << 32) | fst2;
2210 }
2211
2212 uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
2213 {
2214     uint32_t wt2;
2215     uint32_t wth2;
2216
2217     set_float_exception_flags(0, &env->active_fpu.fp_status);
2218     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2219     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2220     update_fcr31();
2221     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2222         wt2 = FLOAT_SNAN32;
2223         wth2 = FLOAT_SNAN32;
2224     }
2225     return ((uint64_t)wth2 << 32) | wt2;
2226 }
2227
2228 uint32_t helper_float_cvts_d(uint64_t fdt0)
2229 {
2230     uint32_t fst2;
2231
2232     set_float_exception_flags(0, &env->active_fpu.fp_status);
2233     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2234     update_fcr31();
2235     return fst2;
2236 }
2237
2238 uint32_t helper_float_cvts_w(uint32_t wt0)
2239 {
2240     uint32_t fst2;
2241
2242     set_float_exception_flags(0, &env->active_fpu.fp_status);
2243     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2244     update_fcr31();
2245     return fst2;
2246 }
2247
2248 uint32_t helper_float_cvts_l(uint64_t dt0)
2249 {
2250     uint32_t fst2;
2251
2252     set_float_exception_flags(0, &env->active_fpu.fp_status);
2253     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2254     update_fcr31();
2255     return fst2;
2256 }
2257
2258 uint32_t helper_float_cvts_pl(uint32_t wt0)
2259 {
2260     uint32_t wt2;
2261
2262     set_float_exception_flags(0, &env->active_fpu.fp_status);
2263     wt2 = wt0;
2264     update_fcr31();
2265     return wt2;
2266 }
2267
2268 uint32_t helper_float_cvts_pu(uint32_t wth0)
2269 {
2270     uint32_t wt2;
2271
2272     set_float_exception_flags(0, &env->active_fpu.fp_status);
2273     wt2 = wth0;
2274     update_fcr31();
2275     return wt2;
2276 }
2277
2278 uint32_t helper_float_cvtw_s(uint32_t fst0)
2279 {
2280     uint32_t wt2;
2281
2282     set_float_exception_flags(0, &env->active_fpu.fp_status);
2283     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2284     update_fcr31();
2285     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2286         wt2 = FLOAT_SNAN32;
2287     return wt2;
2288 }
2289
2290 uint32_t helper_float_cvtw_d(uint64_t fdt0)
2291 {
2292     uint32_t wt2;
2293
2294     set_float_exception_flags(0, &env->active_fpu.fp_status);
2295     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2296     update_fcr31();
2297     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2298         wt2 = FLOAT_SNAN32;
2299     return wt2;
2300 }
2301
2302 uint64_t helper_float_roundl_d(uint64_t fdt0)
2303 {
2304     uint64_t dt2;
2305
2306     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2307     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2308     RESTORE_ROUNDING_MODE;
2309     update_fcr31();
2310     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2311         dt2 = FLOAT_SNAN64;
2312     return dt2;
2313 }
2314
2315 uint64_t helper_float_roundl_s(uint32_t fst0)
2316 {
2317     uint64_t dt2;
2318
2319     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2320     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2321     RESTORE_ROUNDING_MODE;
2322     update_fcr31();
2323     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2324         dt2 = FLOAT_SNAN64;
2325     return dt2;
2326 }
2327
2328 uint32_t helper_float_roundw_d(uint64_t fdt0)
2329 {
2330     uint32_t wt2;
2331
2332     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2333     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2334     RESTORE_ROUNDING_MODE;
2335     update_fcr31();
2336     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2337         wt2 = FLOAT_SNAN32;
2338     return wt2;
2339 }
2340
2341 uint32_t helper_float_roundw_s(uint32_t fst0)
2342 {
2343     uint32_t wt2;
2344
2345     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2346     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2347     RESTORE_ROUNDING_MODE;
2348     update_fcr31();
2349     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2350         wt2 = FLOAT_SNAN32;
2351     return wt2;
2352 }
2353
2354 uint64_t helper_float_truncl_d(uint64_t fdt0)
2355 {
2356     uint64_t dt2;
2357
2358     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2359     update_fcr31();
2360     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2361         dt2 = FLOAT_SNAN64;
2362     return dt2;
2363 }
2364
2365 uint64_t helper_float_truncl_s(uint32_t fst0)
2366 {
2367     uint64_t dt2;
2368
2369     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2370     update_fcr31();
2371     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2372         dt2 = FLOAT_SNAN64;
2373     return dt2;
2374 }
2375
2376 uint32_t helper_float_truncw_d(uint64_t fdt0)
2377 {
2378     uint32_t wt2;
2379
2380     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2381     update_fcr31();
2382     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2383         wt2 = FLOAT_SNAN32;
2384     return wt2;
2385 }
2386
2387 uint32_t helper_float_truncw_s(uint32_t fst0)
2388 {
2389     uint32_t wt2;
2390
2391     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2392     update_fcr31();
2393     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2394         wt2 = FLOAT_SNAN32;
2395     return wt2;
2396 }
2397
2398 uint64_t helper_float_ceill_d(uint64_t fdt0)
2399 {
2400     uint64_t dt2;
2401
2402     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2403     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2404     RESTORE_ROUNDING_MODE;
2405     update_fcr31();
2406     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2407         dt2 = FLOAT_SNAN64;
2408     return dt2;
2409 }
2410
2411 uint64_t helper_float_ceill_s(uint32_t fst0)
2412 {
2413     uint64_t dt2;
2414
2415     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2416     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2417     RESTORE_ROUNDING_MODE;
2418     update_fcr31();
2419     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2420         dt2 = FLOAT_SNAN64;
2421     return dt2;
2422 }
2423
2424 uint32_t helper_float_ceilw_d(uint64_t fdt0)
2425 {
2426     uint32_t wt2;
2427
2428     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2429     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2430     RESTORE_ROUNDING_MODE;
2431     update_fcr31();
2432     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2433         wt2 = FLOAT_SNAN32;
2434     return wt2;
2435 }
2436
2437 uint32_t helper_float_ceilw_s(uint32_t fst0)
2438 {
2439     uint32_t wt2;
2440
2441     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2442     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2443     RESTORE_ROUNDING_MODE;
2444     update_fcr31();
2445     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2446         wt2 = FLOAT_SNAN32;
2447     return wt2;
2448 }
2449
2450 uint64_t helper_float_floorl_d(uint64_t fdt0)
2451 {
2452     uint64_t dt2;
2453
2454     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2455     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2456     RESTORE_ROUNDING_MODE;
2457     update_fcr31();
2458     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2459         dt2 = FLOAT_SNAN64;
2460     return dt2;
2461 }
2462
2463 uint64_t helper_float_floorl_s(uint32_t fst0)
2464 {
2465     uint64_t dt2;
2466
2467     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2468     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2469     RESTORE_ROUNDING_MODE;
2470     update_fcr31();
2471     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2472         dt2 = FLOAT_SNAN64;
2473     return dt2;
2474 }
2475
2476 uint32_t helper_float_floorw_d(uint64_t fdt0)
2477 {
2478     uint32_t wt2;
2479
2480     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2481     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2482     RESTORE_ROUNDING_MODE;
2483     update_fcr31();
2484     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2485         wt2 = FLOAT_SNAN32;
2486     return wt2;
2487 }
2488
2489 uint32_t helper_float_floorw_s(uint32_t fst0)
2490 {
2491     uint32_t wt2;
2492
2493     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2494     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2495     RESTORE_ROUNDING_MODE;
2496     update_fcr31();
2497     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2498         wt2 = FLOAT_SNAN32;
2499     return wt2;
2500 }
2501
2502 /* unary operations, not modifying fp status  */
2503 #define FLOAT_UNOP(name)                                       \
2504 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2505 {                                                              \
2506     return float64_ ## name(fdt0);                             \
2507 }                                                              \
2508 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2509 {                                                              \
2510     return float32_ ## name(fst0);                             \
2511 }                                                              \
2512 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2513 {                                                              \
2514     uint32_t wt0;                                              \
2515     uint32_t wth0;                                             \
2516                                                                \
2517     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2518     wth0 = float32_ ## name(fdt0 >> 32);                       \
2519     return ((uint64_t)wth0 << 32) | wt0;                       \
2520 }
2521 FLOAT_UNOP(abs)
2522 FLOAT_UNOP(chs)
2523 #undef FLOAT_UNOP
2524
2525 /* MIPS specific unary operations */
2526 uint64_t helper_float_recip_d(uint64_t fdt0)
2527 {
2528     uint64_t fdt2;
2529
2530     set_float_exception_flags(0, &env->active_fpu.fp_status);
2531     fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2532     update_fcr31();
2533     return fdt2;
2534 }
2535
2536 uint32_t helper_float_recip_s(uint32_t fst0)
2537 {
2538     uint32_t fst2;
2539
2540     set_float_exception_flags(0, &env->active_fpu.fp_status);
2541     fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2542     update_fcr31();
2543     return fst2;
2544 }
2545
2546 uint64_t helper_float_rsqrt_d(uint64_t fdt0)
2547 {
2548     uint64_t fdt2;
2549
2550     set_float_exception_flags(0, &env->active_fpu.fp_status);
2551     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2552     fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2553     update_fcr31();
2554     return fdt2;
2555 }
2556
2557 uint32_t helper_float_rsqrt_s(uint32_t fst0)
2558 {
2559     uint32_t fst2;
2560
2561     set_float_exception_flags(0, &env->active_fpu.fp_status);
2562     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2563     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2564     update_fcr31();
2565     return fst2;
2566 }
2567
2568 uint64_t helper_float_recip1_d(uint64_t fdt0)
2569 {
2570     uint64_t fdt2;
2571
2572     set_float_exception_flags(0, &env->active_fpu.fp_status);
2573     fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2574     update_fcr31();
2575     return fdt2;
2576 }
2577
2578 uint32_t helper_float_recip1_s(uint32_t fst0)
2579 {
2580     uint32_t fst2;
2581
2582     set_float_exception_flags(0, &env->active_fpu.fp_status);
2583     fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2584     update_fcr31();
2585     return fst2;
2586 }
2587
2588 uint64_t helper_float_recip1_ps(uint64_t fdt0)
2589 {
2590     uint32_t fst2;
2591     uint32_t fsth2;
2592
2593     set_float_exception_flags(0, &env->active_fpu.fp_status);
2594     fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2595     fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2596     update_fcr31();
2597     return ((uint64_t)fsth2 << 32) | fst2;
2598 }
2599
2600 uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
2601 {
2602     uint64_t fdt2;
2603
2604     set_float_exception_flags(0, &env->active_fpu.fp_status);
2605     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2606     fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2607     update_fcr31();
2608     return fdt2;
2609 }
2610
2611 uint32_t helper_float_rsqrt1_s(uint32_t fst0)
2612 {
2613     uint32_t fst2;
2614
2615     set_float_exception_flags(0, &env->active_fpu.fp_status);
2616     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2617     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2618     update_fcr31();
2619     return fst2;
2620 }
2621
2622 uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
2623 {
2624     uint32_t fst2;
2625     uint32_t fsth2;
2626
2627     set_float_exception_flags(0, &env->active_fpu.fp_status);
2628     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2629     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2630     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2631     fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2632     update_fcr31();
2633     return ((uint64_t)fsth2 << 32) | fst2;
2634 }
2635
2636 #define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
2637
2638 /* binary operations */
2639 #define FLOAT_BINOP(name)                                          \
2640 uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1)     \
2641 {                                                                  \
2642     uint64_t dt2;                                                  \
2643                                                                    \
2644     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
2645     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2646     update_fcr31();                                                \
2647     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID)                \
2648         dt2 = FLOAT_QNAN64;                                        \
2649     return dt2;                                                    \
2650 }                                                                  \
2651                                                                    \
2652 uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1)     \
2653 {                                                                  \
2654     uint32_t wt2;                                                  \
2655                                                                    \
2656     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
2657     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2658     update_fcr31();                                                \
2659     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID)                \
2660         wt2 = FLOAT_QNAN32;                                        \
2661     return wt2;                                                    \
2662 }                                                                  \
2663                                                                    \
2664 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1)    \
2665 {                                                                  \
2666     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2667     uint32_t fsth0 = fdt0 >> 32;                                   \
2668     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2669     uint32_t fsth1 = fdt1 >> 32;                                   \
2670     uint32_t wt2;                                                  \
2671     uint32_t wth2;                                                 \
2672                                                                    \
2673     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
2674     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2675     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2676     update_fcr31();                                                \
2677     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {              \
2678         wt2 = FLOAT_QNAN32;                                        \
2679         wth2 = FLOAT_QNAN32;                                       \
2680     }                                                              \
2681     return ((uint64_t)wth2 << 32) | wt2;                           \
2682 }
2683
2684 FLOAT_BINOP(add)
2685 FLOAT_BINOP(sub)
2686 FLOAT_BINOP(mul)
2687 FLOAT_BINOP(div)
2688 #undef FLOAT_BINOP
2689
2690 /* ternary operations */
2691 #define FLOAT_TERNOP(name1, name2)                                        \
2692 uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1,  \
2693                                            uint64_t fdt2)                 \
2694 {                                                                         \
2695     fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status);          \
2696     return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status);          \
2697 }                                                                         \
2698                                                                           \
2699 uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1,  \
2700                                            uint32_t fst2)                 \
2701 {                                                                         \
2702     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
2703     return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
2704 }                                                                         \
2705                                                                           \
2706 uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2707                                             uint64_t fdt2)                \
2708 {                                                                         \
2709     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                                    \
2710     uint32_t fsth0 = fdt0 >> 32;                                          \
2711     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                                    \
2712     uint32_t fsth1 = fdt1 >> 32;                                          \
2713     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                                    \
2714     uint32_t fsth2 = fdt2 >> 32;                                          \
2715                                                                           \
2716     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
2717     fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status);       \
2718     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
2719     fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status);       \
2720     return ((uint64_t)fsth2 << 32) | fst2;                                \
2721 }
2722
2723 FLOAT_TERNOP(mul, add)
2724 FLOAT_TERNOP(mul, sub)
2725 #undef FLOAT_TERNOP
2726
2727 /* negated ternary operations */
2728 #define FLOAT_NTERNOP(name1, name2)                                       \
2729 uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2730                                            uint64_t fdt2)                 \
2731 {                                                                         \
2732     fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status);          \
2733     fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status);          \
2734     return float64_chs(fdt2);                                             \
2735 }                                                                         \
2736                                                                           \
2737 uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2738                                            uint32_t fst2)                 \
2739 {                                                                         \
2740     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
2741     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
2742     return float32_chs(fst2);                                             \
2743 }                                                                         \
2744                                                                           \
2745 uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2746                                            uint64_t fdt2)                 \
2747 {                                                                         \
2748     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                                    \
2749     uint32_t fsth0 = fdt0 >> 32;                                          \
2750     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                                    \
2751     uint32_t fsth1 = fdt1 >> 32;                                          \
2752     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                                    \
2753     uint32_t fsth2 = fdt2 >> 32;                                          \
2754                                                                           \
2755     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
2756     fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status);       \
2757     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
2758     fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status);       \
2759     fst2 = float32_chs(fst2);                                             \
2760     fsth2 = float32_chs(fsth2);                                           \
2761     return ((uint64_t)fsth2 << 32) | fst2;                                \
2762 }
2763
2764 FLOAT_NTERNOP(mul, add)
2765 FLOAT_NTERNOP(mul, sub)
2766 #undef FLOAT_NTERNOP
2767
2768 /* MIPS specific binary operations */
2769 uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2770 {
2771     set_float_exception_flags(0, &env->active_fpu.fp_status);
2772     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2773     fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
2774     update_fcr31();
2775     return fdt2;
2776 }
2777
2778 uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
2779 {
2780     set_float_exception_flags(0, &env->active_fpu.fp_status);
2781     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2782     fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2783     update_fcr31();
2784     return fst2;
2785 }
2786
2787 uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2788 {
2789     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2790     uint32_t fsth0 = fdt0 >> 32;
2791     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2792     uint32_t fsth2 = fdt2 >> 32;
2793
2794     set_float_exception_flags(0, &env->active_fpu.fp_status);
2795     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2796     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2797     fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2798     fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
2799     update_fcr31();
2800     return ((uint64_t)fsth2 << 32) | fst2;
2801 }
2802
2803 uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2804 {
2805     set_float_exception_flags(0, &env->active_fpu.fp_status);
2806     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2807     fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2808     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2809     update_fcr31();
2810     return fdt2;
2811 }
2812
2813 uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2814 {
2815     set_float_exception_flags(0, &env->active_fpu.fp_status);
2816     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2817     fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2818     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2819     update_fcr31();
2820     return fst2;
2821 }
2822
2823 uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2824 {
2825     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2826     uint32_t fsth0 = fdt0 >> 32;
2827     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2828     uint32_t fsth2 = fdt2 >> 32;
2829
2830     set_float_exception_flags(0, &env->active_fpu.fp_status);
2831     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2832     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2833     fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2834     fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2835     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2836     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2837     update_fcr31();
2838     return ((uint64_t)fsth2 << 32) | fst2;
2839 }
2840
2841 uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2842 {
2843     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2844     uint32_t fsth0 = fdt0 >> 32;
2845     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2846     uint32_t fsth1 = fdt1 >> 32;
2847     uint32_t fst2;
2848     uint32_t fsth2;
2849
2850     set_float_exception_flags(0, &env->active_fpu.fp_status);
2851     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2852     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2853     update_fcr31();
2854     return ((uint64_t)fsth2 << 32) | fst2;
2855 }
2856
2857 uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2858 {
2859     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2860     uint32_t fsth0 = fdt0 >> 32;
2861     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2862     uint32_t fsth1 = fdt1 >> 32;
2863     uint32_t fst2;
2864     uint32_t fsth2;
2865
2866     set_float_exception_flags(0, &env->active_fpu.fp_status);
2867     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2868     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
2869     update_fcr31();
2870     return ((uint64_t)fsth2 << 32) | fst2;
2871 }
2872
2873 /* compare operations */
2874 #define FOP_COND_D(op, cond)                                   \
2875 void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
2876 {                                                              \
2877     int c = cond;                                              \
2878     update_fcr31();                                            \
2879     if (c)                                                     \
2880         SET_FP_COND(cc, env->active_fpu);                      \
2881     else                                                       \
2882         CLEAR_FP_COND(cc, env->active_fpu);                    \
2883 }                                                              \
2884 void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2885 {                                                              \
2886     int c;                                                     \
2887     fdt0 = float64_abs(fdt0);                                  \
2888     fdt1 = float64_abs(fdt1);                                  \
2889     c = cond;                                                  \
2890     update_fcr31();                                            \
2891     if (c)                                                     \
2892         SET_FP_COND(cc, env->active_fpu);                      \
2893     else                                                       \
2894         CLEAR_FP_COND(cc, env->active_fpu);                    \
2895 }
2896
2897 static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2898 {
2899     if (float64_is_signaling_nan(a) ||
2900         float64_is_signaling_nan(b) ||
2901         (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2902         float_raise(float_flag_invalid, status);
2903         return 1;
2904     } else if (float64_is_nan(a) || float64_is_nan(b)) {
2905         return 1;
2906     } else {
2907         return 0;
2908     }
2909 }
2910
2911 /* NOTE: the comma operator will make "cond" to eval to false,
2912  * but float*_is_unordered() is still called. */
2913 FOP_COND_D(f,   (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2914 FOP_COND_D(un,  float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2915 FOP_COND_D(eq,  !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2916 FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2917 FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2918 FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2919 FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2920 FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2921 /* NOTE: the comma operator will make "cond" to eval to false,
2922  * but float*_is_unordered() is still called. */
2923 FOP_COND_D(sf,  (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2924 FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2925 FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2926 FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2927 FOP_COND_D(lt,  !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2928 FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2929 FOP_COND_D(le,  !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2930 FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2931
2932 #define FOP_COND_S(op, cond)                                   \
2933 void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc)    \
2934 {                                                              \
2935     int c = cond;                                              \
2936     update_fcr31();                                            \
2937     if (c)                                                     \
2938         SET_FP_COND(cc, env->active_fpu);                      \
2939     else                                                       \
2940         CLEAR_FP_COND(cc, env->active_fpu);                    \
2941 }                                                              \
2942 void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2943 {                                                              \
2944     int c;                                                     \
2945     fst0 = float32_abs(fst0);                                  \
2946     fst1 = float32_abs(fst1);                                  \
2947     c = cond;                                                  \
2948     update_fcr31();                                            \
2949     if (c)                                                     \
2950         SET_FP_COND(cc, env->active_fpu);                      \
2951     else                                                       \
2952         CLEAR_FP_COND(cc, env->active_fpu);                    \
2953 }
2954
2955 static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2956 {
2957     if (float32_is_signaling_nan(a) ||
2958         float32_is_signaling_nan(b) ||
2959         (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2960         float_raise(float_flag_invalid, status);
2961         return 1;
2962     } else if (float32_is_nan(a) || float32_is_nan(b)) {
2963         return 1;
2964     } else {
2965         return 0;
2966     }
2967 }
2968
2969 /* NOTE: the comma operator will make "cond" to eval to false,
2970  * but float*_is_unordered() is still called. */
2971 FOP_COND_S(f,   (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2972 FOP_COND_S(un,  float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2973 FOP_COND_S(eq,  !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2974 FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2975 FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2976 FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2977 FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2978 FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2979 /* NOTE: the comma operator will make "cond" to eval to false,
2980  * but float*_is_unordered() is still called. */
2981 FOP_COND_S(sf,  (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2982 FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2983 FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2984 FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2985 FOP_COND_S(lt,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2986 FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2987 FOP_COND_S(le,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2988 FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2989
2990 #define FOP_COND_PS(op, condl, condh)                           \
2991 void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
2992 {                                                               \
2993     uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF);             \
2994     uint32_t fsth0 = float32_abs(fdt0 >> 32);                   \
2995     uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF);             \
2996     uint32_t fsth1 = float32_abs(fdt1 >> 32);                   \
2997     int cl = condl;                                             \
2998     int ch = condh;                                             \
2999                                                                 \
3000     update_fcr31();                                             \
3001     if (cl)                                                     \
3002         SET_FP_COND(cc, env->active_fpu);                       \
3003     else                                                        \
3004         CLEAR_FP_COND(cc, env->active_fpu);                     \
3005     if (ch)                                                     \
3006         SET_FP_COND(cc + 1, env->active_fpu);                   \
3007     else                                                        \
3008         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3009 }                                                               \
3010 void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
3011 {                                                               \
3012     uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF);             \
3013     uint32_t fsth0 = float32_abs(fdt0 >> 32);                   \
3014     uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF);             \
3015     uint32_t fsth1 = float32_abs(fdt1 >> 32);                   \
3016     int cl = condl;                                             \
3017     int ch = condh;                                             \
3018                                                                 \
3019     update_fcr31();                                             \
3020     if (cl)                                                     \
3021         SET_FP_COND(cc, env->active_fpu);                       \
3022     else                                                        \
3023         CLEAR_FP_COND(cc, env->active_fpu);                     \
3024     if (ch)                                                     \
3025         SET_FP_COND(cc + 1, env->active_fpu);                   \
3026     else                                                        \
3027         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3028 }
3029
3030 /* NOTE: the comma operator will make "cond" to eval to false,
3031  * but float*_is_unordered() is still called. */
3032 FOP_COND_PS(f,   (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
3033                  (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3034 FOP_COND_PS(un,  float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
3035                  float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
3036 FOP_COND_PS(eq,  !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3037                  !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3038 FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3039                  float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3040 FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3041                  !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3042 FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3043                  float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3044 FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3045                  !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3046 FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3047                  float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3048 /* NOTE: the comma operator will make "cond" to eval to false,
3049  * but float*_is_unordered() is still called. */
3050 FOP_COND_PS(sf,  (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
3051                  (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3052 FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
3053                  float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
3054 FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3055                  !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3056 FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3057                  float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3058 FOP_COND_PS(lt,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3059                  !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3060 FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3061                  float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3062 FOP_COND_PS(le,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3063                  !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3064 FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3065                  float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))