target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 #include "helper.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "exec/softmmu_exec.h"
  27 #endif /* !defined(CONFIG_USER_ONLY) */
  28
  29 #ifndef CONFIG_USER_ONLY
  30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  31 #endif
  32
  33 /*****************************************************************************/
  34 /* Exceptions processing helpers */
  35
  36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  37                                                         uint32_t exception,
  38                                                         int error_code,
  39                                                         uintptr_t pc)
  40 {
  41     CPUState *cs = CPU(mips_env_get_cpu(env));
  42
  43     if (exception < EXCP_SC) {
  44         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  45     }
  46     cs->exception_index = exception;
  47     env->error_code = error_code;
  48
  49     if (pc) {
  50         /* now we have a real cpu fault */
  51         cpu_restore_state(cs, pc);
  52     }
  53
  54     cpu_loop_exit(cs);
  55 }
  56
  57 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  58                                                     uint32_t exception,
  59                                                     uintptr_t pc)
  60 {
  61     do_raise_exception_err(env, exception, 0, pc);
  62 }
  63
  64 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  65                                 int error_code)
  66 {
  67     do_raise_exception_err(env, exception, error_code, 0);
  68 }
  69
  70 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  71 {
  72     do_raise_exception(env, exception, 0);
  73 }
  74
  75 #if defined(CONFIG_USER_ONLY)
  76 #define HELPER_LD(name, insn, type)                                     \
  77 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  78                              int mem_idx)                               \
  79 {                                                                       \
  80     return (type) insn##_raw(addr);                                     \
  81 }
  82 #else
  83 #define HELPER_LD(name, insn, type)                                     \
  84 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  85                              int mem_idx)                               \
  86 {                                                                       \
  87     switch (mem_idx)                                                    \
  88     {                                                                   \
  89     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  90     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  91     default:                                                            \
  92     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  93     }                                                                   \
  94 }
  95 #endif
  96 HELPER_LD(lbu, ldub, uint8_t)
  97 HELPER_LD(lw, ldl, int32_t)
  98 #ifdef TARGET_MIPS64
  99 HELPER_LD(ld, ldq, int64_t)
 100 #endif
 101 #undef HELPER_LD
 102
 103 #if defined(CONFIG_USER_ONLY)
 104 #define HELPER_ST(name, insn, type)                                     \
 105 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 106                              type val, int mem_idx)                     \
 107 {                                                                       \
 108     insn##_raw(addr, val);                                              \
 109 }
 110 #else
 111 #define HELPER_ST(name, insn, type)                                     \
 112 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 113                              type val, int mem_idx)                     \
 114 {                                                                       \
 115     switch (mem_idx)                                                    \
 116     {                                                                   \
 117     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 118     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 119     default:                                                            \
 120     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 121     }                                                                   \
 122 }
 123 #endif
 124 HELPER_ST(sb, stb, uint8_t)
 125 HELPER_ST(sw, stl, uint32_t)
 126 #ifdef TARGET_MIPS64
 127 HELPER_ST(sd, stq, uint64_t)
 128 #endif
 129 #undef HELPER_ST
 130
 131 target_ulong helper_clo (target_ulong arg1)
 132 {
 133     return clo32(arg1);
 134 }
 135
 136 target_ulong helper_clz (target_ulong arg1)
 137 {
 138     return clz32(arg1);
 139 }
 140
 141 #if defined(TARGET_MIPS64)
 142 target_ulong helper_dclo (target_ulong arg1)
 143 {
 144     return clo64(arg1);
 145 }
 146
 147 target_ulong helper_dclz (target_ulong arg1)
 148 {
 149     return clz64(arg1);
 150 }
 151 #endif /* TARGET_MIPS64 */
 152
 153 /* 64 bits arithmetic for 32 bits hosts */
 154 static inline uint64_t get_HILO(CPUMIPSState *env)
 155 {
 156     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 157 }
 158
 159 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 160 {
 161     target_ulong tmp;
 162     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 163     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 164     return tmp;
 165 }
 166
 167 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 168 {
 169     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 170     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 171     return tmp;
 172 }
 173
 174 /* Multiplication variants of the vr54xx. */
 175 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 176                          target_ulong arg2)
 177 {
 178     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 179                                  (int64_t)(int32_t)arg2));
 180 }
 181
 182 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 183                           target_ulong arg2)
 184 {
 185     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 186                        (uint64_t)(uint32_t)arg2);
 187 }
 188
 189 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 190                          target_ulong arg2)
 191 {
 192     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 193                        (int64_t)(int32_t)arg2);
 194 }
 195
 196 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 197                            target_ulong arg2)
 198 {
 199     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 200                        (int64_t)(int32_t)arg2);
 201 }
 202
 203 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 204                           target_ulong arg2)
 205 {
 206     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 207                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 208 }
 209
 210 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 211                             target_ulong arg2)
 212 {
 213     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 214                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 215 }
 216
 217 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 218                          target_ulong arg2)
 219 {
 220     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 221                        (int64_t)(int32_t)arg2);
 222 }
 223
 224 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 225                            target_ulong arg2)
 226 {
 227     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 228                        (int64_t)(int32_t)arg2);
 229 }
 230
 231 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 232                           target_ulong arg2)
 233 {
 234     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 235                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 236 }
 237
 238 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 239                             target_ulong arg2)
 240 {
 241     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 242                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 243 }
 244
 245 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 246                           target_ulong arg2)
 247 {
 248     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 249 }
 250
 251 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 252                            target_ulong arg2)
 253 {
 254     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 255                        (uint64_t)(uint32_t)arg2);
 256 }
 257
 258 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 259                            target_ulong arg2)
 260 {
 261     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 262                        (int64_t)(int32_t)arg2);
 263 }
 264
 265 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 266                             target_ulong arg2)
 267 {
 268     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 269                        (uint64_t)(uint32_t)arg2);
 270 }
 271
 272 #ifndef CONFIG_USER_ONLY
 273
 274 static inline hwaddr do_translate_address(CPUMIPSState *env,
 275                                                       target_ulong address,
 276                                                       int rw)
 277 {
 278     hwaddr lladdr;
 279
 280     lladdr = cpu_mips_translate_address(env, address, rw);
 281
 282     if (lladdr == -1LL) {
 283         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 284     } else {
 285         return lladdr;
 286     }
 287 }
 288
 289 #define HELPER_LD_ATOMIC(name, insn)                                          \
 290 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 291 {                                                                             \
 292     env->lladdr = do_translate_address(env, arg, 0);                          \
 293     env->llval = do_##insn(env, arg, mem_idx);                                \
 294     return env->llval;                                                        \
 295 }
 296 HELPER_LD_ATOMIC(ll, lw)
 297 #ifdef TARGET_MIPS64
 298 HELPER_LD_ATOMIC(lld, ld)
 299 #endif
 300 #undef HELPER_LD_ATOMIC
 301
 302 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 303 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 304                            target_ulong arg2, int mem_idx)                    \
 305 {                                                                             \
 306     target_long tmp;                                                          \
 307                                                                               \
 308     if (arg2 & almask) {                                                      \
 309         env->CP0_BadVAddr = arg2;                                             \
 310         helper_raise_exception(env, EXCP_AdES);                               \
 311     }                                                                         \
 312     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 313         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 314         if (tmp == env->llval) {                                              \
 315             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 316             return 1;                                                         \
 317         }                                                                     \
 318     }                                                                         \
 319     return 0;                                                                 \
 320 }
 321 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 322 #ifdef TARGET_MIPS64
 323 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 324 #endif
 325 #undef HELPER_ST_ATOMIC
 326 #endif
 327
 328 #ifdef TARGET_WORDS_BIGENDIAN
 329 #define GET_LMASK(v) ((v) & 3)
 330 #define GET_OFFSET(addr, offset) (addr + (offset))
 331 #else
 332 #define GET_LMASK(v) (((v) & 3) ^ 3)
 333 #define GET_OFFSET(addr, offset) (addr - (offset))
 334 #endif
 335
 336 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 337                 int mem_idx)
 338 {
 339     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 340
 341     if (GET_LMASK(arg2) <= 2)
 342         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 343
 344     if (GET_LMASK(arg2) <= 1)
 345         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 346
 347     if (GET_LMASK(arg2) == 0)
 348         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 349 }
 350
 351 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 352                 int mem_idx)
 353 {
 354     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 355
 356     if (GET_LMASK(arg2) >= 1)
 357         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 358
 359     if (GET_LMASK(arg2) >= 2)
 360         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 361
 362     if (GET_LMASK(arg2) == 3)
 363         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 364 }
 365
 366 #if defined(TARGET_MIPS64)
 367 /* "half" load and stores.  We must do the memory access inline,
 368    or fault handling won't work.  */
 369
 370 #ifdef TARGET_WORDS_BIGENDIAN
 371 #define GET_LMASK64(v) ((v) & 7)
 372 #else
 373 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 374 #endif
 375
 376 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 377                 int mem_idx)
 378 {
 379     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 380
 381     if (GET_LMASK64(arg2) <= 6)
 382         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 383
 384     if (GET_LMASK64(arg2) <= 5)
 385         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 386
 387     if (GET_LMASK64(arg2) <= 4)
 388         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 389
 390     if (GET_LMASK64(arg2) <= 3)
 391         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 392
 393     if (GET_LMASK64(arg2) <= 2)
 394         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 395
 396     if (GET_LMASK64(arg2) <= 1)
 397         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 398
 399     if (GET_LMASK64(arg2) <= 0)
 400         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 401 }
 402
 403 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 404                 int mem_idx)
 405 {
 406     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 407
 408     if (GET_LMASK64(arg2) >= 1)
 409         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 410
 411     if (GET_LMASK64(arg2) >= 2)
 412         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 413
 414     if (GET_LMASK64(arg2) >= 3)
 415         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 416
 417     if (GET_LMASK64(arg2) >= 4)
 418         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 419
 420     if (GET_LMASK64(arg2) >= 5)
 421         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 422
 423     if (GET_LMASK64(arg2) >= 6)
 424         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 425
 426     if (GET_LMASK64(arg2) == 7)
 427         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 428 }
 429 #endif /* TARGET_MIPS64 */
 430
 431 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 432
 433 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 434                 uint32_t mem_idx)
 435 {
 436     target_ulong base_reglist = reglist & 0xf;
 437     target_ulong do_r31 = reglist & 0x10;
 438
 439     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 440         target_ulong i;
 441
 442         for (i = 0; i < base_reglist; i++) {
 443             env->active_tc.gpr[multiple_regs[i]] =
 444                 (target_long)do_lw(env, addr, mem_idx);
 445             addr += 4;
 446         }
 447     }
 448
 449     if (do_r31) {
 450         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 451     }
 452 }
 453
 454 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 455                 uint32_t mem_idx)
 456 {
 457     target_ulong base_reglist = reglist & 0xf;
 458     target_ulong do_r31 = reglist & 0x10;
 459
 460     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 461         target_ulong i;
 462
 463         for (i = 0; i < base_reglist; i++) {
 464             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 465             addr += 4;
 466         }
 467     }
 468
 469     if (do_r31) {
 470         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 471     }
 472 }
 473
 474 #if defined(TARGET_MIPS64)
 475 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 476                 uint32_t mem_idx)
 477 {
 478     target_ulong base_reglist = reglist & 0xf;
 479     target_ulong do_r31 = reglist & 0x10;
 480
 481     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 482         target_ulong i;
 483
 484         for (i = 0; i < base_reglist; i++) {
 485             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 486             addr += 8;
 487         }
 488     }
 489
 490     if (do_r31) {
 491         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 492     }
 493 }
 494
 495 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 496                 uint32_t mem_idx)
 497 {
 498     target_ulong base_reglist = reglist & 0xf;
 499     target_ulong do_r31 = reglist & 0x10;
 500
 501     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 502         target_ulong i;
 503
 504         for (i = 0; i < base_reglist; i++) {
 505             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 506             addr += 8;
 507         }
 508     }
 509
 510     if (do_r31) {
 511         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 512     }
 513 }
 514 #endif
 515
 516 #ifndef CONFIG_USER_ONLY
 517 /* SMP helpers.  */
 518 static bool mips_vpe_is_wfi(MIPSCPU *c)
 519 {
 520     CPUState *cpu = CPU(c);
 521     CPUMIPSState *env = &c->env;
 522
 523     /* If the VPE is halted but otherwise active, it means it's waiting for
 524        an interrupt.  */
 525     return cpu->halted && mips_vpe_active(env);
 526 }
 527
 528 static inline void mips_vpe_wake(MIPSCPU *c)
 529 {
 530     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 531        because there might be other conditions that state that c should
 532        be sleeping.  */
 533     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 534 }
 535
 536 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 537 {
 538     CPUState *cs = CPU(cpu);
 539
 540     /* The VPE was shut off, really go to bed.
 541        Reset any old _WAKE requests.  */
 542     cs->halted = 1;
 543     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 544 }
 545
 546 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 547 {
 548     CPUMIPSState *c = &cpu->env;
 549
 550     /* FIXME: TC reschedule.  */
 551     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 552         mips_vpe_wake(cpu);
 553     }
 554 }
 555
 556 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 557 {
 558     CPUMIPSState *c = &cpu->env;
 559
 560     /* FIXME: TC reschedule.  */
 561     if (!mips_vpe_active(c)) {
 562         mips_vpe_sleep(cpu);
 563     }
 564 }
 565
 566 /**
 567  * mips_cpu_map_tc:
 568  * @env: CPU from which mapping is performed.
 569  * @tc: Should point to an int with the value of the global TC index.
 570  *
 571  * This function will transform @tc into a local index within the
 572  * returned #CPUMIPSState.
 573  */
 574 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 575           which depends on runtime setup. Can probably be fixed by
 576           walking the list of CPUMIPSStates.  */
 577 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 578 {
 579     MIPSCPU *cpu;
 580     CPUState *cs;
 581     CPUState *other_cs;
 582     int vpe_idx;
 583     int tc_idx = *tc;
 584
 585     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 586         /* Not allowed to address other CPUs.  */
 587         *tc = env->current_tc;
 588         return env;
 589     }
 590
 591     cs = CPU(mips_env_get_cpu(env));
 592     vpe_idx = tc_idx / cs->nr_threads;
 593     *tc = tc_idx % cs->nr_threads;
 594     other_cs = qemu_get_cpu(vpe_idx);
 595     if (other_cs == NULL) {
 596         return env;
 597     }
 598     cpu = MIPS_CPU(other_cs);
 599     return &cpu->env;
 600 }
 601
 602 /* The per VPE CP0_Status register shares some fields with the per TC
 603    CP0_TCStatus registers. These fields are wired to the same registers,
 604    so changes to either of them should be reflected on both registers.
 605
 606    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 607
 608    These helper call synchronizes the regs for a given cpu.  */
 609
 610 /* Called for updates to CP0_Status.  */
 611 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 612 {
 613     int32_t tcstatus, *tcst;
 614     uint32_t v = cpu->CP0_Status;
 615     uint32_t cu, mx, asid, ksu;
 616     uint32_t mask = ((1 << CP0TCSt_TCU3)
 617                        | (1 << CP0TCSt_TCU2)
 618                        | (1 << CP0TCSt_TCU1)
 619                        | (1 << CP0TCSt_TCU0)
 620                        | (1 << CP0TCSt_TMX)
 621                        | (3 << CP0TCSt_TKSU)
 622                        | (0xff << CP0TCSt_TASID));
 623
 624     cu = (v >> CP0St_CU0) & 0xf;
 625     mx = (v >> CP0St_MX) & 0x1;
 626     ksu = (v >> CP0St_KSU) & 0x3;
 627     asid = env->CP0_EntryHi & 0xff;
 628
 629     tcstatus = cu << CP0TCSt_TCU0;
 630     tcstatus |= mx << CP0TCSt_TMX;
 631     tcstatus |= ksu << CP0TCSt_TKSU;
 632     tcstatus |= asid;
 633
 634     if (tc == cpu->current_tc) {
 635         tcst = &cpu->active_tc.CP0_TCStatus;
 636     } else {
 637         tcst = &cpu->tcs[tc].CP0_TCStatus;
 638     }
 639
 640     *tcst &= ~mask;
 641     *tcst |= tcstatus;
 642     compute_hflags(cpu);
 643 }
 644
 645 /* Called for updates to CP0_TCStatus.  */
 646 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 647                              target_ulong v)
 648 {
 649     uint32_t status;
 650     uint32_t tcu, tmx, tasid, tksu;
 651     uint32_t mask = ((1 << CP0St_CU3)
 652                        | (1 << CP0St_CU2)
 653                        | (1 << CP0St_CU1)
 654                        | (1 << CP0St_CU0)
 655                        | (1 << CP0St_MX)
 656                        | (3 << CP0St_KSU));
 657
 658     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 659     tmx = (v >> CP0TCSt_TMX) & 0x1;
 660     tasid = v & 0xff;
 661     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 662
 663     status = tcu << CP0St_CU0;
 664     status |= tmx << CP0St_MX;
 665     status |= tksu << CP0St_KSU;
 666
 667     cpu->CP0_Status &= ~mask;
 668     cpu->CP0_Status |= status;
 669
 670     /* Sync the TASID with EntryHi.  */
 671     cpu->CP0_EntryHi &= ~0xff;
 672     cpu->CP0_EntryHi = tasid;
 673
 674     compute_hflags(cpu);
 675 }
 676
 677 /* Called for updates to CP0_EntryHi.  */
 678 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 679 {
 680     int32_t *tcst;
 681     uint32_t asid, v = cpu->CP0_EntryHi;
 682
 683     asid = v & 0xff;
 684
 685     if (tc == cpu->current_tc) {
 686         tcst = &cpu->active_tc.CP0_TCStatus;
 687     } else {
 688         tcst = &cpu->tcs[tc].CP0_TCStatus;
 689     }
 690
 691     *tcst &= ~0xff;
 692     *tcst |= asid;
 693 }
 694
 695 /* CP0 helpers */
 696 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 697 {
 698     return env->mvp->CP0_MVPControl;
 699 }
 700
 701 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 702 {
 703     return env->mvp->CP0_MVPConf0;
 704 }
 705
 706 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 707 {
 708     return env->mvp->CP0_MVPConf1;
 709 }
 710
 711 target_ulong helper_mfc0_random(CPUMIPSState *env)
 712 {
 713     return (int32_t)cpu_mips_get_random(env);
 714 }
 715
 716 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 717 {
 718     return env->active_tc.CP0_TCStatus;
 719 }
 720
 721 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 722 {
 723     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 724     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 725
 726     if (other_tc == other->current_tc)
 727         return other->active_tc.CP0_TCStatus;
 728     else
 729         return other->tcs[other_tc].CP0_TCStatus;
 730 }
 731
 732 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 733 {
 734     return env->active_tc.CP0_TCBind;
 735 }
 736
 737 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 738 {
 739     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 740     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 741
 742     if (other_tc == other->current_tc)
 743         return other->active_tc.CP0_TCBind;
 744     else
 745         return other->tcs[other_tc].CP0_TCBind;
 746 }
 747
 748 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 749 {
 750     return env->active_tc.PC;
 751 }
 752
 753 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 754 {
 755     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 756     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 757
 758     if (other_tc == other->current_tc)
 759         return other->active_tc.PC;
 760     else
 761         return other->tcs[other_tc].PC;
 762 }
 763
 764 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 765 {
 766     return env->active_tc.CP0_TCHalt;
 767 }
 768
 769 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 770 {
 771     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 772     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 773
 774     if (other_tc == other->current_tc)
 775         return other->active_tc.CP0_TCHalt;
 776     else
 777         return other->tcs[other_tc].CP0_TCHalt;
 778 }
 779
 780 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 781 {
 782     return env->active_tc.CP0_TCContext;
 783 }
 784
 785 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 786 {
 787     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 788     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 789
 790     if (other_tc == other->current_tc)
 791         return other->active_tc.CP0_TCContext;
 792     else
 793         return other->tcs[other_tc].CP0_TCContext;
 794 }
 795
 796 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 797 {
 798     return env->active_tc.CP0_TCSchedule;
 799 }
 800
 801 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 802 {
 803     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 804     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 805
 806     if (other_tc == other->current_tc)
 807         return other->active_tc.CP0_TCSchedule;
 808     else
 809         return other->tcs[other_tc].CP0_TCSchedule;
 810 }
 811
 812 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 813 {
 814     return env->active_tc.CP0_TCScheFBack;
 815 }
 816
 817 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 818 {
 819     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 820     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 821
 822     if (other_tc == other->current_tc)
 823         return other->active_tc.CP0_TCScheFBack;
 824     else
 825         return other->tcs[other_tc].CP0_TCScheFBack;
 826 }
 827
 828 target_ulong helper_mfc0_count(CPUMIPSState *env)
 829 {
 830     return (int32_t)cpu_mips_get_count(env);
 831 }
 832
 833 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 834 {
 835     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 836     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 837
 838     return other->CP0_EntryHi;
 839 }
 840
 841 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 842 {
 843     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 844     int32_t tccause;
 845     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 846
 847     if (other_tc == other->current_tc) {
 848         tccause = other->CP0_Cause;
 849     } else {
 850         tccause = other->CP0_Cause;
 851     }
 852
 853     return tccause;
 854 }
 855
 856 target_ulong helper_mftc0_status(CPUMIPSState *env)
 857 {
 858     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 859     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 860
 861     return other->CP0_Status;
 862 }
 863
 864 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 865 {
 866     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 867 }
 868
 869 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 870 {
 871     return (int32_t)env->CP0_WatchLo[sel];
 872 }
 873
 874 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 875 {
 876     return env->CP0_WatchHi[sel];
 877 }
 878
 879 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 880 {
 881     target_ulong t0 = env->CP0_Debug;
 882     if (env->hflags & MIPS_HFLAG_DM)
 883         t0 |= 1 << CP0DB_DM;
 884
 885     return t0;
 886 }
 887
 888 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 889 {
 890     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 891     int32_t tcstatus;
 892     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 893
 894     if (other_tc == other->current_tc)
 895         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 896     else
 897         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 898
 899     /* XXX: Might be wrong, check with EJTAG spec. */
 900     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 901             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 902 }
 903
 904 #if defined(TARGET_MIPS64)
 905 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 906 {
 907     return env->active_tc.PC;
 908 }
 909
 910 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 911 {
 912     return env->active_tc.CP0_TCHalt;
 913 }
 914
 915 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 916 {
 917     return env->active_tc.CP0_TCContext;
 918 }
 919
 920 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 921 {
 922     return env->active_tc.CP0_TCSchedule;
 923 }
 924
 925 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 926 {
 927     return env->active_tc.CP0_TCScheFBack;
 928 }
 929
 930 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 931 {
 932     return env->lladdr >> env->CP0_LLAddr_shift;
 933 }
 934
 935 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 936 {
 937     return env->CP0_WatchLo[sel];
 938 }
 939 #endif /* TARGET_MIPS64 */
 940
 941 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 942 {
 943     int num = 1;
 944     unsigned int tmp = env->tlb->nb_tlb;
 945
 946     do {
 947         tmp >>= 1;
 948         num <<= 1;
 949     } while (tmp);
 950     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 951 }
 952
 953 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 954 {
 955     uint32_t mask = 0;
 956     uint32_t newval;
 957
 958     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 959         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 960                 (1 << CP0MVPCo_EVP);
 961     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 962         mask |= (1 << CP0MVPCo_STLB);
 963     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 964
 965     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 966
 967     env->mvp->CP0_MVPControl = newval;
 968 }
 969
 970 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 971 {
 972     uint32_t mask;
 973     uint32_t newval;
 974
 975     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 976            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 977     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 978
 979     /* Yield scheduler intercept not implemented. */
 980     /* Gating storage scheduler intercept not implemented. */
 981
 982     // TODO: Enable/disable TCs.
 983
 984     env->CP0_VPEControl = newval;
 985 }
 986
 987 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 988 {
 989     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 990     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 991     uint32_t mask;
 992     uint32_t newval;
 993
 994     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 995            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 996     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 997
 998     /* TODO: Enable/disable TCs.  */
 999
1000     other->CP0_VPEControl = newval;
1001 }
1002
1003 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1004 {
1005     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1006     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1007     /* FIXME: Mask away return zero on read bits.  */
1008     return other->CP0_VPEControl;
1009 }
1010
1011 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1012 {
1013     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1014     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1015
1016     return other->CP0_VPEConf0;
1017 }
1018
1019 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1020 {
1021     uint32_t mask = 0;
1022     uint32_t newval;
1023
1024     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1025         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1026             mask |= (0xff << CP0VPEC0_XTC);
1027         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1028     }
1029     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1030
1031     // TODO: TC exclusive handling due to ERL/EXL.
1032
1033     env->CP0_VPEConf0 = newval;
1034 }
1035
1036 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1037 {
1038     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1039     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1040     uint32_t mask = 0;
1041     uint32_t newval;
1042
1043     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1044     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1045
1046     /* TODO: TC exclusive handling due to ERL/EXL.  */
1047     other->CP0_VPEConf0 = newval;
1048 }
1049
1050 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1051 {
1052     uint32_t mask = 0;
1053     uint32_t newval;
1054
1055     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1056         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1057                 (0xff << CP0VPEC1_NCP1);
1058     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1059
1060     /* UDI not implemented. */
1061     /* CP2 not implemented. */
1062
1063     // TODO: Handle FPU (CP1) binding.
1064
1065     env->CP0_VPEConf1 = newval;
1066 }
1067
1068 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1069 {
1070     /* Yield qualifier inputs not implemented. */
1071     env->CP0_YQMask = 0x00000000;
1072 }
1073
1074 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1075 {
1076     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1077 }
1078
1079 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1080 {
1081     /* Large physaddr (PABITS) not implemented */
1082     /* 1k pages not implemented */
1083     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1084 }
1085
1086 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1087 {
1088     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1089     uint32_t newval;
1090
1091     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1092
1093     env->active_tc.CP0_TCStatus = newval;
1094     sync_c0_tcstatus(env, env->current_tc, newval);
1095 }
1096
1097 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1098 {
1099     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1100     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1101
1102     if (other_tc == other->current_tc)
1103         other->active_tc.CP0_TCStatus = arg1;
1104     else
1105         other->tcs[other_tc].CP0_TCStatus = arg1;
1106     sync_c0_tcstatus(other, other_tc, arg1);
1107 }
1108
1109 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1110 {
1111     uint32_t mask = (1 << CP0TCBd_TBE);
1112     uint32_t newval;
1113
1114     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1115         mask |= (1 << CP0TCBd_CurVPE);
1116     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1117     env->active_tc.CP0_TCBind = newval;
1118 }
1119
1120 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1121 {
1122     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1123     uint32_t mask = (1 << CP0TCBd_TBE);
1124     uint32_t newval;
1125     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1126
1127     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1128         mask |= (1 << CP0TCBd_CurVPE);
1129     if (other_tc == other->current_tc) {
1130         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1131         other->active_tc.CP0_TCBind = newval;
1132     } else {
1133         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1134         other->tcs[other_tc].CP0_TCBind = newval;
1135     }
1136 }
1137
1138 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1139 {
1140     env->active_tc.PC = arg1;
1141     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1142     env->lladdr = 0ULL;
1143     /* MIPS16 not implemented. */
1144 }
1145
1146 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1147 {
1148     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1149     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1150
1151     if (other_tc == other->current_tc) {
1152         other->active_tc.PC = arg1;
1153         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1154         other->lladdr = 0ULL;
1155         /* MIPS16 not implemented. */
1156     } else {
1157         other->tcs[other_tc].PC = arg1;
1158         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1159         other->lladdr = 0ULL;
1160         /* MIPS16 not implemented. */
1161     }
1162 }
1163
1164 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1165 {
1166     MIPSCPU *cpu = mips_env_get_cpu(env);
1167
1168     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1169
1170     // TODO: Halt TC / Restart (if allocated+active) TC.
1171     if (env->active_tc.CP0_TCHalt & 1) {
1172         mips_tc_sleep(cpu, env->current_tc);
1173     } else {
1174         mips_tc_wake(cpu, env->current_tc);
1175     }
1176 }
1177
1178 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1179 {
1180     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1182     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1183
1184     // TODO: Halt TC / Restart (if allocated+active) TC.
1185
1186     if (other_tc == other->current_tc)
1187         other->active_tc.CP0_TCHalt = arg1;
1188     else
1189         other->tcs[other_tc].CP0_TCHalt = arg1;
1190
1191     if (arg1 & 1) {
1192         mips_tc_sleep(other_cpu, other_tc);
1193     } else {
1194         mips_tc_wake(other_cpu, other_tc);
1195     }
1196 }
1197
1198 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1199 {
1200     env->active_tc.CP0_TCContext = arg1;
1201 }
1202
1203 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1204 {
1205     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1206     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1207
1208     if (other_tc == other->current_tc)
1209         other->active_tc.CP0_TCContext = arg1;
1210     else
1211         other->tcs[other_tc].CP0_TCContext = arg1;
1212 }
1213
1214 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1215 {
1216     env->active_tc.CP0_TCSchedule = arg1;
1217 }
1218
1219 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1220 {
1221     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1222     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1223
1224     if (other_tc == other->current_tc)
1225         other->active_tc.CP0_TCSchedule = arg1;
1226     else
1227         other->tcs[other_tc].CP0_TCSchedule = arg1;
1228 }
1229
1230 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1231 {
1232     env->active_tc.CP0_TCScheFBack = arg1;
1233 }
1234
1235 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1236 {
1237     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1238     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1239
1240     if (other_tc == other->current_tc)
1241         other->active_tc.CP0_TCScheFBack = arg1;
1242     else
1243         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1244 }
1245
1246 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1247 {
1248     /* Large physaddr (PABITS) not implemented */
1249     /* 1k pages not implemented */
1250     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1251 }
1252
1253 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1254 {
1255     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1256 }
1257
1258 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1259 {
1260     /* 1k pages not implemented */
1261     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1262 }
1263
1264 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1265 {
1266     /* SmartMIPS not implemented */
1267     /* Large physaddr (PABITS) not implemented */
1268     /* 1k pages not implemented */
1269     env->CP0_PageGrain = 0;
1270 }
1271
1272 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1273 {
1274     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1275 }
1276
1277 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1278 {
1279     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1280 }
1281
1282 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1283 {
1284     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1285 }
1286
1287 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1288 {
1289     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1290 }
1291
1292 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1293 {
1294     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1295 }
1296
1297 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1298 {
1299     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1300 }
1301
1302 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1303 {
1304     env->CP0_HWREna = arg1 & 0x0000000F;
1305 }
1306
1307 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1308 {
1309     cpu_mips_store_count(env, arg1);
1310 }
1311
1312 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1313 {
1314     target_ulong old, val;
1315
1316     /* 1k pages not implemented */
1317     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1318 #if defined(TARGET_MIPS64)
1319     val &= env->SEGMask;
1320 #endif
1321     old = env->CP0_EntryHi;
1322     env->CP0_EntryHi = val;
1323     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1324         sync_c0_entryhi(env, env->current_tc);
1325     }
1326     /* If the ASID changes, flush qemu's TLB.  */
1327     if ((old & 0xFF) != (val & 0xFF))
1328         cpu_mips_tlb_flush(env, 1);
1329 }
1330
1331 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1332 {
1333     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1334     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1335
1336     other->CP0_EntryHi = arg1;
1337     sync_c0_entryhi(other, other_tc);
1338 }
1339
1340 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1341 {
1342     cpu_mips_store_compare(env, arg1);
1343 }
1344
1345 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1346 {
1347     uint32_t val, old;
1348     uint32_t mask = env->CP0_Status_rw_bitmask;
1349
1350     val = arg1 & mask;
1351     old = env->CP0_Status;
1352     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1353     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1354         sync_c0_status(env, env, env->current_tc);
1355     } else {
1356         compute_hflags(env);
1357     }
1358
1359     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1360         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1361                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1362                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1363                 env->CP0_Cause);
1364         switch (env->hflags & MIPS_HFLAG_KSU) {
1365         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1366         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1367         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1368         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1369         }
1370     }
1371 }
1372
1373 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1374 {
1375     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1376     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1377
1378     other->CP0_Status = arg1 & ~0xf1000018;
1379     sync_c0_status(env, other, other_tc);
1380 }
1381
1382 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1383 {
1384     /* vectored interrupts not implemented, no performance counters. */
1385     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1386 }
1387
1388 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1389 {
1390     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1391     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1392 }
1393
1394 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1395 {
1396     uint32_t mask = 0x00C00300;
1397     uint32_t old = cpu->CP0_Cause;
1398     int i;
1399
1400     if (cpu->insn_flags & ISA_MIPS32R2) {
1401         mask |= 1 << CP0Ca_DC;
1402     }
1403
1404     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1405
1406     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1407         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1408             cpu_mips_stop_count(cpu);
1409         } else {
1410             cpu_mips_start_count(cpu);
1411         }
1412     }
1413
1414     /* Set/reset software interrupts */
1415     for (i = 0 ; i < 2 ; i++) {
1416         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1417             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1418         }
1419     }
1420 }
1421
1422 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1423 {
1424     mtc0_cause(env, arg1);
1425 }
1426
1427 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1428 {
1429     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1430     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1431
1432     mtc0_cause(other, arg1);
1433 }
1434
1435 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1436 {
1437     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1438     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1439
1440     return other->CP0_EPC;
1441 }
1442
1443 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1444 {
1445     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1446     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1447
1448     return other->CP0_EBase;
1449 }
1450
1451 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1452 {
1453     /* vectored interrupts not implemented */
1454     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1455 }
1456
1457 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1458 {
1459     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1460     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1461     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1462 }
1463
1464 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1465 {
1466     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1467     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1468
1469     switch (idx) {
1470     case 0: return other->CP0_Config0;
1471     case 1: return other->CP0_Config1;
1472     case 2: return other->CP0_Config2;
1473     case 3: return other->CP0_Config3;
1474     /* 4 and 5 are reserved.  */
1475     case 6: return other->CP0_Config6;
1476     case 7: return other->CP0_Config7;
1477     default:
1478         break;
1479     }
1480     return 0;
1481 }
1482
1483 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1484 {
1485     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1486 }
1487
1488 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1489 {
1490     /* tertiary/secondary caches not implemented */
1491     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1492 }
1493
1494 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1495 {
1496     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1497                        (arg1 & env->CP0_Config4_rw_bitmask);
1498 }
1499
1500 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1501 {
1502     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1503                        (arg1 & env->CP0_Config5_rw_bitmask);
1504 }
1505
1506 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1507 {
1508     target_long mask = env->CP0_LLAddr_rw_bitmask;
1509     arg1 = arg1 << env->CP0_LLAddr_shift;
1510     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1511 }
1512
1513 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1514 {
1515     /* Watch exceptions for instructions, data loads, data stores
1516        not implemented. */
1517     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1518 }
1519
1520 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1521 {
1522     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1523     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1524 }
1525
1526 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1527 {
1528     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1529     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1530 }
1531
1532 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1533 {
1534     env->CP0_Framemask = arg1; /* XXX */
1535 }
1536
1537 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1538 {
1539     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1540     if (arg1 & (1 << CP0DB_DM))
1541         env->hflags |= MIPS_HFLAG_DM;
1542     else
1543         env->hflags &= ~MIPS_HFLAG_DM;
1544 }
1545
1546 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1547 {
1548     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1549     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1550     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1551
1552     /* XXX: Might be wrong, check with EJTAG spec. */
1553     if (other_tc == other->current_tc)
1554         other->active_tc.CP0_Debug_tcstatus = val;
1555     else
1556         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1557     other->CP0_Debug = (other->CP0_Debug &
1558                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1559                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1560 }
1561
1562 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1563 {
1564     env->CP0_Performance0 = arg1 & 0x000007ff;
1565 }
1566
1567 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1568 {
1569     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1570 }
1571
1572 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1573 {
1574     env->CP0_DataLo = arg1; /* XXX */
1575 }
1576
1577 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1578 {
1579     env->CP0_TagHi = arg1; /* XXX */
1580 }
1581
1582 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1583 {
1584     env->CP0_DataHi = arg1; /* XXX */
1585 }
1586
1587 /* MIPS MT functions */
1588 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1589 {
1590     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1591     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1592
1593     if (other_tc == other->current_tc)
1594         return other->active_tc.gpr[sel];
1595     else
1596         return other->tcs[other_tc].gpr[sel];
1597 }
1598
1599 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1600 {
1601     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1602     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1603
1604     if (other_tc == other->current_tc)
1605         return other->active_tc.LO[sel];
1606     else
1607         return other->tcs[other_tc].LO[sel];
1608 }
1609
1610 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1611 {
1612     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1613     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1614
1615     if (other_tc == other->current_tc)
1616         return other->active_tc.HI[sel];
1617     else
1618         return other->tcs[other_tc].HI[sel];
1619 }
1620
1621 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1622 {
1623     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1624     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1625
1626     if (other_tc == other->current_tc)
1627         return other->active_tc.ACX[sel];
1628     else
1629         return other->tcs[other_tc].ACX[sel];
1630 }
1631
1632 target_ulong helper_mftdsp(CPUMIPSState *env)
1633 {
1634     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1635     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1636
1637     if (other_tc == other->current_tc)
1638         return other->active_tc.DSPControl;
1639     else
1640         return other->tcs[other_tc].DSPControl;
1641 }
1642
1643 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1644 {
1645     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1646     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1647
1648     if (other_tc == other->current_tc)
1649         other->active_tc.gpr[sel] = arg1;
1650     else
1651         other->tcs[other_tc].gpr[sel] = arg1;
1652 }
1653
1654 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1655 {
1656     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1657     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1658
1659     if (other_tc == other->current_tc)
1660         other->active_tc.LO[sel] = arg1;
1661     else
1662         other->tcs[other_tc].LO[sel] = arg1;
1663 }
1664
1665 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1666 {
1667     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1668     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1669
1670     if (other_tc == other->current_tc)
1671         other->active_tc.HI[sel] = arg1;
1672     else
1673         other->tcs[other_tc].HI[sel] = arg1;
1674 }
1675
1676 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1677 {
1678     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1679     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1680
1681     if (other_tc == other->current_tc)
1682         other->active_tc.ACX[sel] = arg1;
1683     else
1684         other->tcs[other_tc].ACX[sel] = arg1;
1685 }
1686
1687 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1688 {
1689     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1690     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1691
1692     if (other_tc == other->current_tc)
1693         other->active_tc.DSPControl = arg1;
1694     else
1695         other->tcs[other_tc].DSPControl = arg1;
1696 }
1697
1698 /* MIPS MT functions */
1699 target_ulong helper_dmt(void)
1700 {
1701     // TODO
1702      return 0;
1703 }
1704
1705 target_ulong helper_emt(void)
1706 {
1707     // TODO
1708     return 0;
1709 }
1710
1711 target_ulong helper_dvpe(CPUMIPSState *env)
1712 {
1713     CPUState *other_cs = first_cpu;
1714     target_ulong prev = env->mvp->CP0_MVPControl;
1715
1716     CPU_FOREACH(other_cs) {
1717         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1718         /* Turn off all VPEs except the one executing the dvpe.  */
1719         if (&other_cpu->env != env) {
1720             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1721             mips_vpe_sleep(other_cpu);
1722         }
1723     }
1724     return prev;
1725 }
1726
1727 target_ulong helper_evpe(CPUMIPSState *env)
1728 {
1729     CPUState *other_cs = first_cpu;
1730     target_ulong prev = env->mvp->CP0_MVPControl;
1731
1732     CPU_FOREACH(other_cs) {
1733         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1734
1735         if (&other_cpu->env != env
1736             /* If the VPE is WFI, don't disturb its sleep.  */
1737             && !mips_vpe_is_wfi(other_cpu)) {
1738             /* Enable the VPE.  */
1739             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1740             mips_vpe_wake(other_cpu); /* And wake it up.  */
1741         }
1742     }
1743     return prev;
1744 }
1745 #endif /* !CONFIG_USER_ONLY */
1746
1747 void helper_fork(target_ulong arg1, target_ulong arg2)
1748 {
1749     // arg1 = rt, arg2 = rs
1750     // TODO: store to TC register
1751 }
1752
1753 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1754 {
1755     target_long arg1 = arg;
1756
1757     if (arg1 < 0) {
1758         /* No scheduling policy implemented. */
1759         if (arg1 != -2) {
1760             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1761                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1762                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1763                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1764                 helper_raise_exception(env, EXCP_THREAD);
1765             }
1766         }
1767     } else if (arg1 == 0) {
1768         if (0 /* TODO: TC underflow */) {
1769             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1770             helper_raise_exception(env, EXCP_THREAD);
1771         } else {
1772             // TODO: Deallocate TC
1773         }
1774     } else if (arg1 > 0) {
1775         /* Yield qualifier inputs not implemented. */
1776         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1777         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1778         helper_raise_exception(env, EXCP_THREAD);
1779     }
1780     return env->CP0_YQMask;
1781 }
1782
1783 #ifndef CONFIG_USER_ONLY
1784 /* TLB management */
1785 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1786 {
1787     /* Flush qemu's TLB and discard all shadowed entries.  */
1788     tlb_flush (env, flush_global);
1789     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1790 }
1791
1792 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1793 {
1794     /* Discard entries from env->tlb[first] onwards.  */
1795     while (env->tlb->tlb_in_use > first) {
1796         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1797     }
1798 }
1799
1800 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1801 {
1802     r4k_tlb_t *tlb;
1803
1804     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1805     tlb = &env->tlb->mmu.r4k.tlb[idx];
1806     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1807 #if defined(TARGET_MIPS64)
1808     tlb->VPN &= env->SEGMask;
1809 #endif
1810     tlb->ASID = env->CP0_EntryHi & 0xFF;
1811     tlb->PageMask = env->CP0_PageMask;
1812     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1813     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1814     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1815     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1816     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1817     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1818     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1819     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1820     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1821 }
1822
1823 void r4k_helper_tlbwi(CPUMIPSState *env)
1824 {
1825     r4k_tlb_t *tlb;
1826     int idx;
1827     target_ulong VPN;
1828     uint8_t ASID;
1829     bool G, V0, D0, V1, D1;
1830
1831     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1832     tlb = &env->tlb->mmu.r4k.tlb[idx];
1833     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1834 #if defined(TARGET_MIPS64)
1835     VPN &= env->SEGMask;
1836 #endif
1837     ASID = env->CP0_EntryHi & 0xff;
1838     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1839     V0 = (env->CP0_EntryLo0 & 2) != 0;
1840     D0 = (env->CP0_EntryLo0 & 4) != 0;
1841     V1 = (env->CP0_EntryLo1 & 2) != 0;
1842     D1 = (env->CP0_EntryLo1 & 4) != 0;
1843
1844     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1845        permissions on the current entry. */
1846     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1847         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1848         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1849         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1850     }
1851
1852     r4k_invalidate_tlb(env, idx, 0);
1853     r4k_fill_tlb(env, idx);
1854 }
1855
1856 void r4k_helper_tlbwr(CPUMIPSState *env)
1857 {
1858     int r = cpu_mips_get_random(env);
1859
1860     r4k_invalidate_tlb(env, r, 1);
1861     r4k_fill_tlb(env, r);
1862 }
1863
1864 void r4k_helper_tlbp(CPUMIPSState *env)
1865 {
1866     r4k_tlb_t *tlb;
1867     target_ulong mask;
1868     target_ulong tag;
1869     target_ulong VPN;
1870     uint8_t ASID;
1871     int i;
1872
1873     ASID = env->CP0_EntryHi & 0xFF;
1874     for (i = 0; i < env->tlb->nb_tlb; i++) {
1875         tlb = &env->tlb->mmu.r4k.tlb[i];
1876         /* 1k pages are not supported. */
1877         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1878         tag = env->CP0_EntryHi & ~mask;
1879         VPN = tlb->VPN & ~mask;
1880 #if defined(TARGET_MIPS64)
1881         tag &= env->SEGMask;
1882 #endif
1883         /* Check ASID, virtual page number & size */
1884         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1885             /* TLB match */
1886             env->CP0_Index = i;
1887             break;
1888         }
1889     }
1890     if (i == env->tlb->nb_tlb) {
1891         /* No match.  Discard any shadow entries, if any of them match.  */
1892         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1893             tlb = &env->tlb->mmu.r4k.tlb[i];
1894             /* 1k pages are not supported. */
1895             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1896             tag = env->CP0_EntryHi & ~mask;
1897             VPN = tlb->VPN & ~mask;
1898 #if defined(TARGET_MIPS64)
1899             tag &= env->SEGMask;
1900 #endif
1901             /* Check ASID, virtual page number & size */
1902             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1903                 r4k_mips_tlb_flush_extra (env, i);
1904                 break;
1905             }
1906         }
1907
1908         env->CP0_Index |= 0x80000000;
1909     }
1910 }
1911
1912 void r4k_helper_tlbr(CPUMIPSState *env)
1913 {
1914     r4k_tlb_t *tlb;
1915     uint8_t ASID;
1916     int idx;
1917
1918     ASID = env->CP0_EntryHi & 0xFF;
1919     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1920     tlb = &env->tlb->mmu.r4k.tlb[idx];
1921
1922     /* If this will change the current ASID, flush qemu's TLB.  */
1923     if (ASID != tlb->ASID)
1924         cpu_mips_tlb_flush (env, 1);
1925
1926     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1927
1928     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1929     env->CP0_PageMask = tlb->PageMask;
1930     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1931                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1932     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1933                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1934 }
1935
1936 void helper_tlbwi(CPUMIPSState *env)
1937 {
1938     env->tlb->helper_tlbwi(env);
1939 }
1940
1941 void helper_tlbwr(CPUMIPSState *env)
1942 {
1943     env->tlb->helper_tlbwr(env);
1944 }
1945
1946 void helper_tlbp(CPUMIPSState *env)
1947 {
1948     env->tlb->helper_tlbp(env);
1949 }
1950
1951 void helper_tlbr(CPUMIPSState *env)
1952 {
1953     env->tlb->helper_tlbr(env);
1954 }
1955
1956 /* Specials */
1957 target_ulong helper_di(CPUMIPSState *env)
1958 {
1959     target_ulong t0 = env->CP0_Status;
1960
1961     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1962     return t0;
1963 }
1964
1965 target_ulong helper_ei(CPUMIPSState *env)
1966 {
1967     target_ulong t0 = env->CP0_Status;
1968
1969     env->CP0_Status = t0 | (1 << CP0St_IE);
1970     return t0;
1971 }
1972
1973 static void debug_pre_eret(CPUMIPSState *env)
1974 {
1975     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1976         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1977                 env->active_tc.PC, env->CP0_EPC);
1978         if (env->CP0_Status & (1 << CP0St_ERL))
1979             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1980         if (env->hflags & MIPS_HFLAG_DM)
1981             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1982         qemu_log("\n");
1983     }
1984 }
1985
1986 static void debug_post_eret(CPUMIPSState *env)
1987 {
1988     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1989         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1990                 env->active_tc.PC, env->CP0_EPC);
1991         if (env->CP0_Status & (1 << CP0St_ERL))
1992             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1993         if (env->hflags & MIPS_HFLAG_DM)
1994             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1995         switch (env->hflags & MIPS_HFLAG_KSU) {
1996         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1997         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1998         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1999         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
2000         }
2001     }
2002 }
2003
2004 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2005 {
2006     env->active_tc.PC = error_pc & ~(target_ulong)1;
2007     if (error_pc & 1) {
2008         env->hflags |= MIPS_HFLAG_M16;
2009     } else {
2010         env->hflags &= ~(MIPS_HFLAG_M16);
2011     }
2012 }
2013
2014 void helper_eret(CPUMIPSState *env)
2015 {
2016     debug_pre_eret(env);
2017     if (env->CP0_Status & (1 << CP0St_ERL)) {
2018         set_pc(env, env->CP0_ErrorEPC);
2019         env->CP0_Status &= ~(1 << CP0St_ERL);
2020     } else {
2021         set_pc(env, env->CP0_EPC);
2022         env->CP0_Status &= ~(1 << CP0St_EXL);
2023     }
2024     compute_hflags(env);
2025     debug_post_eret(env);
2026     env->lladdr = 1;
2027 }
2028
2029 void helper_deret(CPUMIPSState *env)
2030 {
2031     debug_pre_eret(env);
2032     set_pc(env, env->CP0_DEPC);
2033
2034     env->hflags &= MIPS_HFLAG_DM;
2035     compute_hflags(env);
2036     debug_post_eret(env);
2037     env->lladdr = 1;
2038 }
2039 #endif /* !CONFIG_USER_ONLY */
2040
2041 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2042 {
2043     if ((env->hflags & MIPS_HFLAG_CP0) ||
2044         (env->CP0_HWREna & (1 << 0)))
2045         return env->CP0_EBase & 0x3ff;
2046     else
2047         helper_raise_exception(env, EXCP_RI);
2048
2049     return 0;
2050 }
2051
2052 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2053 {
2054     if ((env->hflags & MIPS_HFLAG_CP0) ||
2055         (env->CP0_HWREna & (1 << 1)))
2056         return env->SYNCI_Step;
2057     else
2058         helper_raise_exception(env, EXCP_RI);
2059
2060     return 0;
2061 }
2062
2063 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2064 {
2065     if ((env->hflags & MIPS_HFLAG_CP0) ||
2066         (env->CP0_HWREna & (1 << 2)))
2067         return env->CP0_Count;
2068     else
2069         helper_raise_exception(env, EXCP_RI);
2070
2071     return 0;
2072 }
2073
2074 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2075 {
2076     if ((env->hflags & MIPS_HFLAG_CP0) ||
2077         (env->CP0_HWREna & (1 << 3)))
2078         return env->CCRes;
2079     else
2080         helper_raise_exception(env, EXCP_RI);
2081
2082     return 0;
2083 }
2084
2085 void helper_pmon(CPUMIPSState *env, int function)
2086 {
2087     function /= 2;
2088     switch (function) {
2089     case 2: /* TODO: char inbyte(int waitflag); */
2090         if (env->active_tc.gpr[4] == 0)
2091             env->active_tc.gpr[2] = -1;
2092         /* Fall through */
2093     case 11: /* TODO: char inbyte (void); */
2094         env->active_tc.gpr[2] = -1;
2095         break;
2096     case 3:
2097     case 12:
2098         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2099         break;
2100     case 17:
2101         break;
2102     case 158:
2103         {
2104             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2105             printf("%s", fmt);
2106         }
2107         break;
2108     }
2109 }
2110
2111 void helper_wait(CPUMIPSState *env)
2112 {
2113     CPUState *cs = CPU(mips_env_get_cpu(env));
2114
2115     cs->halted = 1;
2116     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2117     helper_raise_exception(env, EXCP_HLT);
2118 }
2119
2120 #if !defined(CONFIG_USER_ONLY)
2121
2122 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2123                                               target_ulong addr, int is_write,
2124                                               int is_user, uintptr_t retaddr);
2125
2126 #define MMUSUFFIX _mmu
2127 #define ALIGNED_ONLY
2128
2129 #define SHIFT 0
2130 #include "exec/softmmu_template.h"
2131
2132 #define SHIFT 1
2133 #include "exec/softmmu_template.h"
2134
2135 #define SHIFT 2
2136 #include "exec/softmmu_template.h"
2137
2138 #define SHIFT 3
2139 #include "exec/softmmu_template.h"
2140
2141 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2142                                 int is_write, int is_user, uintptr_t retaddr)
2143 {
2144     env->CP0_BadVAddr = addr;
2145     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2146 }
2147
2148 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2149               uintptr_t retaddr)
2150 {
2151     int ret;
2152
2153     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2154     if (ret) {
2155         MIPSCPU *cpu = MIPS_CPU(cs);
2156         CPUMIPSState *env = &cpu->env;
2157
2158         do_raise_exception_err(env, cs->exception_index,
2159                                env->error_code, retaddr);
2160     }
2161 }
2162
2163 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2164                                 bool is_write, bool is_exec, int unused,
2165                                 unsigned size)
2166 {
2167     MIPSCPU *cpu = MIPS_CPU(cs);
2168     CPUMIPSState *env = &cpu->env;
2169
2170     if (is_exec) {
2171         helper_raise_exception(env, EXCP_IBE);
2172     } else {
2173         helper_raise_exception(env, EXCP_DBE);
2174     }
2175 }
2176 #endif /* !CONFIG_USER_ONLY */
2177
2178 /* Complex FPU operations which may need stack space. */
2179
2180 #define FLOAT_TWO32 make_float32(1 << 30)
2181 #define FLOAT_TWO64 make_float64(1ULL << 62)
2182 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2183 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2184
2185 /* convert MIPS rounding mode in FCR31 to IEEE library */
2186 static unsigned int ieee_rm[] = {
2187     float_round_nearest_even,
2188     float_round_to_zero,
2189     float_round_up,
2190     float_round_down
2191 };
2192
2193 static inline void restore_rounding_mode(CPUMIPSState *env)
2194 {
2195     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2196                             &env->active_fpu.fp_status);
2197 }
2198
2199 static inline void restore_flush_mode(CPUMIPSState *env)
2200 {
2201     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2202                       &env->active_fpu.fp_status);
2203 }
2204
2205 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2206 {
2207     target_ulong arg1 = 0;
2208
2209     switch (reg) {
2210     case 0:
2211         arg1 = (int32_t)env->active_fpu.fcr0;
2212         break;
2213     case 1:
2214         /* UFR Support - Read Status FR */
2215         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2216             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2217                 arg1 = (int32_t)
2218                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2219             } else {
2220                 helper_raise_exception(env, EXCP_RI);
2221             }
2222         }
2223         break;
2224     case 25:
2225         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2226         break;
2227     case 26:
2228         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2229         break;
2230     case 28:
2231         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2232         break;
2233     default:
2234         arg1 = (int32_t)env->active_fpu.fcr31;
2235         break;
2236     }
2237
2238     return arg1;
2239 }
2240
2241 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2242 {
2243     switch (fs) {
2244     case 1:
2245         /* UFR Alias - Reset Status FR */
2246         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2247             return;
2248         }
2249         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2250             env->CP0_Status &= ~(1 << CP0St_FR);
2251             compute_hflags(env);
2252         } else {
2253             helper_raise_exception(env, EXCP_RI);
2254         }
2255         break;
2256     case 4:
2257         /* UNFR Alias - Set Status FR */
2258         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2259             return;
2260         }
2261         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2262             env->CP0_Status |= (1 << CP0St_FR);
2263             compute_hflags(env);
2264         } else {
2265             helper_raise_exception(env, EXCP_RI);
2266         }
2267         break;
2268     case 25:
2269         if (arg1 & 0xffffff00)
2270             return;
2271         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2272                      ((arg1 & 0x1) << 23);
2273         break;
2274     case 26:
2275         if (arg1 & 0x007c0000)
2276             return;
2277         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2278         break;
2279     case 28:
2280         if (arg1 & 0x007c0000)
2281             return;
2282         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2283                      ((arg1 & 0x4) << 22);
2284         break;
2285     case 31:
2286         if (arg1 & 0x007c0000)
2287             return;
2288         env->active_fpu.fcr31 = arg1;
2289         break;
2290     default:
2291         return;
2292     }
2293     /* set rounding mode */
2294     restore_rounding_mode(env);
2295     /* set flush-to-zero mode */
2296     restore_flush_mode(env);
2297     set_float_exception_flags(0, &env->active_fpu.fp_status);
2298     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2299         do_raise_exception(env, EXCP_FPE, GETPC());
2300 }
2301
2302 static inline int ieee_ex_to_mips(int xcpt)
2303 {
2304     int ret = 0;
2305     if (xcpt) {
2306         if (xcpt & float_flag_invalid) {
2307             ret |= FP_INVALID;
2308         }
2309         if (xcpt & float_flag_overflow) {
2310             ret |= FP_OVERFLOW;
2311         }
2312         if (xcpt & float_flag_underflow) {
2313             ret |= FP_UNDERFLOW;
2314         }
2315         if (xcpt & float_flag_divbyzero) {
2316             ret |= FP_DIV0;
2317         }
2318         if (xcpt & float_flag_inexact) {
2319             ret |= FP_INEXACT;
2320         }
2321     }
2322     return ret;
2323 }
2324
2325 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2326 {
2327     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2328
2329     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2330
2331     if (tmp) {
2332         set_float_exception_flags(0, &env->active_fpu.fp_status);
2333
2334         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2335             do_raise_exception(env, EXCP_FPE, pc);
2336         } else {
2337             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2338         }
2339     }
2340 }
2341
2342 /* Float support.
2343    Single precition routines have a "s" suffix, double precision a
2344    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2345    paired single lower "pl", paired single upper "pu".  */
2346
2347 /* unary operations, modifying fp status  */
2348 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2349 {
2350     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2351     update_fcr31(env, GETPC());
2352     return fdt0;
2353 }
2354
2355 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2356 {
2357     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2358     update_fcr31(env, GETPC());
2359     return fst0;
2360 }
2361
2362 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2363 {
2364     uint64_t fdt2;
2365
2366     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2367     update_fcr31(env, GETPC());
2368     return fdt2;
2369 }
2370
2371 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2372 {
2373     uint64_t fdt2;
2374
2375     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2376     update_fcr31(env, GETPC());
2377     return fdt2;
2378 }
2379
2380 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2381 {
2382     uint64_t fdt2;
2383
2384     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2385     update_fcr31(env, GETPC());
2386     return fdt2;
2387 }
2388
2389 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2390 {
2391     uint64_t dt2;
2392
2393     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2394     if (get_float_exception_flags(&env->active_fpu.fp_status)
2395         & (float_flag_invalid | float_flag_overflow)) {
2396         dt2 = FP_TO_INT64_OVERFLOW;
2397     }
2398     update_fcr31(env, GETPC());
2399     return dt2;
2400 }
2401
2402 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2403 {
2404     uint64_t dt2;
2405
2406     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2407     if (get_float_exception_flags(&env->active_fpu.fp_status)
2408         & (float_flag_invalid | float_flag_overflow)) {
2409         dt2 = FP_TO_INT64_OVERFLOW;
2410     }
2411     update_fcr31(env, GETPC());
2412     return dt2;
2413 }
2414
2415 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2416 {
2417     uint32_t fst2;
2418     uint32_t fsth2;
2419
2420     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2421     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2422     update_fcr31(env, GETPC());
2423     return ((uint64_t)fsth2 << 32) | fst2;
2424 }
2425
2426 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2427 {
2428     uint32_t wt2;
2429     uint32_t wth2;
2430     int excp, excph;
2431
2432     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2433     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2434     if (excp & (float_flag_overflow | float_flag_invalid)) {
2435         wt2 = FP_TO_INT32_OVERFLOW;
2436     }
2437
2438     set_float_exception_flags(0, &env->active_fpu.fp_status);
2439     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2440     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2441     if (excph & (float_flag_overflow | float_flag_invalid)) {
2442         wth2 = FP_TO_INT32_OVERFLOW;
2443     }
2444
2445     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2446     update_fcr31(env, GETPC());
2447
2448     return ((uint64_t)wth2 << 32) | wt2;
2449 }
2450
2451 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2452 {
2453     uint32_t fst2;
2454
2455     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2456     update_fcr31(env, GETPC());
2457     return fst2;
2458 }
2459
2460 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2461 {
2462     uint32_t fst2;
2463
2464     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2465     update_fcr31(env, GETPC());
2466     return fst2;
2467 }
2468
2469 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2470 {
2471     uint32_t fst2;
2472
2473     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2474     update_fcr31(env, GETPC());
2475     return fst2;
2476 }
2477
2478 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2479 {
2480     uint32_t wt2;
2481
2482     wt2 = wt0;
2483     update_fcr31(env, GETPC());
2484     return wt2;
2485 }
2486
2487 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2488 {
2489     uint32_t wt2;
2490
2491     wt2 = wth0;
2492     update_fcr31(env, GETPC());
2493     return wt2;
2494 }
2495
2496 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2497 {
2498     uint32_t wt2;
2499
2500     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2501     update_fcr31(env, GETPC());
2502     if (get_float_exception_flags(&env->active_fpu.fp_status)
2503         & (float_flag_invalid | float_flag_overflow)) {
2504         wt2 = FP_TO_INT32_OVERFLOW;
2505     }
2506     return wt2;
2507 }
2508
2509 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2510 {
2511     uint32_t wt2;
2512
2513     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2514     if (get_float_exception_flags(&env->active_fpu.fp_status)
2515         & (float_flag_invalid | float_flag_overflow)) {
2516         wt2 = FP_TO_INT32_OVERFLOW;
2517     }
2518     update_fcr31(env, GETPC());
2519     return wt2;
2520 }
2521
2522 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2523 {
2524     uint64_t dt2;
2525
2526     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2527     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2528     restore_rounding_mode(env);
2529     if (get_float_exception_flags(&env->active_fpu.fp_status)
2530         & (float_flag_invalid | float_flag_overflow)) {
2531         dt2 = FP_TO_INT64_OVERFLOW;
2532     }
2533     update_fcr31(env, GETPC());
2534     return dt2;
2535 }
2536
2537 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2538 {
2539     uint64_t dt2;
2540
2541     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2542     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2543     restore_rounding_mode(env);
2544     if (get_float_exception_flags(&env->active_fpu.fp_status)
2545         & (float_flag_invalid | float_flag_overflow)) {
2546         dt2 = FP_TO_INT64_OVERFLOW;
2547     }
2548     update_fcr31(env, GETPC());
2549     return dt2;
2550 }
2551
2552 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2553 {
2554     uint32_t wt2;
2555
2556     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2557     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2558     restore_rounding_mode(env);
2559     if (get_float_exception_flags(&env->active_fpu.fp_status)
2560         & (float_flag_invalid | float_flag_overflow)) {
2561         wt2 = FP_TO_INT32_OVERFLOW;
2562     }
2563     update_fcr31(env, GETPC());
2564     return wt2;
2565 }
2566
2567 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2568 {
2569     uint32_t wt2;
2570
2571     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2572     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2573     restore_rounding_mode(env);
2574     if (get_float_exception_flags(&env->active_fpu.fp_status)
2575         & (float_flag_invalid | float_flag_overflow)) {
2576         wt2 = FP_TO_INT32_OVERFLOW;
2577     }
2578     update_fcr31(env, GETPC());
2579     return wt2;
2580 }
2581
2582 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2583 {
2584     uint64_t dt2;
2585
2586     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2587     if (get_float_exception_flags(&env->active_fpu.fp_status)
2588         & (float_flag_invalid | float_flag_overflow)) {
2589         dt2 = FP_TO_INT64_OVERFLOW;
2590     }
2591     update_fcr31(env, GETPC());
2592     return dt2;
2593 }
2594
2595 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2596 {
2597     uint64_t dt2;
2598
2599     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2600     if (get_float_exception_flags(&env->active_fpu.fp_status)
2601         & (float_flag_invalid | float_flag_overflow)) {
2602         dt2 = FP_TO_INT64_OVERFLOW;
2603     }
2604     update_fcr31(env, GETPC());
2605     return dt2;
2606 }
2607
2608 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2609 {
2610     uint32_t wt2;
2611
2612     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2613     if (get_float_exception_flags(&env->active_fpu.fp_status)
2614         & (float_flag_invalid | float_flag_overflow)) {
2615         wt2 = FP_TO_INT32_OVERFLOW;
2616     }
2617     update_fcr31(env, GETPC());
2618     return wt2;
2619 }
2620
2621 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2622 {
2623     uint32_t wt2;
2624
2625     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2626     if (get_float_exception_flags(&env->active_fpu.fp_status)
2627         & (float_flag_invalid | float_flag_overflow)) {
2628         wt2 = FP_TO_INT32_OVERFLOW;
2629     }
2630     update_fcr31(env, GETPC());
2631     return wt2;
2632 }
2633
2634 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2635 {
2636     uint64_t dt2;
2637
2638     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2639     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2640     restore_rounding_mode(env);
2641     if (get_float_exception_flags(&env->active_fpu.fp_status)
2642         & (float_flag_invalid | float_flag_overflow)) {
2643         dt2 = FP_TO_INT64_OVERFLOW;
2644     }
2645     update_fcr31(env, GETPC());
2646     return dt2;
2647 }
2648
2649 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2650 {
2651     uint64_t dt2;
2652
2653     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2654     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2655     restore_rounding_mode(env);
2656     if (get_float_exception_flags(&env->active_fpu.fp_status)
2657         & (float_flag_invalid | float_flag_overflow)) {
2658         dt2 = FP_TO_INT64_OVERFLOW;
2659     }
2660     update_fcr31(env, GETPC());
2661     return dt2;
2662 }
2663
2664 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2665 {
2666     uint32_t wt2;
2667
2668     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2669     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2670     restore_rounding_mode(env);
2671     if (get_float_exception_flags(&env->active_fpu.fp_status)
2672         & (float_flag_invalid | float_flag_overflow)) {
2673         wt2 = FP_TO_INT32_OVERFLOW;
2674     }
2675     update_fcr31(env, GETPC());
2676     return wt2;
2677 }
2678
2679 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2680 {
2681     uint32_t wt2;
2682
2683     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2684     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2685     restore_rounding_mode(env);
2686     if (get_float_exception_flags(&env->active_fpu.fp_status)
2687         & (float_flag_invalid | float_flag_overflow)) {
2688         wt2 = FP_TO_INT32_OVERFLOW;
2689     }
2690     update_fcr31(env, GETPC());
2691     return wt2;
2692 }
2693
2694 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2695 {
2696     uint64_t dt2;
2697
2698     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2699     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2700     restore_rounding_mode(env);
2701     if (get_float_exception_flags(&env->active_fpu.fp_status)
2702         & (float_flag_invalid | float_flag_overflow)) {
2703         dt2 = FP_TO_INT64_OVERFLOW;
2704     }
2705     update_fcr31(env, GETPC());
2706     return dt2;
2707 }
2708
2709 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2710 {
2711     uint64_t dt2;
2712
2713     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2714     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2715     restore_rounding_mode(env);
2716     if (get_float_exception_flags(&env->active_fpu.fp_status)
2717         & (float_flag_invalid | float_flag_overflow)) {
2718         dt2 = FP_TO_INT64_OVERFLOW;
2719     }
2720     update_fcr31(env, GETPC());
2721     return dt2;
2722 }
2723
2724 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2725 {
2726     uint32_t wt2;
2727
2728     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2729     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2730     restore_rounding_mode(env);
2731     if (get_float_exception_flags(&env->active_fpu.fp_status)
2732         & (float_flag_invalid | float_flag_overflow)) {
2733         wt2 = FP_TO_INT32_OVERFLOW;
2734     }
2735     update_fcr31(env, GETPC());
2736     return wt2;
2737 }
2738
2739 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2740 {
2741     uint32_t wt2;
2742
2743     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2744     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2745     restore_rounding_mode(env);
2746     if (get_float_exception_flags(&env->active_fpu.fp_status)
2747         & (float_flag_invalid | float_flag_overflow)) {
2748         wt2 = FP_TO_INT32_OVERFLOW;
2749     }
2750     update_fcr31(env, GETPC());
2751     return wt2;
2752 }
2753
2754 /* unary operations, not modifying fp status  */
2755 #define FLOAT_UNOP(name)                                       \
2756 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2757 {                                                              \
2758     return float64_ ## name(fdt0);                             \
2759 }                                                              \
2760 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2761 {                                                              \
2762     return float32_ ## name(fst0);                             \
2763 }                                                              \
2764 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2765 {                                                              \
2766     uint32_t wt0;                                              \
2767     uint32_t wth0;                                             \
2768                                                                \
2769     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2770     wth0 = float32_ ## name(fdt0 >> 32);                       \
2771     return ((uint64_t)wth0 << 32) | wt0;                       \
2772 }
2773 FLOAT_UNOP(abs)
2774 FLOAT_UNOP(chs)
2775 #undef FLOAT_UNOP
2776
2777 /* MIPS specific unary operations */
2778 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2779 {
2780     uint64_t fdt2;
2781
2782     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2783     update_fcr31(env, GETPC());
2784     return fdt2;
2785 }
2786
2787 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2788 {
2789     uint32_t fst2;
2790
2791     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2792     update_fcr31(env, GETPC());
2793     return fst2;
2794 }
2795
2796 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2797 {
2798     uint64_t fdt2;
2799
2800     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2801     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2802     update_fcr31(env, GETPC());
2803     return fdt2;
2804 }
2805
2806 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2807 {
2808     uint32_t fst2;
2809
2810     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2811     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2812     update_fcr31(env, GETPC());
2813     return fst2;
2814 }
2815
2816 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2817 {
2818     uint64_t fdt2;
2819
2820     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2821     update_fcr31(env, GETPC());
2822     return fdt2;
2823 }
2824
2825 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2826 {
2827     uint32_t fst2;
2828
2829     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2830     update_fcr31(env, GETPC());
2831     return fst2;
2832 }
2833
2834 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2835 {
2836     uint32_t fst2;
2837     uint32_t fsth2;
2838
2839     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2840     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2841     update_fcr31(env, GETPC());
2842     return ((uint64_t)fsth2 << 32) | fst2;
2843 }
2844
2845 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2846 {
2847     uint64_t fdt2;
2848
2849     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2850     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2851     update_fcr31(env, GETPC());
2852     return fdt2;
2853 }
2854
2855 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2856 {
2857     uint32_t fst2;
2858
2859     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2860     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2861     update_fcr31(env, GETPC());
2862     return fst2;
2863 }
2864
2865 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2866 {
2867     uint32_t fst2;
2868     uint32_t fsth2;
2869
2870     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2871     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2872     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2873     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2874     update_fcr31(env, GETPC());
2875     return ((uint64_t)fsth2 << 32) | fst2;
2876 }
2877
2878 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2879
2880 /* binary operations */
2881 #define FLOAT_BINOP(name)                                          \
2882 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2883                                      uint64_t fdt0, uint64_t fdt1) \
2884 {                                                                  \
2885     uint64_t dt2;                                                  \
2886                                                                    \
2887     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2888     update_fcr31(env, GETPC());                                    \
2889     return dt2;                                                    \
2890 }                                                                  \
2891                                                                    \
2892 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2893                                      uint32_t fst0, uint32_t fst1) \
2894 {                                                                  \
2895     uint32_t wt2;                                                  \
2896                                                                    \
2897     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2898     update_fcr31(env, GETPC());                                    \
2899     return wt2;                                                    \
2900 }                                                                  \
2901                                                                    \
2902 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2903                                       uint64_t fdt0,               \
2904                                       uint64_t fdt1)               \
2905 {                                                                  \
2906     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2907     uint32_t fsth0 = fdt0 >> 32;                                   \
2908     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2909     uint32_t fsth1 = fdt1 >> 32;                                   \
2910     uint32_t wt2;                                                  \
2911     uint32_t wth2;                                                 \
2912                                                                    \
2913     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2914     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2915     update_fcr31(env, GETPC());                                    \
2916     return ((uint64_t)wth2 << 32) | wt2;                           \
2917 }
2918
2919 FLOAT_BINOP(add)
2920 FLOAT_BINOP(sub)
2921 FLOAT_BINOP(mul)
2922 FLOAT_BINOP(div)
2923 #undef FLOAT_BINOP
2924
2925 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
2926 {                                                                    \
2927     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
2928     if ((flags) & float_muladd_negate_c) {                           \
2929         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
2930     } else {                                                         \
2931         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
2932     }                                                                \
2933     if ((flags) & float_muladd_negate_result) {                      \
2934         a = prefix##_chs(a);                                         \
2935     }                                                                \
2936 }
2937
2938 /* FMA based operations */
2939 #define FLOAT_FMA(name, type)                                        \
2940 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2941                                      uint64_t fdt0, uint64_t fdt1,   \
2942                                      uint64_t fdt2)                  \
2943 {                                                                    \
2944     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
2945     update_fcr31(env, GETPC());                                      \
2946     return fdt0;                                                     \
2947 }                                                                    \
2948                                                                      \
2949 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
2950                                      uint32_t fst0, uint32_t fst1,   \
2951                                      uint32_t fst2)                  \
2952 {                                                                    \
2953     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2954     update_fcr31(env, GETPC());                                      \
2955     return fst0;                                                     \
2956 }                                                                    \
2957                                                                      \
2958 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
2959                                       uint64_t fdt0, uint64_t fdt1,  \
2960                                       uint64_t fdt2)                 \
2961 {                                                                    \
2962     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
2963     uint32_t fsth0 = fdt0 >> 32;                                     \
2964     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
2965     uint32_t fsth1 = fdt1 >> 32;                                     \
2966     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
2967     uint32_t fsth2 = fdt2 >> 32;                                     \
2968                                                                      \
2969     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2970     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
2971     update_fcr31(env, GETPC());                                      \
2972     return ((uint64_t)fsth0 << 32) | fst0;                           \
2973 }
2974 FLOAT_FMA(madd, 0)
2975 FLOAT_FMA(msub, float_muladd_negate_c)
2976 FLOAT_FMA(nmadd, float_muladd_negate_result)
2977 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2978 #undef FLOAT_FMA
2979
2980 /* MIPS specific binary operations */
2981 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2982 {
2983     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2984     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2985     update_fcr31(env, GETPC());
2986     return fdt2;
2987 }
2988
2989 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2990 {
2991     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2992     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2993     update_fcr31(env, GETPC());
2994     return fst2;
2995 }
2996
2997 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2998 {
2999     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3000     uint32_t fsth0 = fdt0 >> 32;
3001     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3002     uint32_t fsth2 = fdt2 >> 32;
3003
3004     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3005     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3006     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3007     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3008     update_fcr31(env, GETPC());
3009     return ((uint64_t)fsth2 << 32) | fst2;
3010 }
3011
3012 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3013 {
3014     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3015     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3016     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3017     update_fcr31(env, GETPC());
3018     return fdt2;
3019 }
3020
3021 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3022 {
3023     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3024     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3025     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3026     update_fcr31(env, GETPC());
3027     return fst2;
3028 }
3029
3030 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3031 {
3032     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3033     uint32_t fsth0 = fdt0 >> 32;
3034     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3035     uint32_t fsth2 = fdt2 >> 32;
3036
3037     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3038     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3039     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3040     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3041     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3042     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3043     update_fcr31(env, GETPC());
3044     return ((uint64_t)fsth2 << 32) | fst2;
3045 }
3046
3047 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3048 {
3049     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3050     uint32_t fsth0 = fdt0 >> 32;
3051     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3052     uint32_t fsth1 = fdt1 >> 32;
3053     uint32_t fst2;
3054     uint32_t fsth2;
3055
3056     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3057     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3058     update_fcr31(env, GETPC());
3059     return ((uint64_t)fsth2 << 32) | fst2;
3060 }
3061
3062 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3063 {
3064     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3065     uint32_t fsth0 = fdt0 >> 32;
3066     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3067     uint32_t fsth1 = fdt1 >> 32;
3068     uint32_t fst2;
3069     uint32_t fsth2;
3070
3071     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3072     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3073     update_fcr31(env, GETPC());
3074     return ((uint64_t)fsth2 << 32) | fst2;
3075 }
3076
3077 /* compare operations */
3078 #define FOP_COND_D(op, cond)                                   \
3079 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3080                          uint64_t fdt1, int cc)                \
3081 {                                                              \
3082     int c;                                                     \
3083     c = cond;                                                  \
3084     update_fcr31(env, GETPC());                                \
3085     if (c)                                                     \
3086         SET_FP_COND(cc, env->active_fpu);                      \
3087     else                                                       \
3088         CLEAR_FP_COND(cc, env->active_fpu);                    \
3089 }                                                              \
3090 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3091                             uint64_t fdt1, int cc)             \
3092 {                                                              \
3093     int c;                                                     \
3094     fdt0 = float64_abs(fdt0);                                  \
3095     fdt1 = float64_abs(fdt1);                                  \
3096     c = cond;                                                  \
3097     update_fcr31(env, GETPC());                                \
3098     if (c)                                                     \
3099         SET_FP_COND(cc, env->active_fpu);                      \
3100     else                                                       \
3101         CLEAR_FP_COND(cc, env->active_fpu);                    \
3102 }
3103
3104 /* NOTE: the comma operator will make "cond" to eval to false,
3105  * but float64_unordered_quiet() is still called. */
3106 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3107 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3108 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3109 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3110 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3111 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3112 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3113 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3114 /* NOTE: the comma operator will make "cond" to eval to false,
3115  * but float64_unordered() is still called. */
3116 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3117 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3118 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3119 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3120 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3121 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3122 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3123 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3124
3125 #define FOP_COND_S(op, cond)                                   \
3126 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3127                          uint32_t fst1, int cc)                \
3128 {                                                              \
3129     int c;                                                     \
3130     c = cond;                                                  \
3131     update_fcr31(env, GETPC());                                \
3132     if (c)                                                     \
3133         SET_FP_COND(cc, env->active_fpu);                      \
3134     else                                                       \
3135         CLEAR_FP_COND(cc, env->active_fpu);                    \
3136 }                                                              \
3137 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3138                             uint32_t fst1, int cc)             \
3139 {                                                              \
3140     int c;                                                     \
3141     fst0 = float32_abs(fst0);                                  \
3142     fst1 = float32_abs(fst1);                                  \
3143     c = cond;                                                  \
3144     update_fcr31(env, GETPC());                                \
3145     if (c)                                                     \
3146         SET_FP_COND(cc, env->active_fpu);                      \
3147     else                                                       \
3148         CLEAR_FP_COND(cc, env->active_fpu);                    \
3149 }
3150
3151 /* NOTE: the comma operator will make "cond" to eval to false,
3152  * but float32_unordered_quiet() is still called. */
3153 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3154 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3155 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3156 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3157 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3158 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3159 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3160 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3161 /* NOTE: the comma operator will make "cond" to eval to false,
3162  * but float32_unordered() is still called. */
3163 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3164 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3165 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3166 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3167 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3168 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3169 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3170 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3171
3172 #define FOP_COND_PS(op, condl, condh)                           \
3173 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3174                           uint64_t fdt1, int cc)                \
3175 {                                                               \
3176     uint32_t fst0, fsth0, fst1, fsth1;                          \
3177     int ch, cl;                                                 \
3178     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3179     fsth0 = fdt0 >> 32;                                         \
3180     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3181     fsth1 = fdt1 >> 32;                                         \
3182     cl = condl;                                                 \
3183     ch = condh;                                                 \
3184     update_fcr31(env, GETPC());                                 \
3185     if (cl)                                                     \
3186         SET_FP_COND(cc, env->active_fpu);                       \
3187     else                                                        \
3188         CLEAR_FP_COND(cc, env->active_fpu);                     \
3189     if (ch)                                                     \
3190         SET_FP_COND(cc + 1, env->active_fpu);                   \
3191     else                                                        \
3192         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3193 }                                                               \
3194 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3195                              uint64_t fdt1, int cc)             \
3196 {                                                               \
3197     uint32_t fst0, fsth0, fst1, fsth1;                          \
3198     int ch, cl;                                                 \
3199     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3200     fsth0 = float32_abs(fdt0 >> 32);                            \
3201     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3202     fsth1 = float32_abs(fdt1 >> 32);                            \
3203     cl = condl;                                                 \
3204     ch = condh;                                                 \
3205     update_fcr31(env, GETPC());                                 \
3206     if (cl)                                                     \
3207         SET_FP_COND(cc, env->active_fpu);                       \
3208     else                                                        \
3209         CLEAR_FP_COND(cc, env->active_fpu);                     \
3210     if (ch)                                                     \
3211         SET_FP_COND(cc + 1, env->active_fpu);                   \
3212     else                                                        \
3213         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3214 }
3215
3216 /* NOTE: the comma operator will make "cond" to eval to false,
3217  * but float32_unordered_quiet() is still called. */
3218 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3219                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3220 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3221                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3222 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3223                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3224 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3225                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3226 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3227                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3228 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3229                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3230 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3231                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3232 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3233                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3234 /* NOTE: the comma operator will make "cond" to eval to false,
3235  * but float32_unordered() is still called. */
3236 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3237                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3238 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3239                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3240 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3241                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3242 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3243                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3244 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3245                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3246 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3247                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3248 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3249                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3250 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3251                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))