target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 #include "helper.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "exec/softmmu_exec.h"
  27 #endif /* !defined(CONFIG_USER_ONLY) */
  28
  29 #ifndef CONFIG_USER_ONLY
  30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  31 #endif
  32
  33 /*****************************************************************************/
  34 /* Exceptions processing helpers */
  35
  36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  37                                                         uint32_t exception,
  38                                                         int error_code,
  39                                                         uintptr_t pc)
  40 {
  41 #if 1
  42     if (exception < 0x100)
  43         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  44 #endif
  45     env->exception_index = exception;
  46     env->error_code = error_code;
  47
  48     if (pc) {
  49         /* now we have a real cpu fault */
  50         cpu_restore_state(env, pc);
  51     }
  52
  53     cpu_loop_exit(env);
  54 }
  55
  56 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  57                                                     uint32_t exception,
  58                                                     uintptr_t pc)
  59 {
  60     do_raise_exception_err(env, exception, 0, pc);
  61 }
  62
  63 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  64                                 int error_code)
  65 {
  66     do_raise_exception_err(env, exception, error_code, 0);
  67 }
  68
  69 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  70 {
  71     do_raise_exception(env, exception, 0);
  72 }
  73
  74 #if defined(CONFIG_USER_ONLY)
  75 #define HELPER_LD(name, insn, type)                                     \
  76 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  77                              int mem_idx)                               \
  78 {                                                                       \
  79     return (type) insn##_raw(addr);                                     \
  80 }
  81 #else
  82 #define HELPER_LD(name, insn, type)                                     \
  83 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  84                              int mem_idx)                               \
  85 {                                                                       \
  86     switch (mem_idx)                                                    \
  87     {                                                                   \
  88     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  89     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  90     default:                                                            \
  91     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  92     }                                                                   \
  93 }
  94 #endif
  95 HELPER_LD(lbu, ldub, uint8_t)
  96 HELPER_LD(lw, ldl, int32_t)
  97 #ifdef TARGET_MIPS64
  98 HELPER_LD(ld, ldq, int64_t)
  99 #endif
 100 #undef HELPER_LD
 101
 102 #if defined(CONFIG_USER_ONLY)
 103 #define HELPER_ST(name, insn, type)                                     \
 104 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 105                              type val, int mem_idx)                     \
 106 {                                                                       \
 107     insn##_raw(addr, val);                                              \
 108 }
 109 #else
 110 #define HELPER_ST(name, insn, type)                                     \
 111 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 112                              type val, int mem_idx)                     \
 113 {                                                                       \
 114     switch (mem_idx)                                                    \
 115     {                                                                   \
 116     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 117     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 118     default:                                                            \
 119     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 120     }                                                                   \
 121 }
 122 #endif
 123 HELPER_ST(sb, stb, uint8_t)
 124 HELPER_ST(sw, stl, uint32_t)
 125 #ifdef TARGET_MIPS64
 126 HELPER_ST(sd, stq, uint64_t)
 127 #endif
 128 #undef HELPER_ST
 129
 130 target_ulong helper_clo (target_ulong arg1)
 131 {
 132     return clo32(arg1);
 133 }
 134
 135 target_ulong helper_clz (target_ulong arg1)
 136 {
 137     return clz32(arg1);
 138 }
 139
 140 #if defined(TARGET_MIPS64)
 141 target_ulong helper_dclo (target_ulong arg1)
 142 {
 143     return clo64(arg1);
 144 }
 145
 146 target_ulong helper_dclz (target_ulong arg1)
 147 {
 148     return clz64(arg1);
 149 }
 150 #endif /* TARGET_MIPS64 */
 151
 152 /* 64 bits arithmetic for 32 bits hosts */
 153 static inline uint64_t get_HILO(CPUMIPSState *env)
 154 {
 155     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 156 }
 157
 158 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 159 {
 160     target_ulong tmp;
 161     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 162     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 163     return tmp;
 164 }
 165
 166 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 167 {
 168     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 169     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 170     return tmp;
 171 }
 172
 173 /* Multiplication variants of the vr54xx. */
 174 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 175                          target_ulong arg2)
 176 {
 177     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 178                                  (int64_t)(int32_t)arg2));
 179 }
 180
 181 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 182                           target_ulong arg2)
 183 {
 184     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 185                        (uint64_t)(uint32_t)arg2);
 186 }
 187
 188 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 189                          target_ulong arg2)
 190 {
 191     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 192                        (int64_t)(int32_t)arg2);
 193 }
 194
 195 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 196                            target_ulong arg2)
 197 {
 198     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 199                        (int64_t)(int32_t)arg2);
 200 }
 201
 202 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 203                           target_ulong arg2)
 204 {
 205     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 206                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 207 }
 208
 209 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 210                             target_ulong arg2)
 211 {
 212     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 213                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 214 }
 215
 216 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 217                          target_ulong arg2)
 218 {
 219     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 220                        (int64_t)(int32_t)arg2);
 221 }
 222
 223 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 224                            target_ulong arg2)
 225 {
 226     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 227                        (int64_t)(int32_t)arg2);
 228 }
 229
 230 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 231                           target_ulong arg2)
 232 {
 233     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 234                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 235 }
 236
 237 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 238                             target_ulong arg2)
 239 {
 240     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 241                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 242 }
 243
 244 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 245                           target_ulong arg2)
 246 {
 247     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 248 }
 249
 250 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 251                            target_ulong arg2)
 252 {
 253     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 254                        (uint64_t)(uint32_t)arg2);
 255 }
 256
 257 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 258                            target_ulong arg2)
 259 {
 260     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 261                        (int64_t)(int32_t)arg2);
 262 }
 263
 264 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 265                             target_ulong arg2)
 266 {
 267     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 268                        (uint64_t)(uint32_t)arg2);
 269 }
 270
 271 #ifdef TARGET_MIPS64
 272 void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 273 {
 274     muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 275 }
 276
 277 void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 278 {
 279     mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 280 }
 281 #endif
 282
 283 #ifndef CONFIG_USER_ONLY
 284
 285 static inline hwaddr do_translate_address(CPUMIPSState *env,
 286                                                       target_ulong address,
 287                                                       int rw)
 288 {
 289     hwaddr lladdr;
 290
 291     lladdr = cpu_mips_translate_address(env, address, rw);
 292
 293     if (lladdr == -1LL) {
 294         cpu_loop_exit(env);
 295     } else {
 296         return lladdr;
 297     }
 298 }
 299
 300 #define HELPER_LD_ATOMIC(name, insn)                                          \
 301 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 302 {                                                                             \
 303     env->lladdr = do_translate_address(env, arg, 0);                          \
 304     env->llval = do_##insn(env, arg, mem_idx);                                \
 305     return env->llval;                                                        \
 306 }
 307 HELPER_LD_ATOMIC(ll, lw)
 308 #ifdef TARGET_MIPS64
 309 HELPER_LD_ATOMIC(lld, ld)
 310 #endif
 311 #undef HELPER_LD_ATOMIC
 312
 313 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 314 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 315                            target_ulong arg2, int mem_idx)                    \
 316 {                                                                             \
 317     target_long tmp;                                                          \
 318                                                                               \
 319     if (arg2 & almask) {                                                      \
 320         env->CP0_BadVAddr = arg2;                                             \
 321         helper_raise_exception(env, EXCP_AdES);                               \
 322     }                                                                         \
 323     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 324         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 325         if (tmp == env->llval) {                                              \
 326             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 327             return 1;                                                         \
 328         }                                                                     \
 329     }                                                                         \
 330     return 0;                                                                 \
 331 }
 332 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 333 #ifdef TARGET_MIPS64
 334 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 335 #endif
 336 #undef HELPER_ST_ATOMIC
 337 #endif
 338
 339 #ifdef TARGET_WORDS_BIGENDIAN
 340 #define GET_LMASK(v) ((v) & 3)
 341 #define GET_OFFSET(addr, offset) (addr + (offset))
 342 #else
 343 #define GET_LMASK(v) (((v) & 3) ^ 3)
 344 #define GET_OFFSET(addr, offset) (addr - (offset))
 345 #endif
 346
 347 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 348                 int mem_idx)
 349 {
 350     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 351
 352     if (GET_LMASK(arg2) <= 2)
 353         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 354
 355     if (GET_LMASK(arg2) <= 1)
 356         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 357
 358     if (GET_LMASK(arg2) == 0)
 359         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 360 }
 361
 362 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 363                 int mem_idx)
 364 {
 365     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 366
 367     if (GET_LMASK(arg2) >= 1)
 368         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 369
 370     if (GET_LMASK(arg2) >= 2)
 371         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 372
 373     if (GET_LMASK(arg2) == 3)
 374         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 375 }
 376
 377 #if defined(TARGET_MIPS64)
 378 /* "half" load and stores.  We must do the memory access inline,
 379    or fault handling won't work.  */
 380
 381 #ifdef TARGET_WORDS_BIGENDIAN
 382 #define GET_LMASK64(v) ((v) & 7)
 383 #else
 384 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 385 #endif
 386
 387 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 388                 int mem_idx)
 389 {
 390     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 391
 392     if (GET_LMASK64(arg2) <= 6)
 393         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 394
 395     if (GET_LMASK64(arg2) <= 5)
 396         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 397
 398     if (GET_LMASK64(arg2) <= 4)
 399         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 400
 401     if (GET_LMASK64(arg2) <= 3)
 402         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 403
 404     if (GET_LMASK64(arg2) <= 2)
 405         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 406
 407     if (GET_LMASK64(arg2) <= 1)
 408         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 409
 410     if (GET_LMASK64(arg2) <= 0)
 411         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 412 }
 413
 414 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 415                 int mem_idx)
 416 {
 417     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 418
 419     if (GET_LMASK64(arg2) >= 1)
 420         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 421
 422     if (GET_LMASK64(arg2) >= 2)
 423         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 424
 425     if (GET_LMASK64(arg2) >= 3)
 426         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 427
 428     if (GET_LMASK64(arg2) >= 4)
 429         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 430
 431     if (GET_LMASK64(arg2) >= 5)
 432         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 433
 434     if (GET_LMASK64(arg2) >= 6)
 435         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 436
 437     if (GET_LMASK64(arg2) == 7)
 438         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 439 }
 440 #endif /* TARGET_MIPS64 */
 441
 442 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 443
 444 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 445                 uint32_t mem_idx)
 446 {
 447     target_ulong base_reglist = reglist & 0xf;
 448     target_ulong do_r31 = reglist & 0x10;
 449
 450     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 451         target_ulong i;
 452
 453         for (i = 0; i < base_reglist; i++) {
 454             env->active_tc.gpr[multiple_regs[i]] =
 455                 (target_long)do_lw(env, addr, mem_idx);
 456             addr += 4;
 457         }
 458     }
 459
 460     if (do_r31) {
 461         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 462     }
 463 }
 464
 465 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 466                 uint32_t mem_idx)
 467 {
 468     target_ulong base_reglist = reglist & 0xf;
 469     target_ulong do_r31 = reglist & 0x10;
 470
 471     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 472         target_ulong i;
 473
 474         for (i = 0; i < base_reglist; i++) {
 475             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 476             addr += 4;
 477         }
 478     }
 479
 480     if (do_r31) {
 481         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 482     }
 483 }
 484
 485 #if defined(TARGET_MIPS64)
 486 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 487                 uint32_t mem_idx)
 488 {
 489     target_ulong base_reglist = reglist & 0xf;
 490     target_ulong do_r31 = reglist & 0x10;
 491
 492     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 493         target_ulong i;
 494
 495         for (i = 0; i < base_reglist; i++) {
 496             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 497             addr += 8;
 498         }
 499     }
 500
 501     if (do_r31) {
 502         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 503     }
 504 }
 505
 506 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 507                 uint32_t mem_idx)
 508 {
 509     target_ulong base_reglist = reglist & 0xf;
 510     target_ulong do_r31 = reglist & 0x10;
 511
 512     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 513         target_ulong i;
 514
 515         for (i = 0; i < base_reglist; i++) {
 516             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 517             addr += 8;
 518         }
 519     }
 520
 521     if (do_r31) {
 522         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 523     }
 524 }
 525 #endif
 526
 527 #ifndef CONFIG_USER_ONLY
 528 /* SMP helpers.  */
 529 static bool mips_vpe_is_wfi(MIPSCPU *c)
 530 {
 531     CPUMIPSState *env = &c->env;
 532
 533     /* If the VPE is halted but otherwise active, it means it's waiting for
 534        an interrupt.  */
 535     return env->halted && mips_vpe_active(env);
 536 }
 537
 538 static inline void mips_vpe_wake(CPUMIPSState *c)
 539 {
 540     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 541        because there might be other conditions that state that c should
 542        be sleeping.  */
 543     cpu_interrupt(c, CPU_INTERRUPT_WAKE);
 544 }
 545
 546 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 547 {
 548     CPUMIPSState *c = &cpu->env;
 549
 550     /* The VPE was shut off, really go to bed.
 551        Reset any old _WAKE requests.  */
 552     c->halted = 1;
 553     cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
 554 }
 555
 556 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 557 {
 558     CPUMIPSState *c = &cpu->env;
 559
 560     /* FIXME: TC reschedule.  */
 561     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 562         mips_vpe_wake(c);
 563     }
 564 }
 565
 566 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 567 {
 568     CPUMIPSState *c = &cpu->env;
 569
 570     /* FIXME: TC reschedule.  */
 571     if (!mips_vpe_active(c)) {
 572         mips_vpe_sleep(cpu);
 573     }
 574 }
 575
 576 /* tc should point to an int with the value of the global TC index.
 577    This function will transform it into a local index within the
 578    returned CPUMIPSState.
 579
 580    FIXME: This code assumes that all VPEs have the same number of TCs,
 581           which depends on runtime setup. Can probably be fixed by
 582           walking the list of CPUMIPSStates.  */
 583 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 584 {
 585     CPUMIPSState *other;
 586     int vpe_idx, nr_threads = env->nr_threads;
 587     int tc_idx = *tc;
 588
 589     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 590         /* Not allowed to address other CPUs.  */
 591         *tc = env->current_tc;
 592         return env;
 593     }
 594
 595     vpe_idx = tc_idx / nr_threads;
 596     *tc = tc_idx % nr_threads;
 597     other = qemu_get_cpu(vpe_idx);
 598     return other ? other : env;
 599 }
 600
 601 /* The per VPE CP0_Status register shares some fields with the per TC
 602    CP0_TCStatus registers. These fields are wired to the same registers,
 603    so changes to either of them should be reflected on both registers.
 604
 605    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 606
 607    These helper call synchronizes the regs for a given cpu.  */
 608
 609 /* Called for updates to CP0_Status.  */
 610 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 611 {
 612     int32_t tcstatus, *tcst;
 613     uint32_t v = cpu->CP0_Status;
 614     uint32_t cu, mx, asid, ksu;
 615     uint32_t mask = ((1 << CP0TCSt_TCU3)
 616                        | (1 << CP0TCSt_TCU2)
 617                        | (1 << CP0TCSt_TCU1)
 618                        | (1 << CP0TCSt_TCU0)
 619                        | (1 << CP0TCSt_TMX)
 620                        | (3 << CP0TCSt_TKSU)
 621                        | (0xff << CP0TCSt_TASID));
 622
 623     cu = (v >> CP0St_CU0) & 0xf;
 624     mx = (v >> CP0St_MX) & 0x1;
 625     ksu = (v >> CP0St_KSU) & 0x3;
 626     asid = env->CP0_EntryHi & 0xff;
 627
 628     tcstatus = cu << CP0TCSt_TCU0;
 629     tcstatus |= mx << CP0TCSt_TMX;
 630     tcstatus |= ksu << CP0TCSt_TKSU;
 631     tcstatus |= asid;
 632
 633     if (tc == cpu->current_tc) {
 634         tcst = &cpu->active_tc.CP0_TCStatus;
 635     } else {
 636         tcst = &cpu->tcs[tc].CP0_TCStatus;
 637     }
 638
 639     *tcst &= ~mask;
 640     *tcst |= tcstatus;
 641     compute_hflags(cpu);
 642 }
 643
 644 /* Called for updates to CP0_TCStatus.  */
 645 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 646                              target_ulong v)
 647 {
 648     uint32_t status;
 649     uint32_t tcu, tmx, tasid, tksu;
 650     uint32_t mask = ((1 << CP0St_CU3)
 651                        | (1 << CP0St_CU2)
 652                        | (1 << CP0St_CU1)
 653                        | (1 << CP0St_CU0)
 654                        | (1 << CP0St_MX)
 655                        | (3 << CP0St_KSU));
 656
 657     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 658     tmx = (v >> CP0TCSt_TMX) & 0x1;
 659     tasid = v & 0xff;
 660     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 661
 662     status = tcu << CP0St_CU0;
 663     status |= tmx << CP0St_MX;
 664     status |= tksu << CP0St_KSU;
 665
 666     cpu->CP0_Status &= ~mask;
 667     cpu->CP0_Status |= status;
 668
 669     /* Sync the TASID with EntryHi.  */
 670     cpu->CP0_EntryHi &= ~0xff;
 671     cpu->CP0_EntryHi = tasid;
 672
 673     compute_hflags(cpu);
 674 }
 675
 676 /* Called for updates to CP0_EntryHi.  */
 677 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 678 {
 679     int32_t *tcst;
 680     uint32_t asid, v = cpu->CP0_EntryHi;
 681
 682     asid = v & 0xff;
 683
 684     if (tc == cpu->current_tc) {
 685         tcst = &cpu->active_tc.CP0_TCStatus;
 686     } else {
 687         tcst = &cpu->tcs[tc].CP0_TCStatus;
 688     }
 689
 690     *tcst &= ~0xff;
 691     *tcst |= asid;
 692 }
 693
 694 /* CP0 helpers */
 695 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 696 {
 697     return env->mvp->CP0_MVPControl;
 698 }
 699
 700 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 701 {
 702     return env->mvp->CP0_MVPConf0;
 703 }
 704
 705 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 706 {
 707     return env->mvp->CP0_MVPConf1;
 708 }
 709
 710 target_ulong helper_mfc0_random(CPUMIPSState *env)
 711 {
 712     return (int32_t)cpu_mips_get_random(env);
 713 }
 714
 715 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 716 {
 717     return env->active_tc.CP0_TCStatus;
 718 }
 719
 720 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 721 {
 722     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 723     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 724
 725     if (other_tc == other->current_tc)
 726         return other->active_tc.CP0_TCStatus;
 727     else
 728         return other->tcs[other_tc].CP0_TCStatus;
 729 }
 730
 731 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 732 {
 733     return env->active_tc.CP0_TCBind;
 734 }
 735
 736 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 737 {
 738     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 739     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 740
 741     if (other_tc == other->current_tc)
 742         return other->active_tc.CP0_TCBind;
 743     else
 744         return other->tcs[other_tc].CP0_TCBind;
 745 }
 746
 747 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 748 {
 749     return env->active_tc.PC;
 750 }
 751
 752 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 753 {
 754     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 755     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 756
 757     if (other_tc == other->current_tc)
 758         return other->active_tc.PC;
 759     else
 760         return other->tcs[other_tc].PC;
 761 }
 762
 763 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 764 {
 765     return env->active_tc.CP0_TCHalt;
 766 }
 767
 768 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 769 {
 770     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 771     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 772
 773     if (other_tc == other->current_tc)
 774         return other->active_tc.CP0_TCHalt;
 775     else
 776         return other->tcs[other_tc].CP0_TCHalt;
 777 }
 778
 779 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 780 {
 781     return env->active_tc.CP0_TCContext;
 782 }
 783
 784 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 785 {
 786     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 787     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 788
 789     if (other_tc == other->current_tc)
 790         return other->active_tc.CP0_TCContext;
 791     else
 792         return other->tcs[other_tc].CP0_TCContext;
 793 }
 794
 795 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 796 {
 797     return env->active_tc.CP0_TCSchedule;
 798 }
 799
 800 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 801 {
 802     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 803     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 804
 805     if (other_tc == other->current_tc)
 806         return other->active_tc.CP0_TCSchedule;
 807     else
 808         return other->tcs[other_tc].CP0_TCSchedule;
 809 }
 810
 811 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 812 {
 813     return env->active_tc.CP0_TCScheFBack;
 814 }
 815
 816 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 817 {
 818     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 819     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 820
 821     if (other_tc == other->current_tc)
 822         return other->active_tc.CP0_TCScheFBack;
 823     else
 824         return other->tcs[other_tc].CP0_TCScheFBack;
 825 }
 826
 827 target_ulong helper_mfc0_count(CPUMIPSState *env)
 828 {
 829     return (int32_t)cpu_mips_get_count(env);
 830 }
 831
 832 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 833 {
 834     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 835     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 836
 837     return other->CP0_EntryHi;
 838 }
 839
 840 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 841 {
 842     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 843     int32_t tccause;
 844     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 845
 846     if (other_tc == other->current_tc) {
 847         tccause = other->CP0_Cause;
 848     } else {
 849         tccause = other->CP0_Cause;
 850     }
 851
 852     return tccause;
 853 }
 854
 855 target_ulong helper_mftc0_status(CPUMIPSState *env)
 856 {
 857     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 858     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 859
 860     return other->CP0_Status;
 861 }
 862
 863 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 864 {
 865     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 866 }
 867
 868 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 869 {
 870     return (int32_t)env->CP0_WatchLo[sel];
 871 }
 872
 873 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 874 {
 875     return env->CP0_WatchHi[sel];
 876 }
 877
 878 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 879 {
 880     target_ulong t0 = env->CP0_Debug;
 881     if (env->hflags & MIPS_HFLAG_DM)
 882         t0 |= 1 << CP0DB_DM;
 883
 884     return t0;
 885 }
 886
 887 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 888 {
 889     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 890     int32_t tcstatus;
 891     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 892
 893     if (other_tc == other->current_tc)
 894         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 895     else
 896         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 897
 898     /* XXX: Might be wrong, check with EJTAG spec. */
 899     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 900             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 901 }
 902
 903 #if defined(TARGET_MIPS64)
 904 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 905 {
 906     return env->active_tc.PC;
 907 }
 908
 909 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 910 {
 911     return env->active_tc.CP0_TCHalt;
 912 }
 913
 914 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 915 {
 916     return env->active_tc.CP0_TCContext;
 917 }
 918
 919 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 920 {
 921     return env->active_tc.CP0_TCSchedule;
 922 }
 923
 924 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 925 {
 926     return env->active_tc.CP0_TCScheFBack;
 927 }
 928
 929 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 930 {
 931     return env->lladdr >> env->CP0_LLAddr_shift;
 932 }
 933
 934 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 935 {
 936     return env->CP0_WatchLo[sel];
 937 }
 938 #endif /* TARGET_MIPS64 */
 939
 940 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 941 {
 942     int num = 1;
 943     unsigned int tmp = env->tlb->nb_tlb;
 944
 945     do {
 946         tmp >>= 1;
 947         num <<= 1;
 948     } while (tmp);
 949     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 950 }
 951
 952 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 953 {
 954     uint32_t mask = 0;
 955     uint32_t newval;
 956
 957     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 958         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 959                 (1 << CP0MVPCo_EVP);
 960     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 961         mask |= (1 << CP0MVPCo_STLB);
 962     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 963
 964     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 965
 966     env->mvp->CP0_MVPControl = newval;
 967 }
 968
 969 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 970 {
 971     uint32_t mask;
 972     uint32_t newval;
 973
 974     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 975            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 976     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 977
 978     /* Yield scheduler intercept not implemented. */
 979     /* Gating storage scheduler intercept not implemented. */
 980
 981     // TODO: Enable/disable TCs.
 982
 983     env->CP0_VPEControl = newval;
 984 }
 985
 986 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 987 {
 988     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 989     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 990     uint32_t mask;
 991     uint32_t newval;
 992
 993     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 994            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 995     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 996
 997     /* TODO: Enable/disable TCs.  */
 998
 999     other->CP0_VPEControl = newval;
1000 }
1001
1002 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1003 {
1004     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1005     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1006     /* FIXME: Mask away return zero on read bits.  */
1007     return other->CP0_VPEControl;
1008 }
1009
1010 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1011 {
1012     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1013     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1014
1015     return other->CP0_VPEConf0;
1016 }
1017
1018 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1019 {
1020     uint32_t mask = 0;
1021     uint32_t newval;
1022
1023     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1024         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1025             mask |= (0xff << CP0VPEC0_XTC);
1026         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1027     }
1028     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1029
1030     // TODO: TC exclusive handling due to ERL/EXL.
1031
1032     env->CP0_VPEConf0 = newval;
1033 }
1034
1035 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1036 {
1037     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1038     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1039     uint32_t mask = 0;
1040     uint32_t newval;
1041
1042     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1043     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1044
1045     /* TODO: TC exclusive handling due to ERL/EXL.  */
1046     other->CP0_VPEConf0 = newval;
1047 }
1048
1049 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1050 {
1051     uint32_t mask = 0;
1052     uint32_t newval;
1053
1054     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1055         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1056                 (0xff << CP0VPEC1_NCP1);
1057     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1058
1059     /* UDI not implemented. */
1060     /* CP2 not implemented. */
1061
1062     // TODO: Handle FPU (CP1) binding.
1063
1064     env->CP0_VPEConf1 = newval;
1065 }
1066
1067 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1068 {
1069     /* Yield qualifier inputs not implemented. */
1070     env->CP0_YQMask = 0x00000000;
1071 }
1072
1073 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1074 {
1075     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1076 }
1077
1078 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1079 {
1080     /* Large physaddr (PABITS) not implemented */
1081     /* 1k pages not implemented */
1082     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1083 }
1084
1085 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1086 {
1087     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1088     uint32_t newval;
1089
1090     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1091
1092     env->active_tc.CP0_TCStatus = newval;
1093     sync_c0_tcstatus(env, env->current_tc, newval);
1094 }
1095
1096 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1097 {
1098     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1099     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1100
1101     if (other_tc == other->current_tc)
1102         other->active_tc.CP0_TCStatus = arg1;
1103     else
1104         other->tcs[other_tc].CP0_TCStatus = arg1;
1105     sync_c0_tcstatus(other, other_tc, arg1);
1106 }
1107
1108 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1109 {
1110     uint32_t mask = (1 << CP0TCBd_TBE);
1111     uint32_t newval;
1112
1113     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1114         mask |= (1 << CP0TCBd_CurVPE);
1115     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1116     env->active_tc.CP0_TCBind = newval;
1117 }
1118
1119 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1120 {
1121     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1122     uint32_t mask = (1 << CP0TCBd_TBE);
1123     uint32_t newval;
1124     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1125
1126     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1127         mask |= (1 << CP0TCBd_CurVPE);
1128     if (other_tc == other->current_tc) {
1129         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1130         other->active_tc.CP0_TCBind = newval;
1131     } else {
1132         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1133         other->tcs[other_tc].CP0_TCBind = newval;
1134     }
1135 }
1136
1137 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1138 {
1139     env->active_tc.PC = arg1;
1140     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1141     env->lladdr = 0ULL;
1142     /* MIPS16 not implemented. */
1143 }
1144
1145 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1146 {
1147     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1148     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1149
1150     if (other_tc == other->current_tc) {
1151         other->active_tc.PC = arg1;
1152         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1153         other->lladdr = 0ULL;
1154         /* MIPS16 not implemented. */
1155     } else {
1156         other->tcs[other_tc].PC = arg1;
1157         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1158         other->lladdr = 0ULL;
1159         /* MIPS16 not implemented. */
1160     }
1161 }
1162
1163 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1164 {
1165     MIPSCPU *cpu = mips_env_get_cpu(env);
1166
1167     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1168
1169     // TODO: Halt TC / Restart (if allocated+active) TC.
1170     if (env->active_tc.CP0_TCHalt & 1) {
1171         mips_tc_sleep(cpu, env->current_tc);
1172     } else {
1173         mips_tc_wake(cpu, env->current_tc);
1174     }
1175 }
1176
1177 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1178 {
1179     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1180     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1181     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1182
1183     // TODO: Halt TC / Restart (if allocated+active) TC.
1184
1185     if (other_tc == other->current_tc)
1186         other->active_tc.CP0_TCHalt = arg1;
1187     else
1188         other->tcs[other_tc].CP0_TCHalt = arg1;
1189
1190     if (arg1 & 1) {
1191         mips_tc_sleep(other_cpu, other_tc);
1192     } else {
1193         mips_tc_wake(other_cpu, other_tc);
1194     }
1195 }
1196
1197 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1198 {
1199     env->active_tc.CP0_TCContext = arg1;
1200 }
1201
1202 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1203 {
1204     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1205     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1206
1207     if (other_tc == other->current_tc)
1208         other->active_tc.CP0_TCContext = arg1;
1209     else
1210         other->tcs[other_tc].CP0_TCContext = arg1;
1211 }
1212
1213 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1214 {
1215     env->active_tc.CP0_TCSchedule = arg1;
1216 }
1217
1218 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1219 {
1220     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1221     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1222
1223     if (other_tc == other->current_tc)
1224         other->active_tc.CP0_TCSchedule = arg1;
1225     else
1226         other->tcs[other_tc].CP0_TCSchedule = arg1;
1227 }
1228
1229 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1230 {
1231     env->active_tc.CP0_TCScheFBack = arg1;
1232 }
1233
1234 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1235 {
1236     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1237     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1238
1239     if (other_tc == other->current_tc)
1240         other->active_tc.CP0_TCScheFBack = arg1;
1241     else
1242         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1243 }
1244
1245 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1246 {
1247     /* Large physaddr (PABITS) not implemented */
1248     /* 1k pages not implemented */
1249     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1250 }
1251
1252 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1253 {
1254     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1255 }
1256
1257 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1258 {
1259     /* 1k pages not implemented */
1260     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1261 }
1262
1263 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1264 {
1265     /* SmartMIPS not implemented */
1266     /* Large physaddr (PABITS) not implemented */
1267     /* 1k pages not implemented */
1268     env->CP0_PageGrain = 0;
1269 }
1270
1271 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1272 {
1273     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1274 }
1275
1276 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1277 {
1278     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1279 }
1280
1281 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1282 {
1283     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1284 }
1285
1286 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1287 {
1288     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1289 }
1290
1291 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1292 {
1293     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1294 }
1295
1296 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1297 {
1298     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1299 }
1300
1301 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1302 {
1303     env->CP0_HWREna = arg1 & 0x0000000F;
1304 }
1305
1306 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1307 {
1308     cpu_mips_store_count(env, arg1);
1309 }
1310
1311 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1312 {
1313     target_ulong old, val;
1314
1315     /* 1k pages not implemented */
1316     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1317 #if defined(TARGET_MIPS64)
1318     val &= env->SEGMask;
1319 #endif
1320     old = env->CP0_EntryHi;
1321     env->CP0_EntryHi = val;
1322     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1323         sync_c0_entryhi(env, env->current_tc);
1324     }
1325     /* If the ASID changes, flush qemu's TLB.  */
1326     if ((old & 0xFF) != (val & 0xFF))
1327         cpu_mips_tlb_flush(env, 1);
1328 }
1329
1330 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1331 {
1332     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1333     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1334
1335     other->CP0_EntryHi = arg1;
1336     sync_c0_entryhi(other, other_tc);
1337 }
1338
1339 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1340 {
1341     cpu_mips_store_compare(env, arg1);
1342 }
1343
1344 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1345 {
1346     uint32_t val, old;
1347     uint32_t mask = env->CP0_Status_rw_bitmask;
1348
1349     val = arg1 & mask;
1350     old = env->CP0_Status;
1351     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1352     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1353         sync_c0_status(env, env, env->current_tc);
1354     } else {
1355         compute_hflags(env);
1356     }
1357
1358     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1359         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1360                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1361                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1362                 env->CP0_Cause);
1363         switch (env->hflags & MIPS_HFLAG_KSU) {
1364         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1365         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1366         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1367         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1368         }
1369     }
1370 }
1371
1372 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1373 {
1374     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1375     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1376
1377     other->CP0_Status = arg1 & ~0xf1000018;
1378     sync_c0_status(env, other, other_tc);
1379 }
1380
1381 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1382 {
1383     /* vectored interrupts not implemented, no performance counters. */
1384     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1385 }
1386
1387 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1388 {
1389     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1390     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1391 }
1392
1393 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1394 {
1395     uint32_t mask = 0x00C00300;
1396     uint32_t old = cpu->CP0_Cause;
1397     int i;
1398
1399     if (cpu->insn_flags & ISA_MIPS32R2) {
1400         mask |= 1 << CP0Ca_DC;
1401     }
1402
1403     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1404
1405     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1406         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1407             cpu_mips_stop_count(cpu);
1408         } else {
1409             cpu_mips_start_count(cpu);
1410         }
1411     }
1412
1413     /* Set/reset software interrupts */
1414     for (i = 0 ; i < 2 ; i++) {
1415         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1416             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1417         }
1418     }
1419 }
1420
1421 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1422 {
1423     mtc0_cause(env, arg1);
1424 }
1425
1426 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1427 {
1428     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1429     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1430
1431     mtc0_cause(other, arg1);
1432 }
1433
1434 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1435 {
1436     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1437     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1438
1439     return other->CP0_EPC;
1440 }
1441
1442 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1443 {
1444     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1445     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1446
1447     return other->CP0_EBase;
1448 }
1449
1450 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1451 {
1452     /* vectored interrupts not implemented */
1453     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1454 }
1455
1456 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1457 {
1458     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1459     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1460     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1461 }
1462
1463 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1464 {
1465     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1466     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1467
1468     switch (idx) {
1469     case 0: return other->CP0_Config0;
1470     case 1: return other->CP0_Config1;
1471     case 2: return other->CP0_Config2;
1472     case 3: return other->CP0_Config3;
1473     /* 4 and 5 are reserved.  */
1474     case 6: return other->CP0_Config6;
1475     case 7: return other->CP0_Config7;
1476     default:
1477         break;
1478     }
1479     return 0;
1480 }
1481
1482 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1483 {
1484     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1485 }
1486
1487 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1488 {
1489     /* tertiary/secondary caches not implemented */
1490     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1491 }
1492
1493 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1494 {
1495     target_long mask = env->CP0_LLAddr_rw_bitmask;
1496     arg1 = arg1 << env->CP0_LLAddr_shift;
1497     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1498 }
1499
1500 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1501 {
1502     /* Watch exceptions for instructions, data loads, data stores
1503        not implemented. */
1504     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1505 }
1506
1507 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1508 {
1509     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1510     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1511 }
1512
1513 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1514 {
1515     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1516     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1517 }
1518
1519 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1520 {
1521     env->CP0_Framemask = arg1; /* XXX */
1522 }
1523
1524 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1525 {
1526     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1527     if (arg1 & (1 << CP0DB_DM))
1528         env->hflags |= MIPS_HFLAG_DM;
1529     else
1530         env->hflags &= ~MIPS_HFLAG_DM;
1531 }
1532
1533 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1534 {
1535     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1536     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1537     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1538
1539     /* XXX: Might be wrong, check with EJTAG spec. */
1540     if (other_tc == other->current_tc)
1541         other->active_tc.CP0_Debug_tcstatus = val;
1542     else
1543         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1544     other->CP0_Debug = (other->CP0_Debug &
1545                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1546                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1547 }
1548
1549 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1550 {
1551     env->CP0_Performance0 = arg1 & 0x000007ff;
1552 }
1553
1554 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1555 {
1556     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1557 }
1558
1559 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1560 {
1561     env->CP0_DataLo = arg1; /* XXX */
1562 }
1563
1564 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1565 {
1566     env->CP0_TagHi = arg1; /* XXX */
1567 }
1568
1569 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1570 {
1571     env->CP0_DataHi = arg1; /* XXX */
1572 }
1573
1574 /* MIPS MT functions */
1575 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1576 {
1577     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1578     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1579
1580     if (other_tc == other->current_tc)
1581         return other->active_tc.gpr[sel];
1582     else
1583         return other->tcs[other_tc].gpr[sel];
1584 }
1585
1586 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1587 {
1588     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1589     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1590
1591     if (other_tc == other->current_tc)
1592         return other->active_tc.LO[sel];
1593     else
1594         return other->tcs[other_tc].LO[sel];
1595 }
1596
1597 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1598 {
1599     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1600     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1601
1602     if (other_tc == other->current_tc)
1603         return other->active_tc.HI[sel];
1604     else
1605         return other->tcs[other_tc].HI[sel];
1606 }
1607
1608 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1609 {
1610     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1611     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1612
1613     if (other_tc == other->current_tc)
1614         return other->active_tc.ACX[sel];
1615     else
1616         return other->tcs[other_tc].ACX[sel];
1617 }
1618
1619 target_ulong helper_mftdsp(CPUMIPSState *env)
1620 {
1621     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1622     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1623
1624     if (other_tc == other->current_tc)
1625         return other->active_tc.DSPControl;
1626     else
1627         return other->tcs[other_tc].DSPControl;
1628 }
1629
1630 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1631 {
1632     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1633     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1634
1635     if (other_tc == other->current_tc)
1636         other->active_tc.gpr[sel] = arg1;
1637     else
1638         other->tcs[other_tc].gpr[sel] = arg1;
1639 }
1640
1641 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1642 {
1643     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1644     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1645
1646     if (other_tc == other->current_tc)
1647         other->active_tc.LO[sel] = arg1;
1648     else
1649         other->tcs[other_tc].LO[sel] = arg1;
1650 }
1651
1652 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1653 {
1654     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1655     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1656
1657     if (other_tc == other->current_tc)
1658         other->active_tc.HI[sel] = arg1;
1659     else
1660         other->tcs[other_tc].HI[sel] = arg1;
1661 }
1662
1663 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1664 {
1665     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1666     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1667
1668     if (other_tc == other->current_tc)
1669         other->active_tc.ACX[sel] = arg1;
1670     else
1671         other->tcs[other_tc].ACX[sel] = arg1;
1672 }
1673
1674 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1675 {
1676     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1677     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1678
1679     if (other_tc == other->current_tc)
1680         other->active_tc.DSPControl = arg1;
1681     else
1682         other->tcs[other_tc].DSPControl = arg1;
1683 }
1684
1685 /* MIPS MT functions */
1686 target_ulong helper_dmt(void)
1687 {
1688     // TODO
1689      return 0;
1690 }
1691
1692 target_ulong helper_emt(void)
1693 {
1694     // TODO
1695     return 0;
1696 }
1697
1698 target_ulong helper_dvpe(CPUMIPSState *env)
1699 {
1700     CPUMIPSState *other_cpu_env = first_cpu;
1701     target_ulong prev = env->mvp->CP0_MVPControl;
1702
1703     do {
1704         /* Turn off all VPEs except the one executing the dvpe.  */
1705         if (other_cpu_env != env) {
1706             MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1707
1708             other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1709             mips_vpe_sleep(other_cpu);
1710         }
1711         other_cpu_env = other_cpu_env->next_cpu;
1712     } while (other_cpu_env);
1713     return prev;
1714 }
1715
1716 target_ulong helper_evpe(CPUMIPSState *env)
1717 {
1718     CPUMIPSState *other_cpu_env = first_cpu;
1719     target_ulong prev = env->mvp->CP0_MVPControl;
1720
1721     do {
1722         MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1723
1724         if (other_cpu_env != env
1725             /* If the VPE is WFI, don't disturb its sleep.  */
1726             && !mips_vpe_is_wfi(other_cpu)) {
1727             /* Enable the VPE.  */
1728             other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1729             mips_vpe_wake(other_cpu_env); /* And wake it up.  */
1730         }
1731         other_cpu_env = other_cpu_env->next_cpu;
1732     } while (other_cpu_env);
1733     return prev;
1734 }
1735 #endif /* !CONFIG_USER_ONLY */
1736
1737 void helper_fork(target_ulong arg1, target_ulong arg2)
1738 {
1739     // arg1 = rt, arg2 = rs
1740     arg1 = 0;
1741     // TODO: store to TC register
1742 }
1743
1744 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1745 {
1746     target_long arg1 = arg;
1747
1748     if (arg1 < 0) {
1749         /* No scheduling policy implemented. */
1750         if (arg1 != -2) {
1751             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1752                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1753                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1754                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1755                 helper_raise_exception(env, EXCP_THREAD);
1756             }
1757         }
1758     } else if (arg1 == 0) {
1759         if (0 /* TODO: TC underflow */) {
1760             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1761             helper_raise_exception(env, EXCP_THREAD);
1762         } else {
1763             // TODO: Deallocate TC
1764         }
1765     } else if (arg1 > 0) {
1766         /* Yield qualifier inputs not implemented. */
1767         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1768         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1769         helper_raise_exception(env, EXCP_THREAD);
1770     }
1771     return env->CP0_YQMask;
1772 }
1773
1774 #ifndef CONFIG_USER_ONLY
1775 /* TLB management */
1776 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1777 {
1778     /* Flush qemu's TLB and discard all shadowed entries.  */
1779     tlb_flush (env, flush_global);
1780     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1781 }
1782
1783 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1784 {
1785     /* Discard entries from env->tlb[first] onwards.  */
1786     while (env->tlb->tlb_in_use > first) {
1787         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1788     }
1789 }
1790
1791 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1792 {
1793     r4k_tlb_t *tlb;
1794
1795     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1796     tlb = &env->tlb->mmu.r4k.tlb[idx];
1797     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1798 #if defined(TARGET_MIPS64)
1799     tlb->VPN &= env->SEGMask;
1800 #endif
1801     tlb->ASID = env->CP0_EntryHi & 0xFF;
1802     tlb->PageMask = env->CP0_PageMask;
1803     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1804     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1805     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1806     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1807     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1808     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1809     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1810     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1811     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1812 }
1813
1814 void r4k_helper_tlbwi(CPUMIPSState *env)
1815 {
1816     r4k_tlb_t *tlb;
1817     int idx;
1818     target_ulong VPN;
1819     uint8_t ASID;
1820     bool G, V0, D0, V1, D1;
1821
1822     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1823     tlb = &env->tlb->mmu.r4k.tlb[idx];
1824     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1825 #if defined(TARGET_MIPS64)
1826     VPN &= env->SEGMask;
1827 #endif
1828     ASID = env->CP0_EntryHi & 0xff;
1829     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1830     V0 = (env->CP0_EntryLo0 & 2) != 0;
1831     D0 = (env->CP0_EntryLo0 & 4) != 0;
1832     V1 = (env->CP0_EntryLo1 & 2) != 0;
1833     D1 = (env->CP0_EntryLo1 & 4) != 0;
1834
1835     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1836        permissions on the current entry. */
1837     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1838         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1839         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1840         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1841     }
1842
1843     r4k_invalidate_tlb(env, idx, 0);
1844     r4k_fill_tlb(env, idx);
1845 }
1846
1847 void r4k_helper_tlbwr(CPUMIPSState *env)
1848 {
1849     int r = cpu_mips_get_random(env);
1850
1851     r4k_invalidate_tlb(env, r, 1);
1852     r4k_fill_tlb(env, r);
1853 }
1854
1855 void r4k_helper_tlbp(CPUMIPSState *env)
1856 {
1857     r4k_tlb_t *tlb;
1858     target_ulong mask;
1859     target_ulong tag;
1860     target_ulong VPN;
1861     uint8_t ASID;
1862     int i;
1863
1864     ASID = env->CP0_EntryHi & 0xFF;
1865     for (i = 0; i < env->tlb->nb_tlb; i++) {
1866         tlb = &env->tlb->mmu.r4k.tlb[i];
1867         /* 1k pages are not supported. */
1868         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1869         tag = env->CP0_EntryHi & ~mask;
1870         VPN = tlb->VPN & ~mask;
1871 #if defined(TARGET_MIPS64)
1872         tag &= env->SEGMask;
1873 #endif
1874         /* Check ASID, virtual page number & size */
1875         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1876             /* TLB match */
1877             env->CP0_Index = i;
1878             break;
1879         }
1880     }
1881     if (i == env->tlb->nb_tlb) {
1882         /* No match.  Discard any shadow entries, if any of them match.  */
1883         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1884             tlb = &env->tlb->mmu.r4k.tlb[i];
1885             /* 1k pages are not supported. */
1886             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1887             tag = env->CP0_EntryHi & ~mask;
1888             VPN = tlb->VPN & ~mask;
1889 #if defined(TARGET_MIPS64)
1890             tag &= env->SEGMask;
1891 #endif
1892             /* Check ASID, virtual page number & size */
1893             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1894                 r4k_mips_tlb_flush_extra (env, i);
1895                 break;
1896             }
1897         }
1898
1899         env->CP0_Index |= 0x80000000;
1900     }
1901 }
1902
1903 void r4k_helper_tlbr(CPUMIPSState *env)
1904 {
1905     r4k_tlb_t *tlb;
1906     uint8_t ASID;
1907     int idx;
1908
1909     ASID = env->CP0_EntryHi & 0xFF;
1910     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1911     tlb = &env->tlb->mmu.r4k.tlb[idx];
1912
1913     /* If this will change the current ASID, flush qemu's TLB.  */
1914     if (ASID != tlb->ASID)
1915         cpu_mips_tlb_flush (env, 1);
1916
1917     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1918
1919     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1920     env->CP0_PageMask = tlb->PageMask;
1921     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1922                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1923     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1924                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1925 }
1926
1927 void helper_tlbwi(CPUMIPSState *env)
1928 {
1929     env->tlb->helper_tlbwi(env);
1930 }
1931
1932 void helper_tlbwr(CPUMIPSState *env)
1933 {
1934     env->tlb->helper_tlbwr(env);
1935 }
1936
1937 void helper_tlbp(CPUMIPSState *env)
1938 {
1939     env->tlb->helper_tlbp(env);
1940 }
1941
1942 void helper_tlbr(CPUMIPSState *env)
1943 {
1944     env->tlb->helper_tlbr(env);
1945 }
1946
1947 /* Specials */
1948 target_ulong helper_di(CPUMIPSState *env)
1949 {
1950     target_ulong t0 = env->CP0_Status;
1951
1952     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1953     return t0;
1954 }
1955
1956 target_ulong helper_ei(CPUMIPSState *env)
1957 {
1958     target_ulong t0 = env->CP0_Status;
1959
1960     env->CP0_Status = t0 | (1 << CP0St_IE);
1961     return t0;
1962 }
1963
1964 static void debug_pre_eret(CPUMIPSState *env)
1965 {
1966     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1967         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1968                 env->active_tc.PC, env->CP0_EPC);
1969         if (env->CP0_Status & (1 << CP0St_ERL))
1970             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1971         if (env->hflags & MIPS_HFLAG_DM)
1972             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1973         qemu_log("\n");
1974     }
1975 }
1976
1977 static void debug_post_eret(CPUMIPSState *env)
1978 {
1979     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1980         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1981                 env->active_tc.PC, env->CP0_EPC);
1982         if (env->CP0_Status & (1 << CP0St_ERL))
1983             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1984         if (env->hflags & MIPS_HFLAG_DM)
1985             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1986         switch (env->hflags & MIPS_HFLAG_KSU) {
1987         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1988         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1989         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1990         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1991         }
1992     }
1993 }
1994
1995 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
1996 {
1997     env->active_tc.PC = error_pc & ~(target_ulong)1;
1998     if (error_pc & 1) {
1999         env->hflags |= MIPS_HFLAG_M16;
2000     } else {
2001         env->hflags &= ~(MIPS_HFLAG_M16);
2002     }
2003 }
2004
2005 void helper_eret(CPUMIPSState *env)
2006 {
2007     debug_pre_eret(env);
2008     if (env->CP0_Status & (1 << CP0St_ERL)) {
2009         set_pc(env, env->CP0_ErrorEPC);
2010         env->CP0_Status &= ~(1 << CP0St_ERL);
2011     } else {
2012         set_pc(env, env->CP0_EPC);
2013         env->CP0_Status &= ~(1 << CP0St_EXL);
2014     }
2015     compute_hflags(env);
2016     debug_post_eret(env);
2017     env->lladdr = 1;
2018 }
2019
2020 void helper_deret(CPUMIPSState *env)
2021 {
2022     debug_pre_eret(env);
2023     set_pc(env, env->CP0_DEPC);
2024
2025     env->hflags &= MIPS_HFLAG_DM;
2026     compute_hflags(env);
2027     debug_post_eret(env);
2028     env->lladdr = 1;
2029 }
2030 #endif /* !CONFIG_USER_ONLY */
2031
2032 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2033 {
2034     if ((env->hflags & MIPS_HFLAG_CP0) ||
2035         (env->CP0_HWREna & (1 << 0)))
2036         return env->CP0_EBase & 0x3ff;
2037     else
2038         helper_raise_exception(env, EXCP_RI);
2039
2040     return 0;
2041 }
2042
2043 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2044 {
2045     if ((env->hflags & MIPS_HFLAG_CP0) ||
2046         (env->CP0_HWREna & (1 << 1)))
2047         return env->SYNCI_Step;
2048     else
2049         helper_raise_exception(env, EXCP_RI);
2050
2051     return 0;
2052 }
2053
2054 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2055 {
2056     if ((env->hflags & MIPS_HFLAG_CP0) ||
2057         (env->CP0_HWREna & (1 << 2)))
2058         return env->CP0_Count;
2059     else
2060         helper_raise_exception(env, EXCP_RI);
2061
2062     return 0;
2063 }
2064
2065 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2066 {
2067     if ((env->hflags & MIPS_HFLAG_CP0) ||
2068         (env->CP0_HWREna & (1 << 3)))
2069         return env->CCRes;
2070     else
2071         helper_raise_exception(env, EXCP_RI);
2072
2073     return 0;
2074 }
2075
2076 void helper_pmon(CPUMIPSState *env, int function)
2077 {
2078     function /= 2;
2079     switch (function) {
2080     case 2: /* TODO: char inbyte(int waitflag); */
2081         if (env->active_tc.gpr[4] == 0)
2082             env->active_tc.gpr[2] = -1;
2083         /* Fall through */
2084     case 11: /* TODO: char inbyte (void); */
2085         env->active_tc.gpr[2] = -1;
2086         break;
2087     case 3:
2088     case 12:
2089         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2090         break;
2091     case 17:
2092         break;
2093     case 158:
2094         {
2095             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2096             printf("%s", fmt);
2097         }
2098         break;
2099     }
2100 }
2101
2102 void helper_wait(CPUMIPSState *env)
2103 {
2104     env->halted = 1;
2105     cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
2106     helper_raise_exception(env, EXCP_HLT);
2107 }
2108
2109 #if !defined(CONFIG_USER_ONLY)
2110
2111 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2112                                               target_ulong addr, int is_write,
2113                                               int is_user, uintptr_t retaddr);
2114
2115 #define MMUSUFFIX _mmu
2116 #define ALIGNED_ONLY
2117
2118 #define SHIFT 0
2119 #include "exec/softmmu_template.h"
2120
2121 #define SHIFT 1
2122 #include "exec/softmmu_template.h"
2123
2124 #define SHIFT 2
2125 #include "exec/softmmu_template.h"
2126
2127 #define SHIFT 3
2128 #include "exec/softmmu_template.h"
2129
2130 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2131                                 int is_write, int is_user, uintptr_t retaddr)
2132 {
2133     env->CP0_BadVAddr = addr;
2134     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2135 }
2136
2137 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2138               uintptr_t retaddr)
2139 {
2140     int ret;
2141
2142     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2143     if (ret) {
2144         do_raise_exception_err(env, env->exception_index,
2145                                env->error_code, retaddr);
2146     }
2147 }
2148
2149 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
2150                            int is_write, int is_exec, int unused, int size)
2151 {
2152     if (is_exec)
2153         helper_raise_exception(env, EXCP_IBE);
2154     else
2155         helper_raise_exception(env, EXCP_DBE);
2156 }
2157 #endif /* !CONFIG_USER_ONLY */
2158
2159 /* Complex FPU operations which may need stack space. */
2160
2161 #define FLOAT_TWO32 make_float32(1 << 30)
2162 #define FLOAT_TWO64 make_float64(1ULL << 62)
2163 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2164 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2165
2166 /* convert MIPS rounding mode in FCR31 to IEEE library */
2167 static unsigned int ieee_rm[] = {
2168     float_round_nearest_even,
2169     float_round_to_zero,
2170     float_round_up,
2171     float_round_down
2172 };
2173
2174 #define RESTORE_ROUNDING_MODE \
2175     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
2176
2177 #define RESTORE_FLUSH_MODE \
2178     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2179
2180 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2181 {
2182     target_ulong arg1;
2183
2184     switch (reg) {
2185     case 0:
2186         arg1 = (int32_t)env->active_fpu.fcr0;
2187         break;
2188     case 25:
2189         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2190         break;
2191     case 26:
2192         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2193         break;
2194     case 28:
2195         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2196         break;
2197     default:
2198         arg1 = (int32_t)env->active_fpu.fcr31;
2199         break;
2200     }
2201
2202     return arg1;
2203 }
2204
2205 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2206 {
2207     switch(reg) {
2208     case 25:
2209         if (arg1 & 0xffffff00)
2210             return;
2211         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2212                      ((arg1 & 0x1) << 23);
2213         break;
2214     case 26:
2215         if (arg1 & 0x007c0000)
2216             return;
2217         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2218         break;
2219     case 28:
2220         if (arg1 & 0x007c0000)
2221             return;
2222         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2223                      ((arg1 & 0x4) << 22);
2224         break;
2225     case 31:
2226         if (arg1 & 0x007c0000)
2227             return;
2228         env->active_fpu.fcr31 = arg1;
2229         break;
2230     default:
2231         return;
2232     }
2233     /* set rounding mode */
2234     RESTORE_ROUNDING_MODE;
2235     /* set flush-to-zero mode */
2236     RESTORE_FLUSH_MODE;
2237     set_float_exception_flags(0, &env->active_fpu.fp_status);
2238     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2239         do_raise_exception(env, EXCP_FPE, GETPC());
2240 }
2241
2242 static inline int ieee_ex_to_mips(int xcpt)
2243 {
2244     int ret = 0;
2245     if (xcpt) {
2246         if (xcpt & float_flag_invalid) {
2247             ret |= FP_INVALID;
2248         }
2249         if (xcpt & float_flag_overflow) {
2250             ret |= FP_OVERFLOW;
2251         }
2252         if (xcpt & float_flag_underflow) {
2253             ret |= FP_UNDERFLOW;
2254         }
2255         if (xcpt & float_flag_divbyzero) {
2256             ret |= FP_DIV0;
2257         }
2258         if (xcpt & float_flag_inexact) {
2259             ret |= FP_INEXACT;
2260         }
2261     }
2262     return ret;
2263 }
2264
2265 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2266 {
2267     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2268
2269     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2270
2271     if (tmp) {
2272         set_float_exception_flags(0, &env->active_fpu.fp_status);
2273
2274         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2275             do_raise_exception(env, EXCP_FPE, pc);
2276         } else {
2277             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2278         }
2279     }
2280 }
2281
2282 /* Float support.
2283    Single precition routines have a "s" suffix, double precision a
2284    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2285    paired single lower "pl", paired single upper "pu".  */
2286
2287 /* unary operations, modifying fp status  */
2288 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2289 {
2290     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2291     update_fcr31(env, GETPC());
2292     return fdt0;
2293 }
2294
2295 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2296 {
2297     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2298     update_fcr31(env, GETPC());
2299     return fst0;
2300 }
2301
2302 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2303 {
2304     uint64_t fdt2;
2305
2306     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2307     update_fcr31(env, GETPC());
2308     return fdt2;
2309 }
2310
2311 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2312 {
2313     uint64_t fdt2;
2314
2315     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2316     update_fcr31(env, GETPC());
2317     return fdt2;
2318 }
2319
2320 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2321 {
2322     uint64_t fdt2;
2323
2324     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2325     update_fcr31(env, GETPC());
2326     return fdt2;
2327 }
2328
2329 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2330 {
2331     uint64_t dt2;
2332
2333     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2334     if (get_float_exception_flags(&env->active_fpu.fp_status)
2335         & (float_flag_invalid | float_flag_overflow)) {
2336         dt2 = FP_TO_INT64_OVERFLOW;
2337     }
2338     update_fcr31(env, GETPC());
2339     return dt2;
2340 }
2341
2342 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2343 {
2344     uint64_t dt2;
2345
2346     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2347     if (get_float_exception_flags(&env->active_fpu.fp_status)
2348         & (float_flag_invalid | float_flag_overflow)) {
2349         dt2 = FP_TO_INT64_OVERFLOW;
2350     }
2351     update_fcr31(env, GETPC());
2352     return dt2;
2353 }
2354
2355 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2356 {
2357     uint32_t fst2;
2358     uint32_t fsth2;
2359
2360     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2361     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2362     update_fcr31(env, GETPC());
2363     return ((uint64_t)fsth2 << 32) | fst2;
2364 }
2365
2366 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2367 {
2368     uint32_t wt2;
2369     uint32_t wth2;
2370     int excp, excph;
2371
2372     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2373     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2374     if (excp & (float_flag_overflow | float_flag_invalid)) {
2375         wt2 = FP_TO_INT32_OVERFLOW;
2376     }
2377
2378     set_float_exception_flags(0, &env->active_fpu.fp_status);
2379     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2380     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2381     if (excph & (float_flag_overflow | float_flag_invalid)) {
2382         wth2 = FP_TO_INT32_OVERFLOW;
2383     }
2384
2385     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2386     update_fcr31(env, GETPC());
2387
2388     return ((uint64_t)wth2 << 32) | wt2;
2389 }
2390
2391 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2392 {
2393     uint32_t fst2;
2394
2395     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2396     update_fcr31(env, GETPC());
2397     return fst2;
2398 }
2399
2400 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2401 {
2402     uint32_t fst2;
2403
2404     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2405     update_fcr31(env, GETPC());
2406     return fst2;
2407 }
2408
2409 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2410 {
2411     uint32_t fst2;
2412
2413     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2414     update_fcr31(env, GETPC());
2415     return fst2;
2416 }
2417
2418 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2419 {
2420     uint32_t wt2;
2421
2422     wt2 = wt0;
2423     update_fcr31(env, GETPC());
2424     return wt2;
2425 }
2426
2427 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2428 {
2429     uint32_t wt2;
2430
2431     wt2 = wth0;
2432     update_fcr31(env, GETPC());
2433     return wt2;
2434 }
2435
2436 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2437 {
2438     uint32_t wt2;
2439
2440     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2441     update_fcr31(env, GETPC());
2442     if (get_float_exception_flags(&env->active_fpu.fp_status)
2443         & (float_flag_invalid | float_flag_overflow)) {
2444         wt2 = FP_TO_INT32_OVERFLOW;
2445     }
2446     return wt2;
2447 }
2448
2449 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2450 {
2451     uint32_t wt2;
2452
2453     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2454     if (get_float_exception_flags(&env->active_fpu.fp_status)
2455         & (float_flag_invalid | float_flag_overflow)) {
2456         wt2 = FP_TO_INT32_OVERFLOW;
2457     }
2458     update_fcr31(env, GETPC());
2459     return wt2;
2460 }
2461
2462 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2463 {
2464     uint64_t dt2;
2465
2466     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2467     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2468     RESTORE_ROUNDING_MODE;
2469     if (get_float_exception_flags(&env->active_fpu.fp_status)
2470         & (float_flag_invalid | float_flag_overflow)) {
2471         dt2 = FP_TO_INT64_OVERFLOW;
2472     }
2473     update_fcr31(env, GETPC());
2474     return dt2;
2475 }
2476
2477 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2478 {
2479     uint64_t dt2;
2480
2481     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2482     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2483     RESTORE_ROUNDING_MODE;
2484     if (get_float_exception_flags(&env->active_fpu.fp_status)
2485         & (float_flag_invalid | float_flag_overflow)) {
2486         dt2 = FP_TO_INT64_OVERFLOW;
2487     }
2488     update_fcr31(env, GETPC());
2489     return dt2;
2490 }
2491
2492 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2493 {
2494     uint32_t wt2;
2495
2496     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2497     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2498     RESTORE_ROUNDING_MODE;
2499     if (get_float_exception_flags(&env->active_fpu.fp_status)
2500         & (float_flag_invalid | float_flag_overflow)) {
2501         wt2 = FP_TO_INT32_OVERFLOW;
2502     }
2503     update_fcr31(env, GETPC());
2504     return wt2;
2505 }
2506
2507 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2508 {
2509     uint32_t wt2;
2510
2511     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2512     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2513     RESTORE_ROUNDING_MODE;
2514     if (get_float_exception_flags(&env->active_fpu.fp_status)
2515         & (float_flag_invalid | float_flag_overflow)) {
2516         wt2 = FP_TO_INT32_OVERFLOW;
2517     }
2518     update_fcr31(env, GETPC());
2519     return wt2;
2520 }
2521
2522 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2523 {
2524     uint64_t dt2;
2525
2526     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2527     if (get_float_exception_flags(&env->active_fpu.fp_status)
2528         & (float_flag_invalid | float_flag_overflow)) {
2529         dt2 = FP_TO_INT64_OVERFLOW;
2530     }
2531     update_fcr31(env, GETPC());
2532     return dt2;
2533 }
2534
2535 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2536 {
2537     uint64_t dt2;
2538
2539     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2540     if (get_float_exception_flags(&env->active_fpu.fp_status)
2541         & (float_flag_invalid | float_flag_overflow)) {
2542         dt2 = FP_TO_INT64_OVERFLOW;
2543     }
2544     update_fcr31(env, GETPC());
2545     return dt2;
2546 }
2547
2548 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2549 {
2550     uint32_t wt2;
2551
2552     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2553     if (get_float_exception_flags(&env->active_fpu.fp_status)
2554         & (float_flag_invalid | float_flag_overflow)) {
2555         wt2 = FP_TO_INT32_OVERFLOW;
2556     }
2557     update_fcr31(env, GETPC());
2558     return wt2;
2559 }
2560
2561 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2562 {
2563     uint32_t wt2;
2564
2565     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2566     if (get_float_exception_flags(&env->active_fpu.fp_status)
2567         & (float_flag_invalid | float_flag_overflow)) {
2568         wt2 = FP_TO_INT32_OVERFLOW;
2569     }
2570     update_fcr31(env, GETPC());
2571     return wt2;
2572 }
2573
2574 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2575 {
2576     uint64_t dt2;
2577
2578     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2579     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2580     RESTORE_ROUNDING_MODE;
2581     if (get_float_exception_flags(&env->active_fpu.fp_status)
2582         & (float_flag_invalid | float_flag_overflow)) {
2583         dt2 = FP_TO_INT64_OVERFLOW;
2584     }
2585     update_fcr31(env, GETPC());
2586     return dt2;
2587 }
2588
2589 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2590 {
2591     uint64_t dt2;
2592
2593     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2594     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2595     RESTORE_ROUNDING_MODE;
2596     if (get_float_exception_flags(&env->active_fpu.fp_status)
2597         & (float_flag_invalid | float_flag_overflow)) {
2598         dt2 = FP_TO_INT64_OVERFLOW;
2599     }
2600     update_fcr31(env, GETPC());
2601     return dt2;
2602 }
2603
2604 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2605 {
2606     uint32_t wt2;
2607
2608     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2609     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2610     RESTORE_ROUNDING_MODE;
2611     if (get_float_exception_flags(&env->active_fpu.fp_status)
2612         & (float_flag_invalid | float_flag_overflow)) {
2613         wt2 = FP_TO_INT32_OVERFLOW;
2614     }
2615     update_fcr31(env, GETPC());
2616     return wt2;
2617 }
2618
2619 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2620 {
2621     uint32_t wt2;
2622
2623     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2624     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2625     RESTORE_ROUNDING_MODE;
2626     if (get_float_exception_flags(&env->active_fpu.fp_status)
2627         & (float_flag_invalid | float_flag_overflow)) {
2628         wt2 = FP_TO_INT32_OVERFLOW;
2629     }
2630     update_fcr31(env, GETPC());
2631     return wt2;
2632 }
2633
2634 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2635 {
2636     uint64_t dt2;
2637
2638     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2639     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2640     RESTORE_ROUNDING_MODE;
2641     if (get_float_exception_flags(&env->active_fpu.fp_status)
2642         & (float_flag_invalid | float_flag_overflow)) {
2643         dt2 = FP_TO_INT64_OVERFLOW;
2644     }
2645     update_fcr31(env, GETPC());
2646     return dt2;
2647 }
2648
2649 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2650 {
2651     uint64_t dt2;
2652
2653     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2654     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2655     RESTORE_ROUNDING_MODE;
2656     if (get_float_exception_flags(&env->active_fpu.fp_status)
2657         & (float_flag_invalid | float_flag_overflow)) {
2658         dt2 = FP_TO_INT64_OVERFLOW;
2659     }
2660     update_fcr31(env, GETPC());
2661     return dt2;
2662 }
2663
2664 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2665 {
2666     uint32_t wt2;
2667
2668     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2669     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2670     RESTORE_ROUNDING_MODE;
2671     if (get_float_exception_flags(&env->active_fpu.fp_status)
2672         & (float_flag_invalid | float_flag_overflow)) {
2673         wt2 = FP_TO_INT32_OVERFLOW;
2674     }
2675     update_fcr31(env, GETPC());
2676     return wt2;
2677 }
2678
2679 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2680 {
2681     uint32_t wt2;
2682
2683     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2684     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2685     RESTORE_ROUNDING_MODE;
2686     if (get_float_exception_flags(&env->active_fpu.fp_status)
2687         & (float_flag_invalid | float_flag_overflow)) {
2688         wt2 = FP_TO_INT32_OVERFLOW;
2689     }
2690     update_fcr31(env, GETPC());
2691     return wt2;
2692 }
2693
2694 /* unary operations, not modifying fp status  */
2695 #define FLOAT_UNOP(name)                                       \
2696 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2697 {                                                              \
2698     return float64_ ## name(fdt0);                             \
2699 }                                                              \
2700 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2701 {                                                              \
2702     return float32_ ## name(fst0);                             \
2703 }                                                              \
2704 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2705 {                                                              \
2706     uint32_t wt0;                                              \
2707     uint32_t wth0;                                             \
2708                                                                \
2709     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2710     wth0 = float32_ ## name(fdt0 >> 32);                       \
2711     return ((uint64_t)wth0 << 32) | wt0;                       \
2712 }
2713 FLOAT_UNOP(abs)
2714 FLOAT_UNOP(chs)
2715 #undef FLOAT_UNOP
2716
2717 /* MIPS specific unary operations */
2718 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2719 {
2720     uint64_t fdt2;
2721
2722     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2723     update_fcr31(env, GETPC());
2724     return fdt2;
2725 }
2726
2727 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2728 {
2729     uint32_t fst2;
2730
2731     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2732     update_fcr31(env, GETPC());
2733     return fst2;
2734 }
2735
2736 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2737 {
2738     uint64_t fdt2;
2739
2740     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2741     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2742     update_fcr31(env, GETPC());
2743     return fdt2;
2744 }
2745
2746 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2747 {
2748     uint32_t fst2;
2749
2750     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2751     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2752     update_fcr31(env, GETPC());
2753     return fst2;
2754 }
2755
2756 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2757 {
2758     uint64_t fdt2;
2759
2760     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2761     update_fcr31(env, GETPC());
2762     return fdt2;
2763 }
2764
2765 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2766 {
2767     uint32_t fst2;
2768
2769     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2770     update_fcr31(env, GETPC());
2771     return fst2;
2772 }
2773
2774 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2775 {
2776     uint32_t fst2;
2777     uint32_t fsth2;
2778
2779     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2780     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2781     update_fcr31(env, GETPC());
2782     return ((uint64_t)fsth2 << 32) | fst2;
2783 }
2784
2785 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2786 {
2787     uint64_t fdt2;
2788
2789     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2790     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2791     update_fcr31(env, GETPC());
2792     return fdt2;
2793 }
2794
2795 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2796 {
2797     uint32_t fst2;
2798
2799     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2800     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2801     update_fcr31(env, GETPC());
2802     return fst2;
2803 }
2804
2805 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2806 {
2807     uint32_t fst2;
2808     uint32_t fsth2;
2809
2810     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2811     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2812     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2813     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2814     update_fcr31(env, GETPC());
2815     return ((uint64_t)fsth2 << 32) | fst2;
2816 }
2817
2818 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2819
2820 /* binary operations */
2821 #define FLOAT_BINOP(name)                                          \
2822 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2823                                      uint64_t fdt0, uint64_t fdt1) \
2824 {                                                                  \
2825     uint64_t dt2;                                                  \
2826                                                                    \
2827     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2828     update_fcr31(env, GETPC());                                    \
2829     return dt2;                                                    \
2830 }                                                                  \
2831                                                                    \
2832 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2833                                      uint32_t fst0, uint32_t fst1) \
2834 {                                                                  \
2835     uint32_t wt2;                                                  \
2836                                                                    \
2837     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2838     update_fcr31(env, GETPC());                                    \
2839     return wt2;                                                    \
2840 }                                                                  \
2841                                                                    \
2842 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2843                                       uint64_t fdt0,               \
2844                                       uint64_t fdt1)               \
2845 {                                                                  \
2846     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2847     uint32_t fsth0 = fdt0 >> 32;                                   \
2848     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2849     uint32_t fsth1 = fdt1 >> 32;                                   \
2850     uint32_t wt2;                                                  \
2851     uint32_t wth2;                                                 \
2852                                                                    \
2853     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2854     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2855     update_fcr31(env, GETPC());                                    \
2856     return ((uint64_t)wth2 << 32) | wt2;                           \
2857 }
2858
2859 FLOAT_BINOP(add)
2860 FLOAT_BINOP(sub)
2861 FLOAT_BINOP(mul)
2862 FLOAT_BINOP(div)
2863 #undef FLOAT_BINOP
2864
2865 /* FMA based operations */
2866 #define FLOAT_FMA(name, type)                                        \
2867 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2868                                      uint64_t fdt0, uint64_t fdt1,   \
2869                                      uint64_t fdt2)                  \
2870 {                                                                    \
2871     fdt0 = float64_muladd(fdt0, fdt1, fdt2, type,                    \
2872                          &env->active_fpu.fp_status);                \
2873     update_fcr31(env, GETPC());                                      \
2874     return fdt0;                                                     \
2875 }                                                                    \
2876                                                                      \
2877 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
2878                                      uint32_t fst0, uint32_t fst1,   \
2879                                      uint32_t fst2)                  \
2880 {                                                                    \
2881     fst0 = float32_muladd(fst0, fst1, fst2, type,                    \
2882                          &env->active_fpu.fp_status);                \
2883     update_fcr31(env, GETPC());                                      \
2884     return fst0;                                                     \
2885 }                                                                    \
2886                                                                      \
2887 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
2888                                       uint64_t fdt0, uint64_t fdt1,  \
2889                                       uint64_t fdt2)                 \
2890 {                                                                    \
2891     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
2892     uint32_t fsth0 = fdt0 >> 32;                                     \
2893     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
2894     uint32_t fsth1 = fdt1 >> 32;                                     \
2895     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
2896     uint32_t fsth2 = fdt2 >> 32;                                     \
2897                                                                      \
2898     fst0 = float32_muladd(fst0, fst1, fst2, type,                    \
2899                           &env->active_fpu.fp_status);               \
2900     fsth0 = float32_muladd(fsth0, fsth1, fsth2, type,                \
2901                            &env->active_fpu.fp_status);              \
2902     update_fcr31(env, GETPC());                                      \
2903     return ((uint64_t)fsth0 << 32) | fst0;                           \
2904 }
2905 FLOAT_FMA(madd, 0)
2906 FLOAT_FMA(msub, float_muladd_negate_c)
2907 FLOAT_FMA(nmadd, float_muladd_negate_result)
2908 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2909 #undef FLOAT_FMA
2910
2911 /* MIPS specific binary operations */
2912 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2913 {
2914     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2915     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2916     update_fcr31(env, GETPC());
2917     return fdt2;
2918 }
2919
2920 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2921 {
2922     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2923     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2924     update_fcr31(env, GETPC());
2925     return fst2;
2926 }
2927
2928 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2929 {
2930     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2931     uint32_t fsth0 = fdt0 >> 32;
2932     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2933     uint32_t fsth2 = fdt2 >> 32;
2934
2935     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2936     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2937     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2938     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
2939     update_fcr31(env, GETPC());
2940     return ((uint64_t)fsth2 << 32) | fst2;
2941 }
2942
2943 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2944 {
2945     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2946     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
2947     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2948     update_fcr31(env, GETPC());
2949     return fdt2;
2950 }
2951
2952 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2953 {
2954     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2955     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2956     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2957     update_fcr31(env, GETPC());
2958     return fst2;
2959 }
2960
2961 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2962 {
2963     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2964     uint32_t fsth0 = fdt0 >> 32;
2965     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2966     uint32_t fsth2 = fdt2 >> 32;
2967
2968     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2969     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2970     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2971     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
2972     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2973     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2974     update_fcr31(env, GETPC());
2975     return ((uint64_t)fsth2 << 32) | fst2;
2976 }
2977
2978 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
2979 {
2980     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2981     uint32_t fsth0 = fdt0 >> 32;
2982     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2983     uint32_t fsth1 = fdt1 >> 32;
2984     uint32_t fst2;
2985     uint32_t fsth2;
2986
2987     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2988     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2989     update_fcr31(env, GETPC());
2990     return ((uint64_t)fsth2 << 32) | fst2;
2991 }
2992
2993 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
2994 {
2995     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2996     uint32_t fsth0 = fdt0 >> 32;
2997     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2998     uint32_t fsth1 = fdt1 >> 32;
2999     uint32_t fst2;
3000     uint32_t fsth2;
3001
3002     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3003     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3004     update_fcr31(env, GETPC());
3005     return ((uint64_t)fsth2 << 32) | fst2;
3006 }
3007
3008 /* compare operations */
3009 #define FOP_COND_D(op, cond)                                   \
3010 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3011                          uint64_t fdt1, int cc)                \
3012 {                                                              \
3013     int c;                                                     \
3014     c = cond;                                                  \
3015     update_fcr31(env, GETPC());                                \
3016     if (c)                                                     \
3017         SET_FP_COND(cc, env->active_fpu);                      \
3018     else                                                       \
3019         CLEAR_FP_COND(cc, env->active_fpu);                    \
3020 }                                                              \
3021 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3022                             uint64_t fdt1, int cc)             \
3023 {                                                              \
3024     int c;                                                     \
3025     fdt0 = float64_abs(fdt0);                                  \
3026     fdt1 = float64_abs(fdt1);                                  \
3027     c = cond;                                                  \
3028     update_fcr31(env, GETPC());                                \
3029     if (c)                                                     \
3030         SET_FP_COND(cc, env->active_fpu);                      \
3031     else                                                       \
3032         CLEAR_FP_COND(cc, env->active_fpu);                    \
3033 }
3034
3035 /* NOTE: the comma operator will make "cond" to eval to false,
3036  * but float64_unordered_quiet() is still called. */
3037 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3038 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3039 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3040 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3041 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3042 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3043 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3044 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3045 /* NOTE: the comma operator will make "cond" to eval to false,
3046  * but float64_unordered() is still called. */
3047 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3048 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3049 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3050 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3051 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3052 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3053 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3054 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3055
3056 #define FOP_COND_S(op, cond)                                   \
3057 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3058                          uint32_t fst1, int cc)                \
3059 {                                                              \
3060     int c;                                                     \
3061     c = cond;                                                  \
3062     update_fcr31(env, GETPC());                                \
3063     if (c)                                                     \
3064         SET_FP_COND(cc, env->active_fpu);                      \
3065     else                                                       \
3066         CLEAR_FP_COND(cc, env->active_fpu);                    \
3067 }                                                              \
3068 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3069                             uint32_t fst1, int cc)             \
3070 {                                                              \
3071     int c;                                                     \
3072     fst0 = float32_abs(fst0);                                  \
3073     fst1 = float32_abs(fst1);                                  \
3074     c = cond;                                                  \
3075     update_fcr31(env, GETPC());                                \
3076     if (c)                                                     \
3077         SET_FP_COND(cc, env->active_fpu);                      \
3078     else                                                       \
3079         CLEAR_FP_COND(cc, env->active_fpu);                    \
3080 }
3081
3082 /* NOTE: the comma operator will make "cond" to eval to false,
3083  * but float32_unordered_quiet() is still called. */
3084 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3085 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3086 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3087 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3088 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3089 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3090 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3091 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3092 /* NOTE: the comma operator will make "cond" to eval to false,
3093  * but float32_unordered() is still called. */
3094 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3095 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3096 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3097 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3098 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3099 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3100 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3101 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3102
3103 #define FOP_COND_PS(op, condl, condh)                           \
3104 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3105                           uint64_t fdt1, int cc)                \
3106 {                                                               \
3107     uint32_t fst0, fsth0, fst1, fsth1;                          \
3108     int ch, cl;                                                 \
3109     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3110     fsth0 = fdt0 >> 32;                                         \
3111     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3112     fsth1 = fdt1 >> 32;                                         \
3113     cl = condl;                                                 \
3114     ch = condh;                                                 \
3115     update_fcr31(env, GETPC());                                 \
3116     if (cl)                                                     \
3117         SET_FP_COND(cc, env->active_fpu);                       \
3118     else                                                        \
3119         CLEAR_FP_COND(cc, env->active_fpu);                     \
3120     if (ch)                                                     \
3121         SET_FP_COND(cc + 1, env->active_fpu);                   \
3122     else                                                        \
3123         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3124 }                                                               \
3125 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3126                              uint64_t fdt1, int cc)             \
3127 {                                                               \
3128     uint32_t fst0, fsth0, fst1, fsth1;                          \
3129     int ch, cl;                                                 \
3130     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3131     fsth0 = float32_abs(fdt0 >> 32);                            \
3132     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3133     fsth1 = float32_abs(fdt1 >> 32);                            \
3134     cl = condl;                                                 \
3135     ch = condh;                                                 \
3136     update_fcr31(env, GETPC());                                 \
3137     if (cl)                                                     \
3138         SET_FP_COND(cc, env->active_fpu);                       \
3139     else                                                        \
3140         CLEAR_FP_COND(cc, env->active_fpu);                     \
3141     if (ch)                                                     \
3142         SET_FP_COND(cc + 1, env->active_fpu);                   \
3143     else                                                        \
3144         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3145 }
3146
3147 /* NOTE: the comma operator will make "cond" to eval to false,
3148  * but float32_unordered_quiet() is still called. */
3149 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3150                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3151 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3152                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3153 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3154                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3155 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3156                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3157 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3158                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3159 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3160                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3161 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3162                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3163 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3164                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3165 /* NOTE: the comma operator will make "cond" to eval to false,
3166  * but float32_unordered() is still called. */
3167 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3168                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3169 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3170                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3171 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3172                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3173 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3174                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3175 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3176                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3177 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3178                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3179 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3180                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3181 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3182                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))