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Remove remaining uses of T0 in the MIPS target.
[mirror_qemu.git] / target-mips / op_helper.c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdlib.h>
21 #include "exec.h"
22
23 #include "host-utils.h"
24
25 /*****************************************************************************/
26 /* Exceptions processing helpers */
27
28 void do_raise_exception_err (uint32_t exception, int error_code)
29 {
30 #if 1
31 if (logfile && exception < 0x100)
32 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
33 #endif
34 env->exception_index = exception;
35 env->error_code = error_code;
36 cpu_loop_exit();
37 }
38
39 void do_raise_exception (uint32_t exception)
40 {
41 do_raise_exception_err(exception, 0);
42 }
43
44 void do_interrupt_restart (void)
45 {
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
47 !(env->CP0_Status & (1 << CP0St_ERL)) &&
48 !(env->hflags & MIPS_HFLAG_DM) &&
49 (env->CP0_Status & (1 << CP0St_IE)) &&
50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
51 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
52 do_raise_exception(EXCP_EXT_INTERRUPT);
53 }
54 }
55
56 void do_restore_state (void *pc_ptr)
57 {
58 TranslationBlock *tb;
59 unsigned long pc = (unsigned long) pc_ptr;
60
61 tb = tb_find_pc (pc);
62 if (tb) {
63 cpu_restore_state (tb, env, pc, NULL);
64 }
65 }
66
67 target_ulong do_clo (target_ulong t0)
68 {
69 return clo32(t0);
70 }
71
72 target_ulong do_clz (target_ulong t0)
73 {
74 return clz32(t0);
75 }
76
77 #if defined(TARGET_MIPS64)
78 target_ulong do_dclo (target_ulong t0)
79 {
80 return clo64(t0);
81 }
82
83 target_ulong do_dclz (target_ulong t0)
84 {
85 return clz64(t0);
86 }
87 #endif /* TARGET_MIPS64 */
88
89 /* 64 bits arithmetic for 32 bits hosts */
90 static always_inline uint64_t get_HILO (void)
91 {
92 return ((uint64_t)(env->HI[env->current_tc][0]) << 32) | (uint32_t)env->LO[env->current_tc][0];
93 }
94
95 static always_inline void set_HILO (uint64_t HILO)
96 {
97 env->LO[env->current_tc][0] = (int32_t)HILO;
98 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
99 }
100
101 static always_inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
102 {
103 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
104 t0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
105 }
106
107 static always_inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
108 {
109 t0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
110 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
111 }
112
113 #if TARGET_LONG_BITS > HOST_LONG_BITS
114 void do_madd (target_ulong t0, target_ulong t1)
115 {
116 int64_t tmp;
117
118 tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
119 set_HILO((int64_t)get_HILO() + tmp);
120 }
121
122 void do_maddu (target_ulong t0, target_ulong t1)
123 {
124 uint64_t tmp;
125
126 tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
127 set_HILO(get_HILO() + tmp);
128 }
129
130 void do_msub (target_ulong t0, target_ulong t1)
131 {
132 int64_t tmp;
133
134 tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
135 set_HILO((int64_t)get_HILO() - tmp);
136 }
137
138 void do_msubu (target_ulong t0, target_ulong t1)
139 {
140 uint64_t tmp;
141
142 tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
143 set_HILO(get_HILO() - tmp);
144 }
145 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
146
147 /* Multiplication variants of the vr54xx. */
148 target_ulong do_muls (target_ulong t0, target_ulong t1)
149 {
150 set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
151
152 return t0;
153 }
154
155 target_ulong do_mulsu (target_ulong t0, target_ulong t1)
156 {
157 set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
158
159 return t0;
160 }
161
162 target_ulong do_macc (target_ulong t0, target_ulong t1)
163 {
164 set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
165
166 return t0;
167 }
168
169 target_ulong do_macchi (target_ulong t0, target_ulong t1)
170 {
171 set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
172
173 return t0;
174 }
175
176 target_ulong do_maccu (target_ulong t0, target_ulong t1)
177 {
178 set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
179
180 return t0;
181 }
182
183 target_ulong do_macchiu (target_ulong t0, target_ulong t1)
184 {
185 set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
186
187 return t0;
188 }
189
190 target_ulong do_msac (target_ulong t0, target_ulong t1)
191 {
192 set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
193
194 return t0;
195 }
196
197 target_ulong do_msachi (target_ulong t0, target_ulong t1)
198 {
199 set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
200
201 return t0;
202 }
203
204 target_ulong do_msacu (target_ulong t0, target_ulong t1)
205 {
206 set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
207
208 return t0;
209 }
210
211 target_ulong do_msachiu (target_ulong t0, target_ulong t1)
212 {
213 set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
214
215 return t0;
216 }
217
218 target_ulong do_mulhi (target_ulong t0, target_ulong t1)
219 {
220 set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
221
222 return t0;
223 }
224
225 target_ulong do_mulhiu (target_ulong t0, target_ulong t1)
226 {
227 set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
228
229 return t0;
230 }
231
232 target_ulong do_mulshi (target_ulong t0, target_ulong t1)
233 {
234 set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
235
236 return t0;
237 }
238
239 target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
240 {
241 set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
242
243 return t0;
244 }
245
246 #ifdef TARGET_MIPS64
247 void do_dmult (target_ulong t0, target_ulong t1)
248 {
249 muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1);
250 }
251
252 void do_dmultu (target_ulong t0, target_ulong t1)
253 {
254 mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1);
255 }
256 #endif
257
258 #ifdef TARGET_WORDS_BIGENDIAN
259 #define GET_LMASK(v) ((v) & 3)
260 #define GET_OFFSET(addr, offset) (addr + (offset))
261 #else
262 #define GET_LMASK(v) (((v) & 3) ^ 3)
263 #define GET_OFFSET(addr, offset) (addr - (offset))
264 #endif
265
266 target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
267 {
268 target_ulong tmp;
269
270 #ifdef CONFIG_USER_ONLY
271 #define ldfun ldub_raw
272 #else
273 int (*ldfun)(target_ulong);
274
275 switch (mem_idx)
276 {
277 case 0: ldfun = ldub_kernel; break;
278 case 1: ldfun = ldub_super; break;
279 default:
280 case 2: ldfun = ldub_user; break;
281 }
282 #endif
283 tmp = ldfun(t0);
284 t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
285
286 if (GET_LMASK(t0) <= 2) {
287 tmp = ldfun(GET_OFFSET(t0, 1));
288 t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
289 }
290
291 if (GET_LMASK(t0) <= 1) {
292 tmp = ldfun(GET_OFFSET(t0, 2));
293 t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
294 }
295
296 if (GET_LMASK(t0) == 0) {
297 tmp = ldfun(GET_OFFSET(t0, 3));
298 t1 = (t1 & 0xFFFFFF00) | tmp;
299 }
300 return (int32_t)t1;
301 }
302
303 target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
304 {
305 target_ulong tmp;
306
307 #ifdef CONFIG_USER_ONLY
308 #define ldfun ldub_raw
309 #else
310 int (*ldfun)(target_ulong);
311
312 switch (mem_idx)
313 {
314 case 0: ldfun = ldub_kernel; break;
315 case 1: ldfun = ldub_super; break;
316 default:
317 case 2: ldfun = ldub_user; break;
318 }
319 #endif
320 tmp = ldfun(t0);
321 t1 = (t1 & 0xFFFFFF00) | tmp;
322
323 if (GET_LMASK(t0) >= 1) {
324 tmp = ldfun(GET_OFFSET(t0, -1));
325 t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
326 }
327
328 if (GET_LMASK(t0) >= 2) {
329 tmp = ldfun(GET_OFFSET(t0, -2));
330 t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
331 }
332
333 if (GET_LMASK(t0) == 3) {
334 tmp = ldfun(GET_OFFSET(t0, -3));
335 t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
336 }
337 return (int32_t)t1;
338 }
339
340 void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
341 {
342 #ifdef CONFIG_USER_ONLY
343 #define stfun stb_raw
344 #else
345 void (*stfun)(target_ulong, int);
346
347 switch (mem_idx)
348 {
349 case 0: stfun = stb_kernel; break;
350 case 1: stfun = stb_super; break;
351 default:
352 case 2: stfun = stb_user; break;
353 }
354 #endif
355 stfun(t0, (uint8_t)(t1 >> 24));
356
357 if (GET_LMASK(t0) <= 2)
358 stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
359
360 if (GET_LMASK(t0) <= 1)
361 stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
362
363 if (GET_LMASK(t0) == 0)
364 stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
365 }
366
367 void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
368 {
369 #ifdef CONFIG_USER_ONLY
370 #define stfun stb_raw
371 #else
372 void (*stfun)(target_ulong, int);
373
374 switch (mem_idx)
375 {
376 case 0: stfun = stb_kernel; break;
377 case 1: stfun = stb_super; break;
378 default:
379 case 2: stfun = stb_user; break;
380 }
381 #endif
382 stfun(t0, (uint8_t)t1);
383
384 if (GET_LMASK(t0) >= 1)
385 stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
386
387 if (GET_LMASK(t0) >= 2)
388 stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
389
390 if (GET_LMASK(t0) == 3)
391 stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
392 }
393
394 #if defined(TARGET_MIPS64)
395 /* "half" load and stores. We must do the memory access inline,
396 or fault handling won't work. */
397
398 #ifdef TARGET_WORDS_BIGENDIAN
399 #define GET_LMASK64(v) ((v) & 7)
400 #else
401 #define GET_LMASK64(v) (((v) & 7) ^ 7)
402 #endif
403
404 target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
405 {
406 uint64_t tmp;
407
408 #ifdef CONFIG_USER_ONLY
409 #define ldfun ldub_raw
410 #else
411 int (*ldfun)(target_ulong);
412
413 switch (mem_idx)
414 {
415 case 0: ldfun = ldub_kernel; break;
416 case 1: ldfun = ldub_super; break;
417 default:
418 case 2: ldfun = ldub_user; break;
419 }
420 #endif
421 tmp = ldfun(t0);
422 t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
423
424 if (GET_LMASK64(t0) <= 6) {
425 tmp = ldfun(GET_OFFSET(t0, 1));
426 t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
427 }
428
429 if (GET_LMASK64(t0) <= 5) {
430 tmp = ldfun(GET_OFFSET(t0, 2));
431 t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
432 }
433
434 if (GET_LMASK64(t0) <= 4) {
435 tmp = ldfun(GET_OFFSET(t0, 3));
436 t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
437 }
438
439 if (GET_LMASK64(t0) <= 3) {
440 tmp = ldfun(GET_OFFSET(t0, 4));
441 t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
442 }
443
444 if (GET_LMASK64(t0) <= 2) {
445 tmp = ldfun(GET_OFFSET(t0, 5));
446 t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
447 }
448
449 if (GET_LMASK64(t0) <= 1) {
450 tmp = ldfun(GET_OFFSET(t0, 6));
451 t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
452 }
453
454 if (GET_LMASK64(t0) == 0) {
455 tmp = ldfun(GET_OFFSET(t0, 7));
456 t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
457 }
458
459 return t1;
460 }
461
462 target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
463 {
464 uint64_t tmp;
465
466 #ifdef CONFIG_USER_ONLY
467 #define ldfun ldub_raw
468 #else
469 int (*ldfun)(target_ulong);
470
471 switch (mem_idx)
472 {
473 case 0: ldfun = ldub_kernel; break;
474 case 1: ldfun = ldub_super; break;
475 default:
476 case 2: ldfun = ldub_user; break;
477 }
478 #endif
479 tmp = ldfun(t0);
480 t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
481
482 if (GET_LMASK64(t0) >= 1) {
483 tmp = ldfun(GET_OFFSET(t0, -1));
484 t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
485 }
486
487 if (GET_LMASK64(t0) >= 2) {
488 tmp = ldfun(GET_OFFSET(t0, -2));
489 t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
490 }
491
492 if (GET_LMASK64(t0) >= 3) {
493 tmp = ldfun(GET_OFFSET(t0, -3));
494 t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
495 }
496
497 if (GET_LMASK64(t0) >= 4) {
498 tmp = ldfun(GET_OFFSET(t0, -4));
499 t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
500 }
501
502 if (GET_LMASK64(t0) >= 5) {
503 tmp = ldfun(GET_OFFSET(t0, -5));
504 t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
505 }
506
507 if (GET_LMASK64(t0) >= 6) {
508 tmp = ldfun(GET_OFFSET(t0, -6));
509 t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
510 }
511
512 if (GET_LMASK64(t0) == 7) {
513 tmp = ldfun(GET_OFFSET(t0, -7));
514 t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
515 }
516
517 return t1;
518 }
519
520 void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
521 {
522 #ifdef CONFIG_USER_ONLY
523 #define stfun stb_raw
524 #else
525 void (*stfun)(target_ulong, int);
526
527 switch (mem_idx)
528 {
529 case 0: stfun = stb_kernel; break;
530 case 1: stfun = stb_super; break;
531 default:
532 case 2: stfun = stb_user; break;
533 }
534 #endif
535 stfun(t0, (uint8_t)(t1 >> 56));
536
537 if (GET_LMASK64(t0) <= 6)
538 stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
539
540 if (GET_LMASK64(t0) <= 5)
541 stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
542
543 if (GET_LMASK64(t0) <= 4)
544 stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
545
546 if (GET_LMASK64(t0) <= 3)
547 stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
548
549 if (GET_LMASK64(t0) <= 2)
550 stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
551
552 if (GET_LMASK64(t0) <= 1)
553 stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
554
555 if (GET_LMASK64(t0) <= 0)
556 stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
557 }
558
559 void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
560 {
561 #ifdef CONFIG_USER_ONLY
562 #define stfun stb_raw
563 #else
564 void (*stfun)(target_ulong, int);
565
566 switch (mem_idx)
567 {
568 case 0: stfun = stb_kernel; break;
569 case 1: stfun = stb_super; break;
570 default:
571 case 2: stfun = stb_user; break;
572 }
573 #endif
574 stfun(t0, (uint8_t)t1);
575
576 if (GET_LMASK64(t0) >= 1)
577 stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
578
579 if (GET_LMASK64(t0) >= 2)
580 stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
581
582 if (GET_LMASK64(t0) >= 3)
583 stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
584
585 if (GET_LMASK64(t0) >= 4)
586 stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
587
588 if (GET_LMASK64(t0) >= 5)
589 stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
590
591 if (GET_LMASK64(t0) >= 6)
592 stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
593
594 if (GET_LMASK64(t0) == 7)
595 stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
596 }
597 #endif /* TARGET_MIPS64 */
598
599 #ifdef CONFIG_USER_ONLY
600 void do_mfc0_random (void)
601 {
602 cpu_abort(env, "mfc0 random\n");
603 }
604
605 void do_mfc0_count (void)
606 {
607 cpu_abort(env, "mfc0 count\n");
608 }
609
610 void cpu_mips_store_count(CPUState *env, uint32_t value)
611 {
612 cpu_abort(env, "mtc0 count\n");
613 }
614
615 void cpu_mips_store_compare(CPUState *env, uint32_t value)
616 {
617 cpu_abort(env, "mtc0 compare\n");
618 }
619
620 void cpu_mips_start_count(CPUState *env)
621 {
622 cpu_abort(env, "start count\n");
623 }
624
625 void cpu_mips_stop_count(CPUState *env)
626 {
627 cpu_abort(env, "stop count\n");
628 }
629
630 void cpu_mips_update_irq(CPUState *env)
631 {
632 cpu_abort(env, "mtc0 status / mtc0 cause\n");
633 }
634
635 void do_mtc0_status_debug(uint32_t old, uint32_t val)
636 {
637 cpu_abort(env, "mtc0 status debug\n");
638 }
639
640 void do_mtc0_status_irqraise_debug (void)
641 {
642 cpu_abort(env, "mtc0 status irqraise debug\n");
643 }
644
645 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
646 {
647 cpu_abort(env, "mips_tlb_flush\n");
648 }
649
650 #else
651
652 /* CP0 helpers */
653 target_ulong do_mfc0_mvpcontrol (void)
654 {
655 return env->mvp->CP0_MVPControl;
656 }
657
658 target_ulong do_mfc0_mvpconf0 (void)
659 {
660 return env->mvp->CP0_MVPConf0;
661 }
662
663 target_ulong do_mfc0_mvpconf1 (void)
664 {
665 return env->mvp->CP0_MVPConf1;
666 }
667
668 target_ulong do_mfc0_random (void)
669 {
670 return (int32_t)cpu_mips_get_random(env);
671 }
672
673 target_ulong do_mfc0_tcstatus (void)
674 {
675 return env->CP0_TCStatus[env->current_tc];
676 }
677
678 target_ulong do_mftc0_tcstatus(void)
679 {
680 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
681
682 return env->CP0_TCStatus[other_tc];
683 }
684
685 target_ulong do_mfc0_tcbind (void)
686 {
687 return env->CP0_TCBind[env->current_tc];
688 }
689
690 target_ulong do_mftc0_tcbind(void)
691 {
692 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
693
694 return env->CP0_TCBind[other_tc];
695 }
696
697 target_ulong do_mfc0_tcrestart (void)
698 {
699 return env->PC[env->current_tc];
700 }
701
702 target_ulong do_mftc0_tcrestart(void)
703 {
704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
705
706 return env->PC[other_tc];
707 }
708
709 target_ulong do_mfc0_tchalt (void)
710 {
711 return env->CP0_TCHalt[env->current_tc];
712 }
713
714 target_ulong do_mftc0_tchalt(void)
715 {
716 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
717
718 return env->CP0_TCHalt[other_tc];
719 }
720
721 target_ulong do_mfc0_tccontext (void)
722 {
723 return env->CP0_TCContext[env->current_tc];
724 }
725
726 target_ulong do_mftc0_tccontext(void)
727 {
728 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
729
730 return env->CP0_TCContext[other_tc];
731 }
732
733 target_ulong do_mfc0_tcschedule (void)
734 {
735 return env->CP0_TCSchedule[env->current_tc];
736 }
737
738 target_ulong do_mftc0_tcschedule(void)
739 {
740 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
741
742 return env->CP0_TCSchedule[other_tc];
743 }
744
745 target_ulong do_mfc0_tcschefback (void)
746 {
747 return env->CP0_TCScheFBack[env->current_tc];
748 }
749
750 target_ulong do_mftc0_tcschefback(void)
751 {
752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
753
754 return env->CP0_TCScheFBack[other_tc];
755 }
756
757 target_ulong do_mfc0_count (void)
758 {
759 return (int32_t)cpu_mips_get_count(env);
760 }
761
762 target_ulong do_mftc0_entryhi(void)
763 {
764 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
765
766 return (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
767 }
768
769 target_ulong do_mftc0_status(void)
770 {
771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
772 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
773 target_ulong t0;
774
775 t0 = env->CP0_Status & ~0xf1000018;
776 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
777 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
778 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
779
780 return t0;
781 }
782
783 target_ulong do_mfc0_lladdr (void)
784 {
785 return (int32_t)env->CP0_LLAddr >> 4;
786 }
787
788 target_ulong do_mfc0_watchlo (uint32_t sel)
789 {
790 return (int32_t)env->CP0_WatchLo[sel];
791 }
792
793 target_ulong do_mfc0_watchhi (uint32_t sel)
794 {
795 return env->CP0_WatchHi[sel];
796 }
797
798 target_ulong do_mfc0_debug (void)
799 {
800 target_ulong t0 = env->CP0_Debug;
801 if (env->hflags & MIPS_HFLAG_DM)
802 t0 |= 1 << CP0DB_DM;
803
804 return t0;
805 }
806
807 target_ulong do_mftc0_debug(void)
808 {
809 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
810
811 /* XXX: Might be wrong, check with EJTAG spec. */
812 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
813 (env->CP0_Debug_tcstatus[other_tc] &
814 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
815 }
816
817 #if defined(TARGET_MIPS64)
818 target_ulong do_dmfc0_tcrestart (void)
819 {
820 return env->PC[env->current_tc];
821 }
822
823 target_ulong do_dmfc0_tchalt (void)
824 {
825 return env->CP0_TCHalt[env->current_tc];
826 }
827
828 target_ulong do_dmfc0_tccontext (void)
829 {
830 return env->CP0_TCContext[env->current_tc];
831 }
832
833 target_ulong do_dmfc0_tcschedule (void)
834 {
835 return env->CP0_TCSchedule[env->current_tc];
836 }
837
838 target_ulong do_dmfc0_tcschefback (void)
839 {
840 return env->CP0_TCScheFBack[env->current_tc];
841 }
842
843 target_ulong do_dmfc0_lladdr (void)
844 {
845 return env->CP0_LLAddr >> 4;
846 }
847
848 target_ulong do_dmfc0_watchlo (uint32_t sel)
849 {
850 return env->CP0_WatchLo[sel];
851 }
852 #endif /* TARGET_MIPS64 */
853
854 void do_mtc0_index (target_ulong t0)
855 {
856 int num = 1;
857 unsigned int tmp = env->tlb->nb_tlb;
858
859 do {
860 tmp >>= 1;
861 num <<= 1;
862 } while (tmp);
863 env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
864 }
865
866 void do_mtc0_mvpcontrol (target_ulong t0)
867 {
868 uint32_t mask = 0;
869 uint32_t newval;
870
871 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
872 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
873 (1 << CP0MVPCo_EVP);
874 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
875 mask |= (1 << CP0MVPCo_STLB);
876 newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
877
878 // TODO: Enable/disable shared TLB, enable/disable VPEs.
879
880 env->mvp->CP0_MVPControl = newval;
881 }
882
883 void do_mtc0_vpecontrol (target_ulong t0)
884 {
885 uint32_t mask;
886 uint32_t newval;
887
888 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
889 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
890 newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
891
892 /* Yield scheduler intercept not implemented. */
893 /* Gating storage scheduler intercept not implemented. */
894
895 // TODO: Enable/disable TCs.
896
897 env->CP0_VPEControl = newval;
898 }
899
900 void do_mtc0_vpeconf0 (target_ulong t0)
901 {
902 uint32_t mask = 0;
903 uint32_t newval;
904
905 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
906 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
907 mask |= (0xff << CP0VPEC0_XTC);
908 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
909 }
910 newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
911
912 // TODO: TC exclusive handling due to ERL/EXL.
913
914 env->CP0_VPEConf0 = newval;
915 }
916
917 void do_mtc0_vpeconf1 (target_ulong t0)
918 {
919 uint32_t mask = 0;
920 uint32_t newval;
921
922 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
923 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
924 (0xff << CP0VPEC1_NCP1);
925 newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
926
927 /* UDI not implemented. */
928 /* CP2 not implemented. */
929
930 // TODO: Handle FPU (CP1) binding.
931
932 env->CP0_VPEConf1 = newval;
933 }
934
935 void do_mtc0_yqmask (target_ulong t0)
936 {
937 /* Yield qualifier inputs not implemented. */
938 env->CP0_YQMask = 0x00000000;
939 }
940
941 void do_mtc0_vpeopt (target_ulong t0)
942 {
943 env->CP0_VPEOpt = t0 & 0x0000ffff;
944 }
945
946 void do_mtc0_entrylo0 (target_ulong t0)
947 {
948 /* Large physaddr (PABITS) not implemented */
949 /* 1k pages not implemented */
950 env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
951 }
952
953 void do_mtc0_tcstatus (target_ulong t0)
954 {
955 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
956 uint32_t newval;
957
958 newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (t0 & mask);
959
960 // TODO: Sync with CP0_Status.
961
962 env->CP0_TCStatus[env->current_tc] = newval;
963 }
964
965 void do_mttc0_tcstatus (target_ulong t0)
966 {
967 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
968
969 // TODO: Sync with CP0_Status.
970
971 env->CP0_TCStatus[other_tc] = t0;
972 }
973
974 void do_mtc0_tcbind (target_ulong t0)
975 {
976 uint32_t mask = (1 << CP0TCBd_TBE);
977 uint32_t newval;
978
979 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
980 mask |= (1 << CP0TCBd_CurVPE);
981 newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (t0 & mask);
982 env->CP0_TCBind[env->current_tc] = newval;
983 }
984
985 void do_mttc0_tcbind (target_ulong t0)
986 {
987 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
988 uint32_t mask = (1 << CP0TCBd_TBE);
989 uint32_t newval;
990
991 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
992 mask |= (1 << CP0TCBd_CurVPE);
993 newval = (env->CP0_TCBind[other_tc] & ~mask) | (t0 & mask);
994 env->CP0_TCBind[other_tc] = newval;
995 }
996
997 void do_mtc0_tcrestart (target_ulong t0)
998 {
999 env->PC[env->current_tc] = t0;
1000 env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
1001 env->CP0_LLAddr = 0ULL;
1002 /* MIPS16 not implemented. */
1003 }
1004
1005 void do_mttc0_tcrestart (target_ulong t0)
1006 {
1007 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1008
1009 env->PC[other_tc] = t0;
1010 env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
1011 env->CP0_LLAddr = 0ULL;
1012 /* MIPS16 not implemented. */
1013 }
1014
1015 void do_mtc0_tchalt (target_ulong t0)
1016 {
1017 env->CP0_TCHalt[env->current_tc] = t0 & 0x1;
1018
1019 // TODO: Halt TC / Restart (if allocated+active) TC.
1020 }
1021
1022 void do_mttc0_tchalt (target_ulong t0)
1023 {
1024 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1025
1026 // TODO: Halt TC / Restart (if allocated+active) TC.
1027
1028 env->CP0_TCHalt[other_tc] = t0;
1029 }
1030
1031 void do_mtc0_tccontext (target_ulong t0)
1032 {
1033 env->CP0_TCContext[env->current_tc] = t0;
1034 }
1035
1036 void do_mttc0_tccontext (target_ulong t0)
1037 {
1038 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1039
1040 env->CP0_TCContext[other_tc] = t0;
1041 }
1042
1043 void do_mtc0_tcschedule (target_ulong t0)
1044 {
1045 env->CP0_TCSchedule[env->current_tc] = t0;
1046 }
1047
1048 void do_mttc0_tcschedule (target_ulong t0)
1049 {
1050 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1051
1052 env->CP0_TCSchedule[other_tc] = t0;
1053 }
1054
1055 void do_mtc0_tcschefback (target_ulong t0)
1056 {
1057 env->CP0_TCScheFBack[env->current_tc] = t0;
1058 }
1059
1060 void do_mttc0_tcschefback (target_ulong t0)
1061 {
1062 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1063
1064 env->CP0_TCScheFBack[other_tc] = t0;
1065 }
1066
1067 void do_mtc0_entrylo1 (target_ulong t0)
1068 {
1069 /* Large physaddr (PABITS) not implemented */
1070 /* 1k pages not implemented */
1071 env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
1072 }
1073
1074 void do_mtc0_context (target_ulong t0)
1075 {
1076 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
1077 }
1078
1079 void do_mtc0_pagemask (target_ulong t0)
1080 {
1081 /* 1k pages not implemented */
1082 env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1083 }
1084
1085 void do_mtc0_pagegrain (target_ulong t0)
1086 {
1087 /* SmartMIPS not implemented */
1088 /* Large physaddr (PABITS) not implemented */
1089 /* 1k pages not implemented */
1090 env->CP0_PageGrain = 0;
1091 }
1092
1093 void do_mtc0_wired (target_ulong t0)
1094 {
1095 env->CP0_Wired = t0 % env->tlb->nb_tlb;
1096 }
1097
1098 void do_mtc0_srsconf0 (target_ulong t0)
1099 {
1100 env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
1101 }
1102
1103 void do_mtc0_srsconf1 (target_ulong t0)
1104 {
1105 env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
1106 }
1107
1108 void do_mtc0_srsconf2 (target_ulong t0)
1109 {
1110 env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
1111 }
1112
1113 void do_mtc0_srsconf3 (target_ulong t0)
1114 {
1115 env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
1116 }
1117
1118 void do_mtc0_srsconf4 (target_ulong t0)
1119 {
1120 env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
1121 }
1122
1123 void do_mtc0_hwrena (target_ulong t0)
1124 {
1125 env->CP0_HWREna = t0 & 0x0000000F;
1126 }
1127
1128 void do_mtc0_count (target_ulong t0)
1129 {
1130 cpu_mips_store_count(env, t0);
1131 }
1132
1133 void do_mtc0_entryhi (target_ulong t0)
1134 {
1135 target_ulong old, val;
1136
1137 /* 1k pages not implemented */
1138 val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1139 #if defined(TARGET_MIPS64)
1140 val &= env->SEGMask;
1141 #endif
1142 old = env->CP0_EntryHi;
1143 env->CP0_EntryHi = val;
1144 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1145 uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
1146 env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
1147 }
1148 /* If the ASID changes, flush qemu's TLB. */
1149 if ((old & 0xFF) != (val & 0xFF))
1150 cpu_mips_tlb_flush(env, 1);
1151 }
1152
1153 void do_mttc0_entryhi(target_ulong t0)
1154 {
1155 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1156
1157 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
1158 env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (t0 & 0xff);
1159 }
1160
1161 void do_mtc0_compare (target_ulong t0)
1162 {
1163 cpu_mips_store_compare(env, t0);
1164 }
1165
1166 void do_mtc0_status (target_ulong t0)
1167 {
1168 uint32_t val, old;
1169 uint32_t mask = env->CP0_Status_rw_bitmask;
1170
1171 val = t0 & mask;
1172 old = env->CP0_Status;
1173 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1174 compute_hflags(env);
1175 if (loglevel & CPU_LOG_EXEC)
1176 do_mtc0_status_debug(old, val);
1177 cpu_mips_update_irq(env);
1178 }
1179
1180 void do_mttc0_status(target_ulong t0)
1181 {
1182 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1183 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
1184
1185 env->CP0_Status = t0 & ~0xf1000018;
1186 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
1187 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1188 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1189 env->CP0_TCStatus[other_tc] = tcstatus;
1190 }
1191
1192 void do_mtc0_intctl (target_ulong t0)
1193 {
1194 /* vectored interrupts not implemented, no performance counters. */
1195 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
1196 }
1197
1198 void do_mtc0_srsctl (target_ulong t0)
1199 {
1200 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1201 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
1202 }
1203
1204 void do_mtc0_cause (target_ulong t0)
1205 {
1206 uint32_t mask = 0x00C00300;
1207 uint32_t old = env->CP0_Cause;
1208
1209 if (env->insn_flags & ISA_MIPS32R2)
1210 mask |= 1 << CP0Ca_DC;
1211
1212 env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
1213
1214 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1215 if (env->CP0_Cause & (1 << CP0Ca_DC))
1216 cpu_mips_stop_count(env);
1217 else
1218 cpu_mips_start_count(env);
1219 }
1220
1221 /* Handle the software interrupt as an hardware one, as they
1222 are very similar */
1223 if (t0 & CP0Ca_IP_mask) {
1224 cpu_mips_update_irq(env);
1225 }
1226 }
1227
1228 void do_mtc0_ebase (target_ulong t0)
1229 {
1230 /* vectored interrupts not implemented */
1231 /* Multi-CPU not implemented */
1232 env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
1233 }
1234
1235 void do_mtc0_config0 (target_ulong t0)
1236 {
1237 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
1238 }
1239
1240 void do_mtc0_config2 (target_ulong t0)
1241 {
1242 /* tertiary/secondary caches not implemented */
1243 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1244 }
1245
1246 void do_mtc0_watchlo (target_ulong t0, uint32_t sel)
1247 {
1248 /* Watch exceptions for instructions, data loads, data stores
1249 not implemented. */
1250 env->CP0_WatchLo[sel] = (t0 & ~0x7);
1251 }
1252
1253 void do_mtc0_watchhi (target_ulong t0, uint32_t sel)
1254 {
1255 env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
1256 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
1257 }
1258
1259 void do_mtc0_xcontext (target_ulong t0)
1260 {
1261 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1262 env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
1263 }
1264
1265 void do_mtc0_framemask (target_ulong t0)
1266 {
1267 env->CP0_Framemask = t0; /* XXX */
1268 }
1269
1270 void do_mtc0_debug (target_ulong t0)
1271 {
1272 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
1273 if (t0 & (1 << CP0DB_DM))
1274 env->hflags |= MIPS_HFLAG_DM;
1275 else
1276 env->hflags &= ~MIPS_HFLAG_DM;
1277 }
1278
1279 void do_mttc0_debug(target_ulong t0)
1280 {
1281 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1282
1283 /* XXX: Might be wrong, check with EJTAG spec. */
1284 env->CP0_Debug_tcstatus[other_tc] = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1285 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1286 (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1287 }
1288
1289 void do_mtc0_performance0 (target_ulong t0)
1290 {
1291 env->CP0_Performance0 = t0 & 0x000007ff;
1292 }
1293
1294 void do_mtc0_taglo (target_ulong t0)
1295 {
1296 env->CP0_TagLo = t0 & 0xFFFFFCF6;
1297 }
1298
1299 void do_mtc0_datalo (target_ulong t0)
1300 {
1301 env->CP0_DataLo = t0; /* XXX */
1302 }
1303
1304 void do_mtc0_taghi (target_ulong t0)
1305 {
1306 env->CP0_TagHi = t0; /* XXX */
1307 }
1308
1309 void do_mtc0_datahi (target_ulong t0)
1310 {
1311 env->CP0_DataHi = t0; /* XXX */
1312 }
1313
1314 void do_mtc0_status_debug(uint32_t old, uint32_t val)
1315 {
1316 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
1317 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1318 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1319 env->CP0_Cause);
1320 switch (env->hflags & MIPS_HFLAG_KSU) {
1321 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
1322 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
1323 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
1324 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1325 }
1326 }
1327
1328 void do_mtc0_status_irqraise_debug(void)
1329 {
1330 fprintf(logfile, "Raise pending IRQs\n");
1331 }
1332 #endif /* !CONFIG_USER_ONLY */
1333
1334 /* MIPS MT functions */
1335 target_ulong do_mftgpr(target_ulong t0, uint32_t sel)
1336 {
1337 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1338
1339 return env->gpr[other_tc][sel];
1340 }
1341
1342 target_ulong do_mftlo(target_ulong t0, uint32_t sel)
1343 {
1344 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1345
1346 return env->LO[other_tc][sel];
1347 }
1348
1349 target_ulong do_mfthi(target_ulong t0, uint32_t sel)
1350 {
1351 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1352
1353 return env->HI[other_tc][sel];
1354 }
1355
1356 target_ulong do_mftacx(target_ulong t0, uint32_t sel)
1357 {
1358 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1359
1360 return env->ACX[other_tc][sel];
1361 }
1362
1363 target_ulong do_mftdsp(target_ulong t0)
1364 {
1365 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1366
1367 return env->DSPControl[other_tc];
1368 }
1369
1370 void do_mttgpr(target_ulong t0, uint32_t sel)
1371 {
1372 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1373
1374 env->gpr[other_tc][sel] = t0;
1375 }
1376
1377 void do_mttlo(target_ulong t0, uint32_t sel)
1378 {
1379 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1380
1381 env->LO[other_tc][sel] = t0;
1382 }
1383
1384 void do_mtthi(target_ulong t0, uint32_t sel)
1385 {
1386 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1387
1388 env->HI[other_tc][sel] = t0;
1389 }
1390
1391 void do_mttacx(target_ulong t0, uint32_t sel)
1392 {
1393 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1394
1395 env->ACX[other_tc][sel] = t0;
1396 }
1397
1398 void do_mttdsp(target_ulong t0)
1399 {
1400 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1401
1402 env->DSPControl[other_tc] = t0;
1403 }
1404
1405 /* MIPS MT functions */
1406 target_ulong do_dmt(target_ulong t0)
1407 {
1408 // TODO
1409 t0 = 0;
1410 // rt = t0
1411
1412 return t0;
1413 }
1414
1415 target_ulong do_emt(target_ulong t0)
1416 {
1417 // TODO
1418 t0 = 0;
1419 // rt = t0
1420
1421 return t0;
1422 }
1423
1424 target_ulong do_dvpe(target_ulong t0)
1425 {
1426 // TODO
1427 t0 = 0;
1428 // rt = t0
1429
1430 return t0;
1431 }
1432
1433 target_ulong do_evpe(target_ulong t0)
1434 {
1435 // TODO
1436 t0 = 0;
1437 // rt = t0
1438
1439 return t0;
1440 }
1441
1442 void do_fork(target_ulong t0, target_ulong t1)
1443 {
1444 // t0 = rt, t1 = rs
1445 t0 = 0;
1446 // TODO: store to TC register
1447 }
1448
1449 target_ulong do_yield(target_ulong t0)
1450 {
1451 if (t0 < 0) {
1452 /* No scheduling policy implemented. */
1453 if (t0 != -2) {
1454 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1455 env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
1456 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1457 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1458 do_raise_exception(EXCP_THREAD);
1459 }
1460 }
1461 } else if (t0 == 0) {
1462 if (0 /* TODO: TC underflow */) {
1463 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1464 do_raise_exception(EXCP_THREAD);
1465 } else {
1466 // TODO: Deallocate TC
1467 }
1468 } else if (t0 > 0) {
1469 /* Yield qualifier inputs not implemented. */
1470 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1471 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1472 do_raise_exception(EXCP_THREAD);
1473 }
1474 return env->CP0_YQMask;
1475 }
1476
1477 /* CP1 functions */
1478 void fpu_handle_exception(void)
1479 {
1480 #ifdef CONFIG_SOFTFLOAT
1481 int flags = get_float_exception_flags(&env->fpu->fp_status);
1482 unsigned int cpuflags = 0, enable, cause = 0;
1483
1484 enable = GET_FP_ENABLE(env->fpu->fcr31);
1485
1486 /* determine current flags */
1487 if (flags & float_flag_invalid) {
1488 cpuflags |= FP_INVALID;
1489 cause |= FP_INVALID & enable;
1490 }
1491 if (flags & float_flag_divbyzero) {
1492 cpuflags |= FP_DIV0;
1493 cause |= FP_DIV0 & enable;
1494 }
1495 if (flags & float_flag_overflow) {
1496 cpuflags |= FP_OVERFLOW;
1497 cause |= FP_OVERFLOW & enable;
1498 }
1499 if (flags & float_flag_underflow) {
1500 cpuflags |= FP_UNDERFLOW;
1501 cause |= FP_UNDERFLOW & enable;
1502 }
1503 if (flags & float_flag_inexact) {
1504 cpuflags |= FP_INEXACT;
1505 cause |= FP_INEXACT & enable;
1506 }
1507 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
1508 SET_FP_CAUSE(env->fpu->fcr31, cause);
1509 #else
1510 SET_FP_FLAGS(env->fpu->fcr31, 0);
1511 SET_FP_CAUSE(env->fpu->fcr31, 0);
1512 #endif
1513 }
1514
1515 #ifndef CONFIG_USER_ONLY
1516 /* TLB management */
1517 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1518 {
1519 /* Flush qemu's TLB and discard all shadowed entries. */
1520 tlb_flush (env, flush_global);
1521 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1522 }
1523
1524 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
1525 {
1526 /* Discard entries from env->tlb[first] onwards. */
1527 while (env->tlb->tlb_in_use > first) {
1528 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1529 }
1530 }
1531
1532 static void r4k_fill_tlb (int idx)
1533 {
1534 r4k_tlb_t *tlb;
1535
1536 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1537 tlb = &env->tlb->mmu.r4k.tlb[idx];
1538 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1539 #if defined(TARGET_MIPS64)
1540 tlb->VPN &= env->SEGMask;
1541 #endif
1542 tlb->ASID = env->CP0_EntryHi & 0xFF;
1543 tlb->PageMask = env->CP0_PageMask;
1544 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1545 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1546 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1547 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1548 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1549 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1550 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1551 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1552 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1553 }
1554
1555 void r4k_do_tlbwi (void)
1556 {
1557 /* Discard cached TLB entries. We could avoid doing this if the
1558 tlbwi is just upgrading access permissions on the current entry;
1559 that might be a further win. */
1560 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
1561
1562 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
1563 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
1564 }
1565
1566 void r4k_do_tlbwr (void)
1567 {
1568 int r = cpu_mips_get_random(env);
1569
1570 r4k_invalidate_tlb(env, r, 1);
1571 r4k_fill_tlb(r);
1572 }
1573
1574 void r4k_do_tlbp (void)
1575 {
1576 r4k_tlb_t *tlb;
1577 target_ulong mask;
1578 target_ulong tag;
1579 target_ulong VPN;
1580 uint8_t ASID;
1581 int i;
1582
1583 ASID = env->CP0_EntryHi & 0xFF;
1584 for (i = 0; i < env->tlb->nb_tlb; i++) {
1585 tlb = &env->tlb->mmu.r4k.tlb[i];
1586 /* 1k pages are not supported. */
1587 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1588 tag = env->CP0_EntryHi & ~mask;
1589 VPN = tlb->VPN & ~mask;
1590 /* Check ASID, virtual page number & size */
1591 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1592 /* TLB match */
1593 env->CP0_Index = i;
1594 break;
1595 }
1596 }
1597 if (i == env->tlb->nb_tlb) {
1598 /* No match. Discard any shadow entries, if any of them match. */
1599 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1600 tlb = &env->tlb->mmu.r4k.tlb[i];
1601 /* 1k pages are not supported. */
1602 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1603 tag = env->CP0_EntryHi & ~mask;
1604 VPN = tlb->VPN & ~mask;
1605 /* Check ASID, virtual page number & size */
1606 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1607 r4k_mips_tlb_flush_extra (env, i);
1608 break;
1609 }
1610 }
1611
1612 env->CP0_Index |= 0x80000000;
1613 }
1614 }
1615
1616 void r4k_do_tlbr (void)
1617 {
1618 r4k_tlb_t *tlb;
1619 uint8_t ASID;
1620
1621 ASID = env->CP0_EntryHi & 0xFF;
1622 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
1623
1624 /* If this will change the current ASID, flush qemu's TLB. */
1625 if (ASID != tlb->ASID)
1626 cpu_mips_tlb_flush (env, 1);
1627
1628 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1629
1630 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1631 env->CP0_PageMask = tlb->PageMask;
1632 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1633 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1634 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1635 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1636 }
1637
1638 #endif /* !CONFIG_USER_ONLY */
1639
1640 /* Specials */
1641 target_ulong do_di (target_ulong t0)
1642 {
1643 t0 = env->CP0_Status;
1644 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1645 cpu_mips_update_irq(env);
1646
1647 return t0;
1648 }
1649
1650 target_ulong do_ei (target_ulong t0)
1651 {
1652 t0 = env->CP0_Status;
1653 env->CP0_Status = t0 | (1 << CP0St_IE);
1654 cpu_mips_update_irq(env);
1655
1656 return t0;
1657 }
1658
1659 void debug_pre_eret (void)
1660 {
1661 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1662 env->PC[env->current_tc], env->CP0_EPC);
1663 if (env->CP0_Status & (1 << CP0St_ERL))
1664 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1665 if (env->hflags & MIPS_HFLAG_DM)
1666 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1667 fputs("\n", logfile);
1668 }
1669
1670 void debug_post_eret (void)
1671 {
1672 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1673 env->PC[env->current_tc], env->CP0_EPC);
1674 if (env->CP0_Status & (1 << CP0St_ERL))
1675 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1676 if (env->hflags & MIPS_HFLAG_DM)
1677 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1678 switch (env->hflags & MIPS_HFLAG_KSU) {
1679 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
1680 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
1681 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
1682 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1683 }
1684 }
1685
1686 void do_eret (void)
1687 {
1688 if (loglevel & CPU_LOG_EXEC)
1689 debug_pre_eret();
1690 if (env->CP0_Status & (1 << CP0St_ERL)) {
1691 env->PC[env->current_tc] = env->CP0_ErrorEPC;
1692 env->CP0_Status &= ~(1 << CP0St_ERL);
1693 } else {
1694 env->PC[env->current_tc] = env->CP0_EPC;
1695 env->CP0_Status &= ~(1 << CP0St_EXL);
1696 }
1697 compute_hflags(env);
1698 if (loglevel & CPU_LOG_EXEC)
1699 debug_post_eret();
1700 env->CP0_LLAddr = 1;
1701 }
1702
1703 void do_deret (void)
1704 {
1705 if (loglevel & CPU_LOG_EXEC)
1706 debug_pre_eret();
1707 env->PC[env->current_tc] = env->CP0_DEPC;
1708 env->hflags &= MIPS_HFLAG_DM;
1709 compute_hflags(env);
1710 if (loglevel & CPU_LOG_EXEC)
1711 debug_post_eret();
1712 env->CP0_LLAddr = 1;
1713 }
1714
1715 target_ulong do_rdhwr_cpunum(target_ulong t0)
1716 {
1717 if ((env->hflags & MIPS_HFLAG_CP0) ||
1718 (env->CP0_HWREna & (1 << 0)))
1719 t0 = env->CP0_EBase & 0x3ff;
1720 else
1721 do_raise_exception(EXCP_RI);
1722
1723 return t0;
1724 }
1725
1726 target_ulong do_rdhwr_synci_step(target_ulong t0)
1727 {
1728 if ((env->hflags & MIPS_HFLAG_CP0) ||
1729 (env->CP0_HWREna & (1 << 1)))
1730 t0 = env->SYNCI_Step;
1731 else
1732 do_raise_exception(EXCP_RI);
1733
1734 return t0;
1735 }
1736
1737 target_ulong do_rdhwr_cc(target_ulong t0)
1738 {
1739 if ((env->hflags & MIPS_HFLAG_CP0) ||
1740 (env->CP0_HWREna & (1 << 2)))
1741 t0 = env->CP0_Count;
1742 else
1743 do_raise_exception(EXCP_RI);
1744
1745 return t0;
1746 }
1747
1748 target_ulong do_rdhwr_ccres(target_ulong t0)
1749 {
1750 if ((env->hflags & MIPS_HFLAG_CP0) ||
1751 (env->CP0_HWREna & (1 << 3)))
1752 t0 = env->CCRes;
1753 else
1754 do_raise_exception(EXCP_RI);
1755
1756 return t0;
1757 }
1758
1759 /* Bitfield operations. */
1760 target_ulong do_ext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
1761 {
1762 return (int32_t)((t1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
1763 }
1764
1765 target_ulong do_ins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
1766 {
1767 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
1768
1769 return (int32_t)((t0 & ~mask) | ((t1 << pos) & mask));
1770 }
1771
1772 target_ulong do_wsbh(target_ulong t0, target_ulong t1)
1773 {
1774 return (int32_t)(((t1 << 8) & ~0x00FF00FF) | ((t1 >> 8) & 0x00FF00FF));
1775 }
1776
1777 #if defined(TARGET_MIPS64)
1778 target_ulong do_dext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
1779 {
1780 return (t1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
1781 }
1782
1783 target_ulong do_dins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
1784 {
1785 target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
1786
1787 return (t0 & ~mask) | ((t1 << pos) & mask);
1788 }
1789
1790 target_ulong do_dsbh(target_ulong t0, target_ulong t1)
1791 {
1792 return ((t1 << 8) & ~0x00FF00FF00FF00FFULL) | ((t1 >> 8) & 0x00FF00FF00FF00FFULL);
1793 }
1794
1795 target_ulong do_dshd(target_ulong t0, target_ulong t1)
1796 {
1797 t1 = ((t1 << 16) & ~0x0000FFFF0000FFFFULL) | ((t1 >> 16) & 0x0000FFFF0000FFFFULL);
1798 return (t1 << 32) | (t1 >> 32);
1799 }
1800 #endif
1801
1802 void do_pmon (int function)
1803 {
1804 function /= 2;
1805 switch (function) {
1806 case 2: /* TODO: char inbyte(int waitflag); */
1807 if (env->gpr[env->current_tc][4] == 0)
1808 env->gpr[env->current_tc][2] = -1;
1809 /* Fall through */
1810 case 11: /* TODO: char inbyte (void); */
1811 env->gpr[env->current_tc][2] = -1;
1812 break;
1813 case 3:
1814 case 12:
1815 printf("%c", (char)(env->gpr[env->current_tc][4] & 0xFF));
1816 break;
1817 case 17:
1818 break;
1819 case 158:
1820 {
1821 unsigned char *fmt = (void *)(unsigned long)env->gpr[env->current_tc][4];
1822 printf("%s", fmt);
1823 }
1824 break;
1825 }
1826 }
1827
1828 void do_wait (void)
1829 {
1830 env->halted = 1;
1831 do_raise_exception(EXCP_HLT);
1832 }
1833
1834 #if !defined(CONFIG_USER_ONLY)
1835
1836 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1837
1838 #define MMUSUFFIX _mmu
1839 #define ALIGNED_ONLY
1840
1841 #define SHIFT 0
1842 #include "softmmu_template.h"
1843
1844 #define SHIFT 1
1845 #include "softmmu_template.h"
1846
1847 #define SHIFT 2
1848 #include "softmmu_template.h"
1849
1850 #define SHIFT 3
1851 #include "softmmu_template.h"
1852
1853 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1854 {
1855 env->CP0_BadVAddr = addr;
1856 do_restore_state (retaddr);
1857 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1858 }
1859
1860 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1861 {
1862 TranslationBlock *tb;
1863 CPUState *saved_env;
1864 unsigned long pc;
1865 int ret;
1866
1867 /* XXX: hack to restore env in all cases, even if not called from
1868 generated code */
1869 saved_env = env;
1870 env = cpu_single_env;
1871 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1872 if (ret) {
1873 if (retaddr) {
1874 /* now we have a real cpu fault */
1875 pc = (unsigned long)retaddr;
1876 tb = tb_find_pc(pc);
1877 if (tb) {
1878 /* the PC is inside the translated code. It means that we have
1879 a virtual CPU fault */
1880 cpu_restore_state(tb, env, pc, NULL);
1881 }
1882 }
1883 do_raise_exception_err(env->exception_index, env->error_code);
1884 }
1885 env = saved_env;
1886 }
1887
1888 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1889 int unused)
1890 {
1891 if (is_exec)
1892 do_raise_exception(EXCP_IBE);
1893 else
1894 do_raise_exception(EXCP_DBE);
1895 }
1896 #endif /* !CONFIG_USER_ONLY */
1897
1898 /* Complex FPU operations which may need stack space. */
1899
1900 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1901 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1902 #define FLOAT_TWO32 make_float32(1 << 30)
1903 #define FLOAT_TWO64 make_float64(1ULL << 62)
1904 #define FLOAT_QNAN32 0x7fbfffff
1905 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1906 #define FLOAT_SNAN32 0x7fffffff
1907 #define FLOAT_SNAN64 0x7fffffffffffffffULL
1908
1909 /* convert MIPS rounding mode in FCR31 to IEEE library */
1910 unsigned int ieee_rm[] = {
1911 float_round_nearest_even,
1912 float_round_to_zero,
1913 float_round_up,
1914 float_round_down
1915 };
1916
1917 #define RESTORE_ROUNDING_MODE \
1918 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
1919
1920 target_ulong do_cfc1 (uint32_t reg)
1921 {
1922 target_ulong t0;
1923
1924 switch (reg) {
1925 case 0:
1926 t0 = (int32_t)env->fpu->fcr0;
1927 break;
1928 case 25:
1929 t0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
1930 break;
1931 case 26:
1932 t0 = env->fpu->fcr31 & 0x0003f07c;
1933 break;
1934 case 28:
1935 t0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
1936 break;
1937 default:
1938 t0 = (int32_t)env->fpu->fcr31;
1939 break;
1940 }
1941
1942 return t0;
1943 }
1944
1945 void do_ctc1 (target_ulong t0, uint32_t reg)
1946 {
1947 switch(reg) {
1948 case 25:
1949 if (t0 & 0xffffff00)
1950 return;
1951 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
1952 ((t0 & 0x1) << 23);
1953 break;
1954 case 26:
1955 if (t0 & 0x007c0000)
1956 return;
1957 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
1958 break;
1959 case 28:
1960 if (t0 & 0x007c0000)
1961 return;
1962 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
1963 ((t0 & 0x4) << 22);
1964 break;
1965 case 31:
1966 if (t0 & 0x007c0000)
1967 return;
1968 env->fpu->fcr31 = t0;
1969 break;
1970 default:
1971 return;
1972 }
1973 /* set rounding mode */
1974 RESTORE_ROUNDING_MODE;
1975 set_float_exception_flags(0, &env->fpu->fp_status);
1976 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
1977 do_raise_exception(EXCP_FPE);
1978 }
1979
1980 static always_inline char ieee_ex_to_mips(char xcpt)
1981 {
1982 return (xcpt & float_flag_inexact) >> 5 |
1983 (xcpt & float_flag_underflow) >> 3 |
1984 (xcpt & float_flag_overflow) >> 1 |
1985 (xcpt & float_flag_divbyzero) << 1 |
1986 (xcpt & float_flag_invalid) << 4;
1987 }
1988
1989 static always_inline char mips_ex_to_ieee(char xcpt)
1990 {
1991 return (xcpt & FP_INEXACT) << 5 |
1992 (xcpt & FP_UNDERFLOW) << 3 |
1993 (xcpt & FP_OVERFLOW) << 1 |
1994 (xcpt & FP_DIV0) >> 1 |
1995 (xcpt & FP_INVALID) >> 4;
1996 }
1997
1998 static always_inline void update_fcr31(void)
1999 {
2000 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
2001
2002 SET_FP_CAUSE(env->fpu->fcr31, tmp);
2003 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
2004 do_raise_exception(EXCP_FPE);
2005 else
2006 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
2007 }
2008
2009 /* Float support.
2010 Single precition routines have a "s" suffix, double precision a
2011 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2012 paired single lower "pl", paired single upper "pu". */
2013
2014 #define FLOAT_OP(name, p) void do_float_##name##_##p(void)
2015
2016 /* unary operations, modifying fp status */
2017 #define FLOAT_UNOP(name) \
2018 FLOAT_OP(name, d) \
2019 { \
2020 FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \
2021 } \
2022 FLOAT_OP(name, s) \
2023 { \
2024 FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \
2025 }
2026 FLOAT_UNOP(sqrt)
2027 #undef FLOAT_UNOP
2028
2029 FLOAT_OP(cvtd, s)
2030 {
2031 set_float_exception_flags(0, &env->fpu->fp_status);
2032 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
2033 update_fcr31();
2034 }
2035 FLOAT_OP(cvtd, w)
2036 {
2037 set_float_exception_flags(0, &env->fpu->fp_status);
2038 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
2039 update_fcr31();
2040 }
2041 FLOAT_OP(cvtd, l)
2042 {
2043 set_float_exception_flags(0, &env->fpu->fp_status);
2044 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
2045 update_fcr31();
2046 }
2047 FLOAT_OP(cvtl, d)
2048 {
2049 set_float_exception_flags(0, &env->fpu->fp_status);
2050 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
2051 update_fcr31();
2052 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2053 DT2 = FLOAT_SNAN64;
2054 }
2055 FLOAT_OP(cvtl, s)
2056 {
2057 set_float_exception_flags(0, &env->fpu->fp_status);
2058 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
2059 update_fcr31();
2060 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2061 DT2 = FLOAT_SNAN64;
2062 }
2063
2064 FLOAT_OP(cvtps, pw)
2065 {
2066 set_float_exception_flags(0, &env->fpu->fp_status);
2067 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
2068 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
2069 update_fcr31();
2070 }
2071 FLOAT_OP(cvtpw, ps)
2072 {
2073 set_float_exception_flags(0, &env->fpu->fp_status);
2074 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
2075 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
2076 update_fcr31();
2077 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2078 WT2 = FLOAT_SNAN32;
2079 }
2080 FLOAT_OP(cvts, d)
2081 {
2082 set_float_exception_flags(0, &env->fpu->fp_status);
2083 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
2084 update_fcr31();
2085 }
2086 FLOAT_OP(cvts, w)
2087 {
2088 set_float_exception_flags(0, &env->fpu->fp_status);
2089 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
2090 update_fcr31();
2091 }
2092 FLOAT_OP(cvts, l)
2093 {
2094 set_float_exception_flags(0, &env->fpu->fp_status);
2095 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
2096 update_fcr31();
2097 }
2098 FLOAT_OP(cvts, pl)
2099 {
2100 set_float_exception_flags(0, &env->fpu->fp_status);
2101 WT2 = WT0;
2102 update_fcr31();
2103 }
2104 FLOAT_OP(cvts, pu)
2105 {
2106 set_float_exception_flags(0, &env->fpu->fp_status);
2107 WT2 = WTH0;
2108 update_fcr31();
2109 }
2110 FLOAT_OP(cvtw, s)
2111 {
2112 set_float_exception_flags(0, &env->fpu->fp_status);
2113 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
2114 update_fcr31();
2115 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2116 WT2 = FLOAT_SNAN32;
2117 }
2118 FLOAT_OP(cvtw, d)
2119 {
2120 set_float_exception_flags(0, &env->fpu->fp_status);
2121 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
2122 update_fcr31();
2123 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2124 WT2 = FLOAT_SNAN32;
2125 }
2126
2127 FLOAT_OP(roundl, d)
2128 {
2129 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2130 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
2131 RESTORE_ROUNDING_MODE;
2132 update_fcr31();
2133 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2134 DT2 = FLOAT_SNAN64;
2135 }
2136 FLOAT_OP(roundl, s)
2137 {
2138 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2139 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
2140 RESTORE_ROUNDING_MODE;
2141 update_fcr31();
2142 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2143 DT2 = FLOAT_SNAN64;
2144 }
2145 FLOAT_OP(roundw, d)
2146 {
2147 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2148 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
2149 RESTORE_ROUNDING_MODE;
2150 update_fcr31();
2151 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2152 WT2 = FLOAT_SNAN32;
2153 }
2154 FLOAT_OP(roundw, s)
2155 {
2156 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2157 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
2158 RESTORE_ROUNDING_MODE;
2159 update_fcr31();
2160 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2161 WT2 = FLOAT_SNAN32;
2162 }
2163
2164 FLOAT_OP(truncl, d)
2165 {
2166 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
2167 update_fcr31();
2168 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2169 DT2 = FLOAT_SNAN64;
2170 }
2171 FLOAT_OP(truncl, s)
2172 {
2173 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
2174 update_fcr31();
2175 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2176 DT2 = FLOAT_SNAN64;
2177 }
2178 FLOAT_OP(truncw, d)
2179 {
2180 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
2181 update_fcr31();
2182 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2183 WT2 = FLOAT_SNAN32;
2184 }
2185 FLOAT_OP(truncw, s)
2186 {
2187 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
2188 update_fcr31();
2189 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2190 WT2 = FLOAT_SNAN32;
2191 }
2192
2193 FLOAT_OP(ceill, d)
2194 {
2195 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2196 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
2197 RESTORE_ROUNDING_MODE;
2198 update_fcr31();
2199 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2200 DT2 = FLOAT_SNAN64;
2201 }
2202 FLOAT_OP(ceill, s)
2203 {
2204 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2205 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
2206 RESTORE_ROUNDING_MODE;
2207 update_fcr31();
2208 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2209 DT2 = FLOAT_SNAN64;
2210 }
2211 FLOAT_OP(ceilw, d)
2212 {
2213 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2214 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
2215 RESTORE_ROUNDING_MODE;
2216 update_fcr31();
2217 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2218 WT2 = FLOAT_SNAN32;
2219 }
2220 FLOAT_OP(ceilw, s)
2221 {
2222 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2223 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
2224 RESTORE_ROUNDING_MODE;
2225 update_fcr31();
2226 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2227 WT2 = FLOAT_SNAN32;
2228 }
2229
2230 FLOAT_OP(floorl, d)
2231 {
2232 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2233 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
2234 RESTORE_ROUNDING_MODE;
2235 update_fcr31();
2236 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2237 DT2 = FLOAT_SNAN64;
2238 }
2239 FLOAT_OP(floorl, s)
2240 {
2241 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2242 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
2243 RESTORE_ROUNDING_MODE;
2244 update_fcr31();
2245 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2246 DT2 = FLOAT_SNAN64;
2247 }
2248 FLOAT_OP(floorw, d)
2249 {
2250 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2251 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
2252 RESTORE_ROUNDING_MODE;
2253 update_fcr31();
2254 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2255 WT2 = FLOAT_SNAN32;
2256 }
2257 FLOAT_OP(floorw, s)
2258 {
2259 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2260 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
2261 RESTORE_ROUNDING_MODE;
2262 update_fcr31();
2263 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2264 WT2 = FLOAT_SNAN32;
2265 }
2266
2267 /* unary operations, not modifying fp status */
2268 #define FLOAT_UNOP(name) \
2269 FLOAT_OP(name, d) \
2270 { \
2271 FDT2 = float64_ ## name(FDT0); \
2272 } \
2273 FLOAT_OP(name, s) \
2274 { \
2275 FST2 = float32_ ## name(FST0); \
2276 } \
2277 FLOAT_OP(name, ps) \
2278 { \
2279 FST2 = float32_ ## name(FST0); \
2280 FSTH2 = float32_ ## name(FSTH0); \
2281 }
2282 FLOAT_UNOP(abs)
2283 FLOAT_UNOP(chs)
2284 #undef FLOAT_UNOP
2285
2286 /* MIPS specific unary operations */
2287 FLOAT_OP(recip, d)
2288 {
2289 set_float_exception_flags(0, &env->fpu->fp_status);
2290 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
2291 update_fcr31();
2292 }
2293 FLOAT_OP(recip, s)
2294 {
2295 set_float_exception_flags(0, &env->fpu->fp_status);
2296 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
2297 update_fcr31();
2298 }
2299
2300 FLOAT_OP(rsqrt, d)
2301 {
2302 set_float_exception_flags(0, &env->fpu->fp_status);
2303 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
2304 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
2305 update_fcr31();
2306 }
2307 FLOAT_OP(rsqrt, s)
2308 {
2309 set_float_exception_flags(0, &env->fpu->fp_status);
2310 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2311 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
2312 update_fcr31();
2313 }
2314
2315 FLOAT_OP(recip1, d)
2316 {
2317 set_float_exception_flags(0, &env->fpu->fp_status);
2318 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
2319 update_fcr31();
2320 }
2321 FLOAT_OP(recip1, s)
2322 {
2323 set_float_exception_flags(0, &env->fpu->fp_status);
2324 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
2325 update_fcr31();
2326 }
2327 FLOAT_OP(recip1, ps)
2328 {
2329 set_float_exception_flags(0, &env->fpu->fp_status);
2330 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
2331 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
2332 update_fcr31();
2333 }
2334
2335 FLOAT_OP(rsqrt1, d)
2336 {
2337 set_float_exception_flags(0, &env->fpu->fp_status);
2338 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
2339 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
2340 update_fcr31();
2341 }
2342 FLOAT_OP(rsqrt1, s)
2343 {
2344 set_float_exception_flags(0, &env->fpu->fp_status);
2345 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2346 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
2347 update_fcr31();
2348 }
2349 FLOAT_OP(rsqrt1, ps)
2350 {
2351 set_float_exception_flags(0, &env->fpu->fp_status);
2352 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2353 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
2354 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
2355 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
2356 update_fcr31();
2357 }
2358
2359 /* binary operations */
2360 #define FLOAT_BINOP(name) \
2361 FLOAT_OP(name, d) \
2362 { \
2363 set_float_exception_flags(0, &env->fpu->fp_status); \
2364 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
2365 update_fcr31(); \
2366 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
2367 DT2 = FLOAT_QNAN64; \
2368 } \
2369 FLOAT_OP(name, s) \
2370 { \
2371 set_float_exception_flags(0, &env->fpu->fp_status); \
2372 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
2373 update_fcr31(); \
2374 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
2375 WT2 = FLOAT_QNAN32; \
2376 } \
2377 FLOAT_OP(name, ps) \
2378 { \
2379 set_float_exception_flags(0, &env->fpu->fp_status); \
2380 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
2381 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
2382 update_fcr31(); \
2383 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
2384 WT2 = FLOAT_QNAN32; \
2385 WTH2 = FLOAT_QNAN32; \
2386 } \
2387 }
2388 FLOAT_BINOP(add)
2389 FLOAT_BINOP(sub)
2390 FLOAT_BINOP(mul)
2391 FLOAT_BINOP(div)
2392 #undef FLOAT_BINOP
2393
2394 /* ternary operations */
2395 #define FLOAT_TERNOP(name1, name2) \
2396 FLOAT_OP(name1 ## name2, d) \
2397 { \
2398 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2399 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2400 } \
2401 FLOAT_OP(name1 ## name2, s) \
2402 { \
2403 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2404 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2405 } \
2406 FLOAT_OP(name1 ## name2, ps) \
2407 { \
2408 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2409 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2410 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2411 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2412 }
2413 FLOAT_TERNOP(mul, add)
2414 FLOAT_TERNOP(mul, sub)
2415 #undef FLOAT_TERNOP
2416
2417 /* negated ternary operations */
2418 #define FLOAT_NTERNOP(name1, name2) \
2419 FLOAT_OP(n ## name1 ## name2, d) \
2420 { \
2421 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2422 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2423 FDT2 = float64_chs(FDT2); \
2424 } \
2425 FLOAT_OP(n ## name1 ## name2, s) \
2426 { \
2427 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2428 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2429 FST2 = float32_chs(FST2); \
2430 } \
2431 FLOAT_OP(n ## name1 ## name2, ps) \
2432 { \
2433 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2434 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2435 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2436 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2437 FST2 = float32_chs(FST2); \
2438 FSTH2 = float32_chs(FSTH2); \
2439 }
2440 FLOAT_NTERNOP(mul, add)
2441 FLOAT_NTERNOP(mul, sub)
2442 #undef FLOAT_NTERNOP
2443
2444 /* MIPS specific binary operations */
2445 FLOAT_OP(recip2, d)
2446 {
2447 set_float_exception_flags(0, &env->fpu->fp_status);
2448 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
2449 FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
2450 update_fcr31();
2451 }
2452 FLOAT_OP(recip2, s)
2453 {
2454 set_float_exception_flags(0, &env->fpu->fp_status);
2455 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2456 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
2457 update_fcr31();
2458 }
2459 FLOAT_OP(recip2, ps)
2460 {
2461 set_float_exception_flags(0, &env->fpu->fp_status);
2462 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2463 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
2464 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
2465 FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
2466 update_fcr31();
2467 }
2468
2469 FLOAT_OP(rsqrt2, d)
2470 {
2471 set_float_exception_flags(0, &env->fpu->fp_status);
2472 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
2473 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
2474 FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
2475 update_fcr31();
2476 }
2477 FLOAT_OP(rsqrt2, s)
2478 {
2479 set_float_exception_flags(0, &env->fpu->fp_status);
2480 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2481 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
2482 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
2483 update_fcr31();
2484 }
2485 FLOAT_OP(rsqrt2, ps)
2486 {
2487 set_float_exception_flags(0, &env->fpu->fp_status);
2488 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2489 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
2490 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
2491 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
2492 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
2493 FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
2494 update_fcr31();
2495 }
2496
2497 FLOAT_OP(addr, ps)
2498 {
2499 set_float_exception_flags(0, &env->fpu->fp_status);
2500 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
2501 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
2502 update_fcr31();
2503 }
2504
2505 FLOAT_OP(mulr, ps)
2506 {
2507 set_float_exception_flags(0, &env->fpu->fp_status);
2508 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
2509 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
2510 update_fcr31();
2511 }
2512
2513 /* compare operations */
2514 #define FOP_COND_D(op, cond) \
2515 void do_cmp_d_ ## op (long cc) \
2516 { \
2517 int c = cond; \
2518 update_fcr31(); \
2519 if (c) \
2520 SET_FP_COND(cc, env->fpu); \
2521 else \
2522 CLEAR_FP_COND(cc, env->fpu); \
2523 } \
2524 void do_cmpabs_d_ ## op (long cc) \
2525 { \
2526 int c; \
2527 FDT0 = float64_abs(FDT0); \
2528 FDT1 = float64_abs(FDT1); \
2529 c = cond; \
2530 update_fcr31(); \
2531 if (c) \
2532 SET_FP_COND(cc, env->fpu); \
2533 else \
2534 CLEAR_FP_COND(cc, env->fpu); \
2535 }
2536
2537 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2538 {
2539 if (float64_is_signaling_nan(a) ||
2540 float64_is_signaling_nan(b) ||
2541 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2542 float_raise(float_flag_invalid, status);
2543 return 1;
2544 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2545 return 1;
2546 } else {
2547 return 0;
2548 }
2549 }
2550
2551 /* NOTE: the comma operator will make "cond" to eval to false,
2552 * but float*_is_unordered() is still called. */
2553 FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
2554 FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
2555 FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2556 FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2557 FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2558 FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2559 FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
2560 FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
2561 /* NOTE: the comma operator will make "cond" to eval to false,
2562 * but float*_is_unordered() is still called. */
2563 FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
2564 FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
2565 FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2566 FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2567 FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2568 FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2569 FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
2570 FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
2571
2572 #define FOP_COND_S(op, cond) \
2573 void do_cmp_s_ ## op (long cc) \
2574 { \
2575 int c = cond; \
2576 update_fcr31(); \
2577 if (c) \
2578 SET_FP_COND(cc, env->fpu); \
2579 else \
2580 CLEAR_FP_COND(cc, env->fpu); \
2581 } \
2582 void do_cmpabs_s_ ## op (long cc) \
2583 { \
2584 int c; \
2585 FST0 = float32_abs(FST0); \
2586 FST1 = float32_abs(FST1); \
2587 c = cond; \
2588 update_fcr31(); \
2589 if (c) \
2590 SET_FP_COND(cc, env->fpu); \
2591 else \
2592 CLEAR_FP_COND(cc, env->fpu); \
2593 }
2594
2595 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2596 {
2597 if (float32_is_signaling_nan(a) ||
2598 float32_is_signaling_nan(b) ||
2599 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2600 float_raise(float_flag_invalid, status);
2601 return 1;
2602 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2603 return 1;
2604 } else {
2605 return 0;
2606 }
2607 }
2608
2609 /* NOTE: the comma operator will make "cond" to eval to false,
2610 * but float*_is_unordered() is still called. */
2611 FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
2612 FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
2613 FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
2614 FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
2615 FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
2616 FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
2617 FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
2618 FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
2619 /* NOTE: the comma operator will make "cond" to eval to false,
2620 * but float*_is_unordered() is still called. */
2621 FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
2622 FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
2623 FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
2624 FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
2625 FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
2626 FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
2627 FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
2628 FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
2629
2630 #define FOP_COND_PS(op, condl, condh) \
2631 void do_cmp_ps_ ## op (long cc) \
2632 { \
2633 int cl = condl; \
2634 int ch = condh; \
2635 update_fcr31(); \
2636 if (cl) \
2637 SET_FP_COND(cc, env->fpu); \
2638 else \
2639 CLEAR_FP_COND(cc, env->fpu); \
2640 if (ch) \
2641 SET_FP_COND(cc + 1, env->fpu); \
2642 else \
2643 CLEAR_FP_COND(cc + 1, env->fpu); \
2644 } \
2645 void do_cmpabs_ps_ ## op (long cc) \
2646 { \
2647 int cl, ch; \
2648 FST0 = float32_abs(FST0); \
2649 FSTH0 = float32_abs(FSTH0); \
2650 FST1 = float32_abs(FST1); \
2651 FSTH1 = float32_abs(FSTH1); \
2652 cl = condl; \
2653 ch = condh; \
2654 update_fcr31(); \
2655 if (cl) \
2656 SET_FP_COND(cc, env->fpu); \
2657 else \
2658 CLEAR_FP_COND(cc, env->fpu); \
2659 if (ch) \
2660 SET_FP_COND(cc + 1, env->fpu); \
2661 else \
2662 CLEAR_FP_COND(cc + 1, env->fpu); \
2663 }
2664
2665 /* NOTE: the comma operator will make "cond" to eval to false,
2666 * but float*_is_unordered() is still called. */
2667 FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
2668 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
2669 FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
2670 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
2671 FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
2672 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2673 FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
2674 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2675 FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
2676 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2677 FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
2678 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2679 FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
2680 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2681 FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
2682 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2683 /* NOTE: the comma operator will make "cond" to eval to false,
2684 * but float*_is_unordered() is still called. */
2685 FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
2686 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
2687 FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
2688 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
2689 FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
2690 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2691 FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
2692 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2693 FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
2694 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2695 FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
2696 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2697 FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
2698 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2699 FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
2700 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
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