target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdlib.h>
  21 #include "exec.h"
  22
  23 #define MIPS_DEBUG_DISAS
  24
  25 #define GETPC() (__builtin_return_address(0))
  26
  27 /*****************************************************************************/
  28 /* Exceptions processing helpers */
  29 void cpu_loop_exit(void)
  30 {
  31     longjmp(env->jmp_env, 1);
  32 }
  33
  34 void do_raise_exception_err (uint32_t exception, int error_code)
  35 {
  36 #if 1
  37     if (logfile && exception < 0x100)
  38         fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
  39 #endif
  40     env->exception_index = exception;
  41     env->error_code = error_code;
  42     T0 = 0;
  43     cpu_loop_exit();
  44 }
  45
  46 void do_raise_exception (uint32_t exception)
  47 {
  48     do_raise_exception_err(exception, 0);
  49 }
  50
  51 void do_restore_state (void *pc_ptr)
  52 {
  53   TranslationBlock *tb;
  54   unsigned long pc = (unsigned long) pc_ptr;
  55
  56   tb = tb_find_pc (pc);
  57   cpu_restore_state (tb, env, pc, NULL);
  58 }
  59
  60 void do_raise_exception_direct_err (uint32_t exception, int error_code)
  61 {
  62     do_restore_state (GETPC ());
  63     do_raise_exception_err (exception, error_code);
  64 }
  65
  66 void do_raise_exception_direct (uint32_t exception)
  67 {
  68     do_raise_exception_direct_err (exception, 0);
  69 }
  70
  71 #define MEMSUFFIX _raw
  72 #include "op_helper_mem.c"
  73 #undef MEMSUFFIX
  74 #if !defined(CONFIG_USER_ONLY)
  75 #define MEMSUFFIX _user
  76 #include "op_helper_mem.c"
  77 #undef MEMSUFFIX
  78 #define MEMSUFFIX _kernel
  79 #include "op_helper_mem.c"
  80 #undef MEMSUFFIX
  81 #endif
  82
  83 #ifdef TARGET_MIPS64
  84 #if TARGET_LONG_BITS > HOST_LONG_BITS
  85 /* Those might call libgcc functions.  */
  86 void do_dsll (void)
  87 {
  88     T0 = T0 << T1;
  89 }
  90
  91 void do_dsll32 (void)
  92 {
  93     T0 = T0 << (T1 + 32);
  94 }
  95
  96 void do_dsra (void)
  97 {
  98     T0 = (int64_t)T0 >> T1;
  99 }
 100
 101 void do_dsra32 (void)
 102 {
 103     T0 = (int64_t)T0 >> (T1 + 32);
 104 }
 105
 106 void do_dsrl (void)
 107 {
 108     T0 = T0 >> T1;
 109 }
 110
 111 void do_dsrl32 (void)
 112 {
 113     T0 = T0 >> (T1 + 32);
 114 }
 115
 116 void do_drotr (void)
 117 {
 118     target_ulong tmp;
 119
 120     if (T1) {
 121        tmp = T0 << (0x40 - T1);
 122        T0 = (T0 >> T1) | tmp;
 123     } else
 124        T0 = T1;
 125 }
 126
 127 void do_drotr32 (void)
 128 {
 129     target_ulong tmp;
 130
 131     if (T1) {
 132        tmp = T0 << (0x40 - (32 + T1));
 133        T0 = (T0 >> (32 + T1)) | tmp;
 134     } else
 135        T0 = T1;
 136 }
 137
 138 void do_dsllv (void)
 139 {
 140     T0 = T1 << (T0 & 0x3F);
 141 }
 142
 143 void do_dsrav (void)
 144 {
 145     T0 = (int64_t)T1 >> (T0 & 0x3F);
 146 }
 147
 148 void do_dsrlv (void)
 149 {
 150     T0 = T1 >> (T0 & 0x3F);
 151 }
 152
 153 void do_drotrv (void)
 154 {
 155     target_ulong tmp;
 156
 157     T0 &= 0x3F;
 158     if (T0) {
 159        tmp = T1 << (0x40 - T0);
 160        T0 = (T1 >> T0) | tmp;
 161     } else
 162        T0 = T1;
 163 }
 164 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 165 #endif /* TARGET_MIPS64 */
 166
 167 /* 64 bits arithmetic for 32 bits hosts */
 168 #if TARGET_LONG_BITS > HOST_LONG_BITS
 169 static inline uint64_t get_HILO (void)
 170 {
 171     return (env->HI << 32) | (uint32_t)env->LO;
 172 }
 173
 174 static inline void set_HILO (uint64_t HILO)
 175 {
 176     env->LO = (int32_t)HILO;
 177     env->HI = (int32_t)(HILO >> 32);
 178 }
 179
 180 void do_mult (void)
 181 {
 182     set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 183 }
 184
 185 void do_multu (void)
 186 {
 187     set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 188 }
 189
 190 void do_madd (void)
 191 {
 192     int64_t tmp;
 193
 194     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 195     set_HILO((int64_t)get_HILO() + tmp);
 196 }
 197
 198 void do_maddu (void)
 199 {
 200     uint64_t tmp;
 201
 202     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 203     set_HILO(get_HILO() + tmp);
 204 }
 205
 206 void do_msub (void)
 207 {
 208     int64_t tmp;
 209
 210     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 211     set_HILO((int64_t)get_HILO() - tmp);
 212 }
 213
 214 void do_msubu (void)
 215 {
 216     uint64_t tmp;
 217
 218     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 219     set_HILO(get_HILO() - tmp);
 220 }
 221 #endif
 222
 223 #ifdef TARGET_MIPS64
 224 void do_dmult (void)
 225 {
 226     env->LO = (int64_t)T0 * (int64_t)T1;
 227     /* XXX */
 228     env->HI = (env->LO | (1ULL << 63)) ? ~0ULL : 0ULL;
 229 }
 230
 231 void do_dmultu (void)
 232 {
 233     env->LO = T0 * T1;
 234     /* XXX */
 235     env->HI = 0;
 236 }
 237
 238 void do_ddiv (void)
 239 {
 240     if (T1 != 0) {
 241         lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
 242         env->LO = res.quot;
 243         env->HI = res.rem;
 244     }
 245 }
 246
 247 void do_ddivu (void)
 248 {
 249     if (T1 != 0) {
 250         /* XXX: lldivu? */
 251         lldiv_t res = lldiv(T0, T1);
 252         env->LO = (uint64_t)res.quot;
 253         env->HI = (uint64_t)res.rem;
 254     }
 255 }
 256 #endif
 257
 258 #if defined(CONFIG_USER_ONLY)
 259 void do_mfc0_random (void)
 260 {
 261     cpu_abort(env, "mfc0 random\n");
 262 }
 263
 264 void do_mfc0_count (void)
 265 {
 266     cpu_abort(env, "mfc0 count\n");
 267 }
 268
 269 void cpu_mips_store_count(CPUState *env, uint32_t value)
 270 {
 271     cpu_abort(env, "mtc0 count\n");
 272 }
 273
 274 void cpu_mips_store_compare(CPUState *env, uint32_t value)
 275 {
 276     cpu_abort(env, "mtc0 compare\n");
 277 }
 278
 279 void cpu_mips_update_irq(CPUState *env)
 280 {
 281     cpu_abort(env, "mtc0 status / mtc0 cause\n");
 282 }
 283
 284 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 285 {
 286     cpu_abort(env, "mtc0 status debug\n");
 287 }
 288
 289 void do_mtc0_status_irqraise_debug (void)
 290 {
 291     cpu_abort(env, "mtc0 status irqraise debug\n");
 292 }
 293
 294 void do_tlbwi (void)
 295 {
 296     cpu_abort(env, "tlbwi\n");
 297 }
 298
 299 void do_tlbwr (void)
 300 {
 301     cpu_abort(env, "tlbwr\n");
 302 }
 303
 304 void do_tlbp (void)
 305 {
 306     cpu_abort(env, "tlbp\n");
 307 }
 308
 309 void do_tlbr (void)
 310 {
 311     cpu_abort(env, "tlbr\n");
 312 }
 313
 314 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 315 {
 316     cpu_abort(env, "mips_tlb_flush\n");
 317 }
 318
 319 #else
 320
 321 /* CP0 helpers */
 322 void do_mfc0_random (void)
 323 {
 324     T0 = (int32_t)cpu_mips_get_random(env);
 325 }
 326
 327 void do_mfc0_count (void)
 328 {
 329     T0 = (int32_t)cpu_mips_get_count(env);
 330 }
 331
 332 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 333 {
 334     const uint32_t mask = 0x0000FF00;
 335     fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
 336             old, val, env->CP0_Cause, old & mask, val & mask,
 337             env->CP0_Cause & mask);
 338 }
 339
 340 void do_mtc0_status_irqraise_debug(void)
 341 {
 342     fprintf(logfile, "Raise pending IRQs\n");
 343 }
 344
 345 void fpu_handle_exception(void)
 346 {
 347 #ifdef CONFIG_SOFTFLOAT
 348     int flags = get_float_exception_flags(&env->fp_status);
 349     unsigned int cpuflags = 0, enable, cause = 0;
 350
 351     enable = GET_FP_ENABLE(env->fcr31);
 352
 353     /* determine current flags */
 354     if (flags & float_flag_invalid) {
 355         cpuflags |= FP_INVALID;
 356         cause |= FP_INVALID & enable;
 357     }
 358     if (flags & float_flag_divbyzero) {
 359         cpuflags |= FP_DIV0;
 360         cause |= FP_DIV0 & enable;
 361     }
 362     if (flags & float_flag_overflow) {
 363         cpuflags |= FP_OVERFLOW;
 364         cause |= FP_OVERFLOW & enable;
 365     }
 366     if (flags & float_flag_underflow) {
 367         cpuflags |= FP_UNDERFLOW;
 368         cause |= FP_UNDERFLOW & enable;
 369     }
 370     if (flags & float_flag_inexact) {
 371         cpuflags |= FP_INEXACT;
 372         cause |= FP_INEXACT & enable;
 373     }
 374     SET_FP_FLAGS(env->fcr31, cpuflags);
 375     SET_FP_CAUSE(env->fcr31, cause);
 376 #else
 377     SET_FP_FLAGS(env->fcr31, 0);
 378     SET_FP_CAUSE(env->fcr31, 0);
 379 #endif
 380 }
 381
 382 /* TLB management */
 383 #if defined(MIPS_USES_R4K_TLB)
 384 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 385 {
 386     /* Flush qemu's TLB and discard all shadowed entries.  */
 387     tlb_flush (env, flush_global);
 388     env->tlb_in_use = MIPS_TLB_NB;
 389 }
 390
 391 static void mips_tlb_flush_extra (CPUState *env, int first)
 392 {
 393     /* Discard entries from env->tlb[first] onwards.  */
 394     while (env->tlb_in_use > first) {
 395         invalidate_tlb(env, --env->tlb_in_use, 0);
 396     }
 397 }
 398
 399 static void fill_tlb (int idx)
 400 {
 401     tlb_t *tlb;
 402
 403     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
 404     tlb = &env->tlb[idx];
 405     tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
 406     tlb->ASID = env->CP0_EntryHi & 0xFF;
 407     tlb->PageMask = env->CP0_PageMask;
 408     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
 409     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
 410     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
 411     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
 412     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
 413     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
 414     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
 415     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
 416     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
 417 }
 418
 419 void do_tlbwi (void)
 420 {
 421     /* Discard cached TLB entries.  We could avoid doing this if the
 422        tlbwi is just upgrading access permissions on the current entry;
 423        that might be a further win.  */
 424     mips_tlb_flush_extra (env, MIPS_TLB_NB);
 425
 426     /* Wildly undefined effects for CP0_Index containing a too high value and
 427        MIPS_TLB_NB not being a power of two.  But so does real silicon.  */
 428     invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0);
 429     fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
 430 }
 431
 432 void do_tlbwr (void)
 433 {
 434     int r = cpu_mips_get_random(env);
 435
 436     invalidate_tlb(env, r, 1);
 437     fill_tlb(r);
 438 }
 439
 440 void do_tlbp (void)
 441 {
 442     tlb_t *tlb;
 443     target_ulong tag;
 444     uint8_t ASID;
 445     int i;
 446
 447     tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
 448     ASID = env->CP0_EntryHi & 0xFF;
 449     for (i = 0; i < MIPS_TLB_NB; i++) {
 450         tlb = &env->tlb[i];
 451         /* Check ASID, virtual page number & size */
 452         if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
 453             /* TLB match */
 454             env->CP0_Index = i;
 455             break;
 456         }
 457     }
 458     if (i == MIPS_TLB_NB) {
 459         /* No match.  Discard any shadow entries, if any of them match.  */
 460         for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
 461             tlb = &env->tlb[i];
 462
 463             /* Check ASID, virtual page number & size */
 464             if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
 465                 mips_tlb_flush_extra (env, i);
 466                 break;
 467             }
 468         }
 469
 470         env->CP0_Index |= 0x80000000;
 471     }
 472 }
 473
 474 void do_tlbr (void)
 475 {
 476     tlb_t *tlb;
 477     uint8_t ASID;
 478
 479     ASID = env->CP0_EntryHi & 0xFF;
 480     tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
 481
 482     /* If this will change the current ASID, flush qemu's TLB.  */
 483     if (ASID != tlb->ASID)
 484         cpu_mips_tlb_flush (env, 1);
 485
 486     mips_tlb_flush_extra(env, MIPS_TLB_NB);
 487
 488     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
 489     env->CP0_PageMask = tlb->PageMask;
 490     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
 491                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
 492     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
 493                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
 494 }
 495 #endif
 496
 497 #endif /* !CONFIG_USER_ONLY */
 498
 499 void dump_ldst (const unsigned char *func)
 500 {
 501     if (loglevel)
 502         fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
 503 }
 504
 505 void dump_sc (void)
 506 {
 507     if (loglevel) {
 508         fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
 509                 T1, T0, env->CP0_LLAddr);
 510     }
 511 }
 512
 513 void debug_eret (void)
 514 {
 515     if (loglevel) {
 516         fprintf(logfile, "ERET: pc " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
 517                 env->PC, env->CP0_EPC);
 518         if (env->CP0_Status & (1 << CP0St_ERL))
 519             fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
 520         fputs("\n", logfile);
 521     }
 522 }
 523
 524 void do_pmon (int function)
 525 {
 526     function /= 2;
 527     switch (function) {
 528     case 2: /* TODO: char inbyte(int waitflag); */
 529         if (env->gpr[4] == 0)
 530             env->gpr[2] = -1;
 531         /* Fall through */
 532     case 11: /* TODO: char inbyte (void); */
 533         env->gpr[2] = -1;
 534         break;
 535     case 3:
 536     case 12:
 537         printf("%c", (char)(env->gpr[4] & 0xFF));
 538         break;
 539     case 17:
 540         break;
 541     case 158:
 542         {
 543             unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
 544             printf("%s", fmt);
 545         }
 546         break;
 547     }
 548 }
 549
 550 #if !defined(CONFIG_USER_ONLY)
 551
 552 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
 553
 554 #define MMUSUFFIX _mmu
 555 #define ALIGNED_ONLY
 556
 557 #define SHIFT 0
 558 #include "softmmu_template.h"
 559
 560 #define SHIFT 1
 561 #include "softmmu_template.h"
 562
 563 #define SHIFT 2
 564 #include "softmmu_template.h"
 565
 566 #define SHIFT 3
 567 #include "softmmu_template.h"
 568
 569 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
 570 {
 571     env->CP0_BadVAddr = addr;
 572     do_restore_state (retaddr);
 573     do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
 574 }
 575
 576 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
 577 {
 578     TranslationBlock *tb;
 579     CPUState *saved_env;
 580     unsigned long pc;
 581     int ret;
 582
 583     /* XXX: hack to restore env in all cases, even if not called from
 584        generated code */
 585     saved_env = env;
 586     env = cpu_single_env;
 587     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
 588     if (ret) {
 589         if (retaddr) {
 590             /* now we have a real cpu fault */
 591             pc = (unsigned long)retaddr;
 592             tb = tb_find_pc(pc);
 593             if (tb) {
 594                 /* the PC is inside the translated code. It means that we have
 595                    a virtual CPU fault */
 596                 cpu_restore_state(tb, env, pc, NULL);
 597             }
 598         }
 599         do_raise_exception_err(env->exception_index, env->error_code);
 600     }
 601     env = saved_env;
 602 }
 603
 604 #endif