target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 #include "helper.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "exec/softmmu_exec.h"
  27 #endif /* !defined(CONFIG_USER_ONLY) */
  28
  29 #ifndef CONFIG_USER_ONLY
  30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  31 #endif
  32
  33 /*****************************************************************************/
  34 /* Exceptions processing helpers */
  35
  36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  37                                                         uint32_t exception,
  38                                                         int error_code,
  39                                                         uintptr_t pc)
  40 {
  41     if (exception < EXCP_SC) {
  42         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  43     }
  44     env->exception_index = exception;
  45     env->error_code = error_code;
  46
  47     if (pc) {
  48         /* now we have a real cpu fault */
  49         cpu_restore_state(env, pc);
  50     }
  51
  52     cpu_loop_exit(env);
  53 }
  54
  55 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  56                                                     uint32_t exception,
  57                                                     uintptr_t pc)
  58 {
  59     do_raise_exception_err(env, exception, 0, pc);
  60 }
  61
  62 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  63                                 int error_code)
  64 {
  65     do_raise_exception_err(env, exception, error_code, 0);
  66 }
  67
  68 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  69 {
  70     do_raise_exception(env, exception, 0);
  71 }
  72
  73 #if defined(CONFIG_USER_ONLY)
  74 #define HELPER_LD(name, insn, type)                                     \
  75 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  76                              int mem_idx)                               \
  77 {                                                                       \
  78     return (type) insn##_raw(addr);                                     \
  79 }
  80 #else
  81 #define HELPER_LD(name, insn, type)                                     \
  82 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  83                              int mem_idx)                               \
  84 {                                                                       \
  85     switch (mem_idx)                                                    \
  86     {                                                                   \
  87     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  88     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  89     default:                                                            \
  90     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  91     }                                                                   \
  92 }
  93 #endif
  94 HELPER_LD(lbu, ldub, uint8_t)
  95 HELPER_LD(lw, ldl, int32_t)
  96 #ifdef TARGET_MIPS64
  97 HELPER_LD(ld, ldq, int64_t)
  98 #endif
  99 #undef HELPER_LD
 100
 101 #if defined(CONFIG_USER_ONLY)
 102 #define HELPER_ST(name, insn, type)                                     \
 103 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 104                              type val, int mem_idx)                     \
 105 {                                                                       \
 106     insn##_raw(addr, val);                                              \
 107 }
 108 #else
 109 #define HELPER_ST(name, insn, type)                                     \
 110 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 111                              type val, int mem_idx)                     \
 112 {                                                                       \
 113     switch (mem_idx)                                                    \
 114     {                                                                   \
 115     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 116     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 117     default:                                                            \
 118     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 119     }                                                                   \
 120 }
 121 #endif
 122 HELPER_ST(sb, stb, uint8_t)
 123 HELPER_ST(sw, stl, uint32_t)
 124 #ifdef TARGET_MIPS64
 125 HELPER_ST(sd, stq, uint64_t)
 126 #endif
 127 #undef HELPER_ST
 128
 129 target_ulong helper_clo (target_ulong arg1)
 130 {
 131     return clo32(arg1);
 132 }
 133
 134 target_ulong helper_clz (target_ulong arg1)
 135 {
 136     return clz32(arg1);
 137 }
 138
 139 #if defined(TARGET_MIPS64)
 140 target_ulong helper_dclo (target_ulong arg1)
 141 {
 142     return clo64(arg1);
 143 }
 144
 145 target_ulong helper_dclz (target_ulong arg1)
 146 {
 147     return clz64(arg1);
 148 }
 149 #endif /* TARGET_MIPS64 */
 150
 151 /* 64 bits arithmetic for 32 bits hosts */
 152 static inline uint64_t get_HILO(CPUMIPSState *env)
 153 {
 154     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 155 }
 156
 157 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 158 {
 159     target_ulong tmp;
 160     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 161     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 162     return tmp;
 163 }
 164
 165 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 166 {
 167     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 168     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 169     return tmp;
 170 }
 171
 172 /* Multiplication variants of the vr54xx. */
 173 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 174                          target_ulong arg2)
 175 {
 176     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 177                                  (int64_t)(int32_t)arg2));
 178 }
 179
 180 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 181                           target_ulong arg2)
 182 {
 183     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 184                        (uint64_t)(uint32_t)arg2);
 185 }
 186
 187 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 188                          target_ulong arg2)
 189 {
 190     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 191                        (int64_t)(int32_t)arg2);
 192 }
 193
 194 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 195                            target_ulong arg2)
 196 {
 197     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 198                        (int64_t)(int32_t)arg2);
 199 }
 200
 201 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 202                           target_ulong arg2)
 203 {
 204     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 205                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 206 }
 207
 208 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 209                             target_ulong arg2)
 210 {
 211     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 212                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 213 }
 214
 215 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 216                          target_ulong arg2)
 217 {
 218     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 219                        (int64_t)(int32_t)arg2);
 220 }
 221
 222 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 223                            target_ulong arg2)
 224 {
 225     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 226                        (int64_t)(int32_t)arg2);
 227 }
 228
 229 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 230                           target_ulong arg2)
 231 {
 232     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 233                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 234 }
 235
 236 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 237                             target_ulong arg2)
 238 {
 239     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 240                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 241 }
 242
 243 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 244                           target_ulong arg2)
 245 {
 246     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 247 }
 248
 249 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 250                            target_ulong arg2)
 251 {
 252     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 253                        (uint64_t)(uint32_t)arg2);
 254 }
 255
 256 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 257                            target_ulong arg2)
 258 {
 259     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 260                        (int64_t)(int32_t)arg2);
 261 }
 262
 263 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 264                             target_ulong arg2)
 265 {
 266     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 267                        (uint64_t)(uint32_t)arg2);
 268 }
 269
 270 #ifdef TARGET_MIPS64
 271 void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 272 {
 273     muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 274 }
 275
 276 void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 277 {
 278     mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 279 }
 280 #endif
 281
 282 #ifndef CONFIG_USER_ONLY
 283
 284 static inline hwaddr do_translate_address(CPUMIPSState *env,
 285                                                       target_ulong address,
 286                                                       int rw)
 287 {
 288     hwaddr lladdr;
 289
 290     lladdr = cpu_mips_translate_address(env, address, rw);
 291
 292     if (lladdr == -1LL) {
 293         cpu_loop_exit(env);
 294     } else {
 295         return lladdr;
 296     }
 297 }
 298
 299 #define HELPER_LD_ATOMIC(name, insn)                                          \
 300 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 301 {                                                                             \
 302     env->lladdr = do_translate_address(env, arg, 0);                          \
 303     env->llval = do_##insn(env, arg, mem_idx);                                \
 304     return env->llval;                                                        \
 305 }
 306 HELPER_LD_ATOMIC(ll, lw)
 307 #ifdef TARGET_MIPS64
 308 HELPER_LD_ATOMIC(lld, ld)
 309 #endif
 310 #undef HELPER_LD_ATOMIC
 311
 312 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 313 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 314                            target_ulong arg2, int mem_idx)                    \
 315 {                                                                             \
 316     target_long tmp;                                                          \
 317                                                                               \
 318     if (arg2 & almask) {                                                      \
 319         env->CP0_BadVAddr = arg2;                                             \
 320         helper_raise_exception(env, EXCP_AdES);                               \
 321     }                                                                         \
 322     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 323         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 324         if (tmp == env->llval) {                                              \
 325             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 326             return 1;                                                         \
 327         }                                                                     \
 328     }                                                                         \
 329     return 0;                                                                 \
 330 }
 331 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 332 #ifdef TARGET_MIPS64
 333 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 334 #endif
 335 #undef HELPER_ST_ATOMIC
 336 #endif
 337
 338 #ifdef TARGET_WORDS_BIGENDIAN
 339 #define GET_LMASK(v) ((v) & 3)
 340 #define GET_OFFSET(addr, offset) (addr + (offset))
 341 #else
 342 #define GET_LMASK(v) (((v) & 3) ^ 3)
 343 #define GET_OFFSET(addr, offset) (addr - (offset))
 344 #endif
 345
 346 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 347                 int mem_idx)
 348 {
 349     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 350
 351     if (GET_LMASK(arg2) <= 2)
 352         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 353
 354     if (GET_LMASK(arg2) <= 1)
 355         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 356
 357     if (GET_LMASK(arg2) == 0)
 358         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 359 }
 360
 361 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 362                 int mem_idx)
 363 {
 364     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 365
 366     if (GET_LMASK(arg2) >= 1)
 367         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 368
 369     if (GET_LMASK(arg2) >= 2)
 370         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 371
 372     if (GET_LMASK(arg2) == 3)
 373         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 374 }
 375
 376 #if defined(TARGET_MIPS64)
 377 /* "half" load and stores.  We must do the memory access inline,
 378    or fault handling won't work.  */
 379
 380 #ifdef TARGET_WORDS_BIGENDIAN
 381 #define GET_LMASK64(v) ((v) & 7)
 382 #else
 383 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 384 #endif
 385
 386 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 387                 int mem_idx)
 388 {
 389     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 390
 391     if (GET_LMASK64(arg2) <= 6)
 392         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 393
 394     if (GET_LMASK64(arg2) <= 5)
 395         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 396
 397     if (GET_LMASK64(arg2) <= 4)
 398         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 399
 400     if (GET_LMASK64(arg2) <= 3)
 401         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 402
 403     if (GET_LMASK64(arg2) <= 2)
 404         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 405
 406     if (GET_LMASK64(arg2) <= 1)
 407         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 408
 409     if (GET_LMASK64(arg2) <= 0)
 410         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 411 }
 412
 413 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 414                 int mem_idx)
 415 {
 416     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 417
 418     if (GET_LMASK64(arg2) >= 1)
 419         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 420
 421     if (GET_LMASK64(arg2) >= 2)
 422         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 423
 424     if (GET_LMASK64(arg2) >= 3)
 425         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 426
 427     if (GET_LMASK64(arg2) >= 4)
 428         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 429
 430     if (GET_LMASK64(arg2) >= 5)
 431         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 432
 433     if (GET_LMASK64(arg2) >= 6)
 434         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 435
 436     if (GET_LMASK64(arg2) == 7)
 437         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 438 }
 439 #endif /* TARGET_MIPS64 */
 440
 441 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 442
 443 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 444                 uint32_t mem_idx)
 445 {
 446     target_ulong base_reglist = reglist & 0xf;
 447     target_ulong do_r31 = reglist & 0x10;
 448
 449     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 450         target_ulong i;
 451
 452         for (i = 0; i < base_reglist; i++) {
 453             env->active_tc.gpr[multiple_regs[i]] =
 454                 (target_long)do_lw(env, addr, mem_idx);
 455             addr += 4;
 456         }
 457     }
 458
 459     if (do_r31) {
 460         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 461     }
 462 }
 463
 464 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 465                 uint32_t mem_idx)
 466 {
 467     target_ulong base_reglist = reglist & 0xf;
 468     target_ulong do_r31 = reglist & 0x10;
 469
 470     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 471         target_ulong i;
 472
 473         for (i = 0; i < base_reglist; i++) {
 474             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 475             addr += 4;
 476         }
 477     }
 478
 479     if (do_r31) {
 480         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 481     }
 482 }
 483
 484 #if defined(TARGET_MIPS64)
 485 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 486                 uint32_t mem_idx)
 487 {
 488     target_ulong base_reglist = reglist & 0xf;
 489     target_ulong do_r31 = reglist & 0x10;
 490
 491     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 492         target_ulong i;
 493
 494         for (i = 0; i < base_reglist; i++) {
 495             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 496             addr += 8;
 497         }
 498     }
 499
 500     if (do_r31) {
 501         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 502     }
 503 }
 504
 505 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 506                 uint32_t mem_idx)
 507 {
 508     target_ulong base_reglist = reglist & 0xf;
 509     target_ulong do_r31 = reglist & 0x10;
 510
 511     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 512         target_ulong i;
 513
 514         for (i = 0; i < base_reglist; i++) {
 515             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 516             addr += 8;
 517         }
 518     }
 519
 520     if (do_r31) {
 521         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 522     }
 523 }
 524 #endif
 525
 526 #ifndef CONFIG_USER_ONLY
 527 /* SMP helpers.  */
 528 static bool mips_vpe_is_wfi(MIPSCPU *c)
 529 {
 530     CPUMIPSState *env = &c->env;
 531
 532     /* If the VPE is halted but otherwise active, it means it's waiting for
 533        an interrupt.  */
 534     return env->halted && mips_vpe_active(env);
 535 }
 536
 537 static inline void mips_vpe_wake(CPUMIPSState *c)
 538 {
 539     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 540        because there might be other conditions that state that c should
 541        be sleeping.  */
 542     cpu_interrupt(c, CPU_INTERRUPT_WAKE);
 543 }
 544
 545 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 546 {
 547     CPUMIPSState *c = &cpu->env;
 548
 549     /* The VPE was shut off, really go to bed.
 550        Reset any old _WAKE requests.  */
 551     c->halted = 1;
 552     cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
 553 }
 554
 555 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 556 {
 557     CPUMIPSState *c = &cpu->env;
 558
 559     /* FIXME: TC reschedule.  */
 560     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 561         mips_vpe_wake(c);
 562     }
 563 }
 564
 565 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 566 {
 567     CPUMIPSState *c = &cpu->env;
 568
 569     /* FIXME: TC reschedule.  */
 570     if (!mips_vpe_active(c)) {
 571         mips_vpe_sleep(cpu);
 572     }
 573 }
 574
 575 /**
 576  * mips_cpu_map_tc:
 577  * @env: CPU from which mapping is performed.
 578  * @tc: Should point to an int with the value of the global TC index.
 579  *
 580  * This function will transform @tc into a local index within the
 581  * returned #CPUMIPSState.
 582  */
 583 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 584           which depends on runtime setup. Can probably be fixed by
 585           walking the list of CPUMIPSStates.  */
 586 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 587 {
 588     MIPSCPU *cpu;
 589     CPUState *cs;
 590     CPUState *other_cs;
 591     int vpe_idx;
 592     int tc_idx = *tc;
 593
 594     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 595         /* Not allowed to address other CPUs.  */
 596         *tc = env->current_tc;
 597         return env;
 598     }
 599
 600     cs = CPU(mips_env_get_cpu(env));
 601     vpe_idx = tc_idx / cs->nr_threads;
 602     *tc = tc_idx % cs->nr_threads;
 603     other_cs = qemu_get_cpu(vpe_idx);
 604     if (other_cs == NULL) {
 605         return env;
 606     }
 607     cpu = MIPS_CPU(other_cs);
 608     return &cpu->env;
 609 }
 610
 611 /* The per VPE CP0_Status register shares some fields with the per TC
 612    CP0_TCStatus registers. These fields are wired to the same registers,
 613    so changes to either of them should be reflected on both registers.
 614
 615    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 616
 617    These helper call synchronizes the regs for a given cpu.  */
 618
 619 /* Called for updates to CP0_Status.  */
 620 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 621 {
 622     int32_t tcstatus, *tcst;
 623     uint32_t v = cpu->CP0_Status;
 624     uint32_t cu, mx, asid, ksu;
 625     uint32_t mask = ((1 << CP0TCSt_TCU3)
 626                        | (1 << CP0TCSt_TCU2)
 627                        | (1 << CP0TCSt_TCU1)
 628                        | (1 << CP0TCSt_TCU0)
 629                        | (1 << CP0TCSt_TMX)
 630                        | (3 << CP0TCSt_TKSU)
 631                        | (0xff << CP0TCSt_TASID));
 632
 633     cu = (v >> CP0St_CU0) & 0xf;
 634     mx = (v >> CP0St_MX) & 0x1;
 635     ksu = (v >> CP0St_KSU) & 0x3;
 636     asid = env->CP0_EntryHi & 0xff;
 637
 638     tcstatus = cu << CP0TCSt_TCU0;
 639     tcstatus |= mx << CP0TCSt_TMX;
 640     tcstatus |= ksu << CP0TCSt_TKSU;
 641     tcstatus |= asid;
 642
 643     if (tc == cpu->current_tc) {
 644         tcst = &cpu->active_tc.CP0_TCStatus;
 645     } else {
 646         tcst = &cpu->tcs[tc].CP0_TCStatus;
 647     }
 648
 649     *tcst &= ~mask;
 650     *tcst |= tcstatus;
 651     compute_hflags(cpu);
 652 }
 653
 654 /* Called for updates to CP0_TCStatus.  */
 655 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 656                              target_ulong v)
 657 {
 658     uint32_t status;
 659     uint32_t tcu, tmx, tasid, tksu;
 660     uint32_t mask = ((1 << CP0St_CU3)
 661                        | (1 << CP0St_CU2)
 662                        | (1 << CP0St_CU1)
 663                        | (1 << CP0St_CU0)
 664                        | (1 << CP0St_MX)
 665                        | (3 << CP0St_KSU));
 666
 667     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 668     tmx = (v >> CP0TCSt_TMX) & 0x1;
 669     tasid = v & 0xff;
 670     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 671
 672     status = tcu << CP0St_CU0;
 673     status |= tmx << CP0St_MX;
 674     status |= tksu << CP0St_KSU;
 675
 676     cpu->CP0_Status &= ~mask;
 677     cpu->CP0_Status |= status;
 678
 679     /* Sync the TASID with EntryHi.  */
 680     cpu->CP0_EntryHi &= ~0xff;
 681     cpu->CP0_EntryHi = tasid;
 682
 683     compute_hflags(cpu);
 684 }
 685
 686 /* Called for updates to CP0_EntryHi.  */
 687 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 688 {
 689     int32_t *tcst;
 690     uint32_t asid, v = cpu->CP0_EntryHi;
 691
 692     asid = v & 0xff;
 693
 694     if (tc == cpu->current_tc) {
 695         tcst = &cpu->active_tc.CP0_TCStatus;
 696     } else {
 697         tcst = &cpu->tcs[tc].CP0_TCStatus;
 698     }
 699
 700     *tcst &= ~0xff;
 701     *tcst |= asid;
 702 }
 703
 704 /* CP0 helpers */
 705 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 706 {
 707     return env->mvp->CP0_MVPControl;
 708 }
 709
 710 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 711 {
 712     return env->mvp->CP0_MVPConf0;
 713 }
 714
 715 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 716 {
 717     return env->mvp->CP0_MVPConf1;
 718 }
 719
 720 target_ulong helper_mfc0_random(CPUMIPSState *env)
 721 {
 722     return (int32_t)cpu_mips_get_random(env);
 723 }
 724
 725 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 726 {
 727     return env->active_tc.CP0_TCStatus;
 728 }
 729
 730 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 731 {
 732     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 733     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 734
 735     if (other_tc == other->current_tc)
 736         return other->active_tc.CP0_TCStatus;
 737     else
 738         return other->tcs[other_tc].CP0_TCStatus;
 739 }
 740
 741 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 742 {
 743     return env->active_tc.CP0_TCBind;
 744 }
 745
 746 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 747 {
 748     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 749     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 750
 751     if (other_tc == other->current_tc)
 752         return other->active_tc.CP0_TCBind;
 753     else
 754         return other->tcs[other_tc].CP0_TCBind;
 755 }
 756
 757 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 758 {
 759     return env->active_tc.PC;
 760 }
 761
 762 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 763 {
 764     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 765     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 766
 767     if (other_tc == other->current_tc)
 768         return other->active_tc.PC;
 769     else
 770         return other->tcs[other_tc].PC;
 771 }
 772
 773 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 774 {
 775     return env->active_tc.CP0_TCHalt;
 776 }
 777
 778 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 779 {
 780     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 781     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 782
 783     if (other_tc == other->current_tc)
 784         return other->active_tc.CP0_TCHalt;
 785     else
 786         return other->tcs[other_tc].CP0_TCHalt;
 787 }
 788
 789 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 790 {
 791     return env->active_tc.CP0_TCContext;
 792 }
 793
 794 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 795 {
 796     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 797     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 798
 799     if (other_tc == other->current_tc)
 800         return other->active_tc.CP0_TCContext;
 801     else
 802         return other->tcs[other_tc].CP0_TCContext;
 803 }
 804
 805 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 806 {
 807     return env->active_tc.CP0_TCSchedule;
 808 }
 809
 810 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 811 {
 812     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 813     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 814
 815     if (other_tc == other->current_tc)
 816         return other->active_tc.CP0_TCSchedule;
 817     else
 818         return other->tcs[other_tc].CP0_TCSchedule;
 819 }
 820
 821 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 822 {
 823     return env->active_tc.CP0_TCScheFBack;
 824 }
 825
 826 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 827 {
 828     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 829     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 830
 831     if (other_tc == other->current_tc)
 832         return other->active_tc.CP0_TCScheFBack;
 833     else
 834         return other->tcs[other_tc].CP0_TCScheFBack;
 835 }
 836
 837 target_ulong helper_mfc0_count(CPUMIPSState *env)
 838 {
 839     return (int32_t)cpu_mips_get_count(env);
 840 }
 841
 842 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 843 {
 844     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 845     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 846
 847     return other->CP0_EntryHi;
 848 }
 849
 850 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 851 {
 852     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 853     int32_t tccause;
 854     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 855
 856     if (other_tc == other->current_tc) {
 857         tccause = other->CP0_Cause;
 858     } else {
 859         tccause = other->CP0_Cause;
 860     }
 861
 862     return tccause;
 863 }
 864
 865 target_ulong helper_mftc0_status(CPUMIPSState *env)
 866 {
 867     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 868     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 869
 870     return other->CP0_Status;
 871 }
 872
 873 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 874 {
 875     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 876 }
 877
 878 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 879 {
 880     return (int32_t)env->CP0_WatchLo[sel];
 881 }
 882
 883 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 884 {
 885     return env->CP0_WatchHi[sel];
 886 }
 887
 888 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 889 {
 890     target_ulong t0 = env->CP0_Debug;
 891     if (env->hflags & MIPS_HFLAG_DM)
 892         t0 |= 1 << CP0DB_DM;
 893
 894     return t0;
 895 }
 896
 897 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 898 {
 899     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 900     int32_t tcstatus;
 901     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 902
 903     if (other_tc == other->current_tc)
 904         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 905     else
 906         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 907
 908     /* XXX: Might be wrong, check with EJTAG spec. */
 909     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 910             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 911 }
 912
 913 #if defined(TARGET_MIPS64)
 914 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 915 {
 916     return env->active_tc.PC;
 917 }
 918
 919 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 920 {
 921     return env->active_tc.CP0_TCHalt;
 922 }
 923
 924 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 925 {
 926     return env->active_tc.CP0_TCContext;
 927 }
 928
 929 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 930 {
 931     return env->active_tc.CP0_TCSchedule;
 932 }
 933
 934 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 935 {
 936     return env->active_tc.CP0_TCScheFBack;
 937 }
 938
 939 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 940 {
 941     return env->lladdr >> env->CP0_LLAddr_shift;
 942 }
 943
 944 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 945 {
 946     return env->CP0_WatchLo[sel];
 947 }
 948 #endif /* TARGET_MIPS64 */
 949
 950 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 951 {
 952     int num = 1;
 953     unsigned int tmp = env->tlb->nb_tlb;
 954
 955     do {
 956         tmp >>= 1;
 957         num <<= 1;
 958     } while (tmp);
 959     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 960 }
 961
 962 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 963 {
 964     uint32_t mask = 0;
 965     uint32_t newval;
 966
 967     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 968         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 969                 (1 << CP0MVPCo_EVP);
 970     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 971         mask |= (1 << CP0MVPCo_STLB);
 972     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 973
 974     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 975
 976     env->mvp->CP0_MVPControl = newval;
 977 }
 978
 979 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 980 {
 981     uint32_t mask;
 982     uint32_t newval;
 983
 984     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 985            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 986     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 987
 988     /* Yield scheduler intercept not implemented. */
 989     /* Gating storage scheduler intercept not implemented. */
 990
 991     // TODO: Enable/disable TCs.
 992
 993     env->CP0_VPEControl = newval;
 994 }
 995
 996 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 997 {
 998     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 999     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1000     uint32_t mask;
1001     uint32_t newval;
1002
1003     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1004            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1005     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1006
1007     /* TODO: Enable/disable TCs.  */
1008
1009     other->CP0_VPEControl = newval;
1010 }
1011
1012 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1013 {
1014     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1015     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1016     /* FIXME: Mask away return zero on read bits.  */
1017     return other->CP0_VPEControl;
1018 }
1019
1020 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1021 {
1022     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1023     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1024
1025     return other->CP0_VPEConf0;
1026 }
1027
1028 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1029 {
1030     uint32_t mask = 0;
1031     uint32_t newval;
1032
1033     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1034         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1035             mask |= (0xff << CP0VPEC0_XTC);
1036         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1037     }
1038     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1039
1040     // TODO: TC exclusive handling due to ERL/EXL.
1041
1042     env->CP0_VPEConf0 = newval;
1043 }
1044
1045 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1046 {
1047     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1048     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1049     uint32_t mask = 0;
1050     uint32_t newval;
1051
1052     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1053     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1054
1055     /* TODO: TC exclusive handling due to ERL/EXL.  */
1056     other->CP0_VPEConf0 = newval;
1057 }
1058
1059 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1060 {
1061     uint32_t mask = 0;
1062     uint32_t newval;
1063
1064     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1065         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1066                 (0xff << CP0VPEC1_NCP1);
1067     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1068
1069     /* UDI not implemented. */
1070     /* CP2 not implemented. */
1071
1072     // TODO: Handle FPU (CP1) binding.
1073
1074     env->CP0_VPEConf1 = newval;
1075 }
1076
1077 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1078 {
1079     /* Yield qualifier inputs not implemented. */
1080     env->CP0_YQMask = 0x00000000;
1081 }
1082
1083 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1084 {
1085     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1086 }
1087
1088 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1089 {
1090     /* Large physaddr (PABITS) not implemented */
1091     /* 1k pages not implemented */
1092     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1093 }
1094
1095 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1096 {
1097     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1098     uint32_t newval;
1099
1100     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1101
1102     env->active_tc.CP0_TCStatus = newval;
1103     sync_c0_tcstatus(env, env->current_tc, newval);
1104 }
1105
1106 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1107 {
1108     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1109     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1110
1111     if (other_tc == other->current_tc)
1112         other->active_tc.CP0_TCStatus = arg1;
1113     else
1114         other->tcs[other_tc].CP0_TCStatus = arg1;
1115     sync_c0_tcstatus(other, other_tc, arg1);
1116 }
1117
1118 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1119 {
1120     uint32_t mask = (1 << CP0TCBd_TBE);
1121     uint32_t newval;
1122
1123     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1124         mask |= (1 << CP0TCBd_CurVPE);
1125     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1126     env->active_tc.CP0_TCBind = newval;
1127 }
1128
1129 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1130 {
1131     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1132     uint32_t mask = (1 << CP0TCBd_TBE);
1133     uint32_t newval;
1134     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1135
1136     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1137         mask |= (1 << CP0TCBd_CurVPE);
1138     if (other_tc == other->current_tc) {
1139         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1140         other->active_tc.CP0_TCBind = newval;
1141     } else {
1142         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1143         other->tcs[other_tc].CP0_TCBind = newval;
1144     }
1145 }
1146
1147 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1148 {
1149     env->active_tc.PC = arg1;
1150     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1151     env->lladdr = 0ULL;
1152     /* MIPS16 not implemented. */
1153 }
1154
1155 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1156 {
1157     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1158     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1159
1160     if (other_tc == other->current_tc) {
1161         other->active_tc.PC = arg1;
1162         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1163         other->lladdr = 0ULL;
1164         /* MIPS16 not implemented. */
1165     } else {
1166         other->tcs[other_tc].PC = arg1;
1167         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1168         other->lladdr = 0ULL;
1169         /* MIPS16 not implemented. */
1170     }
1171 }
1172
1173 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1174 {
1175     MIPSCPU *cpu = mips_env_get_cpu(env);
1176
1177     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1178
1179     // TODO: Halt TC / Restart (if allocated+active) TC.
1180     if (env->active_tc.CP0_TCHalt & 1) {
1181         mips_tc_sleep(cpu, env->current_tc);
1182     } else {
1183         mips_tc_wake(cpu, env->current_tc);
1184     }
1185 }
1186
1187 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1188 {
1189     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1190     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1191     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1192
1193     // TODO: Halt TC / Restart (if allocated+active) TC.
1194
1195     if (other_tc == other->current_tc)
1196         other->active_tc.CP0_TCHalt = arg1;
1197     else
1198         other->tcs[other_tc].CP0_TCHalt = arg1;
1199
1200     if (arg1 & 1) {
1201         mips_tc_sleep(other_cpu, other_tc);
1202     } else {
1203         mips_tc_wake(other_cpu, other_tc);
1204     }
1205 }
1206
1207 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1208 {
1209     env->active_tc.CP0_TCContext = arg1;
1210 }
1211
1212 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1213 {
1214     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1215     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1216
1217     if (other_tc == other->current_tc)
1218         other->active_tc.CP0_TCContext = arg1;
1219     else
1220         other->tcs[other_tc].CP0_TCContext = arg1;
1221 }
1222
1223 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1224 {
1225     env->active_tc.CP0_TCSchedule = arg1;
1226 }
1227
1228 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1229 {
1230     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1231     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1232
1233     if (other_tc == other->current_tc)
1234         other->active_tc.CP0_TCSchedule = arg1;
1235     else
1236         other->tcs[other_tc].CP0_TCSchedule = arg1;
1237 }
1238
1239 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1240 {
1241     env->active_tc.CP0_TCScheFBack = arg1;
1242 }
1243
1244 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1245 {
1246     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1247     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1248
1249     if (other_tc == other->current_tc)
1250         other->active_tc.CP0_TCScheFBack = arg1;
1251     else
1252         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1253 }
1254
1255 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1256 {
1257     /* Large physaddr (PABITS) not implemented */
1258     /* 1k pages not implemented */
1259     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1260 }
1261
1262 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1263 {
1264     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1265 }
1266
1267 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1268 {
1269     /* 1k pages not implemented */
1270     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1271 }
1272
1273 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1274 {
1275     /* SmartMIPS not implemented */
1276     /* Large physaddr (PABITS) not implemented */
1277     /* 1k pages not implemented */
1278     env->CP0_PageGrain = 0;
1279 }
1280
1281 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1282 {
1283     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1284 }
1285
1286 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1287 {
1288     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1289 }
1290
1291 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1292 {
1293     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1294 }
1295
1296 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1297 {
1298     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1299 }
1300
1301 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1302 {
1303     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1304 }
1305
1306 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1307 {
1308     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1309 }
1310
1311 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1312 {
1313     env->CP0_HWREna = arg1 & 0x0000000F;
1314 }
1315
1316 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1317 {
1318     cpu_mips_store_count(env, arg1);
1319 }
1320
1321 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1322 {
1323     target_ulong old, val;
1324
1325     /* 1k pages not implemented */
1326     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1327 #if defined(TARGET_MIPS64)
1328     val &= env->SEGMask;
1329 #endif
1330     old = env->CP0_EntryHi;
1331     env->CP0_EntryHi = val;
1332     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1333         sync_c0_entryhi(env, env->current_tc);
1334     }
1335     /* If the ASID changes, flush qemu's TLB.  */
1336     if ((old & 0xFF) != (val & 0xFF))
1337         cpu_mips_tlb_flush(env, 1);
1338 }
1339
1340 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1341 {
1342     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1343     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1344
1345     other->CP0_EntryHi = arg1;
1346     sync_c0_entryhi(other, other_tc);
1347 }
1348
1349 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1350 {
1351     cpu_mips_store_compare(env, arg1);
1352 }
1353
1354 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1355 {
1356     uint32_t val, old;
1357     uint32_t mask = env->CP0_Status_rw_bitmask;
1358
1359     val = arg1 & mask;
1360     old = env->CP0_Status;
1361     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1362     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1363         sync_c0_status(env, env, env->current_tc);
1364     } else {
1365         compute_hflags(env);
1366     }
1367
1368     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1369         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1370                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1371                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1372                 env->CP0_Cause);
1373         switch (env->hflags & MIPS_HFLAG_KSU) {
1374         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1375         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1376         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1377         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1378         }
1379     }
1380 }
1381
1382 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1383 {
1384     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1385     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1386
1387     other->CP0_Status = arg1 & ~0xf1000018;
1388     sync_c0_status(env, other, other_tc);
1389 }
1390
1391 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1392 {
1393     /* vectored interrupts not implemented, no performance counters. */
1394     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1395 }
1396
1397 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1398 {
1399     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1400     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1401 }
1402
1403 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1404 {
1405     uint32_t mask = 0x00C00300;
1406     uint32_t old = cpu->CP0_Cause;
1407     int i;
1408
1409     if (cpu->insn_flags & ISA_MIPS32R2) {
1410         mask |= 1 << CP0Ca_DC;
1411     }
1412
1413     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1414
1415     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1416         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1417             cpu_mips_stop_count(cpu);
1418         } else {
1419             cpu_mips_start_count(cpu);
1420         }
1421     }
1422
1423     /* Set/reset software interrupts */
1424     for (i = 0 ; i < 2 ; i++) {
1425         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1426             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1427         }
1428     }
1429 }
1430
1431 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1432 {
1433     mtc0_cause(env, arg1);
1434 }
1435
1436 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1437 {
1438     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1439     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1440
1441     mtc0_cause(other, arg1);
1442 }
1443
1444 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1445 {
1446     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1447     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1448
1449     return other->CP0_EPC;
1450 }
1451
1452 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1453 {
1454     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1455     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1456
1457     return other->CP0_EBase;
1458 }
1459
1460 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1461 {
1462     /* vectored interrupts not implemented */
1463     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1464 }
1465
1466 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1467 {
1468     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1469     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1470     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1471 }
1472
1473 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1474 {
1475     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1476     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1477
1478     switch (idx) {
1479     case 0: return other->CP0_Config0;
1480     case 1: return other->CP0_Config1;
1481     case 2: return other->CP0_Config2;
1482     case 3: return other->CP0_Config3;
1483     /* 4 and 5 are reserved.  */
1484     case 6: return other->CP0_Config6;
1485     case 7: return other->CP0_Config7;
1486     default:
1487         break;
1488     }
1489     return 0;
1490 }
1491
1492 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1493 {
1494     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1495 }
1496
1497 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1498 {
1499     /* tertiary/secondary caches not implemented */
1500     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1501 }
1502
1503 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1504 {
1505     target_long mask = env->CP0_LLAddr_rw_bitmask;
1506     arg1 = arg1 << env->CP0_LLAddr_shift;
1507     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1508 }
1509
1510 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1511 {
1512     /* Watch exceptions for instructions, data loads, data stores
1513        not implemented. */
1514     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1515 }
1516
1517 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1518 {
1519     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1520     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1521 }
1522
1523 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1524 {
1525     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1526     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1527 }
1528
1529 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1530 {
1531     env->CP0_Framemask = arg1; /* XXX */
1532 }
1533
1534 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1535 {
1536     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1537     if (arg1 & (1 << CP0DB_DM))
1538         env->hflags |= MIPS_HFLAG_DM;
1539     else
1540         env->hflags &= ~MIPS_HFLAG_DM;
1541 }
1542
1543 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1544 {
1545     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1546     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1547     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1548
1549     /* XXX: Might be wrong, check with EJTAG spec. */
1550     if (other_tc == other->current_tc)
1551         other->active_tc.CP0_Debug_tcstatus = val;
1552     else
1553         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1554     other->CP0_Debug = (other->CP0_Debug &
1555                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1556                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1557 }
1558
1559 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1560 {
1561     env->CP0_Performance0 = arg1 & 0x000007ff;
1562 }
1563
1564 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1565 {
1566     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1567 }
1568
1569 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1570 {
1571     env->CP0_DataLo = arg1; /* XXX */
1572 }
1573
1574 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1575 {
1576     env->CP0_TagHi = arg1; /* XXX */
1577 }
1578
1579 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1580 {
1581     env->CP0_DataHi = arg1; /* XXX */
1582 }
1583
1584 /* MIPS MT functions */
1585 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1586 {
1587     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1588     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1589
1590     if (other_tc == other->current_tc)
1591         return other->active_tc.gpr[sel];
1592     else
1593         return other->tcs[other_tc].gpr[sel];
1594 }
1595
1596 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1597 {
1598     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1599     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1600
1601     if (other_tc == other->current_tc)
1602         return other->active_tc.LO[sel];
1603     else
1604         return other->tcs[other_tc].LO[sel];
1605 }
1606
1607 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1608 {
1609     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1610     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1611
1612     if (other_tc == other->current_tc)
1613         return other->active_tc.HI[sel];
1614     else
1615         return other->tcs[other_tc].HI[sel];
1616 }
1617
1618 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1619 {
1620     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1621     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1622
1623     if (other_tc == other->current_tc)
1624         return other->active_tc.ACX[sel];
1625     else
1626         return other->tcs[other_tc].ACX[sel];
1627 }
1628
1629 target_ulong helper_mftdsp(CPUMIPSState *env)
1630 {
1631     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1632     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1633
1634     if (other_tc == other->current_tc)
1635         return other->active_tc.DSPControl;
1636     else
1637         return other->tcs[other_tc].DSPControl;
1638 }
1639
1640 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1641 {
1642     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1643     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1644
1645     if (other_tc == other->current_tc)
1646         other->active_tc.gpr[sel] = arg1;
1647     else
1648         other->tcs[other_tc].gpr[sel] = arg1;
1649 }
1650
1651 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1652 {
1653     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1654     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1655
1656     if (other_tc == other->current_tc)
1657         other->active_tc.LO[sel] = arg1;
1658     else
1659         other->tcs[other_tc].LO[sel] = arg1;
1660 }
1661
1662 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1663 {
1664     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1665     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1666
1667     if (other_tc == other->current_tc)
1668         other->active_tc.HI[sel] = arg1;
1669     else
1670         other->tcs[other_tc].HI[sel] = arg1;
1671 }
1672
1673 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1674 {
1675     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1676     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1677
1678     if (other_tc == other->current_tc)
1679         other->active_tc.ACX[sel] = arg1;
1680     else
1681         other->tcs[other_tc].ACX[sel] = arg1;
1682 }
1683
1684 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1685 {
1686     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1687     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1688
1689     if (other_tc == other->current_tc)
1690         other->active_tc.DSPControl = arg1;
1691     else
1692         other->tcs[other_tc].DSPControl = arg1;
1693 }
1694
1695 /* MIPS MT functions */
1696 target_ulong helper_dmt(void)
1697 {
1698     // TODO
1699      return 0;
1700 }
1701
1702 target_ulong helper_emt(void)
1703 {
1704     // TODO
1705     return 0;
1706 }
1707
1708 target_ulong helper_dvpe(CPUMIPSState *env)
1709 {
1710     CPUMIPSState *other_cpu_env = first_cpu;
1711     target_ulong prev = env->mvp->CP0_MVPControl;
1712
1713     do {
1714         /* Turn off all VPEs except the one executing the dvpe.  */
1715         if (other_cpu_env != env) {
1716             MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1717
1718             other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1719             mips_vpe_sleep(other_cpu);
1720         }
1721         other_cpu_env = other_cpu_env->next_cpu;
1722     } while (other_cpu_env);
1723     return prev;
1724 }
1725
1726 target_ulong helper_evpe(CPUMIPSState *env)
1727 {
1728     CPUMIPSState *other_cpu_env = first_cpu;
1729     target_ulong prev = env->mvp->CP0_MVPControl;
1730
1731     do {
1732         MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1733
1734         if (other_cpu_env != env
1735             /* If the VPE is WFI, don't disturb its sleep.  */
1736             && !mips_vpe_is_wfi(other_cpu)) {
1737             /* Enable the VPE.  */
1738             other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1739             mips_vpe_wake(other_cpu_env); /* And wake it up.  */
1740         }
1741         other_cpu_env = other_cpu_env->next_cpu;
1742     } while (other_cpu_env);
1743     return prev;
1744 }
1745 #endif /* !CONFIG_USER_ONLY */
1746
1747 void helper_fork(target_ulong arg1, target_ulong arg2)
1748 {
1749     // arg1 = rt, arg2 = rs
1750     arg1 = 0;
1751     // TODO: store to TC register
1752 }
1753
1754 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1755 {
1756     target_long arg1 = arg;
1757
1758     if (arg1 < 0) {
1759         /* No scheduling policy implemented. */
1760         if (arg1 != -2) {
1761             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1762                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1763                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1764                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1765                 helper_raise_exception(env, EXCP_THREAD);
1766             }
1767         }
1768     } else if (arg1 == 0) {
1769         if (0 /* TODO: TC underflow */) {
1770             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1771             helper_raise_exception(env, EXCP_THREAD);
1772         } else {
1773             // TODO: Deallocate TC
1774         }
1775     } else if (arg1 > 0) {
1776         /* Yield qualifier inputs not implemented. */
1777         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1778         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1779         helper_raise_exception(env, EXCP_THREAD);
1780     }
1781     return env->CP0_YQMask;
1782 }
1783
1784 #ifndef CONFIG_USER_ONLY
1785 /* TLB management */
1786 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1787 {
1788     /* Flush qemu's TLB and discard all shadowed entries.  */
1789     tlb_flush (env, flush_global);
1790     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1791 }
1792
1793 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1794 {
1795     /* Discard entries from env->tlb[first] onwards.  */
1796     while (env->tlb->tlb_in_use > first) {
1797         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1798     }
1799 }
1800
1801 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1802 {
1803     r4k_tlb_t *tlb;
1804
1805     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1806     tlb = &env->tlb->mmu.r4k.tlb[idx];
1807     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1808 #if defined(TARGET_MIPS64)
1809     tlb->VPN &= env->SEGMask;
1810 #endif
1811     tlb->ASID = env->CP0_EntryHi & 0xFF;
1812     tlb->PageMask = env->CP0_PageMask;
1813     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1814     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1815     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1816     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1817     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1818     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1819     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1820     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1821     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1822 }
1823
1824 void r4k_helper_tlbwi(CPUMIPSState *env)
1825 {
1826     r4k_tlb_t *tlb;
1827     int idx;
1828     target_ulong VPN;
1829     uint8_t ASID;
1830     bool G, V0, D0, V1, D1;
1831
1832     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1833     tlb = &env->tlb->mmu.r4k.tlb[idx];
1834     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1835 #if defined(TARGET_MIPS64)
1836     VPN &= env->SEGMask;
1837 #endif
1838     ASID = env->CP0_EntryHi & 0xff;
1839     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1840     V0 = (env->CP0_EntryLo0 & 2) != 0;
1841     D0 = (env->CP0_EntryLo0 & 4) != 0;
1842     V1 = (env->CP0_EntryLo1 & 2) != 0;
1843     D1 = (env->CP0_EntryLo1 & 4) != 0;
1844
1845     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1846        permissions on the current entry. */
1847     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1848         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1849         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1850         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1851     }
1852
1853     r4k_invalidate_tlb(env, idx, 0);
1854     r4k_fill_tlb(env, idx);
1855 }
1856
1857 void r4k_helper_tlbwr(CPUMIPSState *env)
1858 {
1859     int r = cpu_mips_get_random(env);
1860
1861     r4k_invalidate_tlb(env, r, 1);
1862     r4k_fill_tlb(env, r);
1863 }
1864
1865 void r4k_helper_tlbp(CPUMIPSState *env)
1866 {
1867     r4k_tlb_t *tlb;
1868     target_ulong mask;
1869     target_ulong tag;
1870     target_ulong VPN;
1871     uint8_t ASID;
1872     int i;
1873
1874     ASID = env->CP0_EntryHi & 0xFF;
1875     for (i = 0; i < env->tlb->nb_tlb; i++) {
1876         tlb = &env->tlb->mmu.r4k.tlb[i];
1877         /* 1k pages are not supported. */
1878         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1879         tag = env->CP0_EntryHi & ~mask;
1880         VPN = tlb->VPN & ~mask;
1881 #if defined(TARGET_MIPS64)
1882         tag &= env->SEGMask;
1883 #endif
1884         /* Check ASID, virtual page number & size */
1885         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1886             /* TLB match */
1887             env->CP0_Index = i;
1888             break;
1889         }
1890     }
1891     if (i == env->tlb->nb_tlb) {
1892         /* No match.  Discard any shadow entries, if any of them match.  */
1893         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1894             tlb = &env->tlb->mmu.r4k.tlb[i];
1895             /* 1k pages are not supported. */
1896             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1897             tag = env->CP0_EntryHi & ~mask;
1898             VPN = tlb->VPN & ~mask;
1899 #if defined(TARGET_MIPS64)
1900             tag &= env->SEGMask;
1901 #endif
1902             /* Check ASID, virtual page number & size */
1903             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1904                 r4k_mips_tlb_flush_extra (env, i);
1905                 break;
1906             }
1907         }
1908
1909         env->CP0_Index |= 0x80000000;
1910     }
1911 }
1912
1913 void r4k_helper_tlbr(CPUMIPSState *env)
1914 {
1915     r4k_tlb_t *tlb;
1916     uint8_t ASID;
1917     int idx;
1918
1919     ASID = env->CP0_EntryHi & 0xFF;
1920     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1921     tlb = &env->tlb->mmu.r4k.tlb[idx];
1922
1923     /* If this will change the current ASID, flush qemu's TLB.  */
1924     if (ASID != tlb->ASID)
1925         cpu_mips_tlb_flush (env, 1);
1926
1927     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1928
1929     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1930     env->CP0_PageMask = tlb->PageMask;
1931     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1932                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1933     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1934                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1935 }
1936
1937 void helper_tlbwi(CPUMIPSState *env)
1938 {
1939     env->tlb->helper_tlbwi(env);
1940 }
1941
1942 void helper_tlbwr(CPUMIPSState *env)
1943 {
1944     env->tlb->helper_tlbwr(env);
1945 }
1946
1947 void helper_tlbp(CPUMIPSState *env)
1948 {
1949     env->tlb->helper_tlbp(env);
1950 }
1951
1952 void helper_tlbr(CPUMIPSState *env)
1953 {
1954     env->tlb->helper_tlbr(env);
1955 }
1956
1957 /* Specials */
1958 target_ulong helper_di(CPUMIPSState *env)
1959 {
1960     target_ulong t0 = env->CP0_Status;
1961
1962     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1963     return t0;
1964 }
1965
1966 target_ulong helper_ei(CPUMIPSState *env)
1967 {
1968     target_ulong t0 = env->CP0_Status;
1969
1970     env->CP0_Status = t0 | (1 << CP0St_IE);
1971     return t0;
1972 }
1973
1974 static void debug_pre_eret(CPUMIPSState *env)
1975 {
1976     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1977         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1978                 env->active_tc.PC, env->CP0_EPC);
1979         if (env->CP0_Status & (1 << CP0St_ERL))
1980             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1981         if (env->hflags & MIPS_HFLAG_DM)
1982             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1983         qemu_log("\n");
1984     }
1985 }
1986
1987 static void debug_post_eret(CPUMIPSState *env)
1988 {
1989     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1990         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1991                 env->active_tc.PC, env->CP0_EPC);
1992         if (env->CP0_Status & (1 << CP0St_ERL))
1993             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1994         if (env->hflags & MIPS_HFLAG_DM)
1995             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1996         switch (env->hflags & MIPS_HFLAG_KSU) {
1997         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1998         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1999         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2000         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
2001         }
2002     }
2003 }
2004
2005 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2006 {
2007     env->active_tc.PC = error_pc & ~(target_ulong)1;
2008     if (error_pc & 1) {
2009         env->hflags |= MIPS_HFLAG_M16;
2010     } else {
2011         env->hflags &= ~(MIPS_HFLAG_M16);
2012     }
2013 }
2014
2015 void helper_eret(CPUMIPSState *env)
2016 {
2017     debug_pre_eret(env);
2018     if (env->CP0_Status & (1 << CP0St_ERL)) {
2019         set_pc(env, env->CP0_ErrorEPC);
2020         env->CP0_Status &= ~(1 << CP0St_ERL);
2021     } else {
2022         set_pc(env, env->CP0_EPC);
2023         env->CP0_Status &= ~(1 << CP0St_EXL);
2024     }
2025     compute_hflags(env);
2026     debug_post_eret(env);
2027     env->lladdr = 1;
2028 }
2029
2030 void helper_deret(CPUMIPSState *env)
2031 {
2032     debug_pre_eret(env);
2033     set_pc(env, env->CP0_DEPC);
2034
2035     env->hflags &= MIPS_HFLAG_DM;
2036     compute_hflags(env);
2037     debug_post_eret(env);
2038     env->lladdr = 1;
2039 }
2040 #endif /* !CONFIG_USER_ONLY */
2041
2042 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2043 {
2044     if ((env->hflags & MIPS_HFLAG_CP0) ||
2045         (env->CP0_HWREna & (1 << 0)))
2046         return env->CP0_EBase & 0x3ff;
2047     else
2048         helper_raise_exception(env, EXCP_RI);
2049
2050     return 0;
2051 }
2052
2053 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2054 {
2055     if ((env->hflags & MIPS_HFLAG_CP0) ||
2056         (env->CP0_HWREna & (1 << 1)))
2057         return env->SYNCI_Step;
2058     else
2059         helper_raise_exception(env, EXCP_RI);
2060
2061     return 0;
2062 }
2063
2064 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2065 {
2066     if ((env->hflags & MIPS_HFLAG_CP0) ||
2067         (env->CP0_HWREna & (1 << 2)))
2068         return env->CP0_Count;
2069     else
2070         helper_raise_exception(env, EXCP_RI);
2071
2072     return 0;
2073 }
2074
2075 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2076 {
2077     if ((env->hflags & MIPS_HFLAG_CP0) ||
2078         (env->CP0_HWREna & (1 << 3)))
2079         return env->CCRes;
2080     else
2081         helper_raise_exception(env, EXCP_RI);
2082
2083     return 0;
2084 }
2085
2086 void helper_pmon(CPUMIPSState *env, int function)
2087 {
2088     function /= 2;
2089     switch (function) {
2090     case 2: /* TODO: char inbyte(int waitflag); */
2091         if (env->active_tc.gpr[4] == 0)
2092             env->active_tc.gpr[2] = -1;
2093         /* Fall through */
2094     case 11: /* TODO: char inbyte (void); */
2095         env->active_tc.gpr[2] = -1;
2096         break;
2097     case 3:
2098     case 12:
2099         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2100         break;
2101     case 17:
2102         break;
2103     case 158:
2104         {
2105             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2106             printf("%s", fmt);
2107         }
2108         break;
2109     }
2110 }
2111
2112 void helper_wait(CPUMIPSState *env)
2113 {
2114     env->halted = 1;
2115     cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
2116     helper_raise_exception(env, EXCP_HLT);
2117 }
2118
2119 #if !defined(CONFIG_USER_ONLY)
2120
2121 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2122                                               target_ulong addr, int is_write,
2123                                               int is_user, uintptr_t retaddr);
2124
2125 #define MMUSUFFIX _mmu
2126 #define ALIGNED_ONLY
2127
2128 #define SHIFT 0
2129 #include "exec/softmmu_template.h"
2130
2131 #define SHIFT 1
2132 #include "exec/softmmu_template.h"
2133
2134 #define SHIFT 2
2135 #include "exec/softmmu_template.h"
2136
2137 #define SHIFT 3
2138 #include "exec/softmmu_template.h"
2139
2140 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2141                                 int is_write, int is_user, uintptr_t retaddr)
2142 {
2143     env->CP0_BadVAddr = addr;
2144     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2145 }
2146
2147 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2148               uintptr_t retaddr)
2149 {
2150     int ret;
2151
2152     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2153     if (ret) {
2154         do_raise_exception_err(env, env->exception_index,
2155                                env->error_code, retaddr);
2156     }
2157 }
2158
2159 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
2160                            int is_write, int is_exec, int unused, int size)
2161 {
2162     if (is_exec)
2163         helper_raise_exception(env, EXCP_IBE);
2164     else
2165         helper_raise_exception(env, EXCP_DBE);
2166 }
2167 #endif /* !CONFIG_USER_ONLY */
2168
2169 /* Complex FPU operations which may need stack space. */
2170
2171 #define FLOAT_TWO32 make_float32(1 << 30)
2172 #define FLOAT_TWO64 make_float64(1ULL << 62)
2173 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2174 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2175
2176 /* convert MIPS rounding mode in FCR31 to IEEE library */
2177 static unsigned int ieee_rm[] = {
2178     float_round_nearest_even,
2179     float_round_to_zero,
2180     float_round_up,
2181     float_round_down
2182 };
2183
2184 static inline void restore_rounding_mode(CPUMIPSState *env)
2185 {
2186     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2187                             &env->active_fpu.fp_status);
2188 }
2189
2190 static inline void restore_flush_mode(CPUMIPSState *env)
2191 {
2192     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2193                       &env->active_fpu.fp_status);
2194 }
2195
2196 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2197 {
2198     target_ulong arg1;
2199
2200     switch (reg) {
2201     case 0:
2202         arg1 = (int32_t)env->active_fpu.fcr0;
2203         break;
2204     case 25:
2205         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2206         break;
2207     case 26:
2208         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2209         break;
2210     case 28:
2211         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2212         break;
2213     default:
2214         arg1 = (int32_t)env->active_fpu.fcr31;
2215         break;
2216     }
2217
2218     return arg1;
2219 }
2220
2221 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2222 {
2223     switch(reg) {
2224     case 25:
2225         if (arg1 & 0xffffff00)
2226             return;
2227         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2228                      ((arg1 & 0x1) << 23);
2229         break;
2230     case 26:
2231         if (arg1 & 0x007c0000)
2232             return;
2233         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2234         break;
2235     case 28:
2236         if (arg1 & 0x007c0000)
2237             return;
2238         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2239                      ((arg1 & 0x4) << 22);
2240         break;
2241     case 31:
2242         if (arg1 & 0x007c0000)
2243             return;
2244         env->active_fpu.fcr31 = arg1;
2245         break;
2246     default:
2247         return;
2248     }
2249     /* set rounding mode */
2250     restore_rounding_mode(env);
2251     /* set flush-to-zero mode */
2252     restore_flush_mode(env);
2253     set_float_exception_flags(0, &env->active_fpu.fp_status);
2254     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2255         do_raise_exception(env, EXCP_FPE, GETPC());
2256 }
2257
2258 static inline int ieee_ex_to_mips(int xcpt)
2259 {
2260     int ret = 0;
2261     if (xcpt) {
2262         if (xcpt & float_flag_invalid) {
2263             ret |= FP_INVALID;
2264         }
2265         if (xcpt & float_flag_overflow) {
2266             ret |= FP_OVERFLOW;
2267         }
2268         if (xcpt & float_flag_underflow) {
2269             ret |= FP_UNDERFLOW;
2270         }
2271         if (xcpt & float_flag_divbyzero) {
2272             ret |= FP_DIV0;
2273         }
2274         if (xcpt & float_flag_inexact) {
2275             ret |= FP_INEXACT;
2276         }
2277     }
2278     return ret;
2279 }
2280
2281 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2282 {
2283     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2284
2285     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2286
2287     if (tmp) {
2288         set_float_exception_flags(0, &env->active_fpu.fp_status);
2289
2290         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2291             do_raise_exception(env, EXCP_FPE, pc);
2292         } else {
2293             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2294         }
2295     }
2296 }
2297
2298 /* Float support.
2299    Single precition routines have a "s" suffix, double precision a
2300    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2301    paired single lower "pl", paired single upper "pu".  */
2302
2303 /* unary operations, modifying fp status  */
2304 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2305 {
2306     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2307     update_fcr31(env, GETPC());
2308     return fdt0;
2309 }
2310
2311 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2312 {
2313     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2314     update_fcr31(env, GETPC());
2315     return fst0;
2316 }
2317
2318 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2319 {
2320     uint64_t fdt2;
2321
2322     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2323     update_fcr31(env, GETPC());
2324     return fdt2;
2325 }
2326
2327 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2328 {
2329     uint64_t fdt2;
2330
2331     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2332     update_fcr31(env, GETPC());
2333     return fdt2;
2334 }
2335
2336 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2337 {
2338     uint64_t fdt2;
2339
2340     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2341     update_fcr31(env, GETPC());
2342     return fdt2;
2343 }
2344
2345 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2346 {
2347     uint64_t dt2;
2348
2349     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2350     if (get_float_exception_flags(&env->active_fpu.fp_status)
2351         & (float_flag_invalid | float_flag_overflow)) {
2352         dt2 = FP_TO_INT64_OVERFLOW;
2353     }
2354     update_fcr31(env, GETPC());
2355     return dt2;
2356 }
2357
2358 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2359 {
2360     uint64_t dt2;
2361
2362     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2363     if (get_float_exception_flags(&env->active_fpu.fp_status)
2364         & (float_flag_invalid | float_flag_overflow)) {
2365         dt2 = FP_TO_INT64_OVERFLOW;
2366     }
2367     update_fcr31(env, GETPC());
2368     return dt2;
2369 }
2370
2371 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2372 {
2373     uint32_t fst2;
2374     uint32_t fsth2;
2375
2376     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2377     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2378     update_fcr31(env, GETPC());
2379     return ((uint64_t)fsth2 << 32) | fst2;
2380 }
2381
2382 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2383 {
2384     uint32_t wt2;
2385     uint32_t wth2;
2386     int excp, excph;
2387
2388     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2389     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2390     if (excp & (float_flag_overflow | float_flag_invalid)) {
2391         wt2 = FP_TO_INT32_OVERFLOW;
2392     }
2393
2394     set_float_exception_flags(0, &env->active_fpu.fp_status);
2395     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2396     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2397     if (excph & (float_flag_overflow | float_flag_invalid)) {
2398         wth2 = FP_TO_INT32_OVERFLOW;
2399     }
2400
2401     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2402     update_fcr31(env, GETPC());
2403
2404     return ((uint64_t)wth2 << 32) | wt2;
2405 }
2406
2407 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2408 {
2409     uint32_t fst2;
2410
2411     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2412     update_fcr31(env, GETPC());
2413     return fst2;
2414 }
2415
2416 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2417 {
2418     uint32_t fst2;
2419
2420     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2421     update_fcr31(env, GETPC());
2422     return fst2;
2423 }
2424
2425 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2426 {
2427     uint32_t fst2;
2428
2429     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2430     update_fcr31(env, GETPC());
2431     return fst2;
2432 }
2433
2434 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2435 {
2436     uint32_t wt2;
2437
2438     wt2 = wt0;
2439     update_fcr31(env, GETPC());
2440     return wt2;
2441 }
2442
2443 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2444 {
2445     uint32_t wt2;
2446
2447     wt2 = wth0;
2448     update_fcr31(env, GETPC());
2449     return wt2;
2450 }
2451
2452 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2453 {
2454     uint32_t wt2;
2455
2456     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2457     update_fcr31(env, GETPC());
2458     if (get_float_exception_flags(&env->active_fpu.fp_status)
2459         & (float_flag_invalid | float_flag_overflow)) {
2460         wt2 = FP_TO_INT32_OVERFLOW;
2461     }
2462     return wt2;
2463 }
2464
2465 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2466 {
2467     uint32_t wt2;
2468
2469     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2470     if (get_float_exception_flags(&env->active_fpu.fp_status)
2471         & (float_flag_invalid | float_flag_overflow)) {
2472         wt2 = FP_TO_INT32_OVERFLOW;
2473     }
2474     update_fcr31(env, GETPC());
2475     return wt2;
2476 }
2477
2478 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2479 {
2480     uint64_t dt2;
2481
2482     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2483     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2484     restore_rounding_mode(env);
2485     if (get_float_exception_flags(&env->active_fpu.fp_status)
2486         & (float_flag_invalid | float_flag_overflow)) {
2487         dt2 = FP_TO_INT64_OVERFLOW;
2488     }
2489     update_fcr31(env, GETPC());
2490     return dt2;
2491 }
2492
2493 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2494 {
2495     uint64_t dt2;
2496
2497     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2498     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2499     restore_rounding_mode(env);
2500     if (get_float_exception_flags(&env->active_fpu.fp_status)
2501         & (float_flag_invalid | float_flag_overflow)) {
2502         dt2 = FP_TO_INT64_OVERFLOW;
2503     }
2504     update_fcr31(env, GETPC());
2505     return dt2;
2506 }
2507
2508 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2509 {
2510     uint32_t wt2;
2511
2512     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2513     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2514     restore_rounding_mode(env);
2515     if (get_float_exception_flags(&env->active_fpu.fp_status)
2516         & (float_flag_invalid | float_flag_overflow)) {
2517         wt2 = FP_TO_INT32_OVERFLOW;
2518     }
2519     update_fcr31(env, GETPC());
2520     return wt2;
2521 }
2522
2523 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2524 {
2525     uint32_t wt2;
2526
2527     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2528     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2529     restore_rounding_mode(env);
2530     if (get_float_exception_flags(&env->active_fpu.fp_status)
2531         & (float_flag_invalid | float_flag_overflow)) {
2532         wt2 = FP_TO_INT32_OVERFLOW;
2533     }
2534     update_fcr31(env, GETPC());
2535     return wt2;
2536 }
2537
2538 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2539 {
2540     uint64_t dt2;
2541
2542     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2543     if (get_float_exception_flags(&env->active_fpu.fp_status)
2544         & (float_flag_invalid | float_flag_overflow)) {
2545         dt2 = FP_TO_INT64_OVERFLOW;
2546     }
2547     update_fcr31(env, GETPC());
2548     return dt2;
2549 }
2550
2551 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2552 {
2553     uint64_t dt2;
2554
2555     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2556     if (get_float_exception_flags(&env->active_fpu.fp_status)
2557         & (float_flag_invalid | float_flag_overflow)) {
2558         dt2 = FP_TO_INT64_OVERFLOW;
2559     }
2560     update_fcr31(env, GETPC());
2561     return dt2;
2562 }
2563
2564 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2565 {
2566     uint32_t wt2;
2567
2568     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2569     if (get_float_exception_flags(&env->active_fpu.fp_status)
2570         & (float_flag_invalid | float_flag_overflow)) {
2571         wt2 = FP_TO_INT32_OVERFLOW;
2572     }
2573     update_fcr31(env, GETPC());
2574     return wt2;
2575 }
2576
2577 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2578 {
2579     uint32_t wt2;
2580
2581     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2582     if (get_float_exception_flags(&env->active_fpu.fp_status)
2583         & (float_flag_invalid | float_flag_overflow)) {
2584         wt2 = FP_TO_INT32_OVERFLOW;
2585     }
2586     update_fcr31(env, GETPC());
2587     return wt2;
2588 }
2589
2590 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2591 {
2592     uint64_t dt2;
2593
2594     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2595     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2596     restore_rounding_mode(env);
2597     if (get_float_exception_flags(&env->active_fpu.fp_status)
2598         & (float_flag_invalid | float_flag_overflow)) {
2599         dt2 = FP_TO_INT64_OVERFLOW;
2600     }
2601     update_fcr31(env, GETPC());
2602     return dt2;
2603 }
2604
2605 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2606 {
2607     uint64_t dt2;
2608
2609     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2610     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2611     restore_rounding_mode(env);
2612     if (get_float_exception_flags(&env->active_fpu.fp_status)
2613         & (float_flag_invalid | float_flag_overflow)) {
2614         dt2 = FP_TO_INT64_OVERFLOW;
2615     }
2616     update_fcr31(env, GETPC());
2617     return dt2;
2618 }
2619
2620 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2621 {
2622     uint32_t wt2;
2623
2624     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2625     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2626     restore_rounding_mode(env);
2627     if (get_float_exception_flags(&env->active_fpu.fp_status)
2628         & (float_flag_invalid | float_flag_overflow)) {
2629         wt2 = FP_TO_INT32_OVERFLOW;
2630     }
2631     update_fcr31(env, GETPC());
2632     return wt2;
2633 }
2634
2635 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2636 {
2637     uint32_t wt2;
2638
2639     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2640     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2641     restore_rounding_mode(env);
2642     if (get_float_exception_flags(&env->active_fpu.fp_status)
2643         & (float_flag_invalid | float_flag_overflow)) {
2644         wt2 = FP_TO_INT32_OVERFLOW;
2645     }
2646     update_fcr31(env, GETPC());
2647     return wt2;
2648 }
2649
2650 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2651 {
2652     uint64_t dt2;
2653
2654     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2655     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2656     restore_rounding_mode(env);
2657     if (get_float_exception_flags(&env->active_fpu.fp_status)
2658         & (float_flag_invalid | float_flag_overflow)) {
2659         dt2 = FP_TO_INT64_OVERFLOW;
2660     }
2661     update_fcr31(env, GETPC());
2662     return dt2;
2663 }
2664
2665 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2666 {
2667     uint64_t dt2;
2668
2669     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2670     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2671     restore_rounding_mode(env);
2672     if (get_float_exception_flags(&env->active_fpu.fp_status)
2673         & (float_flag_invalid | float_flag_overflow)) {
2674         dt2 = FP_TO_INT64_OVERFLOW;
2675     }
2676     update_fcr31(env, GETPC());
2677     return dt2;
2678 }
2679
2680 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2681 {
2682     uint32_t wt2;
2683
2684     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2685     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2686     restore_rounding_mode(env);
2687     if (get_float_exception_flags(&env->active_fpu.fp_status)
2688         & (float_flag_invalid | float_flag_overflow)) {
2689         wt2 = FP_TO_INT32_OVERFLOW;
2690     }
2691     update_fcr31(env, GETPC());
2692     return wt2;
2693 }
2694
2695 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2696 {
2697     uint32_t wt2;
2698
2699     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2700     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2701     restore_rounding_mode(env);
2702     if (get_float_exception_flags(&env->active_fpu.fp_status)
2703         & (float_flag_invalid | float_flag_overflow)) {
2704         wt2 = FP_TO_INT32_OVERFLOW;
2705     }
2706     update_fcr31(env, GETPC());
2707     return wt2;
2708 }
2709
2710 /* unary operations, not modifying fp status  */
2711 #define FLOAT_UNOP(name)                                       \
2712 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2713 {                                                              \
2714     return float64_ ## name(fdt0);                             \
2715 }                                                              \
2716 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2717 {                                                              \
2718     return float32_ ## name(fst0);                             \
2719 }                                                              \
2720 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2721 {                                                              \
2722     uint32_t wt0;                                              \
2723     uint32_t wth0;                                             \
2724                                                                \
2725     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2726     wth0 = float32_ ## name(fdt0 >> 32);                       \
2727     return ((uint64_t)wth0 << 32) | wt0;                       \
2728 }
2729 FLOAT_UNOP(abs)
2730 FLOAT_UNOP(chs)
2731 #undef FLOAT_UNOP
2732
2733 /* MIPS specific unary operations */
2734 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2735 {
2736     uint64_t fdt2;
2737
2738     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2739     update_fcr31(env, GETPC());
2740     return fdt2;
2741 }
2742
2743 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2744 {
2745     uint32_t fst2;
2746
2747     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2748     update_fcr31(env, GETPC());
2749     return fst2;
2750 }
2751
2752 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2753 {
2754     uint64_t fdt2;
2755
2756     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2757     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2758     update_fcr31(env, GETPC());
2759     return fdt2;
2760 }
2761
2762 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2763 {
2764     uint32_t fst2;
2765
2766     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2767     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2768     update_fcr31(env, GETPC());
2769     return fst2;
2770 }
2771
2772 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2773 {
2774     uint64_t fdt2;
2775
2776     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2777     update_fcr31(env, GETPC());
2778     return fdt2;
2779 }
2780
2781 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2782 {
2783     uint32_t fst2;
2784
2785     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2786     update_fcr31(env, GETPC());
2787     return fst2;
2788 }
2789
2790 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2791 {
2792     uint32_t fst2;
2793     uint32_t fsth2;
2794
2795     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2796     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2797     update_fcr31(env, GETPC());
2798     return ((uint64_t)fsth2 << 32) | fst2;
2799 }
2800
2801 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2802 {
2803     uint64_t fdt2;
2804
2805     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2806     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2807     update_fcr31(env, GETPC());
2808     return fdt2;
2809 }
2810
2811 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2812 {
2813     uint32_t fst2;
2814
2815     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2816     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2817     update_fcr31(env, GETPC());
2818     return fst2;
2819 }
2820
2821 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2822 {
2823     uint32_t fst2;
2824     uint32_t fsth2;
2825
2826     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2827     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2828     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2829     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2830     update_fcr31(env, GETPC());
2831     return ((uint64_t)fsth2 << 32) | fst2;
2832 }
2833
2834 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2835
2836 /* binary operations */
2837 #define FLOAT_BINOP(name)                                          \
2838 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2839                                      uint64_t fdt0, uint64_t fdt1) \
2840 {                                                                  \
2841     uint64_t dt2;                                                  \
2842                                                                    \
2843     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2844     update_fcr31(env, GETPC());                                    \
2845     return dt2;                                                    \
2846 }                                                                  \
2847                                                                    \
2848 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2849                                      uint32_t fst0, uint32_t fst1) \
2850 {                                                                  \
2851     uint32_t wt2;                                                  \
2852                                                                    \
2853     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2854     update_fcr31(env, GETPC());                                    \
2855     return wt2;                                                    \
2856 }                                                                  \
2857                                                                    \
2858 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2859                                       uint64_t fdt0,               \
2860                                       uint64_t fdt1)               \
2861 {                                                                  \
2862     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2863     uint32_t fsth0 = fdt0 >> 32;                                   \
2864     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2865     uint32_t fsth1 = fdt1 >> 32;                                   \
2866     uint32_t wt2;                                                  \
2867     uint32_t wth2;                                                 \
2868                                                                    \
2869     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2870     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2871     update_fcr31(env, GETPC());                                    \
2872     return ((uint64_t)wth2 << 32) | wt2;                           \
2873 }
2874
2875 FLOAT_BINOP(add)
2876 FLOAT_BINOP(sub)
2877 FLOAT_BINOP(mul)
2878 FLOAT_BINOP(div)
2879 #undef FLOAT_BINOP
2880
2881 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
2882 {                                                                    \
2883     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
2884     if ((flags) & float_muladd_negate_c) {                           \
2885         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
2886     } else {                                                         \
2887         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
2888     }                                                                \
2889     if ((flags) & float_muladd_negate_result) {                      \
2890         a = prefix##_chs(a);                                         \
2891     }                                                                \
2892 }
2893
2894 /* FMA based operations */
2895 #define FLOAT_FMA(name, type)                                        \
2896 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2897                                      uint64_t fdt0, uint64_t fdt1,   \
2898                                      uint64_t fdt2)                  \
2899 {                                                                    \
2900     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
2901     update_fcr31(env, GETPC());                                      \
2902     return fdt0;                                                     \
2903 }                                                                    \
2904                                                                      \
2905 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
2906                                      uint32_t fst0, uint32_t fst1,   \
2907                                      uint32_t fst2)                  \
2908 {                                                                    \
2909     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2910     update_fcr31(env, GETPC());                                      \
2911     return fst0;                                                     \
2912 }                                                                    \
2913                                                                      \
2914 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
2915                                       uint64_t fdt0, uint64_t fdt1,  \
2916                                       uint64_t fdt2)                 \
2917 {                                                                    \
2918     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
2919     uint32_t fsth0 = fdt0 >> 32;                                     \
2920     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
2921     uint32_t fsth1 = fdt1 >> 32;                                     \
2922     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
2923     uint32_t fsth2 = fdt2 >> 32;                                     \
2924                                                                      \
2925     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2926     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
2927     update_fcr31(env, GETPC());                                      \
2928     return ((uint64_t)fsth0 << 32) | fst0;                           \
2929 }
2930 FLOAT_FMA(madd, 0)
2931 FLOAT_FMA(msub, float_muladd_negate_c)
2932 FLOAT_FMA(nmadd, float_muladd_negate_result)
2933 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2934 #undef FLOAT_FMA
2935
2936 /* MIPS specific binary operations */
2937 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2938 {
2939     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2940     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2941     update_fcr31(env, GETPC());
2942     return fdt2;
2943 }
2944
2945 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2946 {
2947     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2948     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2949     update_fcr31(env, GETPC());
2950     return fst2;
2951 }
2952
2953 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2954 {
2955     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2956     uint32_t fsth0 = fdt0 >> 32;
2957     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2958     uint32_t fsth2 = fdt2 >> 32;
2959
2960     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2961     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2962     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2963     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
2964     update_fcr31(env, GETPC());
2965     return ((uint64_t)fsth2 << 32) | fst2;
2966 }
2967
2968 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2969 {
2970     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2971     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
2972     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2973     update_fcr31(env, GETPC());
2974     return fdt2;
2975 }
2976
2977 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2978 {
2979     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2980     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2981     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2982     update_fcr31(env, GETPC());
2983     return fst2;
2984 }
2985
2986 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2987 {
2988     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2989     uint32_t fsth0 = fdt0 >> 32;
2990     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2991     uint32_t fsth2 = fdt2 >> 32;
2992
2993     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2994     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2995     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2996     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
2997     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2998     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2999     update_fcr31(env, GETPC());
3000     return ((uint64_t)fsth2 << 32) | fst2;
3001 }
3002
3003 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3004 {
3005     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3006     uint32_t fsth0 = fdt0 >> 32;
3007     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3008     uint32_t fsth1 = fdt1 >> 32;
3009     uint32_t fst2;
3010     uint32_t fsth2;
3011
3012     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3013     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3014     update_fcr31(env, GETPC());
3015     return ((uint64_t)fsth2 << 32) | fst2;
3016 }
3017
3018 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3019 {
3020     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3021     uint32_t fsth0 = fdt0 >> 32;
3022     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3023     uint32_t fsth1 = fdt1 >> 32;
3024     uint32_t fst2;
3025     uint32_t fsth2;
3026
3027     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3028     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3029     update_fcr31(env, GETPC());
3030     return ((uint64_t)fsth2 << 32) | fst2;
3031 }
3032
3033 /* compare operations */
3034 #define FOP_COND_D(op, cond)                                   \
3035 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3036                          uint64_t fdt1, int cc)                \
3037 {                                                              \
3038     int c;                                                     \
3039     c = cond;                                                  \
3040     update_fcr31(env, GETPC());                                \
3041     if (c)                                                     \
3042         SET_FP_COND(cc, env->active_fpu);                      \
3043     else                                                       \
3044         CLEAR_FP_COND(cc, env->active_fpu);                    \
3045 }                                                              \
3046 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3047                             uint64_t fdt1, int cc)             \
3048 {                                                              \
3049     int c;                                                     \
3050     fdt0 = float64_abs(fdt0);                                  \
3051     fdt1 = float64_abs(fdt1);                                  \
3052     c = cond;                                                  \
3053     update_fcr31(env, GETPC());                                \
3054     if (c)                                                     \
3055         SET_FP_COND(cc, env->active_fpu);                      \
3056     else                                                       \
3057         CLEAR_FP_COND(cc, env->active_fpu);                    \
3058 }
3059
3060 /* NOTE: the comma operator will make "cond" to eval to false,
3061  * but float64_unordered_quiet() is still called. */
3062 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3063 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3064 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3065 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3066 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3067 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3068 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3069 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3070 /* NOTE: the comma operator will make "cond" to eval to false,
3071  * but float64_unordered() is still called. */
3072 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3073 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3074 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3075 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3076 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3077 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3078 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3079 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3080
3081 #define FOP_COND_S(op, cond)                                   \
3082 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3083                          uint32_t fst1, int cc)                \
3084 {                                                              \
3085     int c;                                                     \
3086     c = cond;                                                  \
3087     update_fcr31(env, GETPC());                                \
3088     if (c)                                                     \
3089         SET_FP_COND(cc, env->active_fpu);                      \
3090     else                                                       \
3091         CLEAR_FP_COND(cc, env->active_fpu);                    \
3092 }                                                              \
3093 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3094                             uint32_t fst1, int cc)             \
3095 {                                                              \
3096     int c;                                                     \
3097     fst0 = float32_abs(fst0);                                  \
3098     fst1 = float32_abs(fst1);                                  \
3099     c = cond;                                                  \
3100     update_fcr31(env, GETPC());                                \
3101     if (c)                                                     \
3102         SET_FP_COND(cc, env->active_fpu);                      \
3103     else                                                       \
3104         CLEAR_FP_COND(cc, env->active_fpu);                    \
3105 }
3106
3107 /* NOTE: the comma operator will make "cond" to eval to false,
3108  * but float32_unordered_quiet() is still called. */
3109 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3110 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3111 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3112 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3113 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3114 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3115 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3116 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3117 /* NOTE: the comma operator will make "cond" to eval to false,
3118  * but float32_unordered() is still called. */
3119 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3120 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3121 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3122 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3123 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3124 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3125 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3126 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3127
3128 #define FOP_COND_PS(op, condl, condh)                           \
3129 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3130                           uint64_t fdt1, int cc)                \
3131 {                                                               \
3132     uint32_t fst0, fsth0, fst1, fsth1;                          \
3133     int ch, cl;                                                 \
3134     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3135     fsth0 = fdt0 >> 32;                                         \
3136     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3137     fsth1 = fdt1 >> 32;                                         \
3138     cl = condl;                                                 \
3139     ch = condh;                                                 \
3140     update_fcr31(env, GETPC());                                 \
3141     if (cl)                                                     \
3142         SET_FP_COND(cc, env->active_fpu);                       \
3143     else                                                        \
3144         CLEAR_FP_COND(cc, env->active_fpu);                     \
3145     if (ch)                                                     \
3146         SET_FP_COND(cc + 1, env->active_fpu);                   \
3147     else                                                        \
3148         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3149 }                                                               \
3150 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3151                              uint64_t fdt1, int cc)             \
3152 {                                                               \
3153     uint32_t fst0, fsth0, fst1, fsth1;                          \
3154     int ch, cl;                                                 \
3155     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3156     fsth0 = float32_abs(fdt0 >> 32);                            \
3157     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3158     fsth1 = float32_abs(fdt1 >> 32);                            \
3159     cl = condl;                                                 \
3160     ch = condh;                                                 \
3161     update_fcr31(env, GETPC());                                 \
3162     if (cl)                                                     \
3163         SET_FP_COND(cc, env->active_fpu);                       \
3164     else                                                        \
3165         CLEAR_FP_COND(cc, env->active_fpu);                     \
3166     if (ch)                                                     \
3167         SET_FP_COND(cc + 1, env->active_fpu);                   \
3168     else                                                        \
3169         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3170 }
3171
3172 /* NOTE: the comma operator will make "cond" to eval to false,
3173  * but float32_unordered_quiet() is still called. */
3174 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3175                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3176 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3177                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3178 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3179                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3180 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3181                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3182 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3183                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3184 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3185                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3186 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3187                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3188 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3189                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3190 /* NOTE: the comma operator will make "cond" to eval to false,
3191  * but float32_unordered() is still called. */
3192 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3193                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3194 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3195                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3196 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3197                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3198 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3199                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3200 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3201                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3202 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3203                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3204 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3205                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3206 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3207                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))