2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/host-utils.h"
25 #if !defined(CONFIG_USER_ONLY)
26 #include "exec/softmmu_exec.h"
27 #endif /* !defined(CONFIG_USER_ONLY) */
29 #ifndef CONFIG_USER_ONLY
30 static inline void cpu_mips_tlb_flush (CPUMIPSState
*env
, int flush_global
);
33 /*****************************************************************************/
34 /* Exceptions processing helpers */
36 static inline void QEMU_NORETURN
do_raise_exception_err(CPUMIPSState
*env
,
41 if (exception
< EXCP_SC
) {
42 qemu_log("%s: %d %d\n", __func__
, exception
, error_code
);
44 env
->exception_index
= exception
;
45 env
->error_code
= error_code
;
48 /* now we have a real cpu fault */
49 cpu_restore_state(env
, pc
);
55 static inline void QEMU_NORETURN
do_raise_exception(CPUMIPSState
*env
,
59 do_raise_exception_err(env
, exception
, 0, pc
);
62 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
65 do_raise_exception_err(env
, exception
, error_code
, 0);
68 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
70 do_raise_exception(env
, exception
, 0);
73 #if defined(CONFIG_USER_ONLY)
74 #define HELPER_LD(name, insn, type) \
75 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
78 return (type) insn##_raw(addr); \
81 #define HELPER_LD(name, insn, type) \
82 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
87 case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
88 case 1: return (type) cpu_##insn##_super(env, addr); break; \
90 case 2: return (type) cpu_##insn##_user(env, addr); break; \
94 HELPER_LD(lbu
, ldub
, uint8_t)
95 HELPER_LD(lw
, ldl
, int32_t)
97 HELPER_LD(ld
, ldq
, int64_t)
101 #if defined(CONFIG_USER_ONLY)
102 #define HELPER_ST(name, insn, type) \
103 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
104 type val, int mem_idx) \
106 insn##_raw(addr, val); \
109 #define HELPER_ST(name, insn, type) \
110 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
111 type val, int mem_idx) \
115 case 0: cpu_##insn##_kernel(env, addr, val); break; \
116 case 1: cpu_##insn##_super(env, addr, val); break; \
118 case 2: cpu_##insn##_user(env, addr, val); break; \
122 HELPER_ST(sb
, stb
, uint8_t)
123 HELPER_ST(sw
, stl
, uint32_t)
125 HELPER_ST(sd
, stq
, uint64_t)
129 target_ulong
helper_clo (target_ulong arg1
)
134 target_ulong
helper_clz (target_ulong arg1
)
139 #if defined(TARGET_MIPS64)
140 target_ulong
helper_dclo (target_ulong arg1
)
145 target_ulong
helper_dclz (target_ulong arg1
)
149 #endif /* TARGET_MIPS64 */
151 /* 64 bits arithmetic for 32 bits hosts */
152 static inline uint64_t get_HILO(CPUMIPSState
*env
)
154 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
157 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
160 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
161 tmp
= env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
165 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
167 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
168 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
172 /* Multiplication variants of the vr54xx. */
173 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
176 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
177 (int64_t)(int32_t)arg2
));
180 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
183 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
184 (uint64_t)(uint32_t)arg2
);
187 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
190 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
191 (int64_t)(int32_t)arg2
);
194 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
197 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
198 (int64_t)(int32_t)arg2
);
201 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
204 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
205 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
208 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
211 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
212 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
215 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
218 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
219 (int64_t)(int32_t)arg2
);
222 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
225 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
226 (int64_t)(int32_t)arg2
);
229 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
232 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
233 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
236 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
239 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
240 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
243 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
246 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
249 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
252 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
253 (uint64_t)(uint32_t)arg2
);
256 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
259 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
260 (int64_t)(int32_t)arg2
);
263 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
266 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
267 (uint64_t)(uint32_t)arg2
);
270 #ifndef CONFIG_USER_ONLY
272 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
273 target_ulong address
,
278 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
280 if (lladdr
== -1LL) {
287 #define HELPER_LD_ATOMIC(name, insn) \
288 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
290 env->lladdr = do_translate_address(env, arg, 0); \
291 env->llval = do_##insn(env, arg, mem_idx); \
294 HELPER_LD_ATOMIC(ll
, lw
)
296 HELPER_LD_ATOMIC(lld
, ld
)
298 #undef HELPER_LD_ATOMIC
300 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
301 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
302 target_ulong arg2, int mem_idx) \
306 if (arg2 & almask) { \
307 env->CP0_BadVAddr = arg2; \
308 helper_raise_exception(env, EXCP_AdES); \
310 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
311 tmp = do_##ld_insn(env, arg2, mem_idx); \
312 if (tmp == env->llval) { \
313 do_##st_insn(env, arg2, arg1, mem_idx); \
319 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
321 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
323 #undef HELPER_ST_ATOMIC
326 #ifdef TARGET_WORDS_BIGENDIAN
327 #define GET_LMASK(v) ((v) & 3)
328 #define GET_OFFSET(addr, offset) (addr + (offset))
330 #define GET_LMASK(v) (((v) & 3) ^ 3)
331 #define GET_OFFSET(addr, offset) (addr - (offset))
334 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
337 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
);
339 if (GET_LMASK(arg2
) <= 2)
340 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
);
342 if (GET_LMASK(arg2
) <= 1)
343 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
);
345 if (GET_LMASK(arg2
) == 0)
346 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
);
349 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
352 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
);
354 if (GET_LMASK(arg2
) >= 1)
355 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
);
357 if (GET_LMASK(arg2
) >= 2)
358 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
);
360 if (GET_LMASK(arg2
) == 3)
361 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
);
364 #if defined(TARGET_MIPS64)
365 /* "half" load and stores. We must do the memory access inline,
366 or fault handling won't work. */
368 #ifdef TARGET_WORDS_BIGENDIAN
369 #define GET_LMASK64(v) ((v) & 7)
371 #define GET_LMASK64(v) (((v) & 7) ^ 7)
374 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
377 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
);
379 if (GET_LMASK64(arg2
) <= 6)
380 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
);
382 if (GET_LMASK64(arg2
) <= 5)
383 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
);
385 if (GET_LMASK64(arg2
) <= 4)
386 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
);
388 if (GET_LMASK64(arg2
) <= 3)
389 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
);
391 if (GET_LMASK64(arg2
) <= 2)
392 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
);
394 if (GET_LMASK64(arg2
) <= 1)
395 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
);
397 if (GET_LMASK64(arg2
) <= 0)
398 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
);
401 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
404 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
);
406 if (GET_LMASK64(arg2
) >= 1)
407 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
);
409 if (GET_LMASK64(arg2
) >= 2)
410 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
);
412 if (GET_LMASK64(arg2
) >= 3)
413 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
);
415 if (GET_LMASK64(arg2
) >= 4)
416 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
);
418 if (GET_LMASK64(arg2
) >= 5)
419 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
);
421 if (GET_LMASK64(arg2
) >= 6)
422 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
);
424 if (GET_LMASK64(arg2
) == 7)
425 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
);
427 #endif /* TARGET_MIPS64 */
429 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
431 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
434 target_ulong base_reglist
= reglist
& 0xf;
435 target_ulong do_r31
= reglist
& 0x10;
437 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
440 for (i
= 0; i
< base_reglist
; i
++) {
441 env
->active_tc
.gpr
[multiple_regs
[i
]] =
442 (target_long
)do_lw(env
, addr
, mem_idx
);
448 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
);
452 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
455 target_ulong base_reglist
= reglist
& 0xf;
456 target_ulong do_r31
= reglist
& 0x10;
458 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
461 for (i
= 0; i
< base_reglist
; i
++) {
462 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
);
468 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
);
472 #if defined(TARGET_MIPS64)
473 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
476 target_ulong base_reglist
= reglist
& 0xf;
477 target_ulong do_r31
= reglist
& 0x10;
479 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
482 for (i
= 0; i
< base_reglist
; i
++) {
483 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
);
489 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
);
493 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
496 target_ulong base_reglist
= reglist
& 0xf;
497 target_ulong do_r31
= reglist
& 0x10;
499 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
502 for (i
= 0; i
< base_reglist
; i
++) {
503 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
);
509 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
);
514 #ifndef CONFIG_USER_ONLY
516 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
518 CPUState
*cpu
= CPU(c
);
519 CPUMIPSState
*env
= &c
->env
;
521 /* If the VPE is halted but otherwise active, it means it's waiting for
523 return cpu
->halted
&& mips_vpe_active(env
);
526 static inline void mips_vpe_wake(MIPSCPU
*c
)
528 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
529 because there might be other conditions that state that c should
531 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
534 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
536 CPUState
*cs
= CPU(cpu
);
538 /* The VPE was shut off, really go to bed.
539 Reset any old _WAKE requests. */
541 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
544 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
546 CPUMIPSState
*c
= &cpu
->env
;
548 /* FIXME: TC reschedule. */
549 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
554 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
556 CPUMIPSState
*c
= &cpu
->env
;
558 /* FIXME: TC reschedule. */
559 if (!mips_vpe_active(c
)) {
566 * @env: CPU from which mapping is performed.
567 * @tc: Should point to an int with the value of the global TC index.
569 * This function will transform @tc into a local index within the
570 * returned #CPUMIPSState.
572 /* FIXME: This code assumes that all VPEs have the same number of TCs,
573 which depends on runtime setup. Can probably be fixed by
574 walking the list of CPUMIPSStates. */
575 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
583 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
584 /* Not allowed to address other CPUs. */
585 *tc
= env
->current_tc
;
589 cs
= CPU(mips_env_get_cpu(env
));
590 vpe_idx
= tc_idx
/ cs
->nr_threads
;
591 *tc
= tc_idx
% cs
->nr_threads
;
592 other_cs
= qemu_get_cpu(vpe_idx
);
593 if (other_cs
== NULL
) {
596 cpu
= MIPS_CPU(other_cs
);
600 /* The per VPE CP0_Status register shares some fields with the per TC
601 CP0_TCStatus registers. These fields are wired to the same registers,
602 so changes to either of them should be reflected on both registers.
604 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
606 These helper call synchronizes the regs for a given cpu. */
608 /* Called for updates to CP0_Status. */
609 static void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
)
611 int32_t tcstatus
, *tcst
;
612 uint32_t v
= cpu
->CP0_Status
;
613 uint32_t cu
, mx
, asid
, ksu
;
614 uint32_t mask
= ((1 << CP0TCSt_TCU3
)
615 | (1 << CP0TCSt_TCU2
)
616 | (1 << CP0TCSt_TCU1
)
617 | (1 << CP0TCSt_TCU0
)
619 | (3 << CP0TCSt_TKSU
)
620 | (0xff << CP0TCSt_TASID
));
622 cu
= (v
>> CP0St_CU0
) & 0xf;
623 mx
= (v
>> CP0St_MX
) & 0x1;
624 ksu
= (v
>> CP0St_KSU
) & 0x3;
625 asid
= env
->CP0_EntryHi
& 0xff;
627 tcstatus
= cu
<< CP0TCSt_TCU0
;
628 tcstatus
|= mx
<< CP0TCSt_TMX
;
629 tcstatus
|= ksu
<< CP0TCSt_TKSU
;
632 if (tc
== cpu
->current_tc
) {
633 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
635 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
643 /* Called for updates to CP0_TCStatus. */
644 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
648 uint32_t tcu
, tmx
, tasid
, tksu
;
649 uint32_t mask
= ((1 << CP0St_CU3
)
656 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
657 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
659 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
661 status
= tcu
<< CP0St_CU0
;
662 status
|= tmx
<< CP0St_MX
;
663 status
|= tksu
<< CP0St_KSU
;
665 cpu
->CP0_Status
&= ~mask
;
666 cpu
->CP0_Status
|= status
;
668 /* Sync the TASID with EntryHi. */
669 cpu
->CP0_EntryHi
&= ~0xff;
670 cpu
->CP0_EntryHi
= tasid
;
675 /* Called for updates to CP0_EntryHi. */
676 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
679 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
683 if (tc
== cpu
->current_tc
) {
684 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
686 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
694 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
696 return env
->mvp
->CP0_MVPControl
;
699 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
701 return env
->mvp
->CP0_MVPConf0
;
704 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
706 return env
->mvp
->CP0_MVPConf1
;
709 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
711 return (int32_t)cpu_mips_get_random(env
);
714 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
716 return env
->active_tc
.CP0_TCStatus
;
719 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
721 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
722 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
724 if (other_tc
== other
->current_tc
)
725 return other
->active_tc
.CP0_TCStatus
;
727 return other
->tcs
[other_tc
].CP0_TCStatus
;
730 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
732 return env
->active_tc
.CP0_TCBind
;
735 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
737 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
738 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
740 if (other_tc
== other
->current_tc
)
741 return other
->active_tc
.CP0_TCBind
;
743 return other
->tcs
[other_tc
].CP0_TCBind
;
746 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
748 return env
->active_tc
.PC
;
751 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
753 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
754 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
756 if (other_tc
== other
->current_tc
)
757 return other
->active_tc
.PC
;
759 return other
->tcs
[other_tc
].PC
;
762 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
764 return env
->active_tc
.CP0_TCHalt
;
767 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
769 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
770 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
772 if (other_tc
== other
->current_tc
)
773 return other
->active_tc
.CP0_TCHalt
;
775 return other
->tcs
[other_tc
].CP0_TCHalt
;
778 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
780 return env
->active_tc
.CP0_TCContext
;
783 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
785 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
786 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
788 if (other_tc
== other
->current_tc
)
789 return other
->active_tc
.CP0_TCContext
;
791 return other
->tcs
[other_tc
].CP0_TCContext
;
794 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
796 return env
->active_tc
.CP0_TCSchedule
;
799 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
801 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
802 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
804 if (other_tc
== other
->current_tc
)
805 return other
->active_tc
.CP0_TCSchedule
;
807 return other
->tcs
[other_tc
].CP0_TCSchedule
;
810 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
812 return env
->active_tc
.CP0_TCScheFBack
;
815 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
817 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
818 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
820 if (other_tc
== other
->current_tc
)
821 return other
->active_tc
.CP0_TCScheFBack
;
823 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
826 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
828 return (int32_t)cpu_mips_get_count(env
);
831 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
833 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
834 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
836 return other
->CP0_EntryHi
;
839 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
841 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
843 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
845 if (other_tc
== other
->current_tc
) {
846 tccause
= other
->CP0_Cause
;
848 tccause
= other
->CP0_Cause
;
854 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
856 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
857 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
859 return other
->CP0_Status
;
862 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
864 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
867 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
869 return (int32_t)env
->CP0_WatchLo
[sel
];
872 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
874 return env
->CP0_WatchHi
[sel
];
877 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
879 target_ulong t0
= env
->CP0_Debug
;
880 if (env
->hflags
& MIPS_HFLAG_DM
)
886 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
888 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
890 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
892 if (other_tc
== other
->current_tc
)
893 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
895 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
897 /* XXX: Might be wrong, check with EJTAG spec. */
898 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
899 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
902 #if defined(TARGET_MIPS64)
903 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
905 return env
->active_tc
.PC
;
908 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
910 return env
->active_tc
.CP0_TCHalt
;
913 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
915 return env
->active_tc
.CP0_TCContext
;
918 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
920 return env
->active_tc
.CP0_TCSchedule
;
923 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
925 return env
->active_tc
.CP0_TCScheFBack
;
928 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
930 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
933 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
935 return env
->CP0_WatchLo
[sel
];
937 #endif /* TARGET_MIPS64 */
939 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
942 unsigned int tmp
= env
->tlb
->nb_tlb
;
948 env
->CP0_Index
= (env
->CP0_Index
& 0x80000000) | (arg1
& (num
- 1));
951 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
956 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
957 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
959 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
960 mask
|= (1 << CP0MVPCo_STLB
);
961 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
963 // TODO: Enable/disable shared TLB, enable/disable VPEs.
965 env
->mvp
->CP0_MVPControl
= newval
;
968 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
973 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
974 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
975 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
977 /* Yield scheduler intercept not implemented. */
978 /* Gating storage scheduler intercept not implemented. */
980 // TODO: Enable/disable TCs.
982 env
->CP0_VPEControl
= newval
;
985 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
987 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
988 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
992 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
993 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
994 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
996 /* TODO: Enable/disable TCs. */
998 other
->CP0_VPEControl
= newval
;
1001 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1003 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1004 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1005 /* FIXME: Mask away return zero on read bits. */
1006 return other
->CP0_VPEControl
;
1009 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1011 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1012 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1014 return other
->CP0_VPEConf0
;
1017 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1022 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1023 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1024 mask
|= (0xff << CP0VPEC0_XTC
);
1025 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1027 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1029 // TODO: TC exclusive handling due to ERL/EXL.
1031 env
->CP0_VPEConf0
= newval
;
1034 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1036 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1037 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1041 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1042 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1044 /* TODO: TC exclusive handling due to ERL/EXL. */
1045 other
->CP0_VPEConf0
= newval
;
1048 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1053 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1054 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1055 (0xff << CP0VPEC1_NCP1
);
1056 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1058 /* UDI not implemented. */
1059 /* CP2 not implemented. */
1061 // TODO: Handle FPU (CP1) binding.
1063 env
->CP0_VPEConf1
= newval
;
1066 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1068 /* Yield qualifier inputs not implemented. */
1069 env
->CP0_YQMask
= 0x00000000;
1072 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1074 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1077 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1079 /* Large physaddr (PABITS) not implemented */
1080 /* 1k pages not implemented */
1081 env
->CP0_EntryLo0
= arg1
& 0x3FFFFFFF;
1084 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1086 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1089 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1091 env
->active_tc
.CP0_TCStatus
= newval
;
1092 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1095 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1097 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1098 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1100 if (other_tc
== other
->current_tc
)
1101 other
->active_tc
.CP0_TCStatus
= arg1
;
1103 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1104 sync_c0_tcstatus(other
, other_tc
, arg1
);
1107 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1109 uint32_t mask
= (1 << CP0TCBd_TBE
);
1112 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1113 mask
|= (1 << CP0TCBd_CurVPE
);
1114 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1115 env
->active_tc
.CP0_TCBind
= newval
;
1118 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1120 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1121 uint32_t mask
= (1 << CP0TCBd_TBE
);
1123 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1125 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1126 mask
|= (1 << CP0TCBd_CurVPE
);
1127 if (other_tc
== other
->current_tc
) {
1128 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1129 other
->active_tc
.CP0_TCBind
= newval
;
1131 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1132 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1136 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1138 env
->active_tc
.PC
= arg1
;
1139 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1141 /* MIPS16 not implemented. */
1144 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1146 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1147 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1149 if (other_tc
== other
->current_tc
) {
1150 other
->active_tc
.PC
= arg1
;
1151 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1152 other
->lladdr
= 0ULL;
1153 /* MIPS16 not implemented. */
1155 other
->tcs
[other_tc
].PC
= arg1
;
1156 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1157 other
->lladdr
= 0ULL;
1158 /* MIPS16 not implemented. */
1162 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1164 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1166 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1168 // TODO: Halt TC / Restart (if allocated+active) TC.
1169 if (env
->active_tc
.CP0_TCHalt
& 1) {
1170 mips_tc_sleep(cpu
, env
->current_tc
);
1172 mips_tc_wake(cpu
, env
->current_tc
);
1176 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1178 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1179 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1180 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1182 // TODO: Halt TC / Restart (if allocated+active) TC.
1184 if (other_tc
== other
->current_tc
)
1185 other
->active_tc
.CP0_TCHalt
= arg1
;
1187 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1190 mips_tc_sleep(other_cpu
, other_tc
);
1192 mips_tc_wake(other_cpu
, other_tc
);
1196 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1198 env
->active_tc
.CP0_TCContext
= arg1
;
1201 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1203 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1204 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1206 if (other_tc
== other
->current_tc
)
1207 other
->active_tc
.CP0_TCContext
= arg1
;
1209 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1212 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1214 env
->active_tc
.CP0_TCSchedule
= arg1
;
1217 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1219 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1220 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1222 if (other_tc
== other
->current_tc
)
1223 other
->active_tc
.CP0_TCSchedule
= arg1
;
1225 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1228 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1230 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1233 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1235 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1236 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1238 if (other_tc
== other
->current_tc
)
1239 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1241 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1244 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1246 /* Large physaddr (PABITS) not implemented */
1247 /* 1k pages not implemented */
1248 env
->CP0_EntryLo1
= arg1
& 0x3FFFFFFF;
1251 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1253 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1256 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1258 /* 1k pages not implemented */
1259 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1262 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1264 /* SmartMIPS not implemented */
1265 /* Large physaddr (PABITS) not implemented */
1266 /* 1k pages not implemented */
1267 env
->CP0_PageGrain
= 0;
1270 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1272 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1275 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1277 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1280 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1282 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1285 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1287 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1290 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1292 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1295 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1297 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1300 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1302 env
->CP0_HWREna
= arg1
& 0x0000000F;
1305 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1307 cpu_mips_store_count(env
, arg1
);
1310 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1312 target_ulong old
, val
;
1314 /* 1k pages not implemented */
1315 val
= arg1
& ((TARGET_PAGE_MASK
<< 1) | 0xFF);
1316 #if defined(TARGET_MIPS64)
1317 val
&= env
->SEGMask
;
1319 old
= env
->CP0_EntryHi
;
1320 env
->CP0_EntryHi
= val
;
1321 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1322 sync_c0_entryhi(env
, env
->current_tc
);
1324 /* If the ASID changes, flush qemu's TLB. */
1325 if ((old
& 0xFF) != (val
& 0xFF))
1326 cpu_mips_tlb_flush(env
, 1);
1329 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1331 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1332 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1334 other
->CP0_EntryHi
= arg1
;
1335 sync_c0_entryhi(other
, other_tc
);
1338 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1340 cpu_mips_store_compare(env
, arg1
);
1343 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1346 uint32_t mask
= env
->CP0_Status_rw_bitmask
;
1349 old
= env
->CP0_Status
;
1350 env
->CP0_Status
= (env
->CP0_Status
& ~mask
) | val
;
1351 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1352 sync_c0_status(env
, env
, env
->current_tc
);
1354 compute_hflags(env
);
1357 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1358 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1359 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1360 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1362 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1363 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1364 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1365 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1366 default: cpu_abort(env
, "Invalid MMU mode!\n"); break;
1371 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1373 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1374 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1376 other
->CP0_Status
= arg1
& ~0xf1000018;
1377 sync_c0_status(env
, other
, other_tc
);
1380 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1382 /* vectored interrupts not implemented, no performance counters. */
1383 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1386 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1388 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1389 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1392 static void mtc0_cause(CPUMIPSState
*cpu
, target_ulong arg1
)
1394 uint32_t mask
= 0x00C00300;
1395 uint32_t old
= cpu
->CP0_Cause
;
1398 if (cpu
->insn_flags
& ISA_MIPS32R2
) {
1399 mask
|= 1 << CP0Ca_DC
;
1402 cpu
->CP0_Cause
= (cpu
->CP0_Cause
& ~mask
) | (arg1
& mask
);
1404 if ((old
^ cpu
->CP0_Cause
) & (1 << CP0Ca_DC
)) {
1405 if (cpu
->CP0_Cause
& (1 << CP0Ca_DC
)) {
1406 cpu_mips_stop_count(cpu
);
1408 cpu_mips_start_count(cpu
);
1412 /* Set/reset software interrupts */
1413 for (i
= 0 ; i
< 2 ; i
++) {
1414 if ((old
^ cpu
->CP0_Cause
) & (1 << (CP0Ca_IP
+ i
))) {
1415 cpu_mips_soft_irq(cpu
, i
, cpu
->CP0_Cause
& (1 << (CP0Ca_IP
+ i
)));
1420 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1422 mtc0_cause(env
, arg1
);
1425 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1427 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1428 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1430 mtc0_cause(other
, arg1
);
1433 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1435 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1436 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1438 return other
->CP0_EPC
;
1441 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1443 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1444 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1446 return other
->CP0_EBase
;
1449 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1451 /* vectored interrupts not implemented */
1452 env
->CP0_EBase
= (env
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1455 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1457 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1458 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1459 other
->CP0_EBase
= (other
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1462 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1464 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1465 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1468 case 0: return other
->CP0_Config0
;
1469 case 1: return other
->CP0_Config1
;
1470 case 2: return other
->CP0_Config2
;
1471 case 3: return other
->CP0_Config3
;
1472 /* 4 and 5 are reserved. */
1473 case 6: return other
->CP0_Config6
;
1474 case 7: return other
->CP0_Config7
;
1481 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1483 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1486 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1488 /* tertiary/secondary caches not implemented */
1489 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1492 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1494 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1495 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1496 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1499 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1501 /* Watch exceptions for instructions, data loads, data stores
1503 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1506 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1508 env
->CP0_WatchHi
[sel
] = (arg1
& 0x40FF0FF8);
1509 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1512 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1514 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1515 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1518 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1520 env
->CP0_Framemask
= arg1
; /* XXX */
1523 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1525 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1526 if (arg1
& (1 << CP0DB_DM
))
1527 env
->hflags
|= MIPS_HFLAG_DM
;
1529 env
->hflags
&= ~MIPS_HFLAG_DM
;
1532 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1534 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1535 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1536 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1538 /* XXX: Might be wrong, check with EJTAG spec. */
1539 if (other_tc
== other
->current_tc
)
1540 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1542 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1543 other
->CP0_Debug
= (other
->CP0_Debug
&
1544 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1545 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1548 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1550 env
->CP0_Performance0
= arg1
& 0x000007ff;
1553 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1555 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1558 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1560 env
->CP0_DataLo
= arg1
; /* XXX */
1563 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1565 env
->CP0_TagHi
= arg1
; /* XXX */
1568 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1570 env
->CP0_DataHi
= arg1
; /* XXX */
1573 /* MIPS MT functions */
1574 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1576 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1577 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1579 if (other_tc
== other
->current_tc
)
1580 return other
->active_tc
.gpr
[sel
];
1582 return other
->tcs
[other_tc
].gpr
[sel
];
1585 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1587 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1588 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1590 if (other_tc
== other
->current_tc
)
1591 return other
->active_tc
.LO
[sel
];
1593 return other
->tcs
[other_tc
].LO
[sel
];
1596 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1598 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1599 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1601 if (other_tc
== other
->current_tc
)
1602 return other
->active_tc
.HI
[sel
];
1604 return other
->tcs
[other_tc
].HI
[sel
];
1607 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1609 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1610 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1612 if (other_tc
== other
->current_tc
)
1613 return other
->active_tc
.ACX
[sel
];
1615 return other
->tcs
[other_tc
].ACX
[sel
];
1618 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1620 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1621 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1623 if (other_tc
== other
->current_tc
)
1624 return other
->active_tc
.DSPControl
;
1626 return other
->tcs
[other_tc
].DSPControl
;
1629 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1631 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1632 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1634 if (other_tc
== other
->current_tc
)
1635 other
->active_tc
.gpr
[sel
] = arg1
;
1637 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1640 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1642 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1643 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1645 if (other_tc
== other
->current_tc
)
1646 other
->active_tc
.LO
[sel
] = arg1
;
1648 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1651 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1653 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1654 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1656 if (other_tc
== other
->current_tc
)
1657 other
->active_tc
.HI
[sel
] = arg1
;
1659 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1662 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1664 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1665 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1667 if (other_tc
== other
->current_tc
)
1668 other
->active_tc
.ACX
[sel
] = arg1
;
1670 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1673 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
1675 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1676 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1678 if (other_tc
== other
->current_tc
)
1679 other
->active_tc
.DSPControl
= arg1
;
1681 other
->tcs
[other_tc
].DSPControl
= arg1
;
1684 /* MIPS MT functions */
1685 target_ulong
helper_dmt(void)
1691 target_ulong
helper_emt(void)
1697 target_ulong
helper_dvpe(CPUMIPSState
*env
)
1699 CPUState
*other_cs
= first_cpu
;
1700 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1703 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1704 /* Turn off all VPEs except the one executing the dvpe. */
1705 if (&other_cpu
->env
!= env
) {
1706 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1707 mips_vpe_sleep(other_cpu
);
1709 other_cs
= other_cs
->next_cpu
;
1714 target_ulong
helper_evpe(CPUMIPSState
*env
)
1716 CPUState
*other_cs
= first_cpu
;
1717 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1720 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1722 if (&other_cpu
->env
!= env
1723 /* If the VPE is WFI, don't disturb its sleep. */
1724 && !mips_vpe_is_wfi(other_cpu
)) {
1725 /* Enable the VPE. */
1726 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1727 mips_vpe_wake(other_cpu
); /* And wake it up. */
1729 other_cs
= other_cs
->next_cpu
;
1733 #endif /* !CONFIG_USER_ONLY */
1735 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1737 // arg1 = rt, arg2 = rs
1739 // TODO: store to TC register
1742 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
1744 target_long arg1
= arg
;
1747 /* No scheduling policy implemented. */
1749 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1750 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1751 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1752 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1753 helper_raise_exception(env
, EXCP_THREAD
);
1756 } else if (arg1
== 0) {
1757 if (0 /* TODO: TC underflow */) {
1758 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1759 helper_raise_exception(env
, EXCP_THREAD
);
1761 // TODO: Deallocate TC
1763 } else if (arg1
> 0) {
1764 /* Yield qualifier inputs not implemented. */
1765 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1766 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1767 helper_raise_exception(env
, EXCP_THREAD
);
1769 return env
->CP0_YQMask
;
1772 #ifndef CONFIG_USER_ONLY
1773 /* TLB management */
1774 static void cpu_mips_tlb_flush (CPUMIPSState
*env
, int flush_global
)
1776 /* Flush qemu's TLB and discard all shadowed entries. */
1777 tlb_flush (env
, flush_global
);
1778 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
1781 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
1783 /* Discard entries from env->tlb[first] onwards. */
1784 while (env
->tlb
->tlb_in_use
> first
) {
1785 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1789 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
1793 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1794 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1795 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1796 #if defined(TARGET_MIPS64)
1797 tlb
->VPN
&= env
->SEGMask
;
1799 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
1800 tlb
->PageMask
= env
->CP0_PageMask
;
1801 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1802 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
1803 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
1804 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
1805 tlb
->PFN
[0] = (env
->CP0_EntryLo0
>> 6) << 12;
1806 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
1807 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
1808 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
1809 tlb
->PFN
[1] = (env
->CP0_EntryLo1
>> 6) << 12;
1812 void r4k_helper_tlbwi(CPUMIPSState
*env
)
1818 bool G
, V0
, D0
, V1
, D1
;
1820 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
1821 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1822 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1823 #if defined(TARGET_MIPS64)
1824 VPN
&= env
->SEGMask
;
1826 ASID
= env
->CP0_EntryHi
& 0xff;
1827 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1828 V0
= (env
->CP0_EntryLo0
& 2) != 0;
1829 D0
= (env
->CP0_EntryLo0
& 4) != 0;
1830 V1
= (env
->CP0_EntryLo1
& 2) != 0;
1831 D1
= (env
->CP0_EntryLo1
& 4) != 0;
1833 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1834 permissions on the current entry. */
1835 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
1836 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
1837 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
)) {
1838 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
1841 r4k_invalidate_tlb(env
, idx
, 0);
1842 r4k_fill_tlb(env
, idx
);
1845 void r4k_helper_tlbwr(CPUMIPSState
*env
)
1847 int r
= cpu_mips_get_random(env
);
1849 r4k_invalidate_tlb(env
, r
, 1);
1850 r4k_fill_tlb(env
, r
);
1853 void r4k_helper_tlbp(CPUMIPSState
*env
)
1862 ASID
= env
->CP0_EntryHi
& 0xFF;
1863 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
1864 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1865 /* 1k pages are not supported. */
1866 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1867 tag
= env
->CP0_EntryHi
& ~mask
;
1868 VPN
= tlb
->VPN
& ~mask
;
1869 #if defined(TARGET_MIPS64)
1870 tag
&= env
->SEGMask
;
1872 /* Check ASID, virtual page number & size */
1873 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
1879 if (i
== env
->tlb
->nb_tlb
) {
1880 /* No match. Discard any shadow entries, if any of them match. */
1881 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
1882 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1883 /* 1k pages are not supported. */
1884 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1885 tag
= env
->CP0_EntryHi
& ~mask
;
1886 VPN
= tlb
->VPN
& ~mask
;
1887 #if defined(TARGET_MIPS64)
1888 tag
&= env
->SEGMask
;
1890 /* Check ASID, virtual page number & size */
1891 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
1892 r4k_mips_tlb_flush_extra (env
, i
);
1897 env
->CP0_Index
|= 0x80000000;
1901 void r4k_helper_tlbr(CPUMIPSState
*env
)
1907 ASID
= env
->CP0_EntryHi
& 0xFF;
1908 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
1909 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1911 /* If this will change the current ASID, flush qemu's TLB. */
1912 if (ASID
!= tlb
->ASID
)
1913 cpu_mips_tlb_flush (env
, 1);
1915 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
1917 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
1918 env
->CP0_PageMask
= tlb
->PageMask
;
1919 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
1920 (tlb
->C0
<< 3) | (tlb
->PFN
[0] >> 6);
1921 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
1922 (tlb
->C1
<< 3) | (tlb
->PFN
[1] >> 6);
1925 void helper_tlbwi(CPUMIPSState
*env
)
1927 env
->tlb
->helper_tlbwi(env
);
1930 void helper_tlbwr(CPUMIPSState
*env
)
1932 env
->tlb
->helper_tlbwr(env
);
1935 void helper_tlbp(CPUMIPSState
*env
)
1937 env
->tlb
->helper_tlbp(env
);
1940 void helper_tlbr(CPUMIPSState
*env
)
1942 env
->tlb
->helper_tlbr(env
);
1946 target_ulong
helper_di(CPUMIPSState
*env
)
1948 target_ulong t0
= env
->CP0_Status
;
1950 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
1954 target_ulong
helper_ei(CPUMIPSState
*env
)
1956 target_ulong t0
= env
->CP0_Status
;
1958 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
1962 static void debug_pre_eret(CPUMIPSState
*env
)
1964 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1965 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
1966 env
->active_tc
.PC
, env
->CP0_EPC
);
1967 if (env
->CP0_Status
& (1 << CP0St_ERL
))
1968 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
1969 if (env
->hflags
& MIPS_HFLAG_DM
)
1970 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
1975 static void debug_post_eret(CPUMIPSState
*env
)
1977 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1978 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
1979 env
->active_tc
.PC
, env
->CP0_EPC
);
1980 if (env
->CP0_Status
& (1 << CP0St_ERL
))
1981 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
1982 if (env
->hflags
& MIPS_HFLAG_DM
)
1983 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
1984 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1985 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1986 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1987 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1988 default: cpu_abort(env
, "Invalid MMU mode!\n"); break;
1993 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
1995 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
1997 env
->hflags
|= MIPS_HFLAG_M16
;
1999 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2003 void helper_eret(CPUMIPSState
*env
)
2005 debug_pre_eret(env
);
2006 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2007 set_pc(env
, env
->CP0_ErrorEPC
);
2008 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2010 set_pc(env
, env
->CP0_EPC
);
2011 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2013 compute_hflags(env
);
2014 debug_post_eret(env
);
2018 void helper_deret(CPUMIPSState
*env
)
2020 debug_pre_eret(env
);
2021 set_pc(env
, env
->CP0_DEPC
);
2023 env
->hflags
&= MIPS_HFLAG_DM
;
2024 compute_hflags(env
);
2025 debug_post_eret(env
);
2028 #endif /* !CONFIG_USER_ONLY */
2030 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2032 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2033 (env
->CP0_HWREna
& (1 << 0)))
2034 return env
->CP0_EBase
& 0x3ff;
2036 helper_raise_exception(env
, EXCP_RI
);
2041 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2043 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2044 (env
->CP0_HWREna
& (1 << 1)))
2045 return env
->SYNCI_Step
;
2047 helper_raise_exception(env
, EXCP_RI
);
2052 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2054 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2055 (env
->CP0_HWREna
& (1 << 2)))
2056 return env
->CP0_Count
;
2058 helper_raise_exception(env
, EXCP_RI
);
2063 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2065 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2066 (env
->CP0_HWREna
& (1 << 3)))
2069 helper_raise_exception(env
, EXCP_RI
);
2074 void helper_pmon(CPUMIPSState
*env
, int function
)
2078 case 2: /* TODO: char inbyte(int waitflag); */
2079 if (env
->active_tc
.gpr
[4] == 0)
2080 env
->active_tc
.gpr
[2] = -1;
2082 case 11: /* TODO: char inbyte (void); */
2083 env
->active_tc
.gpr
[2] = -1;
2087 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2093 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2100 void helper_wait(CPUMIPSState
*env
)
2102 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2105 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2106 helper_raise_exception(env
, EXCP_HLT
);
2109 #if !defined(CONFIG_USER_ONLY)
2111 static void QEMU_NORETURN
do_unaligned_access(CPUMIPSState
*env
,
2112 target_ulong addr
, int is_write
,
2113 int is_user
, uintptr_t retaddr
);
2115 #define MMUSUFFIX _mmu
2116 #define ALIGNED_ONLY
2119 #include "exec/softmmu_template.h"
2122 #include "exec/softmmu_template.h"
2125 #include "exec/softmmu_template.h"
2128 #include "exec/softmmu_template.h"
2130 static void do_unaligned_access(CPUMIPSState
*env
, target_ulong addr
,
2131 int is_write
, int is_user
, uintptr_t retaddr
)
2133 env
->CP0_BadVAddr
= addr
;
2134 do_raise_exception(env
, (is_write
== 1) ? EXCP_AdES
: EXCP_AdEL
, retaddr
);
2137 void tlb_fill(CPUMIPSState
*env
, target_ulong addr
, int is_write
, int mmu_idx
,
2142 ret
= cpu_mips_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
);
2144 do_raise_exception_err(env
, env
->exception_index
,
2145 env
->error_code
, retaddr
);
2149 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2150 bool is_write
, bool is_exec
, int unused
,
2153 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2154 CPUMIPSState
*env
= &cpu
->env
;
2157 helper_raise_exception(env
, EXCP_IBE
);
2159 helper_raise_exception(env
, EXCP_DBE
);
2162 #endif /* !CONFIG_USER_ONLY */
2164 /* Complex FPU operations which may need stack space. */
2166 #define FLOAT_TWO32 make_float32(1 << 30)
2167 #define FLOAT_TWO64 make_float64(1ULL << 62)
2168 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2169 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2171 /* convert MIPS rounding mode in FCR31 to IEEE library */
2172 static unsigned int ieee_rm
[] = {
2173 float_round_nearest_even
,
2174 float_round_to_zero
,
2179 static inline void restore_rounding_mode(CPUMIPSState
*env
)
2181 set_float_rounding_mode(ieee_rm
[env
->active_fpu
.fcr31
& 3],
2182 &env
->active_fpu
.fp_status
);
2185 static inline void restore_flush_mode(CPUMIPSState
*env
)
2187 set_flush_to_zero((env
->active_fpu
.fcr31
& (1 << 24)) != 0,
2188 &env
->active_fpu
.fp_status
);
2191 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2197 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2200 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2203 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2206 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2209 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2216 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t reg
)
2220 if (arg1
& 0xffffff00)
2222 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2223 ((arg1
& 0x1) << 23);
2226 if (arg1
& 0x007c0000)
2228 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2231 if (arg1
& 0x007c0000)
2233 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2234 ((arg1
& 0x4) << 22);
2237 if (arg1
& 0x007c0000)
2239 env
->active_fpu
.fcr31
= arg1
;
2244 /* set rounding mode */
2245 restore_rounding_mode(env
);
2246 /* set flush-to-zero mode */
2247 restore_flush_mode(env
);
2248 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2249 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2250 do_raise_exception(env
, EXCP_FPE
, GETPC());
2253 static inline int ieee_ex_to_mips(int xcpt
)
2257 if (xcpt
& float_flag_invalid
) {
2260 if (xcpt
& float_flag_overflow
) {
2263 if (xcpt
& float_flag_underflow
) {
2264 ret
|= FP_UNDERFLOW
;
2266 if (xcpt
& float_flag_divbyzero
) {
2269 if (xcpt
& float_flag_inexact
) {
2276 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2278 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2280 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2283 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2285 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2286 do_raise_exception(env
, EXCP_FPE
, pc
);
2288 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2294 Single precition routines have a "s" suffix, double precision a
2295 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2296 paired single lower "pl", paired single upper "pu". */
2298 /* unary operations, modifying fp status */
2299 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2301 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2302 update_fcr31(env
, GETPC());
2306 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2308 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2309 update_fcr31(env
, GETPC());
2313 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2317 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2318 update_fcr31(env
, GETPC());
2322 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2326 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2327 update_fcr31(env
, GETPC());
2331 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2335 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2336 update_fcr31(env
, GETPC());
2340 uint64_t helper_float_cvtl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2344 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2345 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2346 & (float_flag_invalid
| float_flag_overflow
)) {
2347 dt2
= FP_TO_INT64_OVERFLOW
;
2349 update_fcr31(env
, GETPC());
2353 uint64_t helper_float_cvtl_s(CPUMIPSState
*env
, uint32_t fst0
)
2357 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2358 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2359 & (float_flag_invalid
| float_flag_overflow
)) {
2360 dt2
= FP_TO_INT64_OVERFLOW
;
2362 update_fcr31(env
, GETPC());
2366 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2371 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2372 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2373 update_fcr31(env
, GETPC());
2374 return ((uint64_t)fsth2
<< 32) | fst2
;
2377 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2383 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2384 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2385 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2386 wt2
= FP_TO_INT32_OVERFLOW
;
2389 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2390 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2391 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2392 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2393 wth2
= FP_TO_INT32_OVERFLOW
;
2396 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
2397 update_fcr31(env
, GETPC());
2399 return ((uint64_t)wth2
<< 32) | wt2
;
2402 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
2406 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2407 update_fcr31(env
, GETPC());
2411 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
2415 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2416 update_fcr31(env
, GETPC());
2420 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
2424 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2425 update_fcr31(env
, GETPC());
2429 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
2434 update_fcr31(env
, GETPC());
2438 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
2443 update_fcr31(env
, GETPC());
2447 uint32_t helper_float_cvtw_s(CPUMIPSState
*env
, uint32_t fst0
)
2451 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2452 update_fcr31(env
, GETPC());
2453 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2454 & (float_flag_invalid
| float_flag_overflow
)) {
2455 wt2
= FP_TO_INT32_OVERFLOW
;
2460 uint32_t helper_float_cvtw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2464 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2465 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2466 & (float_flag_invalid
| float_flag_overflow
)) {
2467 wt2
= FP_TO_INT32_OVERFLOW
;
2469 update_fcr31(env
, GETPC());
2473 uint64_t helper_float_roundl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2477 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2478 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2479 restore_rounding_mode(env
);
2480 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2481 & (float_flag_invalid
| float_flag_overflow
)) {
2482 dt2
= FP_TO_INT64_OVERFLOW
;
2484 update_fcr31(env
, GETPC());
2488 uint64_t helper_float_roundl_s(CPUMIPSState
*env
, uint32_t fst0
)
2492 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2493 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2494 restore_rounding_mode(env
);
2495 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2496 & (float_flag_invalid
| float_flag_overflow
)) {
2497 dt2
= FP_TO_INT64_OVERFLOW
;
2499 update_fcr31(env
, GETPC());
2503 uint32_t helper_float_roundw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2507 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2508 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2509 restore_rounding_mode(env
);
2510 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2511 & (float_flag_invalid
| float_flag_overflow
)) {
2512 wt2
= FP_TO_INT32_OVERFLOW
;
2514 update_fcr31(env
, GETPC());
2518 uint32_t helper_float_roundw_s(CPUMIPSState
*env
, uint32_t fst0
)
2522 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2523 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2524 restore_rounding_mode(env
);
2525 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2526 & (float_flag_invalid
| float_flag_overflow
)) {
2527 wt2
= FP_TO_INT32_OVERFLOW
;
2529 update_fcr31(env
, GETPC());
2533 uint64_t helper_float_truncl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2537 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2538 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2539 & (float_flag_invalid
| float_flag_overflow
)) {
2540 dt2
= FP_TO_INT64_OVERFLOW
;
2542 update_fcr31(env
, GETPC());
2546 uint64_t helper_float_truncl_s(CPUMIPSState
*env
, uint32_t fst0
)
2550 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2551 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2552 & (float_flag_invalid
| float_flag_overflow
)) {
2553 dt2
= FP_TO_INT64_OVERFLOW
;
2555 update_fcr31(env
, GETPC());
2559 uint32_t helper_float_truncw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2563 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2564 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2565 & (float_flag_invalid
| float_flag_overflow
)) {
2566 wt2
= FP_TO_INT32_OVERFLOW
;
2568 update_fcr31(env
, GETPC());
2572 uint32_t helper_float_truncw_s(CPUMIPSState
*env
, uint32_t fst0
)
2576 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2577 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2578 & (float_flag_invalid
| float_flag_overflow
)) {
2579 wt2
= FP_TO_INT32_OVERFLOW
;
2581 update_fcr31(env
, GETPC());
2585 uint64_t helper_float_ceill_d(CPUMIPSState
*env
, uint64_t fdt0
)
2589 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2590 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2591 restore_rounding_mode(env
);
2592 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2593 & (float_flag_invalid
| float_flag_overflow
)) {
2594 dt2
= FP_TO_INT64_OVERFLOW
;
2596 update_fcr31(env
, GETPC());
2600 uint64_t helper_float_ceill_s(CPUMIPSState
*env
, uint32_t fst0
)
2604 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2605 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2606 restore_rounding_mode(env
);
2607 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2608 & (float_flag_invalid
| float_flag_overflow
)) {
2609 dt2
= FP_TO_INT64_OVERFLOW
;
2611 update_fcr31(env
, GETPC());
2615 uint32_t helper_float_ceilw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2619 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2620 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2621 restore_rounding_mode(env
);
2622 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2623 & (float_flag_invalid
| float_flag_overflow
)) {
2624 wt2
= FP_TO_INT32_OVERFLOW
;
2626 update_fcr31(env
, GETPC());
2630 uint32_t helper_float_ceilw_s(CPUMIPSState
*env
, uint32_t fst0
)
2634 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2635 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2636 restore_rounding_mode(env
);
2637 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2638 & (float_flag_invalid
| float_flag_overflow
)) {
2639 wt2
= FP_TO_INT32_OVERFLOW
;
2641 update_fcr31(env
, GETPC());
2645 uint64_t helper_float_floorl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2649 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2650 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2651 restore_rounding_mode(env
);
2652 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2653 & (float_flag_invalid
| float_flag_overflow
)) {
2654 dt2
= FP_TO_INT64_OVERFLOW
;
2656 update_fcr31(env
, GETPC());
2660 uint64_t helper_float_floorl_s(CPUMIPSState
*env
, uint32_t fst0
)
2664 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2665 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2666 restore_rounding_mode(env
);
2667 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2668 & (float_flag_invalid
| float_flag_overflow
)) {
2669 dt2
= FP_TO_INT64_OVERFLOW
;
2671 update_fcr31(env
, GETPC());
2675 uint32_t helper_float_floorw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2679 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2680 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2681 restore_rounding_mode(env
);
2682 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2683 & (float_flag_invalid
| float_flag_overflow
)) {
2684 wt2
= FP_TO_INT32_OVERFLOW
;
2686 update_fcr31(env
, GETPC());
2690 uint32_t helper_float_floorw_s(CPUMIPSState
*env
, uint32_t fst0
)
2694 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2695 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2696 restore_rounding_mode(env
);
2697 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2698 & (float_flag_invalid
| float_flag_overflow
)) {
2699 wt2
= FP_TO_INT32_OVERFLOW
;
2701 update_fcr31(env
, GETPC());
2705 /* unary operations, not modifying fp status */
2706 #define FLOAT_UNOP(name) \
2707 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2709 return float64_ ## name(fdt0); \
2711 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2713 return float32_ ## name(fst0); \
2715 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2720 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2721 wth0 = float32_ ## name(fdt0 >> 32); \
2722 return ((uint64_t)wth0 << 32) | wt0; \
2728 /* MIPS specific unary operations */
2729 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
2733 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
2734 update_fcr31(env
, GETPC());
2738 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
2742 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
2743 update_fcr31(env
, GETPC());
2747 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2751 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2752 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
2753 update_fcr31(env
, GETPC());
2757 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2761 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2762 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
2763 update_fcr31(env
, GETPC());
2767 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
2771 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
2772 update_fcr31(env
, GETPC());
2776 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
2780 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
2781 update_fcr31(env
, GETPC());
2785 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2790 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2791 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
2792 update_fcr31(env
, GETPC());
2793 return ((uint64_t)fsth2
<< 32) | fst2
;
2796 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
2800 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2801 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
2802 update_fcr31(env
, GETPC());
2806 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
2810 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2811 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
2812 update_fcr31(env
, GETPC());
2816 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2821 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2822 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2823 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
2824 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
2825 update_fcr31(env
, GETPC());
2826 return ((uint64_t)fsth2
<< 32) | fst2
;
2829 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2831 /* binary operations */
2832 #define FLOAT_BINOP(name) \
2833 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2834 uint64_t fdt0, uint64_t fdt1) \
2838 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2839 update_fcr31(env, GETPC()); \
2843 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2844 uint32_t fst0, uint32_t fst1) \
2848 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2849 update_fcr31(env, GETPC()); \
2853 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2857 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2858 uint32_t fsth0 = fdt0 >> 32; \
2859 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2860 uint32_t fsth1 = fdt1 >> 32; \
2864 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2865 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2866 update_fcr31(env, GETPC()); \
2867 return ((uint64_t)wth2 << 32) | wt2; \
2876 #define UNFUSED_FMA(prefix, a, b, c, flags) \
2878 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
2879 if ((flags) & float_muladd_negate_c) { \
2880 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
2882 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
2884 if ((flags) & float_muladd_negate_result) { \
2885 a = prefix##_chs(a); \
2889 /* FMA based operations */
2890 #define FLOAT_FMA(name, type) \
2891 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2892 uint64_t fdt0, uint64_t fdt1, \
2895 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
2896 update_fcr31(env, GETPC()); \
2900 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2901 uint32_t fst0, uint32_t fst1, \
2904 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2905 update_fcr31(env, GETPC()); \
2909 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2910 uint64_t fdt0, uint64_t fdt1, \
2913 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2914 uint32_t fsth0 = fdt0 >> 32; \
2915 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2916 uint32_t fsth1 = fdt1 >> 32; \
2917 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2918 uint32_t fsth2 = fdt2 >> 32; \
2920 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2921 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
2922 update_fcr31(env, GETPC()); \
2923 return ((uint64_t)fsth0 << 32) | fst0; \
2926 FLOAT_FMA(msub
, float_muladd_negate_c
)
2927 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
2928 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
2931 /* MIPS specific binary operations */
2932 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
2934 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
2935 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
2936 update_fcr31(env
, GETPC());
2940 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
2942 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
2943 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
2944 update_fcr31(env
, GETPC());
2948 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
2950 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
2951 uint32_t fsth0
= fdt0
>> 32;
2952 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
2953 uint32_t fsth2
= fdt2
>> 32;
2955 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
2956 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
2957 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
2958 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
2959 update_fcr31(env
, GETPC());
2960 return ((uint64_t)fsth2
<< 32) | fst2
;
2963 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
2965 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
2966 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
2967 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
2968 update_fcr31(env
, GETPC());
2972 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
2974 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
2975 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
2976 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
2977 update_fcr31(env
, GETPC());
2981 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
2983 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
2984 uint32_t fsth0
= fdt0
>> 32;
2985 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
2986 uint32_t fsth2
= fdt2
>> 32;
2988 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
2989 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
2990 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
2991 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
2992 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
2993 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
2994 update_fcr31(env
, GETPC());
2995 return ((uint64_t)fsth2
<< 32) | fst2
;
2998 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3000 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3001 uint32_t fsth0
= fdt0
>> 32;
3002 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3003 uint32_t fsth1
= fdt1
>> 32;
3007 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3008 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3009 update_fcr31(env
, GETPC());
3010 return ((uint64_t)fsth2
<< 32) | fst2
;
3013 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3015 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3016 uint32_t fsth0
= fdt0
>> 32;
3017 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3018 uint32_t fsth1
= fdt1
>> 32;
3022 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3023 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3024 update_fcr31(env
, GETPC());
3025 return ((uint64_t)fsth2
<< 32) | fst2
;
3028 /* compare operations */
3029 #define FOP_COND_D(op, cond) \
3030 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3031 uint64_t fdt1, int cc) \
3035 update_fcr31(env, GETPC()); \
3037 SET_FP_COND(cc, env->active_fpu); \
3039 CLEAR_FP_COND(cc, env->active_fpu); \
3041 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3042 uint64_t fdt1, int cc) \
3045 fdt0 = float64_abs(fdt0); \
3046 fdt1 = float64_abs(fdt1); \
3048 update_fcr31(env, GETPC()); \
3050 SET_FP_COND(cc, env->active_fpu); \
3052 CLEAR_FP_COND(cc, env->active_fpu); \
3055 /* NOTE: the comma operator will make "cond" to eval to false,
3056 * but float64_unordered_quiet() is still called. */
3057 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3058 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3059 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3060 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3061 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3062 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3063 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3064 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3065 /* NOTE: the comma operator will make "cond" to eval to false,
3066 * but float64_unordered() is still called. */
3067 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3068 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3069 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3070 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3071 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3072 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3073 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3074 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3076 #define FOP_COND_S(op, cond) \
3077 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3078 uint32_t fst1, int cc) \
3082 update_fcr31(env, GETPC()); \
3084 SET_FP_COND(cc, env->active_fpu); \
3086 CLEAR_FP_COND(cc, env->active_fpu); \
3088 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3089 uint32_t fst1, int cc) \
3092 fst0 = float32_abs(fst0); \
3093 fst1 = float32_abs(fst1); \
3095 update_fcr31(env, GETPC()); \
3097 SET_FP_COND(cc, env->active_fpu); \
3099 CLEAR_FP_COND(cc, env->active_fpu); \
3102 /* NOTE: the comma operator will make "cond" to eval to false,
3103 * but float32_unordered_quiet() is still called. */
3104 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3105 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3106 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3107 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3108 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3109 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3110 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3111 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3112 /* NOTE: the comma operator will make "cond" to eval to false,
3113 * but float32_unordered() is still called. */
3114 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3115 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3116 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3117 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3118 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3119 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3120 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3121 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3123 #define FOP_COND_PS(op, condl, condh) \
3124 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3125 uint64_t fdt1, int cc) \
3127 uint32_t fst0, fsth0, fst1, fsth1; \
3129 fst0 = fdt0 & 0XFFFFFFFF; \
3130 fsth0 = fdt0 >> 32; \
3131 fst1 = fdt1 & 0XFFFFFFFF; \
3132 fsth1 = fdt1 >> 32; \
3135 update_fcr31(env, GETPC()); \
3137 SET_FP_COND(cc, env->active_fpu); \
3139 CLEAR_FP_COND(cc, env->active_fpu); \
3141 SET_FP_COND(cc + 1, env->active_fpu); \
3143 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3145 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3146 uint64_t fdt1, int cc) \
3148 uint32_t fst0, fsth0, fst1, fsth1; \
3150 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3151 fsth0 = float32_abs(fdt0 >> 32); \
3152 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3153 fsth1 = float32_abs(fdt1 >> 32); \
3156 update_fcr31(env, GETPC()); \
3158 SET_FP_COND(cc, env->active_fpu); \
3160 CLEAR_FP_COND(cc, env->active_fpu); \
3162 SET_FP_COND(cc + 1, env->active_fpu); \
3164 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3167 /* NOTE: the comma operator will make "cond" to eval to false,
3168 * but float32_unordered_quiet() is still called. */
3169 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3170 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3171 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3172 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3173 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3174 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3175 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3176 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3177 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3178 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3179 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3180 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3181 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3182 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3183 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3184 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3185 /* NOTE: the comma operator will make "cond" to eval to false,
3186 * but float32_unordered() is still called. */
3187 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3188 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3189 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3190 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3191 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3192 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3193 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3194 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3195 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3196 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3197 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3198 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3199 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3200 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3201 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3202 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))