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target-mips: add MSA defines and data structure
[mirror_qemu.git] / target-mips / translate_init.c
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t SEGBITS;
88 int32_t PABITS;
89 int32_t CP0_SRSConf0_rw_bitmask;
90 int32_t CP0_SRSConf0;
91 int32_t CP0_SRSConf1_rw_bitmask;
92 int32_t CP0_SRSConf1;
93 int32_t CP0_SRSConf2_rw_bitmask;
94 int32_t CP0_SRSConf2;
95 int32_t CP0_SRSConf3_rw_bitmask;
96 int32_t CP0_SRSConf3;
97 int32_t CP0_SRSConf4_rw_bitmask;
98 int32_t CP0_SRSConf4;
99 int32_t CP0_PageGrain_rw_bitmask;
100 int32_t CP0_PageGrain;
101 int insn_flags;
102 enum mips_mmu_types mmu_type;
103 };
104
105 /*****************************************************************************/
106 /* MIPS CPU definitions */
107 static const mips_def_t mips_defs[] =
108 {
109 {
110 .name = "4Kc",
111 .CP0_PRid = 0x00018000,
112 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
113 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
114 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
115 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
116 (0 << CP0C1_CA),
117 .CP0_Config2 = MIPS_CONFIG2,
118 .CP0_Config3 = MIPS_CONFIG3,
119 .CP0_LLAddr_rw_bitmask = 0,
120 .CP0_LLAddr_shift = 4,
121 .SYNCI_Step = 32,
122 .CCRes = 2,
123 .CP0_Status_rw_bitmask = 0x1278FF17,
124 .SEGBITS = 32,
125 .PABITS = 32,
126 .insn_flags = CPU_MIPS32,
127 .mmu_type = MMU_TYPE_R4000,
128 },
129 {
130 .name = "4Km",
131 .CP0_PRid = 0x00018300,
132 /* Config1 implemented, fixed mapping MMU,
133 no virtual icache, uncached coherency. */
134 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
135 .CP0_Config1 = MIPS_CONFIG1 |
136 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
137 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
138 (1 << CP0C1_CA),
139 .CP0_Config2 = MIPS_CONFIG2,
140 .CP0_Config3 = MIPS_CONFIG3,
141 .CP0_LLAddr_rw_bitmask = 0,
142 .CP0_LLAddr_shift = 4,
143 .SYNCI_Step = 32,
144 .CCRes = 2,
145 .CP0_Status_rw_bitmask = 0x1258FF17,
146 .SEGBITS = 32,
147 .PABITS = 32,
148 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
149 .mmu_type = MMU_TYPE_FMT,
150 },
151 {
152 .name = "4KEcR1",
153 .CP0_PRid = 0x00018400,
154 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
155 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
156 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
157 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
158 (0 << CP0C1_CA),
159 .CP0_Config2 = MIPS_CONFIG2,
160 .CP0_Config3 = MIPS_CONFIG3,
161 .CP0_LLAddr_rw_bitmask = 0,
162 .CP0_LLAddr_shift = 4,
163 .SYNCI_Step = 32,
164 .CCRes = 2,
165 .CP0_Status_rw_bitmask = 0x1278FF17,
166 .SEGBITS = 32,
167 .PABITS = 32,
168 .insn_flags = CPU_MIPS32,
169 .mmu_type = MMU_TYPE_R4000,
170 },
171 {
172 .name = "4KEmR1",
173 .CP0_PRid = 0x00018500,
174 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
175 .CP0_Config1 = MIPS_CONFIG1 |
176 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
177 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
178 (1 << CP0C1_CA),
179 .CP0_Config2 = MIPS_CONFIG2,
180 .CP0_Config3 = MIPS_CONFIG3,
181 .CP0_LLAddr_rw_bitmask = 0,
182 .CP0_LLAddr_shift = 4,
183 .SYNCI_Step = 32,
184 .CCRes = 2,
185 .CP0_Status_rw_bitmask = 0x1258FF17,
186 .SEGBITS = 32,
187 .PABITS = 32,
188 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
189 .mmu_type = MMU_TYPE_FMT,
190 },
191 {
192 .name = "4KEc",
193 .CP0_PRid = 0x00019000,
194 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
195 (MMU_TYPE_R4000 << CP0C0_MT),
196 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
197 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
198 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
199 (0 << CP0C1_CA),
200 .CP0_Config2 = MIPS_CONFIG2,
201 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
202 .CP0_LLAddr_rw_bitmask = 0,
203 .CP0_LLAddr_shift = 4,
204 .SYNCI_Step = 32,
205 .CCRes = 2,
206 .CP0_Status_rw_bitmask = 0x1278FF17,
207 .SEGBITS = 32,
208 .PABITS = 32,
209 .insn_flags = CPU_MIPS32R2,
210 .mmu_type = MMU_TYPE_R4000,
211 },
212 {
213 .name = "4KEm",
214 .CP0_PRid = 0x00019100,
215 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
216 (MMU_TYPE_FMT << CP0C0_MT),
217 .CP0_Config1 = MIPS_CONFIG1 |
218 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
219 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
220 (1 << CP0C1_CA),
221 .CP0_Config2 = MIPS_CONFIG2,
222 .CP0_Config3 = MIPS_CONFIG3,
223 .CP0_LLAddr_rw_bitmask = 0,
224 .CP0_LLAddr_shift = 4,
225 .SYNCI_Step = 32,
226 .CCRes = 2,
227 .CP0_Status_rw_bitmask = 0x1258FF17,
228 .SEGBITS = 32,
229 .PABITS = 32,
230 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
231 .mmu_type = MMU_TYPE_FMT,
232 },
233 {
234 .name = "24Kc",
235 .CP0_PRid = 0x00019300,
236 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
237 (MMU_TYPE_R4000 << CP0C0_MT),
238 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
239 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
240 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
241 (1 << CP0C1_CA),
242 .CP0_Config2 = MIPS_CONFIG2,
243 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
244 .CP0_LLAddr_rw_bitmask = 0,
245 .CP0_LLAddr_shift = 4,
246 .SYNCI_Step = 32,
247 .CCRes = 2,
248 /* No DSP implemented. */
249 .CP0_Status_rw_bitmask = 0x1278FF1F,
250 .SEGBITS = 32,
251 .PABITS = 32,
252 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
253 .mmu_type = MMU_TYPE_R4000,
254 },
255 {
256 .name = "24Kf",
257 .CP0_PRid = 0x00019300,
258 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
259 (MMU_TYPE_R4000 << CP0C0_MT),
260 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
261 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
262 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
263 (1 << CP0C1_CA),
264 .CP0_Config2 = MIPS_CONFIG2,
265 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
266 .CP0_LLAddr_rw_bitmask = 0,
267 .CP0_LLAddr_shift = 4,
268 .SYNCI_Step = 32,
269 .CCRes = 2,
270 /* No DSP implemented. */
271 .CP0_Status_rw_bitmask = 0x3678FF1F,
272 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
273 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
274 .SEGBITS = 32,
275 .PABITS = 32,
276 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
277 .mmu_type = MMU_TYPE_R4000,
278 },
279 {
280 .name = "34Kf",
281 .CP0_PRid = 0x00019500,
282 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
283 (MMU_TYPE_R4000 << CP0C0_MT),
284 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
285 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
286 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
287 (1 << CP0C1_CA),
288 .CP0_Config2 = MIPS_CONFIG2,
289 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
290 (1 << CP0C3_DSPP),
291 .CP0_LLAddr_rw_bitmask = 0,
292 .CP0_LLAddr_shift = 0,
293 .SYNCI_Step = 32,
294 .CCRes = 2,
295 .CP0_Status_rw_bitmask = 0x3778FF1F,
296 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
297 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
298 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
299 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
300 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
301 (0xff << CP0TCSt_TASID),
302 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
303 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
304 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
305 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
306 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
307 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
308 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
309 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
310 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
311 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
312 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
313 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
314 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
315 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
316 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
317 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
318 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
319 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
320 .SEGBITS = 32,
321 .PABITS = 32,
322 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .mmu_type = MMU_TYPE_R4000,
324 },
325 {
326 .name = "74Kf",
327 .CP0_PRid = 0x00019700,
328 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
329 (MMU_TYPE_R4000 << CP0C0_MT),
330 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
331 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
332 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
333 (1 << CP0C1_CA),
334 .CP0_Config2 = MIPS_CONFIG2,
335 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
336 .CP0_LLAddr_rw_bitmask = 0,
337 .CP0_LLAddr_shift = 4,
338 .SYNCI_Step = 32,
339 .CCRes = 2,
340 .CP0_Status_rw_bitmask = 0x3778FF1F,
341 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
342 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
343 .SEGBITS = 32,
344 .PABITS = 32,
345 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
346 .mmu_type = MMU_TYPE_R4000,
347 },
348 {
349 /* A generic CPU providing MIPS32 Release 5 features.
350 FIXME: Eventually this should be replaced by a real CPU model. */
351 .name = "mips32r5-generic",
352 .CP0_PRid = 0x00019700,
353 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
354 (MMU_TYPE_R4000 << CP0C0_MT),
355 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
356 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
357 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
358 (1 << CP0C1_CA),
359 .CP0_Config2 = MIPS_CONFIG2,
360 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
361 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
362 .CP0_Config4_rw_bitmask = 0,
363 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
364 .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
365 (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
366 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
367 (0 << CP0C5_NFExists),
368 .CP0_LLAddr_rw_bitmask = 0,
369 .CP0_LLAddr_shift = 4,
370 .SYNCI_Step = 32,
371 .CCRes = 2,
372 .CP0_Status_rw_bitmask = 0x3778FF1F,
373 .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
374 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
375 (0x93 << FCR0_PRID),
376 .SEGBITS = 32,
377 .PABITS = 32,
378 .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
379 .mmu_type = MMU_TYPE_R4000,
380 },
381 #if defined(TARGET_MIPS64)
382 {
383 .name = "R4000",
384 .CP0_PRid = 0x00000400,
385 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
386 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
387 /* Note: Config1 is only used internally, the R4000 has only Config0. */
388 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
389 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
390 .CP0_LLAddr_shift = 4,
391 .SYNCI_Step = 16,
392 .CCRes = 2,
393 .CP0_Status_rw_bitmask = 0x3678FFFF,
394 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
395 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
396 .SEGBITS = 40,
397 .PABITS = 36,
398 .insn_flags = CPU_MIPS3,
399 .mmu_type = MMU_TYPE_R4000,
400 },
401 {
402 .name = "VR5432",
403 .CP0_PRid = 0x00005400,
404 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
405 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
406 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
407 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
408 .CP0_LLAddr_shift = 4,
409 .SYNCI_Step = 16,
410 .CCRes = 2,
411 .CP0_Status_rw_bitmask = 0x3678FFFF,
412 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
413 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
414 .SEGBITS = 40,
415 .PABITS = 32,
416 .insn_flags = CPU_VR54XX,
417 .mmu_type = MMU_TYPE_R4000,
418 },
419 {
420 .name = "5Kc",
421 .CP0_PRid = 0x00018100,
422 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
423 (MMU_TYPE_R4000 << CP0C0_MT),
424 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
425 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
426 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
427 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
428 .CP0_Config2 = MIPS_CONFIG2,
429 .CP0_Config3 = MIPS_CONFIG3,
430 .CP0_LLAddr_rw_bitmask = 0,
431 .CP0_LLAddr_shift = 4,
432 .SYNCI_Step = 32,
433 .CCRes = 2,
434 .CP0_Status_rw_bitmask = 0x32F8FFFF,
435 .SEGBITS = 42,
436 .PABITS = 36,
437 .insn_flags = CPU_MIPS64,
438 .mmu_type = MMU_TYPE_R4000,
439 },
440 {
441 .name = "5Kf",
442 .CP0_PRid = 0x00018100,
443 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
444 (MMU_TYPE_R4000 << CP0C0_MT),
445 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
446 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
447 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
448 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
449 .CP0_Config2 = MIPS_CONFIG2,
450 .CP0_Config3 = MIPS_CONFIG3,
451 .CP0_LLAddr_rw_bitmask = 0,
452 .CP0_LLAddr_shift = 4,
453 .SYNCI_Step = 32,
454 .CCRes = 2,
455 .CP0_Status_rw_bitmask = 0x36F8FFFF,
456 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
457 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
458 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
459 .SEGBITS = 42,
460 .PABITS = 36,
461 .insn_flags = CPU_MIPS64,
462 .mmu_type = MMU_TYPE_R4000,
463 },
464 {
465 .name = "20Kc",
466 /* We emulate a later version of the 20Kc, earlier ones had a broken
467 WAIT instruction. */
468 .CP0_PRid = 0x000182a0,
469 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
470 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
471 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
472 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
473 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
474 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
475 .CP0_Config2 = MIPS_CONFIG2,
476 .CP0_Config3 = MIPS_CONFIG3,
477 .CP0_LLAddr_rw_bitmask = 0,
478 .CP0_LLAddr_shift = 0,
479 .SYNCI_Step = 32,
480 .CCRes = 1,
481 .CP0_Status_rw_bitmask = 0x36FBFFFF,
482 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
483 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
484 (1 << FCR0_D) | (1 << FCR0_S) |
485 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
486 .SEGBITS = 40,
487 .PABITS = 36,
488 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
489 .mmu_type = MMU_TYPE_R4000,
490 },
491 {
492 /* A generic CPU providing MIPS64 Release 2 features.
493 FIXME: Eventually this should be replaced by a real CPU model. */
494 .name = "MIPS64R2-generic",
495 .CP0_PRid = 0x00010000,
496 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
497 (MMU_TYPE_R4000 << CP0C0_MT),
498 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
499 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
500 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
501 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
502 .CP0_Config2 = MIPS_CONFIG2,
503 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
504 .CP0_LLAddr_rw_bitmask = 0,
505 .CP0_LLAddr_shift = 0,
506 .SYNCI_Step = 32,
507 .CCRes = 2,
508 .CP0_Status_rw_bitmask = 0x36FBFFFF,
509 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
510 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
511 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
512 .SEGBITS = 42,
513 /* The architectural limit is 59, but we have hardcoded 36 bit
514 in some places...
515 .PABITS = 59, */ /* the architectural limit */
516 .PABITS = 36,
517 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
518 .mmu_type = MMU_TYPE_R4000,
519 },
520 {
521 /* A generic CPU supporting MIPS64 Release 6 ISA.
522 FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
523 Eventually this should be replaced by a real CPU model. */
524 .name = "MIPS64R6-generic",
525 .CP0_PRid = 0x00010000,
526 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
527 (MMU_TYPE_R4000 << CP0C0_MT),
528 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
529 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
530 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
531 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
532 .CP0_Config2 = MIPS_CONFIG2,
533 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
534 (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
535 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
536 (3 << CP0C4_IE) | (1 << CP0C4_M),
537 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI),
538 .CP0_LLAddr_rw_bitmask = 0,
539 .CP0_LLAddr_shift = 0,
540 .SYNCI_Step = 32,
541 .CCRes = 2,
542 .CP0_Status_rw_bitmask = 0x30D8FFFF,
543 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
544 (1U << CP0PG_RIE),
545 .CP0_PageGrain_rw_bitmask = 0,
546 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
547 (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
548 (0x0 << FCR0_REV),
549 .SEGBITS = 42,
550 /* The architectural limit is 59, but we have hardcoded 36 bit
551 in some places...
552 .PABITS = 59, */ /* the architectural limit */
553 .PABITS = 36,
554 .insn_flags = CPU_MIPS64R6,
555 .mmu_type = MMU_TYPE_R4000,
556 },
557 {
558 .name = "Loongson-2E",
559 .CP0_PRid = 0x6302,
560 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
561 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
562 (0x1<<4) | (0x1<<1),
563 /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
564 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
565 .SYNCI_Step = 16,
566 .CCRes = 2,
567 .CP0_Status_rw_bitmask = 0x35D0FFFF,
568 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
569 .SEGBITS = 40,
570 .PABITS = 40,
571 .insn_flags = CPU_LOONGSON2E,
572 .mmu_type = MMU_TYPE_R4000,
573 },
574 {
575 .name = "Loongson-2F",
576 .CP0_PRid = 0x6303,
577 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
578 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
579 (0x1<<4) | (0x1<<1),
580 /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
581 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
582 .SYNCI_Step = 16,
583 .CCRes = 2,
584 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
585 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
586 .SEGBITS = 40,
587 .PABITS = 40,
588 .insn_flags = CPU_LOONGSON2F,
589 .mmu_type = MMU_TYPE_R4000,
590 },
591 {
592 /* A generic CPU providing MIPS64 ASE DSP 2 features.
593 FIXME: Eventually this should be replaced by a real CPU model. */
594 .name = "mips64dspr2",
595 .CP0_PRid = 0x00010000,
596 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
597 (MMU_TYPE_R4000 << CP0C0_MT),
598 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
599 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
600 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
601 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
602 .CP0_Config2 = MIPS_CONFIG2,
603 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
604 .CP0_LLAddr_rw_bitmask = 0,
605 .CP0_LLAddr_shift = 0,
606 .SYNCI_Step = 32,
607 .CCRes = 2,
608 .CP0_Status_rw_bitmask = 0x37FBFFFF,
609 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
610 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
611 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
612 .SEGBITS = 42,
613 /* The architectural limit is 59, but we have hardcoded 36 bit
614 in some places...
615 .PABITS = 59, */ /* the architectural limit */
616 .PABITS = 36,
617 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
618 .mmu_type = MMU_TYPE_R4000,
619 },
620
621 #endif
622 };
623
624 static const mips_def_t *cpu_mips_find_by_name (const char *name)
625 {
626 int i;
627
628 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
629 if (strcasecmp(name, mips_defs[i].name) == 0) {
630 return &mips_defs[i];
631 }
632 }
633 return NULL;
634 }
635
636 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
637 {
638 int i;
639
640 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
641 (*cpu_fprintf)(f, "MIPS '%s'\n",
642 mips_defs[i].name);
643 }
644 }
645
646 #ifndef CONFIG_USER_ONLY
647 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
648 {
649 env->tlb->nb_tlb = 1;
650 env->tlb->map_address = &no_mmu_map_address;
651 }
652
653 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
654 {
655 env->tlb->nb_tlb = 1;
656 env->tlb->map_address = &fixed_mmu_map_address;
657 }
658
659 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
660 {
661 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
662 env->tlb->map_address = &r4k_map_address;
663 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
664 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
665 env->tlb->helper_tlbp = r4k_helper_tlbp;
666 env->tlb->helper_tlbr = r4k_helper_tlbr;
667 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
668 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
669 }
670
671 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
672 {
673 MIPSCPU *cpu = mips_env_get_cpu(env);
674
675 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
676
677 switch (def->mmu_type) {
678 case MMU_TYPE_NONE:
679 no_mmu_init(env, def);
680 break;
681 case MMU_TYPE_R4000:
682 r4k_mmu_init(env, def);
683 break;
684 case MMU_TYPE_FMT:
685 fixed_mmu_init(env, def);
686 break;
687 case MMU_TYPE_R3000:
688 case MMU_TYPE_R6000:
689 case MMU_TYPE_R8000:
690 default:
691 cpu_abort(CPU(cpu), "MMU type not supported\n");
692 }
693 }
694 #endif /* CONFIG_USER_ONLY */
695
696 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
697 {
698 int i;
699
700 for (i = 0; i < MIPS_FPU_MAX; i++)
701 env->fpus[i].fcr0 = def->CP1_fcr0;
702
703 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
704 }
705
706 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
707 {
708 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
709
710 /* MVPConf1 implemented, TLB sharable, no gating storage support,
711 programmable cache partitioning implemented, number of allocatable
712 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
713 implemented, 5 TCs implemented. */
714 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
715 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
716 // TODO: actually do 2 VPEs.
717 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
718 // (0x04 << CP0MVPC0_PTC);
719 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
720 (0x00 << CP0MVPC0_PTC);
721 #if !defined(CONFIG_USER_ONLY)
722 /* Usermode has no TLB support */
723 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
724 #endif
725
726 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
727 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
728 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
729 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
730 (0x1 << CP0MVPC1_PCP1);
731 }
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