target-mips/translate_init.c

   1 /*
   2  *  MIPS emulation for qemu: CPU initialisation routines.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *  Copyright (c) 2007 Herve Poussineau
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /* CPU / CPU family specific config register values. */
  23
  24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
  25    uncached coherency */
  26 #define MIPS_CONFIG0                                              \
  27   ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
  28    (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
  29    (0x2 << CP0C0_K0))
  30
  31 /* Have config2, 64 sets Icache, 16 bytes Icache line,
  32    2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
  33    no coprocessor2 attached, no MDMX support attached,
  34    no performance counters, watch registers present,
  35    no code compression, EJTAG present, no FPU */
  36 #define MIPS_CONFIG1                                              \
  37 ((1 << CP0C1_M) |                                                 \
  38  (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \
  39  (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \
  40  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
  41  (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
  42  (0 << CP0C1_FP))
  43
  44 /* Have config3, no tertiary/secondary caches implemented */
  45 #define MIPS_CONFIG2                                              \
  46 ((1 << CP0C2_M))
  47
  48 /* No config4, no DSP ASE, no large physaddr,
  49    no external interrupt controller, no vectored interupts,
  50    no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
  51 #define MIPS_CONFIG3                                              \
  52 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  53  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
  54  (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
  55
  56 /* Define a implementation number of 1.
  57    Define a major version 1, minor version 0. */
  58 #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
  59
  60
  61 struct mips_def_t {
  62     const unsigned char *name;
  63     int32_t CP0_PRid;
  64     int32_t CP0_Config0;
  65     int32_t CP0_Config1;
  66     int32_t CP0_Config2;
  67     int32_t CP0_Config3;
  68     int32_t CP0_Config6;
  69     int32_t CP0_Config7;
  70     int32_t SYNCI_Step;
  71     int32_t CCRes;
  72     int32_t CP1_fcr0;
  73 };
  74
  75 /*****************************************************************************/
  76 /* MIPS CPU definitions */
  77 static mips_def_t mips_defs[] =
  78 {
  79 #ifndef TARGET_MIPS64
  80     {
  81         .name = "4Kc",
  82         .CP0_PRid = 0x00018000,
  83         .CP0_Config0 = MIPS_CONFIG0,
  84         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
  85         .CP0_Config2 = MIPS_CONFIG2,
  86         .CP0_Config3 = MIPS_CONFIG3,
  87         .SYNCI_Step = 32,
  88         .CCRes = 2,
  89         .CP1_fcr0 = MIPS_FCR0,
  90     },
  91     {
  92         .name = "4KEcR1",
  93         .CP0_PRid = 0x00018400,
  94         .CP0_Config0 = MIPS_CONFIG0,
  95         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
  96         .CP0_Config2 = MIPS_CONFIG2,
  97         .CP0_Config3 = MIPS_CONFIG3,
  98         .SYNCI_Step = 32,
  99         .CCRes = 2,
 100         .CP1_fcr0 = MIPS_FCR0,
 101     },
 102     {
 103         .name = "4KEc",
 104         .CP0_PRid = 0x00019000,
 105         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 106         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
 107         .CP0_Config2 = MIPS_CONFIG2,
 108         .CP0_Config3 = MIPS_CONFIG3,
 109         .SYNCI_Step = 32,
 110         .CCRes = 2,
 111         .CP1_fcr0 = MIPS_FCR0,
 112     },
 113     {
 114         .name = "24Kc",
 115         .CP0_PRid = 0x00019300,
 116         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 117         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
 118         .CP0_Config2 = MIPS_CONFIG2,
 119         .CP0_Config3 = MIPS_CONFIG3,
 120         .SYNCI_Step = 32,
 121         .CCRes = 2,
 122         .CP1_fcr0 = MIPS_FCR0,
 123     },
 124     {
 125         .name = "24Kf",
 126         .CP0_PRid = 0x00019300,
 127         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 128         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU),
 129         .CP0_Config2 = MIPS_CONFIG2,
 130         .CP0_Config3 = MIPS_CONFIG3,
 131         .SYNCI_Step = 32,
 132         .CCRes = 2,
 133         .CP1_fcr0 = MIPS_FCR0,
 134     },
 135 #else
 136     {
 137         .name = "R4000",
 138         .CP0_PRid = 0x00000400,
 139         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
 140         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 141         .CP0_Config2 = MIPS_CONFIG2,
 142         .CP0_Config3 = MIPS_CONFIG3,
 143         .SYNCI_Step = 16,
 144         .CCRes = 2,
 145         .CP1_fcr0 = MIPS_FCR0,
 146     },
 147 #endif
 148 };
 149
 150 int mips_find_by_name (const unsigned char *name, mips_def_t **def)
 151 {
 152     int i, ret;
 153
 154     ret = -1;
 155     *def = NULL;
 156     for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
 157         if (strcasecmp(name, mips_defs[i].name) == 0) {
 158             *def = &mips_defs[i];
 159             ret = 0;
 160             break;
 161         }
 162     }
 163
 164     return ret;
 165 }
 166
 167 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 168 {
 169     int i;
 170
 171     for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
 172         (*cpu_fprintf)(f, "MIPS '%s'\n",
 173                        mips_defs[i].name);
 174     }
 175 }
 176
 177 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
 178 {
 179     if (!def)
 180         cpu_abort(env, "Unable to find MIPS CPU definition\n");
 181     env->CP0_PRid = def->CP0_PRid;
 182 #ifdef TARGET_WORDS_BIGENDIAN
 183     env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE);
 184 #else
 185     env->CP0_Config0 = def->CP0_Config0;
 186 #endif
 187     env->CP0_Config1 = def->CP0_Config1;
 188     env->CP0_Config2 = def->CP0_Config2;
 189     env->CP0_Config3 = def->CP0_Config3;
 190     env->CP0_Config6 = def->CP0_Config6;
 191     env->CP0_Config7 = def->CP0_Config7;
 192     env->SYNCI_Step = def->SYNCI_Step;
 193     env->CCRes = def->CCRes;
 194     env->fcr0 = def->CP1_fcr0;
 195 #if defined (MIPS_USES_R4K_TLB)
 196     env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
 197     env->CP0_Random = env->nb_tlb - 1;
 198     env->tlb_in_use = env->nb_tlb;
 199 #endif
 200     return 0;
 201 }