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git.proxmox.com Git - qemu.git/blob - target-mips/translate_init.c
d327312e556912d2bffd7e86fd7dccd11fcf50ad
2 * MIPS emulation for qemu: CPU initialisation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* CPU / CPU family specific config register values. */
24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
26 #define MIPS_CONFIG0 \
27 ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
28 (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
31 /* Have config2, no coprocessor2 attached, no MDMX support attached,
32 no performance counters, watch registers present,
33 no code compression, EJTAG present, no FPU */
34 #define MIPS_CONFIG1 \
36 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
37 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
40 /* Have config3, no tertiary/secondary caches implemented */
41 #define MIPS_CONFIG2 \
44 /* No config4, no DSP ASE, no large physaddr,
45 no external interrupt controller, no vectored interupts,
46 no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
47 #define MIPS_CONFIG3 \
48 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
49 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
50 (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
52 /* Define a implementation number of 1.
53 Define a major version 1, minor version 0. */
54 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
58 const unsigned char *name
;
68 int32_t Status_rw_bitmask
;
73 /*****************************************************************************/
74 /* MIPS CPU definitions */
75 static mips_def_t mips_defs
[] =
79 .CP0_PRid
= 0x00018000,
80 .CP0_Config0
= MIPS_CONFIG0
,
81 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
82 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
83 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
),
84 .CP0_Config2
= MIPS_CONFIG2
,
85 .CP0_Config3
= MIPS_CONFIG3
,
88 .Status_rw_bitmask
= 0x3278FF17,
92 .CP0_PRid
= 0x00018400,
93 .CP0_Config0
= MIPS_CONFIG0
,
94 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
95 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
96 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
),
97 .CP0_Config2
= MIPS_CONFIG2
,
98 .CP0_Config3
= MIPS_CONFIG3
,
101 .Status_rw_bitmask
= 0x3278FF17,
105 .CP0_PRid
= 0x00019000,
106 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
),
107 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
108 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
109 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
),
110 .CP0_Config2
= MIPS_CONFIG2
,
111 .CP0_Config3
= MIPS_CONFIG3
,
114 .Status_rw_bitmask
= 0x3278FF17,
118 .CP0_PRid
= 0x00019300,
119 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
),
120 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
121 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
122 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
),
123 .CP0_Config2
= MIPS_CONFIG2
,
124 .CP0_Config3
= MIPS_CONFIG3
,
127 .Status_rw_bitmask
= 0x3278FF17,
131 .CP0_PRid
= 0x00019300,
132 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
),
133 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
134 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
135 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
),
136 .CP0_Config2
= MIPS_CONFIG2
,
137 .CP0_Config3
= MIPS_CONFIG3
,
140 .Status_rw_bitmask
= 0x3678FF17,
141 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
142 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x93 << FCR0_PRID
),
147 .CP0_PRid
= 0x00000400,
148 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
),
149 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (47 << CP0C1_MMU
) |
150 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
151 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
),
152 .CP0_Config2
= MIPS_CONFIG2
,
153 .CP0_Config3
= MIPS_CONFIG3
,
156 .Status_rw_bitmask
= 0x3678FFFF,
157 /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
158 .CP1_fcr0
= (0x5 << FCR0_PRID
) | (0x0 << FCR0_REV
),
163 .CP0_PRid
= 0x00018100,
164 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
),
165 .CP0_Config1
= MIPS_CONFIG1
| (31 << CP0C1_MMU
) |
166 (1 << CP0C1_IS
) | (4 << CP0C1_IL
) | (1 << CP0C1_IA
) |
167 (1 << CP0C1_DS
) | (4 << CP0C1_DL
) | (1 << CP0C1_DA
) |
168 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
169 .CP0_Config2
= MIPS_CONFIG2
,
170 .CP0_Config3
= MIPS_CONFIG3
,
173 .Status_rw_bitmask
= 0x32F8FFFF,
178 .CP0_PRid
= 0x00018100,
179 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
),
180 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (31 << CP0C1_MMU
) |
181 (1 << CP0C1_IS
) | (4 << CP0C1_IL
) | (1 << CP0C1_IA
) |
182 (1 << CP0C1_DS
) | (4 << CP0C1_DL
) | (1 << CP0C1_DA
) |
183 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
184 .CP0_Config2
= MIPS_CONFIG2
,
185 .CP0_Config3
= MIPS_CONFIG3
,
188 .Status_rw_bitmask
= 0x36F8FFFF,
189 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
190 .CP1_fcr0
= (1 << FCR0_D
) | (1 << FCR0_S
) |
191 (0x81 << FCR0_PRID
) | (0x0 << FCR0_REV
),
196 /* We emulate a later version of the 20Kc, earlier ones had a broken
198 .CP0_PRid
= 0x000182a0,
199 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
) | (1 << CP0C0_VI
),
200 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (47 << CP0C1_MMU
) |
201 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
202 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
203 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
204 .CP0_Config2
= MIPS_CONFIG2
,
205 .CP0_Config3
= MIPS_CONFIG3
,
208 .Status_rw_bitmask
= 0x36FBFFFF,
209 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
210 .CP1_fcr0
= (1 << FCR0_3D
) | (1 << FCR0_PS
) |
211 (1 << FCR0_D
) | (1 << FCR0_S
) |
212 (0x82 << FCR0_PRID
) | (0x0 << FCR0_REV
),
218 int mips_find_by_name (const unsigned char *name
, mips_def_t
**def
)
224 for (i
= 0; i
< sizeof(mips_defs
) / sizeof(mips_defs
[0]); i
++) {
225 if (strcasecmp(name
, mips_defs
[i
].name
) == 0) {
226 *def
= &mips_defs
[i
];
235 void mips_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
239 for (i
= 0; i
< sizeof(mips_defs
) / sizeof(mips_defs
[0]); i
++) {
240 (*cpu_fprintf
)(f
, "MIPS '%s'\n",
245 #ifndef CONFIG_USER_ONLY
246 static void no_mmu_init (CPUMIPSState
*env
, mips_def_t
*def
)
249 env
->map_address
= &no_mmu_map_address
;
252 static void fixed_mmu_init (CPUMIPSState
*env
, mips_def_t
*def
)
255 env
->map_address
= &fixed_mmu_map_address
;
258 static void r4k_mmu_init (CPUMIPSState
*env
, mips_def_t
*def
)
260 env
->nb_tlb
= 1 + ((def
->CP0_Config1
>> CP0C1_MMU
) & 63);
261 env
->map_address
= &r4k_map_address
;
262 env
->do_tlbwi
= r4k_do_tlbwi
;
263 env
->do_tlbwr
= r4k_do_tlbwr
;
264 env
->do_tlbp
= r4k_do_tlbp
;
265 env
->do_tlbr
= r4k_do_tlbr
;
267 #endif /* CONFIG_USER_ONLY */
269 int cpu_mips_register (CPUMIPSState
*env
, mips_def_t
*def
)
272 def
= env
->cpu_model
;
274 cpu_abort(env
, "Unable to find MIPS CPU definition\n");
275 env
->cpu_model
= def
;
276 env
->CP0_PRid
= def
->CP0_PRid
;
277 env
->CP0_Config0
= def
->CP0_Config0
;
278 #ifdef TARGET_WORDS_BIGENDIAN
279 env
->CP0_Config0
|= (1 << CP0C0_BE
);
281 env
->CP0_Config1
= def
->CP0_Config1
;
282 env
->CP0_Config2
= def
->CP0_Config2
;
283 env
->CP0_Config3
= def
->CP0_Config3
;
284 env
->CP0_Config6
= def
->CP0_Config6
;
285 env
->CP0_Config7
= def
->CP0_Config7
;
286 env
->SYNCI_Step
= def
->SYNCI_Step
;
287 env
->CCRes
= def
->CCRes
;
288 env
->Status_rw_bitmask
= def
->Status_rw_bitmask
;
289 env
->fcr0
= def
->CP1_fcr0
;
291 if ((env
->CP0_Config0
& (0x3 << CP0C0_AT
)))
293 env
->hflags
|= MIPS_HFLAG_64
;
294 env
->SEGBITS
= def
->SEGBITS
;
295 env
->SEGMask
= (3ULL << 62) | ((1ULL << def
->SEGBITS
) - 1);
298 env
->SEGMask
= 0xFFFFFFFF;
301 #ifdef CONFIG_USER_ONLY
302 if (env
->CP0_Config1
& (1 << CP0C1_FP
))
303 env
->hflags
|= MIPS_HFLAG_FPU
;
304 if (env
->fcr0
& (1 << FCR0_F64
))
305 env
->hflags
|= MIPS_HFLAG_F64
;
307 /* There are more full-featured MMU variants in older MIPS CPUs,
308 R3000, R6000 and R8000 come to mind. If we ever support them,
309 this check will need to look up a different place than those
310 newfangled config registers. */
311 switch ((env
->CP0_Config0
>> CP0C0_MT
) & 3) {
313 no_mmu_init(env
, def
);
316 r4k_mmu_init(env
, def
);
319 fixed_mmu_init(env
, def
);
322 cpu_abort(env
, "MMU type not supported\n");
324 env
->CP0_Random
= env
->nb_tlb
- 1;
325 env
->tlb_in_use
= env
->nb_tlb
;
326 #endif /* CONFIG_USER_ONLY */