target-mips/translate_init.c

   1 /*
   2  *  MIPS emulation for qemu: CPU initialisation routines.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *  Copyright (c) 2007 Herve Poussineau
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /* CPU / CPU family specific config register values. */
  23
  24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
  25    uncached coherency */
  26 #define MIPS_CONFIG0                                              \
  27   ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
  28    (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
  29    (0x2 << CP0C0_K0))
  30
  31 /* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
  32    2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
  33    no coprocessor2 attached, no MDMX support attached,
  34    no performance counters, watch registers present,
  35    no code compression, EJTAG present, no FPU */
  36 #define MIPS_CONFIG1                                              \
  37 ((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) |              \
  38  (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \
  39  (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \
  40  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
  41  (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
  42  (0 << CP0C1_FP))
  43
  44 /* Have config3, no tertiary/secondary caches implemented */
  45 #define MIPS_CONFIG2                                              \
  46 ((1 << CP0C2_M))
  47
  48 /* No config4, no DSP ASE, no large physaddr,
  49    no external interrupt controller, no vectored interupts,
  50    no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
  51 #define MIPS_CONFIG3                                              \
  52 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  53  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
  54  (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
  55
  56 /* Define a implementation number of 1.
  57    Define a major version 1, minor version 0. */
  58 #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
  59
  60
  61 struct mips_def_t {
  62     const unsigned char *name;
  63     int32_t CP0_PRid;
  64     int32_t CP0_Config0;
  65     int32_t CP0_Config1;
  66     int32_t CP0_Config2;
  67     int32_t CP0_Config3;
  68     int32_t CP1_fcr0;
  69 };
  70
  71 /*****************************************************************************/
  72 /* MIPS CPU definitions */
  73 static mips_def_t mips_defs[] =
  74 {
  75 #ifndef MIPS_HAS_MIPS64
  76     {
  77         .name = "4Kc",
  78         .CP0_PRid = 0x00018000,
  79         .CP0_Config0 = MIPS_CONFIG0,
  80         .CP0_Config1 = MIPS_CONFIG1,
  81         .CP0_Config2 = MIPS_CONFIG2,
  82         .CP0_Config3 = MIPS_CONFIG3,
  83         .CP1_fcr0 = MIPS_FCR0,
  84     },
  85     {
  86         .name = "4KEc",
  87         .CP0_PRid = 0x00018400,
  88         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
  89         .CP0_Config1 = MIPS_CONFIG1,
  90         .CP0_Config2 = MIPS_CONFIG2,
  91         .CP0_Config3 = MIPS_CONFIG3,
  92         .CP1_fcr0 = MIPS_FCR0,
  93     },
  94     {
  95         .name = "24Kf",
  96         .CP0_PRid = 0x00019300,
  97         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
  98         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
  99         .CP0_Config2 = MIPS_CONFIG2,
 100         .CP0_Config3 = MIPS_CONFIG3,
 101         .CP1_fcr0 = MIPS_FCR0,
 102     },
 103 #else
 104     {
 105         .name = "R4000",
 106         .CP0_PRid = 0x00000400,
 107         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
 108         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
 109         .CP0_Config2 = MIPS_CONFIG2,
 110         .CP0_Config3 = MIPS_CONFIG3,
 111         .CP1_fcr0 = MIPS_FCR0,
 112     },
 113 #endif
 114 };
 115
 116 int mips_find_by_name (const unsigned char *name, mips_def_t **def)
 117 {
 118     int i, ret;
 119
 120     ret = -1;
 121     *def = NULL;
 122     for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
 123         if (strcasecmp(name, mips_defs[i].name) == 0) {
 124             *def = &mips_defs[i];
 125             ret = 0;
 126             break;
 127         }
 128     }
 129
 130     return ret;
 131 }
 132
 133 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 134 {
 135     int i;
 136
 137     for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
 138         (*cpu_fprintf)(f, "MIPS '%s'\n",
 139                        mips_defs[i].name);
 140     }
 141 }
 142
 143 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
 144 {
 145     if (!def)
 146         cpu_abort(env, "Unable to find MIPS CPU definition\n");
 147     env->CP0_PRid = def->CP0_PRid;
 148 #ifdef TARGET_WORDS_BIGENDIAN
 149     env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE);
 150 #else
 151     env->CP0_Config0 = def->CP0_Config0;
 152 #endif
 153     env->CP0_Config1 = def->CP0_Config1;
 154     env->CP0_Config2 = def->CP0_Config2;
 155     env->CP0_Config3 = def->CP0_Config3;
 156     env->fcr0 = def->CP1_fcr0;
 157     return 0;
 158 }