target-openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu-common.h"
  22
  23 /* CPUClass::reset() */
  24 static void openrisc_cpu_reset(CPUState *s)
  25 {
  26     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  27     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  28
  29     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  30         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
  31         log_cpu_state(&cpu->env, 0);
  32     }
  33
  34     occ->parent_reset(s);
  35
  36     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
  37
  38     tlb_flush(&cpu->env, 1);
  39     /*tb_flush(&cpu->env);    FIXME: Do we need it?  */
  40
  41     cpu->env.pc = 0x100;
  42     cpu->env.sr = SR_FO | SR_SM;
  43     cpu->env.exception_index = -1;
  44
  45     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
  46     cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
  47     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  48     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  49
  50 #ifndef CONFIG_USER_ONLY
  51     cpu->env.picmr = 0x00000000;
  52     cpu->env.picsr = 0x00000000;
  53
  54     cpu->env.ttmr = 0x00000000;
  55     cpu->env.ttcr = 0x00000000;
  56 #endif
  57 }
  58
  59 static inline void set_feature(OpenRISCCPU *cpu, int feature)
  60 {
  61     cpu->feature |= feature;
  62     cpu->env.cpucfgr = cpu->feature;
  63 }
  64
  65 void openrisc_cpu_realize(Object *obj, Error **errp)
  66 {
  67     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  68
  69     qemu_init_vcpu(&cpu->env);
  70     cpu_reset(CPU(cpu));
  71 }
  72
  73 static void openrisc_cpu_initfn(Object *obj)
  74 {
  75     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  76     static int inited;
  77
  78     cpu_exec_init(&cpu->env);
  79
  80 #ifndef CONFIG_USER_ONLY
  81     cpu_openrisc_mmu_init(cpu);
  82 #endif
  83
  84     if (tcg_enabled() && !inited) {
  85         inited = 1;
  86         openrisc_translate_init();
  87     }
  88 }
  89
  90 /* CPU models */
  91
  92 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
  93 {
  94     ObjectClass *oc;
  95
  96     if (cpu_model == NULL) {
  97         return NULL;
  98     }
  99
 100     oc = object_class_by_name(cpu_model);
 101     if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU)) {
 102         return NULL;
 103     }
 104     return oc;
 105 }
 106
 107 static void or1200_initfn(Object *obj)
 108 {
 109     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 110
 111     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 112     set_feature(cpu, OPENRISC_FEATURE_OF32S);
 113 }
 114
 115 static void openrisc_any_initfn(Object *obj)
 116 {
 117     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 118
 119     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 120 }
 121
 122 typedef struct OpenRISCCPUInfo {
 123     const char *name;
 124     void (*initfn)(Object *obj);
 125 } OpenRISCCPUInfo;
 126
 127 static const OpenRISCCPUInfo openrisc_cpus[] = {
 128     { .name = "or1200",      .initfn = or1200_initfn },
 129     { .name = "any",         .initfn = openrisc_any_initfn },
 130 };
 131
 132 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 133 {
 134     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 135     CPUClass *cc = CPU_CLASS(occ);
 136
 137     occ->parent_reset = cc->reset;
 138     cc->reset = openrisc_cpu_reset;
 139
 140     cc->class_by_name = openrisc_cpu_class_by_name;
 141 }
 142
 143 static void cpu_register(const OpenRISCCPUInfo *info)
 144 {
 145     TypeInfo type_info = {
 146         .name = info->name,
 147         .parent = TYPE_OPENRISC_CPU,
 148         .instance_size = sizeof(OpenRISCCPU),
 149         .instance_init = info->initfn,
 150         .class_size = sizeof(OpenRISCCPUClass),
 151     };
 152
 153     type_register_static(&type_info);
 154 }
 155
 156 static const TypeInfo openrisc_cpu_type_info = {
 157     .name = TYPE_OPENRISC_CPU,
 158     .parent = TYPE_CPU,
 159     .instance_size = sizeof(OpenRISCCPU),
 160     .instance_init = openrisc_cpu_initfn,
 161     .abstract = false,
 162     .class_size = sizeof(OpenRISCCPUClass),
 163     .class_init = openrisc_cpu_class_init,
 164 };
 165
 166 static void openrisc_cpu_register_types(void)
 167 {
 168     int i;
 169
 170     type_register_static(&openrisc_cpu_type_info);
 171     for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
 172         cpu_register(&openrisc_cpus[i]);
 173     }
 174 }
 175
 176 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
 177 {
 178     OpenRISCCPU *cpu;
 179     ObjectClass *oc;
 180
 181     oc = openrisc_cpu_class_by_name(cpu_model);
 182     if (oc == NULL) {
 183         return NULL;
 184     }
 185     cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
 186     cpu->env.cpu_model_str = cpu_model;
 187
 188     openrisc_cpu_realize(OBJECT(cpu), NULL);
 189
 190     return cpu;
 191 }
 192
 193 /* Sort alphabetically by type name, except for "any". */
 194 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 195 {
 196     ObjectClass *class_a = (ObjectClass *)a;
 197     ObjectClass *class_b = (ObjectClass *)b;
 198     const char *name_a, *name_b;
 199
 200     name_a = object_class_get_name(class_a);
 201     name_b = object_class_get_name(class_b);
 202     if (strcmp(name_a, "any") == 0) {
 203         return 1;
 204     } else if (strcmp(name_b, "any") == 0) {
 205         return -1;
 206     } else {
 207         return strcmp(name_a, name_b);
 208     }
 209 }
 210
 211 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 212 {
 213     ObjectClass *oc = data;
 214     CPUListState *s = user_data;
 215
 216     (*s->cpu_fprintf)(s->file, "  %s\n",
 217                       object_class_get_name(oc));
 218 }
 219
 220 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 221 {
 222     CPUListState s = {
 223         .file = f,
 224         .cpu_fprintf = cpu_fprintf,
 225     };
 226     GSList *list;
 227
 228     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 229     list = g_slist_sort(list, openrisc_cpu_list_compare);
 230     (*cpu_fprintf)(f, "Available CPUs:\n");
 231     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 232     g_slist_free(list);
 233 }
 234
 235 type_init(openrisc_cpu_register_types)