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1 /*
2 * OpenRISC virtual CPU header.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef CPU_OPENRISC_H
21 #define CPU_OPENRISC_H
22
23 #define TARGET_LONG_BITS 32
24 #define ELF_MACHINE EM_OPENRISC
25
26 #define CPUArchState struct CPUOpenRISCState
27
28 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
29 struct OpenRISCCPU;
30
31 #include "config.h"
32 #include "qemu-common.h"
33 #include "cpu-defs.h"
34 #include "softfloat.h"
35 #include "qemu/cpu.h"
36 #include "error.h"
37
38 #define TYPE_OPENRISC_CPU "or32-cpu"
39
40 #define OPENRISC_CPU_CLASS(klass) \
41 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
42 #define OPENRISC_CPU(obj) \
43 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
44 #define OPENRISC_CPU_GET_CLASS(obj) \
45 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
46
47 /**
48 * OpenRISCCPUClass:
49 * @parent_reset: The parent class' reset handler.
50 *
51 * A OpenRISC CPU model.
52 */
53 typedef struct OpenRISCCPUClass {
54 /*< private >*/
55 CPUClass parent_class;
56 /*< public >*/
57
58 void (*parent_reset)(CPUState *cpu);
59 } OpenRISCCPUClass;
60
61 #define NB_MMU_MODES 3
62
63 enum {
64 MMU_NOMMU_IDX = 0,
65 MMU_SUPERVISOR_IDX = 1,
66 MMU_USER_IDX = 2,
67 };
68
69 #define TARGET_PAGE_BITS 13
70
71 #define TARGET_PHYS_ADDR_SPACE_BITS 32
72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
73
74 #define SET_FP_CAUSE(reg, v) do {\
75 (reg) = ((reg) & ~(0x3f << 12)) | \
76 ((v & 0x3f) << 12);\
77 } while (0)
78 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
79 #define UPDATE_FP_FLAGS(reg, v) do {\
80 (reg) |= ((v & 0x1f) << 2);\
81 } while (0)
82
83 /* Version Register */
84 #define SPR_VR 0xFFFF003F
85
86 /* Internal flags, delay slot flag */
87 #define D_FLAG 1
88
89 /* Interrupt */
90 #define NR_IRQS 32
91
92 /* Registers */
93 enum {
94 R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
95 R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
96 R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
97 R31
98 };
99
100 /* Register aliases */
101 enum {
102 R_ZERO = R0,
103 R_SP = R1,
104 R_FP = R2,
105 R_LR = R9,
106 R_RV = R11,
107 R_RVH = R12
108 };
109
110 /* Unit presece register */
111 enum {
112 UPR_UP = (1 << 0),
113 UPR_DCP = (1 << 1),
114 UPR_ICP = (1 << 2),
115 UPR_DMP = (1 << 3),
116 UPR_IMP = (1 << 4),
117 UPR_MP = (1 << 5),
118 UPR_DUP = (1 << 6),
119 UPR_PCUR = (1 << 7),
120 UPR_PMP = (1 << 8),
121 UPR_PICP = (1 << 9),
122 UPR_TTP = (1 << 10),
123 UPR_CUP = (255 << 24),
124 };
125
126 /* CPU configure register */
127 enum {
128 CPUCFGR_NSGF = (15 << 0),
129 CPUCFGR_CGF = (1 << 4),
130 CPUCFGR_OB32S = (1 << 5),
131 CPUCFGR_OB64S = (1 << 6),
132 CPUCFGR_OF32S = (1 << 7),
133 CPUCFGR_OF64S = (1 << 8),
134 CPUCFGR_OV64S = (1 << 9),
135 };
136
137 /* DMMU configure register */
138 enum {
139 DMMUCFGR_NTW = (3 << 0),
140 DMMUCFGR_NTS = (7 << 2),
141 DMMUCFGR_NAE = (7 << 5),
142 DMMUCFGR_CRI = (1 << 8),
143 DMMUCFGR_PRI = (1 << 9),
144 DMMUCFGR_TEIRI = (1 << 10),
145 DMMUCFGR_HTR = (1 << 11),
146 };
147
148 /* IMMU configure register */
149 enum {
150 IMMUCFGR_NTW = (3 << 0),
151 IMMUCFGR_NTS = (7 << 2),
152 IMMUCFGR_NAE = (7 << 5),
153 IMMUCFGR_CRI = (1 << 8),
154 IMMUCFGR_PRI = (1 << 9),
155 IMMUCFGR_TEIRI = (1 << 10),
156 IMMUCFGR_HTR = (1 << 11),
157 };
158
159 /* Float point control status register */
160 enum {
161 FPCSR_FPEE = 1,
162 FPCSR_RM = (3 << 1),
163 FPCSR_OVF = (1 << 3),
164 FPCSR_UNF = (1 << 4),
165 FPCSR_SNF = (1 << 5),
166 FPCSR_QNF = (1 << 6),
167 FPCSR_ZF = (1 << 7),
168 FPCSR_IXF = (1 << 8),
169 FPCSR_IVF = (1 << 9),
170 FPCSR_INF = (1 << 10),
171 FPCSR_DZF = (1 << 11),
172 };
173
174 /* Exceptions indices */
175 enum {
176 EXCP_RESET = 0x1,
177 EXCP_BUSERR = 0x2,
178 EXCP_DPF = 0x3,
179 EXCP_IPF = 0x4,
180 EXCP_TICK = 0x5,
181 EXCP_ALIGN = 0x6,
182 EXCP_ILLEGAL = 0x7,
183 EXCP_INT = 0x8,
184 EXCP_DTLBMISS = 0x9,
185 EXCP_ITLBMISS = 0xa,
186 EXCP_RANGE = 0xb,
187 EXCP_SYSCALL = 0xc,
188 EXCP_FPE = 0xd,
189 EXCP_TRAP = 0xe,
190 EXCP_NR,
191 };
192
193 /* Supervisor register */
194 enum {
195 SR_SM = (1 << 0),
196 SR_TEE = (1 << 1),
197 SR_IEE = (1 << 2),
198 SR_DCE = (1 << 3),
199 SR_ICE = (1 << 4),
200 SR_DME = (1 << 5),
201 SR_IME = (1 << 6),
202 SR_LEE = (1 << 7),
203 SR_CE = (1 << 8),
204 SR_F = (1 << 9),
205 SR_CY = (1 << 10),
206 SR_OV = (1 << 11),
207 SR_OVE = (1 << 12),
208 SR_DSX = (1 << 13),
209 SR_EPH = (1 << 14),
210 SR_FO = (1 << 15),
211 SR_SUMRA = (1 << 16),
212 SR_SCE = (1 << 17),
213 };
214
215 /* OpenRISC Hardware Capabilities */
216 enum {
217 OPENRISC_FEATURE_NSGF = (15 << 0),
218 OPENRISC_FEATURE_CGF = (1 << 4),
219 OPENRISC_FEATURE_OB32S = (1 << 5),
220 OPENRISC_FEATURE_OB64S = (1 << 6),
221 OPENRISC_FEATURE_OF32S = (1 << 7),
222 OPENRISC_FEATURE_OF64S = (1 << 8),
223 OPENRISC_FEATURE_OV64S = (1 << 9),
224 };
225
226 /* Tick Timer Mode Register */
227 enum {
228 TTMR_TP = (0xfffffff),
229 TTMR_IP = (1 << 28),
230 TTMR_IE = (1 << 29),
231 TTMR_M = (3 << 30),
232 };
233
234 /* Timer Mode */
235 enum {
236 TIMER_NONE = (0 << 30),
237 TIMER_INTR = (1 << 30),
238 TIMER_SHOT = (2 << 30),
239 TIMER_CONT = (3 << 30),
240 };
241
242 /* TLB size */
243 enum {
244 DTLB_WAYS = 1,
245 DTLB_SIZE = 64,
246 DTLB_MASK = (DTLB_SIZE-1),
247 ITLB_WAYS = 1,
248 ITLB_SIZE = 64,
249 ITLB_MASK = (ITLB_SIZE-1),
250 };
251
252 /* TLB prot */
253 enum {
254 URE = (1 << 6),
255 UWE = (1 << 7),
256 SRE = (1 << 8),
257 SWE = (1 << 9),
258
259 SXE = (1 << 6),
260 UXE = (1 << 7),
261 };
262
263 /* check if tlb available */
264 enum {
265 TLBRET_INVALID = -3,
266 TLBRET_NOMATCH = -2,
267 TLBRET_BADADDR = -1,
268 TLBRET_MATCH = 0
269 };
270
271 typedef struct OpenRISCTLBEntry {
272 uint32_t mr;
273 uint32_t tr;
274 } OpenRISCTLBEntry;
275
276 #ifndef CONFIG_USER_ONLY
277 typedef struct CPUOpenRISCTLBContext {
278 OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
279 OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
280
281 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
282 target_phys_addr_t *physical,
283 int *prot,
284 target_ulong address, int rw);
285 int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
286 target_phys_addr_t *physical,
287 int *prot,
288 target_ulong address, int rw);
289 } CPUOpenRISCTLBContext;
290 #endif
291
292 typedef struct CPUOpenRISCState {
293 target_ulong gpr[32]; /* General registers */
294 target_ulong pc; /* Program counter */
295 target_ulong npc; /* Next PC */
296 target_ulong ppc; /* Prev PC */
297 target_ulong jmp_pc; /* Jump PC */
298
299 target_ulong machi; /* Multiply register MACHI */
300 target_ulong maclo; /* Multiply register MACLO */
301
302 target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */
303 target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */
304
305 target_ulong epcr; /* Exception PC register */
306 target_ulong eear; /* Exception EA register */
307
308 uint32_t sr; /* Supervisor register */
309 uint32_t vr; /* Version register */
310 uint32_t upr; /* Unit presence register */
311 uint32_t cpucfgr; /* CPU configure register */
312 uint32_t dmmucfgr; /* DMMU configure register */
313 uint32_t immucfgr; /* IMMU configure register */
314 uint32_t esr; /* Exception supervisor register */
315 uint32_t fpcsr; /* Float register */
316 float_status fp_status;
317
318 uint32_t flags; /* cpu_flags, we only use it for exception
319 in solt so far. */
320 uint32_t btaken; /* the SR_F bit */
321
322 CPU_COMMON
323
324 #ifndef CONFIG_USER_ONLY
325 CPUOpenRISCTLBContext * tlb;
326
327 struct QEMUTimer *timer;
328 uint32_t ttmr; /* Timer tick mode register */
329 uint32_t ttcr; /* Timer tick count register */
330
331 uint32_t picmr; /* Interrupt mask register */
332 uint32_t picsr; /* Interrupt contrl register*/
333 #endif
334 void *irq[32]; /* Interrupt irq input */
335 } CPUOpenRISCState;
336
337 /**
338 * OpenRISCCPU:
339 * @env: #CPUOpenRISCState
340 *
341 * A OpenRISC CPU.
342 */
343 typedef struct OpenRISCCPU {
344 /*< private >*/
345 CPUState parent_obj;
346 /*< public >*/
347
348 CPUOpenRISCState env;
349
350 uint32_t feature; /* CPU Capabilities */
351 } OpenRISCCPU;
352
353 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
354 {
355 return OPENRISC_CPU(container_of(env, OpenRISCCPU, env));
356 }
357
358 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
359
360 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
361 void openrisc_cpu_realize(Object *obj, Error **errp);
362
363 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
364 int cpu_openrisc_exec(CPUOpenRISCState *s);
365 void do_interrupt(CPUOpenRISCState *env);
366 void openrisc_translate_init(void);
367 int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
368 target_ulong address,
369 int rw, int mmu_idx);
370 int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
371
372 #define cpu_list cpu_openrisc_list
373 #define cpu_exec cpu_openrisc_exec
374 #define cpu_gen_code cpu_openrisc_gen_code
375 #define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
376 #define cpu_signal_handler cpu_openrisc_signal_handler
377
378 #ifndef CONFIG_USER_ONLY
379 /* hw/openrisc_pic.c */
380 void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
381
382 /* hw/openrisc_timer.c */
383 void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
384 void cpu_openrisc_count_update(OpenRISCCPU *cpu);
385 void cpu_openrisc_count_start(OpenRISCCPU *cpu);
386 void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
387
388 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
389 int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
390 target_phys_addr_t *physical,
391 int *prot, target_ulong address, int rw);
392 int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
393 target_phys_addr_t *physical,
394 int *prot, target_ulong address, int rw);
395 int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
396 target_phys_addr_t *physical,
397 int *prot, target_ulong address, int rw);
398 #endif
399
400 static inline CPUOpenRISCState *cpu_init(const char *cpu_model)
401 {
402 OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model);
403 if (cpu) {
404 return &cpu->env;
405 }
406 return NULL;
407 }
408
409 #if defined(CONFIG_USER_ONLY)
410 static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong newsp)
411 {
412 if (newsp) {
413 env->gpr[1] = newsp;
414 }
415 env->gpr[2] = 0;
416 }
417 #endif
418
419 #include "cpu-all.h"
420
421 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
422 target_ulong *pc,
423 target_ulong *cs_base, int *flags)
424 {
425 *pc = env->pc;
426 *cs_base = 0;
427 /* D_FLAG -- branch instruction exception */
428 *flags = (env->flags & D_FLAG);
429 }
430
431 static inline int cpu_mmu_index(CPUOpenRISCState *env)
432 {
433 if (!(env->sr & SR_IME)) {
434 return MMU_NOMMU_IDX;
435 }
436 return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
437 }
438
439 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
440 static inline bool cpu_has_work(CPUOpenRISCState *env)
441 {
442 return env->interrupt_request & (CPU_INTERRUPT_HARD |
443 CPU_INTERRUPT_TIMER);
444 }
445
446 #include "exec-all.h"
447
448 static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
449 {
450 return env->pc;
451 }
452
453 static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBlock *tb)
454 {
455 env->pc = tb->pc;
456 }
457
458 #endif /* CPU_OPENRISC_H */