]> git.proxmox.com Git - mirror_qemu.git/blob - target-openrisc/translate.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
tcg: Invert the inclusion of helper.h
[mirror_qemu.git] / target-openrisc / translate.c
1 /*
2 * OpenRISC translation
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu-common.h"
26 #include "qemu/log.h"
27 #include "config.h"
28 #include "qemu/bitops.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #define OPENRISC_DISAS
34
35 #ifdef OPENRISC_DISAS
36 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
37 #else
38 # define LOG_DIS(...) do { } while (0)
39 #endif
40
41 typedef struct DisasContext {
42 TranslationBlock *tb;
43 target_ulong pc, ppc, npc;
44 uint32_t tb_flags, synced_flags, flags;
45 uint32_t is_jmp;
46 uint32_t mem_idx;
47 int singlestep_enabled;
48 uint32_t delayed_branch;
49 } DisasContext;
50
51 static TCGv_ptr cpu_env;
52 static TCGv cpu_sr;
53 static TCGv cpu_R[32];
54 static TCGv cpu_pc;
55 static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
56 static TCGv cpu_npc;
57 static TCGv cpu_ppc;
58 static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */
59 static TCGv_i32 fpcsr;
60 static TCGv machi, maclo;
61 static TCGv fpmaddhi, fpmaddlo;
62 static TCGv_i32 env_flags;
63 #include "exec/gen-icount.h"
64
65 void openrisc_translate_init(void)
66 {
67 static const char * const regnames[] = {
68 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
69 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
70 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
71 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
72 };
73 int i;
74
75 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
76 cpu_sr = tcg_global_mem_new(TCG_AREG0,
77 offsetof(CPUOpenRISCState, sr), "sr");
78 env_flags = tcg_global_mem_new_i32(TCG_AREG0,
79 offsetof(CPUOpenRISCState, flags),
80 "flags");
81 cpu_pc = tcg_global_mem_new(TCG_AREG0,
82 offsetof(CPUOpenRISCState, pc), "pc");
83 cpu_npc = tcg_global_mem_new(TCG_AREG0,
84 offsetof(CPUOpenRISCState, npc), "npc");
85 cpu_ppc = tcg_global_mem_new(TCG_AREG0,
86 offsetof(CPUOpenRISCState, ppc), "ppc");
87 jmp_pc = tcg_global_mem_new(TCG_AREG0,
88 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
89 env_btaken = tcg_global_mem_new_i32(TCG_AREG0,
90 offsetof(CPUOpenRISCState, btaken),
91 "btaken");
92 fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
93 offsetof(CPUOpenRISCState, fpcsr),
94 "fpcsr");
95 machi = tcg_global_mem_new(TCG_AREG0,
96 offsetof(CPUOpenRISCState, machi),
97 "machi");
98 maclo = tcg_global_mem_new(TCG_AREG0,
99 offsetof(CPUOpenRISCState, maclo),
100 "maclo");
101 fpmaddhi = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUOpenRISCState, fpmaddhi),
103 "fpmaddhi");
104 fpmaddlo = tcg_global_mem_new(TCG_AREG0,
105 offsetof(CPUOpenRISCState, fpmaddlo),
106 "fpmaddlo");
107 for (i = 0; i < 32; i++) {
108 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
109 offsetof(CPUOpenRISCState, gpr[i]),
110 regnames[i]);
111 }
112 }
113
114 /* Writeback SR_F translation space to execution space. */
115 static inline void wb_SR_F(void)
116 {
117 int label;
118
119 label = gen_new_label();
120 tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
121 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
122 tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
123 gen_set_label(label);
124 }
125
126 static inline int zero_extend(unsigned int val, int width)
127 {
128 return val & ((1 << width) - 1);
129 }
130
131 static inline int sign_extend(unsigned int val, int width)
132 {
133 int sval;
134
135 /* LSL */
136 val <<= TARGET_LONG_BITS - width;
137 sval = val;
138 /* ASR. */
139 sval >>= TARGET_LONG_BITS - width;
140 return sval;
141 }
142
143 static inline void gen_sync_flags(DisasContext *dc)
144 {
145 /* Sync the tb dependent flag between translate and runtime. */
146 if (dc->tb_flags != dc->synced_flags) {
147 tcg_gen_movi_tl(env_flags, dc->tb_flags);
148 dc->synced_flags = dc->tb_flags;
149 }
150 }
151
152 static void gen_exception(DisasContext *dc, unsigned int excp)
153 {
154 TCGv_i32 tmp = tcg_const_i32(excp);
155 gen_helper_exception(cpu_env, tmp);
156 tcg_temp_free_i32(tmp);
157 }
158
159 static void gen_illegal_exception(DisasContext *dc)
160 {
161 tcg_gen_movi_tl(cpu_pc, dc->pc);
162 gen_exception(dc, EXCP_ILLEGAL);
163 dc->is_jmp = DISAS_UPDATE;
164 }
165
166 /* not used yet, open it when we need or64. */
167 /*#ifdef TARGET_OPENRISC64
168 static void check_ob64s(DisasContext *dc)
169 {
170 if (!(dc->flags & CPUCFGR_OB64S)) {
171 gen_illegal_exception(dc);
172 }
173 }
174
175 static void check_of64s(DisasContext *dc)
176 {
177 if (!(dc->flags & CPUCFGR_OF64S)) {
178 gen_illegal_exception(dc);
179 }
180 }
181
182 static void check_ov64s(DisasContext *dc)
183 {
184 if (!(dc->flags & CPUCFGR_OV64S)) {
185 gen_illegal_exception(dc);
186 }
187 }
188 #endif*/
189
190 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
191 {
192 TranslationBlock *tb;
193 tb = dc->tb;
194 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
195 likely(!dc->singlestep_enabled)) {
196 tcg_gen_movi_tl(cpu_pc, dest);
197 tcg_gen_goto_tb(n);
198 tcg_gen_exit_tb((uintptr_t)tb + n);
199 } else {
200 tcg_gen_movi_tl(cpu_pc, dest);
201 if (dc->singlestep_enabled) {
202 gen_exception(dc, EXCP_DEBUG);
203 }
204 tcg_gen_exit_tb(0);
205 }
206 }
207
208 static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
209 {
210 target_ulong tmp_pc;
211 /* N26, 26bits imm */
212 tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
213
214 switch (op0) {
215 case 0x00: /* l.j */
216 tcg_gen_movi_tl(jmp_pc, tmp_pc);
217 break;
218 case 0x01: /* l.jal */
219 tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
220 tcg_gen_movi_tl(jmp_pc, tmp_pc);
221 break;
222 case 0x03: /* l.bnf */
223 case 0x04: /* l.bf */
224 {
225 int lab = gen_new_label();
226 TCGv sr_f = tcg_temp_new();
227 tcg_gen_movi_tl(jmp_pc, dc->pc+8);
228 tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
229 tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
230 sr_f, SR_F, lab);
231 tcg_gen_movi_tl(jmp_pc, tmp_pc);
232 gen_set_label(lab);
233 tcg_temp_free(sr_f);
234 }
235 break;
236 case 0x11: /* l.jr */
237 tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
238 break;
239 case 0x12: /* l.jalr */
240 tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
241 tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
242 break;
243 default:
244 gen_illegal_exception(dc);
245 break;
246 }
247
248 dc->delayed_branch = 2;
249 dc->tb_flags |= D_FLAG;
250 gen_sync_flags(dc);
251 }
252
253
254 static void dec_calc(DisasContext *dc, uint32_t insn)
255 {
256 uint32_t op0, op1, op2;
257 uint32_t ra, rb, rd;
258 op0 = extract32(insn, 0, 4);
259 op1 = extract32(insn, 8, 2);
260 op2 = extract32(insn, 6, 2);
261 ra = extract32(insn, 16, 5);
262 rb = extract32(insn, 11, 5);
263 rd = extract32(insn, 21, 5);
264
265 switch (op0) {
266 case 0x0000:
267 switch (op1) {
268 case 0x00: /* l.add */
269 LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb);
270 {
271 int lab = gen_new_label();
272 TCGv_i64 ta = tcg_temp_new_i64();
273 TCGv_i64 tb = tcg_temp_new_i64();
274 TCGv_i64 td = tcg_temp_local_new_i64();
275 TCGv_i32 res = tcg_temp_local_new_i32();
276 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
277 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
278 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
279 tcg_gen_add_i64(td, ta, tb);
280 tcg_gen_trunc_i64_i32(res, td);
281 tcg_gen_shri_i64(td, td, 31);
282 tcg_gen_andi_i64(td, td, 0x3);
283 /* Jump to lab when no overflow. */
284 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
285 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
286 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
287 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
288 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
289 gen_exception(dc, EXCP_RANGE);
290 gen_set_label(lab);
291 tcg_gen_mov_i32(cpu_R[rd], res);
292 tcg_temp_free_i64(ta);
293 tcg_temp_free_i64(tb);
294 tcg_temp_free_i64(td);
295 tcg_temp_free_i32(res);
296 tcg_temp_free_i32(sr_ove);
297 }
298 break;
299 default:
300 gen_illegal_exception(dc);
301 break;
302 }
303 break;
304
305 case 0x0001: /* l.addc */
306 switch (op1) {
307 case 0x00:
308 LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb);
309 {
310 int lab = gen_new_label();
311 TCGv_i64 ta = tcg_temp_new_i64();
312 TCGv_i64 tb = tcg_temp_new_i64();
313 TCGv_i64 tcy = tcg_temp_local_new_i64();
314 TCGv_i64 td = tcg_temp_local_new_i64();
315 TCGv_i32 res = tcg_temp_local_new_i32();
316 TCGv_i32 sr_cy = tcg_temp_local_new_i32();
317 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
318 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
319 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
320 tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
321 tcg_gen_extu_i32_i64(tcy, sr_cy);
322 tcg_gen_shri_i64(tcy, tcy, 10);
323 tcg_gen_add_i64(td, ta, tb);
324 tcg_gen_add_i64(td, td, tcy);
325 tcg_gen_trunc_i64_i32(res, td);
326 tcg_gen_shri_i64(td, td, 32);
327 tcg_gen_andi_i64(td, td, 0x3);
328 /* Jump to lab when no overflow. */
329 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
330 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
331 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
332 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
333 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
334 gen_exception(dc, EXCP_RANGE);
335 gen_set_label(lab);
336 tcg_gen_mov_i32(cpu_R[rd], res);
337 tcg_temp_free_i64(ta);
338 tcg_temp_free_i64(tb);
339 tcg_temp_free_i64(tcy);
340 tcg_temp_free_i64(td);
341 tcg_temp_free_i32(res);
342 tcg_temp_free_i32(sr_cy);
343 tcg_temp_free_i32(sr_ove);
344 }
345 break;
346 default:
347 gen_illegal_exception(dc);
348 break;
349 }
350 break;
351
352 case 0x0002: /* l.sub */
353 switch (op1) {
354 case 0x00:
355 LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb);
356 {
357 int lab = gen_new_label();
358 TCGv_i64 ta = tcg_temp_new_i64();
359 TCGv_i64 tb = tcg_temp_new_i64();
360 TCGv_i64 td = tcg_temp_local_new_i64();
361 TCGv_i32 res = tcg_temp_local_new_i32();
362 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
363
364 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
365 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
366 tcg_gen_sub_i64(td, ta, tb);
367 tcg_gen_trunc_i64_i32(res, td);
368 tcg_gen_shri_i64(td, td, 31);
369 tcg_gen_andi_i64(td, td, 0x3);
370 /* Jump to lab when no overflow. */
371 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
372 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
373 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
374 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
375 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
376 gen_exception(dc, EXCP_RANGE);
377 gen_set_label(lab);
378 tcg_gen_mov_i32(cpu_R[rd], res);
379 tcg_temp_free_i64(ta);
380 tcg_temp_free_i64(tb);
381 tcg_temp_free_i64(td);
382 tcg_temp_free_i32(res);
383 tcg_temp_free_i32(sr_ove);
384 }
385 break;
386 default:
387 gen_illegal_exception(dc);
388 break;
389 }
390 break;
391
392 case 0x0003: /* l.and */
393 switch (op1) {
394 case 0x00:
395 LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb);
396 tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
397 break;
398 default:
399 gen_illegal_exception(dc);
400 break;
401 }
402 break;
403
404 case 0x0004: /* l.or */
405 switch (op1) {
406 case 0x00:
407 LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb);
408 tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
409 break;
410 default:
411 gen_illegal_exception(dc);
412 break;
413 }
414 break;
415
416 case 0x0005:
417 switch (op1) {
418 case 0x00: /* l.xor */
419 LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb);
420 tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
421 break;
422 default:
423 gen_illegal_exception(dc);
424 break;
425 }
426 break;
427
428 case 0x0006:
429 switch (op1) {
430 case 0x03: /* l.mul */
431 LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb);
432 if (ra != 0 && rb != 0) {
433 gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
434 } else {
435 tcg_gen_movi_tl(cpu_R[rd], 0x0);
436 }
437 break;
438 default:
439 gen_illegal_exception(dc);
440 break;
441 }
442 break;
443
444 case 0x0009:
445 switch (op1) {
446 case 0x03: /* l.div */
447 LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
448 {
449 int lab0 = gen_new_label();
450 int lab1 = gen_new_label();
451 int lab2 = gen_new_label();
452 int lab3 = gen_new_label();
453 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
454 if (rb == 0) {
455 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
456 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
457 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
458 gen_exception(dc, EXCP_RANGE);
459 gen_set_label(lab0);
460 } else {
461 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb],
462 0x00000000, lab1);
463 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[ra],
464 0x80000000, lab2);
465 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
466 0xffffffff, lab2);
467 gen_set_label(lab1);
468 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
469 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
470 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3);
471 gen_exception(dc, EXCP_RANGE);
472 gen_set_label(lab2);
473 tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
474 gen_set_label(lab3);
475 }
476 tcg_temp_free_i32(sr_ove);
477 }
478 break;
479
480 default:
481 gen_illegal_exception(dc);
482 break;
483 }
484 break;
485
486 case 0x000a:
487 switch (op1) {
488 case 0x03: /* l.divu */
489 LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
490 {
491 int lab0 = gen_new_label();
492 int lab1 = gen_new_label();
493 int lab2 = gen_new_label();
494 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
495 if (rb == 0) {
496 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
497 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
498 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
499 gen_exception(dc, EXCP_RANGE);
500 gen_set_label(lab0);
501 } else {
502 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
503 0x00000000, lab1);
504 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
505 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
506 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab2);
507 gen_exception(dc, EXCP_RANGE);
508 gen_set_label(lab1);
509 tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
510 gen_set_label(lab2);
511 }
512 tcg_temp_free_i32(sr_ove);
513 }
514 break;
515
516 default:
517 gen_illegal_exception(dc);
518 break;
519 }
520 break;
521
522 case 0x000b:
523 switch (op1) {
524 case 0x03: /* l.mulu */
525 LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb);
526 if (rb != 0 && ra != 0) {
527 TCGv_i64 result = tcg_temp_local_new_i64();
528 TCGv_i64 tra = tcg_temp_local_new_i64();
529 TCGv_i64 trb = tcg_temp_local_new_i64();
530 TCGv_i64 high = tcg_temp_new_i64();
531 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
532 int lab = gen_new_label();
533 /* Calculate the each result. */
534 tcg_gen_extu_i32_i64(tra, cpu_R[ra]);
535 tcg_gen_extu_i32_i64(trb, cpu_R[rb]);
536 tcg_gen_mul_i64(result, tra, trb);
537 tcg_temp_free_i64(tra);
538 tcg_temp_free_i64(trb);
539 tcg_gen_shri_i64(high, result, TARGET_LONG_BITS);
540 /* Overflow or not. */
541 tcg_gen_brcondi_i64(TCG_COND_EQ, high, 0x00000000, lab);
542 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
543 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
544 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab);
545 gen_exception(dc, EXCP_RANGE);
546 gen_set_label(lab);
547 tcg_temp_free_i64(high);
548 tcg_gen_trunc_i64_tl(cpu_R[rd], result);
549 tcg_temp_free_i64(result);
550 tcg_temp_free_i32(sr_ove);
551 } else {
552 tcg_gen_movi_tl(cpu_R[rd], 0);
553 }
554 break;
555
556 default:
557 gen_illegal_exception(dc);
558 break;
559 }
560 break;
561
562 case 0x000e:
563 switch (op1) {
564 case 0x00: /* l.cmov */
565 LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
566 {
567 int lab = gen_new_label();
568 TCGv res = tcg_temp_local_new();
569 TCGv sr_f = tcg_temp_new();
570 tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
571 tcg_gen_mov_tl(res, cpu_R[rb]);
572 tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
573 tcg_gen_mov_tl(res, cpu_R[ra]);
574 gen_set_label(lab);
575 tcg_gen_mov_tl(cpu_R[rd], res);
576 tcg_temp_free(sr_f);
577 tcg_temp_free(res);
578 }
579 break;
580
581 default:
582 gen_illegal_exception(dc);
583 break;
584 }
585 break;
586
587 case 0x000f:
588 switch (op1) {
589 case 0x00: /* l.ff1 */
590 LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb);
591 gen_helper_ff1(cpu_R[rd], cpu_R[ra]);
592 break;
593 case 0x01: /* l.fl1 */
594 LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb);
595 gen_helper_fl1(cpu_R[rd], cpu_R[ra]);
596 break;
597
598 default:
599 gen_illegal_exception(dc);
600 break;
601 }
602 break;
603
604 case 0x0008:
605 switch (op1) {
606 case 0x00:
607 switch (op2) {
608 case 0x00: /* l.sll */
609 LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb);
610 tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
611 break;
612 case 0x01: /* l.srl */
613 LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb);
614 tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
615 break;
616 case 0x02: /* l.sra */
617 LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb);
618 tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
619 break;
620 case 0x03: /* l.ror */
621 LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb);
622 tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
623 break;
624
625 default:
626 gen_illegal_exception(dc);
627 break;
628 }
629 break;
630
631 default:
632 gen_illegal_exception(dc);
633 break;
634 }
635 break;
636
637 case 0x000c:
638 switch (op1) {
639 case 0x00:
640 switch (op2) {
641 case 0x00: /* l.exths */
642 LOG_DIS("l.exths r%d, r%d\n", rd, ra);
643 tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]);
644 break;
645 case 0x01: /* l.extbs */
646 LOG_DIS("l.extbs r%d, r%d\n", rd, ra);
647 tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]);
648 break;
649 case 0x02: /* l.exthz */
650 LOG_DIS("l.exthz r%d, r%d\n", rd, ra);
651 tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]);
652 break;
653 case 0x03: /* l.extbz */
654 LOG_DIS("l.extbz r%d, r%d\n", rd, ra);
655 tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]);
656 break;
657
658 default:
659 gen_illegal_exception(dc);
660 break;
661 }
662 break;
663
664 default:
665 gen_illegal_exception(dc);
666 break;
667 }
668 break;
669
670 case 0x000d:
671 switch (op1) {
672 case 0x00:
673 switch (op2) {
674 case 0x00: /* l.extws */
675 LOG_DIS("l.extws r%d, r%d\n", rd, ra);
676 tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]);
677 break;
678 case 0x01: /* l.extwz */
679 LOG_DIS("l.extwz r%d, r%d\n", rd, ra);
680 tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]);
681 break;
682
683 default:
684 gen_illegal_exception(dc);
685 break;
686 }
687 break;
688
689 default:
690 gen_illegal_exception(dc);
691 break;
692 }
693 break;
694
695 default:
696 gen_illegal_exception(dc);
697 break;
698 }
699 }
700
701 static void dec_misc(DisasContext *dc, uint32_t insn)
702 {
703 uint32_t op0, op1;
704 uint32_t ra, rb, rd;
705 #ifdef OPENRISC_DISAS
706 uint32_t L6, K5;
707 #endif
708 uint32_t I16, I5, I11, N26, tmp;
709 TCGMemOp mop;
710
711 op0 = extract32(insn, 26, 6);
712 op1 = extract32(insn, 24, 2);
713 ra = extract32(insn, 16, 5);
714 rb = extract32(insn, 11, 5);
715 rd = extract32(insn, 21, 5);
716 #ifdef OPENRISC_DISAS
717 L6 = extract32(insn, 5, 6);
718 K5 = extract32(insn, 0, 5);
719 #endif
720 I16 = extract32(insn, 0, 16);
721 I5 = extract32(insn, 21, 5);
722 I11 = extract32(insn, 0, 11);
723 N26 = extract32(insn, 0, 26);
724 tmp = (I5<<11) + I11;
725
726 switch (op0) {
727 case 0x00: /* l.j */
728 LOG_DIS("l.j %d\n", N26);
729 gen_jump(dc, N26, 0, op0);
730 break;
731
732 case 0x01: /* l.jal */
733 LOG_DIS("l.jal %d\n", N26);
734 gen_jump(dc, N26, 0, op0);
735 break;
736
737 case 0x03: /* l.bnf */
738 LOG_DIS("l.bnf %d\n", N26);
739 gen_jump(dc, N26, 0, op0);
740 break;
741
742 case 0x04: /* l.bf */
743 LOG_DIS("l.bf %d\n", N26);
744 gen_jump(dc, N26, 0, op0);
745 break;
746
747 case 0x05:
748 switch (op1) {
749 case 0x01: /* l.nop */
750 LOG_DIS("l.nop %d\n", I16);
751 break;
752
753 default:
754 gen_illegal_exception(dc);
755 break;
756 }
757 break;
758
759 case 0x11: /* l.jr */
760 LOG_DIS("l.jr r%d\n", rb);
761 gen_jump(dc, 0, rb, op0);
762 break;
763
764 case 0x12: /* l.jalr */
765 LOG_DIS("l.jalr r%d\n", rb);
766 gen_jump(dc, 0, rb, op0);
767 break;
768
769 case 0x13: /* l.maci */
770 LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I11);
771 {
772 TCGv_i64 t1 = tcg_temp_new_i64();
773 TCGv_i64 t2 = tcg_temp_new_i64();
774 TCGv_i32 dst = tcg_temp_new_i32();
775 TCGv ttmp = tcg_const_tl(tmp);
776 tcg_gen_mul_tl(dst, cpu_R[ra], ttmp);
777 tcg_gen_ext_i32_i64(t1, dst);
778 tcg_gen_concat_i32_i64(t2, maclo, machi);
779 tcg_gen_add_i64(t2, t2, t1);
780 tcg_gen_trunc_i64_i32(maclo, t2);
781 tcg_gen_shri_i64(t2, t2, 32);
782 tcg_gen_trunc_i64_i32(machi, t2);
783 tcg_temp_free_i32(dst);
784 tcg_temp_free(ttmp);
785 tcg_temp_free_i64(t1);
786 tcg_temp_free_i64(t2);
787 }
788 break;
789
790 case 0x09: /* l.rfe */
791 LOG_DIS("l.rfe\n");
792 {
793 #if defined(CONFIG_USER_ONLY)
794 return;
795 #else
796 if (dc->mem_idx == MMU_USER_IDX) {
797 gen_illegal_exception(dc);
798 return;
799 }
800 gen_helper_rfe(cpu_env);
801 dc->is_jmp = DISAS_UPDATE;
802 #endif
803 }
804 break;
805
806 case 0x1c: /* l.cust1 */
807 LOG_DIS("l.cust1\n");
808 break;
809
810 case 0x1d: /* l.cust2 */
811 LOG_DIS("l.cust2\n");
812 break;
813
814 case 0x1e: /* l.cust3 */
815 LOG_DIS("l.cust3\n");
816 break;
817
818 case 0x1f: /* l.cust4 */
819 LOG_DIS("l.cust4\n");
820 break;
821
822 case 0x3c: /* l.cust5 */
823 LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5);
824 break;
825
826 case 0x3d: /* l.cust6 */
827 LOG_DIS("l.cust6\n");
828 break;
829
830 case 0x3e: /* l.cust7 */
831 LOG_DIS("l.cust7\n");
832 break;
833
834 case 0x3f: /* l.cust8 */
835 LOG_DIS("l.cust8\n");
836 break;
837
838 /* not used yet, open it when we need or64. */
839 /*#ifdef TARGET_OPENRISC64
840 case 0x20: l.ld
841 LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
842 check_ob64s(dc);
843 mop = MO_TEQ;
844 goto do_load;
845 #endif*/
846
847 case 0x21: /* l.lwz */
848 LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
849 mop = MO_TEUL;
850 goto do_load;
851
852 case 0x22: /* l.lws */
853 LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
854 mop = MO_TESL;
855 goto do_load;
856
857 case 0x23: /* l.lbz */
858 LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
859 mop = MO_UB;
860 goto do_load;
861
862 case 0x24: /* l.lbs */
863 LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
864 mop = MO_SB;
865 goto do_load;
866
867 case 0x25: /* l.lhz */
868 LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
869 mop = MO_TEUW;
870 goto do_load;
871
872 case 0x26: /* l.lhs */
873 LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
874 mop = MO_TESW;
875 goto do_load;
876
877 do_load:
878 {
879 TCGv t0 = tcg_temp_new();
880 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
881 tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop);
882 tcg_temp_free(t0);
883 }
884 break;
885
886 case 0x27: /* l.addi */
887 LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
888 {
889 if (I16 == 0) {
890 tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
891 } else {
892 int lab = gen_new_label();
893 TCGv_i64 ta = tcg_temp_new_i64();
894 TCGv_i64 td = tcg_temp_local_new_i64();
895 TCGv_i32 res = tcg_temp_local_new_i32();
896 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
897 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
898 tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
899 tcg_gen_trunc_i64_i32(res, td);
900 tcg_gen_shri_i64(td, td, 32);
901 tcg_gen_andi_i64(td, td, 0x3);
902 /* Jump to lab when no overflow. */
903 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
904 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
905 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
906 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
907 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
908 gen_exception(dc, EXCP_RANGE);
909 gen_set_label(lab);
910 tcg_gen_mov_i32(cpu_R[rd], res);
911 tcg_temp_free_i64(ta);
912 tcg_temp_free_i64(td);
913 tcg_temp_free_i32(res);
914 tcg_temp_free_i32(sr_ove);
915 }
916 }
917 break;
918
919 case 0x28: /* l.addic */
920 LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16);
921 {
922 int lab = gen_new_label();
923 TCGv_i64 ta = tcg_temp_new_i64();
924 TCGv_i64 td = tcg_temp_local_new_i64();
925 TCGv_i64 tcy = tcg_temp_local_new_i64();
926 TCGv_i32 res = tcg_temp_local_new_i32();
927 TCGv_i32 sr_cy = tcg_temp_local_new_i32();
928 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
929 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
930 tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
931 tcg_gen_shri_i32(sr_cy, sr_cy, 10);
932 tcg_gen_extu_i32_i64(tcy, sr_cy);
933 tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
934 tcg_gen_add_i64(td, td, tcy);
935 tcg_gen_trunc_i64_i32(res, td);
936 tcg_gen_shri_i64(td, td, 32);
937 tcg_gen_andi_i64(td, td, 0x3);
938 /* Jump to lab when no overflow. */
939 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
940 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
941 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
942 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
943 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
944 gen_exception(dc, EXCP_RANGE);
945 gen_set_label(lab);
946 tcg_gen_mov_i32(cpu_R[rd], res);
947 tcg_temp_free_i64(ta);
948 tcg_temp_free_i64(td);
949 tcg_temp_free_i64(tcy);
950 tcg_temp_free_i32(res);
951 tcg_temp_free_i32(sr_cy);
952 tcg_temp_free_i32(sr_ove);
953 }
954 break;
955
956 case 0x29: /* l.andi */
957 LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16);
958 tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
959 break;
960
961 case 0x2a: /* l.ori */
962 LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16);
963 tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
964 break;
965
966 case 0x2b: /* l.xori */
967 LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16);
968 tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16));
969 break;
970
971 case 0x2c: /* l.muli */
972 LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16);
973 if (ra != 0 && I16 != 0) {
974 TCGv_i32 im = tcg_const_i32(I16);
975 gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], im);
976 tcg_temp_free_i32(im);
977 } else {
978 tcg_gen_movi_tl(cpu_R[rd], 0x0);
979 }
980 break;
981
982 case 0x2d: /* l.mfspr */
983 LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16);
984 {
985 #if defined(CONFIG_USER_ONLY)
986 return;
987 #else
988 TCGv_i32 ti = tcg_const_i32(I16);
989 if (dc->mem_idx == MMU_USER_IDX) {
990 gen_illegal_exception(dc);
991 return;
992 }
993 gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti);
994 tcg_temp_free_i32(ti);
995 #endif
996 }
997 break;
998
999 case 0x30: /* l.mtspr */
1000 LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1001 {
1002 #if defined(CONFIG_USER_ONLY)
1003 return;
1004 #else
1005 TCGv_i32 im = tcg_const_i32(tmp);
1006 if (dc->mem_idx == MMU_USER_IDX) {
1007 gen_illegal_exception(dc);
1008 return;
1009 }
1010 gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im);
1011 tcg_temp_free_i32(im);
1012 #endif
1013 }
1014 break;
1015
1016 /* not used yet, open it when we need or64. */
1017 /*#ifdef TARGET_OPENRISC64
1018 case 0x34: l.sd
1019 LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1020 check_ob64s(dc);
1021 mop = MO_TEQ;
1022 goto do_store;
1023 #endif*/
1024
1025 case 0x35: /* l.sw */
1026 LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1027 mop = MO_TEUL;
1028 goto do_store;
1029
1030 case 0x36: /* l.sb */
1031 LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1032 mop = MO_UB;
1033 goto do_store;
1034
1035 case 0x37: /* l.sh */
1036 LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1037 mop = MO_TEUW;
1038 goto do_store;
1039
1040 do_store:
1041 {
1042 TCGv t0 = tcg_temp_new();
1043 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
1044 tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop);
1045 tcg_temp_free(t0);
1046 }
1047 break;
1048
1049 default:
1050 gen_illegal_exception(dc);
1051 break;
1052 }
1053 }
1054
1055 static void dec_mac(DisasContext *dc, uint32_t insn)
1056 {
1057 uint32_t op0;
1058 uint32_t ra, rb;
1059 op0 = extract32(insn, 0, 4);
1060 ra = extract32(insn, 16, 5);
1061 rb = extract32(insn, 11, 5);
1062
1063 switch (op0) {
1064 case 0x0001: /* l.mac */
1065 LOG_DIS("l.mac r%d, r%d\n", ra, rb);
1066 {
1067 TCGv_i32 t0 = tcg_temp_new_i32();
1068 TCGv_i64 t1 = tcg_temp_new_i64();
1069 TCGv_i64 t2 = tcg_temp_new_i64();
1070 tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
1071 tcg_gen_ext_i32_i64(t1, t0);
1072 tcg_gen_concat_i32_i64(t2, maclo, machi);
1073 tcg_gen_add_i64(t2, t2, t1);
1074 tcg_gen_trunc_i64_i32(maclo, t2);
1075 tcg_gen_shri_i64(t2, t2, 32);
1076 tcg_gen_trunc_i64_i32(machi, t2);
1077 tcg_temp_free_i32(t0);
1078 tcg_temp_free_i64(t1);
1079 tcg_temp_free_i64(t2);
1080 }
1081 break;
1082
1083 case 0x0002: /* l.msb */
1084 LOG_DIS("l.msb r%d, r%d\n", ra, rb);
1085 {
1086 TCGv_i32 t0 = tcg_temp_new_i32();
1087 TCGv_i64 t1 = tcg_temp_new_i64();
1088 TCGv_i64 t2 = tcg_temp_new_i64();
1089 tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
1090 tcg_gen_ext_i32_i64(t1, t0);
1091 tcg_gen_concat_i32_i64(t2, maclo, machi);
1092 tcg_gen_sub_i64(t2, t2, t1);
1093 tcg_gen_trunc_i64_i32(maclo, t2);
1094 tcg_gen_shri_i64(t2, t2, 32);
1095 tcg_gen_trunc_i64_i32(machi, t2);
1096 tcg_temp_free_i32(t0);
1097 tcg_temp_free_i64(t1);
1098 tcg_temp_free_i64(t2);
1099 }
1100 break;
1101
1102 default:
1103 gen_illegal_exception(dc);
1104 break;
1105 }
1106 }
1107
1108 static void dec_logic(DisasContext *dc, uint32_t insn)
1109 {
1110 uint32_t op0;
1111 uint32_t rd, ra, L6;
1112 op0 = extract32(insn, 6, 2);
1113 rd = extract32(insn, 21, 5);
1114 ra = extract32(insn, 16, 5);
1115 L6 = extract32(insn, 0, 6);
1116
1117 switch (op0) {
1118 case 0x00: /* l.slli */
1119 LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6);
1120 tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1121 break;
1122
1123 case 0x01: /* l.srli */
1124 LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6);
1125 tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1126 break;
1127
1128 case 0x02: /* l.srai */
1129 LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6);
1130 tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); break;
1131
1132 case 0x03: /* l.rori */
1133 LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6);
1134 tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1135 break;
1136
1137 default:
1138 gen_illegal_exception(dc);
1139 break;
1140 }
1141 }
1142
1143 static void dec_M(DisasContext *dc, uint32_t insn)
1144 {
1145 uint32_t op0;
1146 uint32_t rd;
1147 uint32_t K16;
1148 op0 = extract32(insn, 16, 1);
1149 rd = extract32(insn, 21, 5);
1150 K16 = extract32(insn, 0, 16);
1151
1152 switch (op0) {
1153 case 0x0: /* l.movhi */
1154 LOG_DIS("l.movhi r%d, %d\n", rd, K16);
1155 tcg_gen_movi_tl(cpu_R[rd], (K16 << 16));
1156 break;
1157
1158 case 0x1: /* l.macrc */
1159 LOG_DIS("l.macrc r%d\n", rd);
1160 tcg_gen_mov_tl(cpu_R[rd], maclo);
1161 tcg_gen_movi_tl(maclo, 0x0);
1162 tcg_gen_movi_tl(machi, 0x0);
1163 break;
1164
1165 default:
1166 gen_illegal_exception(dc);
1167 break;
1168 }
1169 }
1170
1171 static void dec_comp(DisasContext *dc, uint32_t insn)
1172 {
1173 uint32_t op0;
1174 uint32_t ra, rb;
1175
1176 op0 = extract32(insn, 21, 5);
1177 ra = extract32(insn, 16, 5);
1178 rb = extract32(insn, 11, 5);
1179
1180 tcg_gen_movi_i32(env_btaken, 0x0);
1181 /* unsigned integers */
1182 tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]);
1183 tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]);
1184
1185 switch (op0) {
1186 case 0x0: /* l.sfeq */
1187 LOG_DIS("l.sfeq r%d, r%d\n", ra, rb);
1188 tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]);
1189 break;
1190
1191 case 0x1: /* l.sfne */
1192 LOG_DIS("l.sfne r%d, r%d\n", ra, rb);
1193 tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]);
1194 break;
1195
1196 case 0x2: /* l.sfgtu */
1197 LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb);
1198 tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]);
1199 break;
1200
1201 case 0x3: /* l.sfgeu */
1202 LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb);
1203 tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]);
1204 break;
1205
1206 case 0x4: /* l.sfltu */
1207 LOG_DIS("l.sfltu r%d, r%d\n", ra, rb);
1208 tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]);
1209 break;
1210
1211 case 0x5: /* l.sfleu */
1212 LOG_DIS("l.sfleu r%d, r%d\n", ra, rb);
1213 tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]);
1214 break;
1215
1216 case 0xa: /* l.sfgts */
1217 LOG_DIS("l.sfgts r%d, r%d\n", ra, rb);
1218 tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]);
1219 break;
1220
1221 case 0xb: /* l.sfges */
1222 LOG_DIS("l.sfges r%d, r%d\n", ra, rb);
1223 tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]);
1224 break;
1225
1226 case 0xc: /* l.sflts */
1227 LOG_DIS("l.sflts r%d, r%d\n", ra, rb);
1228 tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]);
1229 break;
1230
1231 case 0xd: /* l.sfles */
1232 LOG_DIS("l.sfles r%d, r%d\n", ra, rb);
1233 tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]);
1234 break;
1235
1236 default:
1237 gen_illegal_exception(dc);
1238 break;
1239 }
1240 wb_SR_F();
1241 }
1242
1243 static void dec_compi(DisasContext *dc, uint32_t insn)
1244 {
1245 uint32_t op0;
1246 uint32_t ra, I16;
1247
1248 op0 = extract32(insn, 21, 5);
1249 ra = extract32(insn, 16, 5);
1250 I16 = extract32(insn, 0, 16);
1251
1252 tcg_gen_movi_i32(env_btaken, 0x0);
1253 I16 = sign_extend(I16, 16);
1254
1255 switch (op0) {
1256 case 0x0: /* l.sfeqi */
1257 LOG_DIS("l.sfeqi r%d, %d\n", ra, I16);
1258 tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16);
1259 break;
1260
1261 case 0x1: /* l.sfnei */
1262 LOG_DIS("l.sfnei r%d, %d\n", ra, I16);
1263 tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16);
1264 break;
1265
1266 case 0x2: /* l.sfgtui */
1267 LOG_DIS("l.sfgtui r%d, %d\n", ra, I16);
1268 tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16);
1269 break;
1270
1271 case 0x3: /* l.sfgeui */
1272 LOG_DIS("l.sfgeui r%d, %d\n", ra, I16);
1273 tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16);
1274 break;
1275
1276 case 0x4: /* l.sfltui */
1277 LOG_DIS("l.sfltui r%d, %d\n", ra, I16);
1278 tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16);
1279 break;
1280
1281 case 0x5: /* l.sfleui */
1282 LOG_DIS("l.sfleui r%d, %d\n", ra, I16);
1283 tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16);
1284 break;
1285
1286 case 0xa: /* l.sfgtsi */
1287 LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16);
1288 tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16);
1289 break;
1290
1291 case 0xb: /* l.sfgesi */
1292 LOG_DIS("l.sfgesi r%d, %d\n", ra, I16);
1293 tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16);
1294 break;
1295
1296 case 0xc: /* l.sfltsi */
1297 LOG_DIS("l.sfltsi r%d, %d\n", ra, I16);
1298 tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16);
1299 break;
1300
1301 case 0xd: /* l.sflesi */
1302 LOG_DIS("l.sflesi r%d, %d\n", ra, I16);
1303 tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16);
1304 break;
1305
1306 default:
1307 gen_illegal_exception(dc);
1308 break;
1309 }
1310 wb_SR_F();
1311 }
1312
1313 static void dec_sys(DisasContext *dc, uint32_t insn)
1314 {
1315 uint32_t op0;
1316 #ifdef OPENRISC_DISAS
1317 uint32_t K16;
1318 #endif
1319 op0 = extract32(insn, 16, 8);
1320 #ifdef OPENRISC_DISAS
1321 K16 = extract32(insn, 0, 16);
1322 #endif
1323
1324 switch (op0) {
1325 case 0x000: /* l.sys */
1326 LOG_DIS("l.sys %d\n", K16);
1327 tcg_gen_movi_tl(cpu_pc, dc->pc);
1328 gen_exception(dc, EXCP_SYSCALL);
1329 dc->is_jmp = DISAS_UPDATE;
1330 break;
1331
1332 case 0x100: /* l.trap */
1333 LOG_DIS("l.trap %d\n", K16);
1334 #if defined(CONFIG_USER_ONLY)
1335 return;
1336 #else
1337 if (dc->mem_idx == MMU_USER_IDX) {
1338 gen_illegal_exception(dc);
1339 return;
1340 }
1341 tcg_gen_movi_tl(cpu_pc, dc->pc);
1342 gen_exception(dc, EXCP_TRAP);
1343 #endif
1344 break;
1345
1346 case 0x300: /* l.csync */
1347 LOG_DIS("l.csync\n");
1348 #if defined(CONFIG_USER_ONLY)
1349 return;
1350 #else
1351 if (dc->mem_idx == MMU_USER_IDX) {
1352 gen_illegal_exception(dc);
1353 return;
1354 }
1355 #endif
1356 break;
1357
1358 case 0x200: /* l.msync */
1359 LOG_DIS("l.msync\n");
1360 #if defined(CONFIG_USER_ONLY)
1361 return;
1362 #else
1363 if (dc->mem_idx == MMU_USER_IDX) {
1364 gen_illegal_exception(dc);
1365 return;
1366 }
1367 #endif
1368 break;
1369
1370 case 0x270: /* l.psync */
1371 LOG_DIS("l.psync\n");
1372 #if defined(CONFIG_USER_ONLY)
1373 return;
1374 #else
1375 if (dc->mem_idx == MMU_USER_IDX) {
1376 gen_illegal_exception(dc);
1377 return;
1378 }
1379 #endif
1380 break;
1381
1382 default:
1383 gen_illegal_exception(dc);
1384 break;
1385 }
1386 }
1387
1388 static void dec_float(DisasContext *dc, uint32_t insn)
1389 {
1390 uint32_t op0;
1391 uint32_t ra, rb, rd;
1392 op0 = extract32(insn, 0, 8);
1393 ra = extract32(insn, 16, 5);
1394 rb = extract32(insn, 11, 5);
1395 rd = extract32(insn, 21, 5);
1396
1397 switch (op0) {
1398 case 0x00: /* lf.add.s */
1399 LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb);
1400 gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1401 break;
1402
1403 case 0x01: /* lf.sub.s */
1404 LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb);
1405 gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1406 break;
1407
1408
1409 case 0x02: /* lf.mul.s */
1410 LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb);
1411 if (ra != 0 && rb != 0) {
1412 gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1413 } else {
1414 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1415 tcg_gen_movi_i32(cpu_R[rd], 0x0);
1416 }
1417 break;
1418
1419 case 0x03: /* lf.div.s */
1420 LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb);
1421 gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1422 break;
1423
1424 case 0x04: /* lf.itof.s */
1425 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1426 gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]);
1427 break;
1428
1429 case 0x05: /* lf.ftoi.s */
1430 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1431 gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]);
1432 break;
1433
1434 case 0x06: /* lf.rem.s */
1435 LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb);
1436 gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1437 break;
1438
1439 case 0x07: /* lf.madd.s */
1440 LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb);
1441 gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1442 break;
1443
1444 case 0x08: /* lf.sfeq.s */
1445 LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb);
1446 gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1447 break;
1448
1449 case 0x09: /* lf.sfne.s */
1450 LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb);
1451 gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1452 break;
1453
1454 case 0x0a: /* lf.sfgt.s */
1455 LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb);
1456 gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1457 break;
1458
1459 case 0x0b: /* lf.sfge.s */
1460 LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb);
1461 gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1462 break;
1463
1464 case 0x0c: /* lf.sflt.s */
1465 LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb);
1466 gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1467 break;
1468
1469 case 0x0d: /* lf.sfle.s */
1470 LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb);
1471 gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1472 break;
1473
1474 /* not used yet, open it when we need or64. */
1475 /*#ifdef TARGET_OPENRISC64
1476 case 0x10: lf.add.d
1477 LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
1478 check_of64s(dc);
1479 gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1480 break;
1481
1482 case 0x11: lf.sub.d
1483 LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb);
1484 check_of64s(dc);
1485 gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1486 break;
1487
1488 case 0x12: lf.mul.d
1489 LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb);
1490 check_of64s(dc);
1491 if (ra != 0 && rb != 0) {
1492 gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1493 } else {
1494 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1495 tcg_gen_movi_i64(cpu_R[rd], 0x0);
1496 }
1497 break;
1498
1499 case 0x13: lf.div.d
1500 LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb);
1501 check_of64s(dc);
1502 gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1503 break;
1504
1505 case 0x14: lf.itof.d
1506 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1507 check_of64s(dc);
1508 gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]);
1509 break;
1510
1511 case 0x15: lf.ftoi.d
1512 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1513 check_of64s(dc);
1514 gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]);
1515 break;
1516
1517 case 0x16: lf.rem.d
1518 LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb);
1519 check_of64s(dc);
1520 gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1521 break;
1522
1523 case 0x17: lf.madd.d
1524 LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
1525 check_of64s(dc);
1526 gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1527 break;
1528
1529 case 0x18: lf.sfeq.d
1530 LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
1531 check_of64s(dc);
1532 gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1533 break;
1534
1535 case 0x1a: lf.sfgt.d
1536 LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
1537 check_of64s(dc);
1538 gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1539 break;
1540
1541 case 0x1b: lf.sfge.d
1542 LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
1543 check_of64s(dc);
1544 gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1545 break;
1546
1547 case 0x19: lf.sfne.d
1548 LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
1549 check_of64s(dc);
1550 gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1551 break;
1552
1553 case 0x1c: lf.sflt.d
1554 LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
1555 check_of64s(dc);
1556 gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1557 break;
1558
1559 case 0x1d: lf.sfle.d
1560 LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
1561 check_of64s(dc);
1562 gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1563 break;
1564 #endif*/
1565
1566 default:
1567 gen_illegal_exception(dc);
1568 break;
1569 }
1570 wb_SR_F();
1571 }
1572
1573 static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
1574 {
1575 uint32_t op0;
1576 uint32_t insn;
1577 insn = cpu_ldl_code(&cpu->env, dc->pc);
1578 op0 = extract32(insn, 26, 6);
1579
1580 switch (op0) {
1581 case 0x06:
1582 dec_M(dc, insn);
1583 break;
1584
1585 case 0x08:
1586 dec_sys(dc, insn);
1587 break;
1588
1589 case 0x2e:
1590 dec_logic(dc, insn);
1591 break;
1592
1593 case 0x2f:
1594 dec_compi(dc, insn);
1595 break;
1596
1597 case 0x31:
1598 dec_mac(dc, insn);
1599 break;
1600
1601 case 0x32:
1602 dec_float(dc, insn);
1603 break;
1604
1605 case 0x38:
1606 dec_calc(dc, insn);
1607 break;
1608
1609 case 0x39:
1610 dec_comp(dc, insn);
1611 break;
1612
1613 default:
1614 dec_misc(dc, insn);
1615 break;
1616 }
1617 }
1618
1619 static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc)
1620 {
1621 CPUState *cs = CPU(cpu);
1622 CPUBreakpoint *bp;
1623
1624 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
1625 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
1626 if (bp->pc == dc->pc) {
1627 tcg_gen_movi_tl(cpu_pc, dc->pc);
1628 gen_exception(dc, EXCP_DEBUG);
1629 dc->is_jmp = DISAS_UPDATE;
1630 }
1631 }
1632 }
1633 }
1634
1635 static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
1636 TranslationBlock *tb,
1637 int search_pc)
1638 {
1639 CPUState *cs = CPU(cpu);
1640 struct DisasContext ctx, *dc = &ctx;
1641 uint16_t *gen_opc_end;
1642 uint32_t pc_start;
1643 int j, k;
1644 uint32_t next_page_start;
1645 int num_insns;
1646 int max_insns;
1647
1648 pc_start = tb->pc;
1649 dc->tb = tb;
1650
1651 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1652 dc->is_jmp = DISAS_NEXT;
1653 dc->ppc = pc_start;
1654 dc->pc = pc_start;
1655 dc->flags = cpu->env.cpucfgr;
1656 dc->mem_idx = cpu_mmu_index(&cpu->env);
1657 dc->synced_flags = dc->tb_flags = tb->flags;
1658 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1659 dc->singlestep_enabled = cs->singlestep_enabled;
1660 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1661 qemu_log("-----------------------------------------\n");
1662 log_cpu_state(CPU(cpu), 0);
1663 }
1664
1665 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1666 k = -1;
1667 num_insns = 0;
1668 max_insns = tb->cflags & CF_COUNT_MASK;
1669
1670 if (max_insns == 0) {
1671 max_insns = CF_COUNT_MASK;
1672 }
1673
1674 gen_tb_start();
1675
1676 do {
1677 check_breakpoint(cpu, dc);
1678 if (search_pc) {
1679 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1680 if (k < j) {
1681 k++;
1682 while (k < j) {
1683 tcg_ctx.gen_opc_instr_start[k++] = 0;
1684 }
1685 }
1686 tcg_ctx.gen_opc_pc[k] = dc->pc;
1687 tcg_ctx.gen_opc_instr_start[k] = 1;
1688 tcg_ctx.gen_opc_icount[k] = num_insns;
1689 }
1690
1691 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1692 tcg_gen_debug_insn_start(dc->pc);
1693 }
1694
1695 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1696 gen_io_start();
1697 }
1698 dc->ppc = dc->pc - 4;
1699 dc->npc = dc->pc + 4;
1700 tcg_gen_movi_tl(cpu_ppc, dc->ppc);
1701 tcg_gen_movi_tl(cpu_npc, dc->npc);
1702 disas_openrisc_insn(dc, cpu);
1703 dc->pc = dc->npc;
1704 num_insns++;
1705 /* delay slot */
1706 if (dc->delayed_branch) {
1707 dc->delayed_branch--;
1708 if (!dc->delayed_branch) {
1709 dc->tb_flags &= ~D_FLAG;
1710 gen_sync_flags(dc);
1711 tcg_gen_mov_tl(cpu_pc, jmp_pc);
1712 tcg_gen_mov_tl(cpu_npc, jmp_pc);
1713 tcg_gen_movi_tl(jmp_pc, 0);
1714 tcg_gen_exit_tb(0);
1715 dc->is_jmp = DISAS_JUMP;
1716 break;
1717 }
1718 }
1719 } while (!dc->is_jmp
1720 && tcg_ctx.gen_opc_ptr < gen_opc_end
1721 && !cs->singlestep_enabled
1722 && !singlestep
1723 && (dc->pc < next_page_start)
1724 && num_insns < max_insns);
1725
1726 if (tb->cflags & CF_LAST_IO) {
1727 gen_io_end();
1728 }
1729 if (dc->is_jmp == DISAS_NEXT) {
1730 dc->is_jmp = DISAS_UPDATE;
1731 tcg_gen_movi_tl(cpu_pc, dc->pc);
1732 }
1733 if (unlikely(cs->singlestep_enabled)) {
1734 if (dc->is_jmp == DISAS_NEXT) {
1735 tcg_gen_movi_tl(cpu_pc, dc->pc);
1736 }
1737 gen_exception(dc, EXCP_DEBUG);
1738 } else {
1739 switch (dc->is_jmp) {
1740 case DISAS_NEXT:
1741 gen_goto_tb(dc, 0, dc->pc);
1742 break;
1743 default:
1744 case DISAS_JUMP:
1745 break;
1746 case DISAS_UPDATE:
1747 /* indicate that the hash table must be used
1748 to find the next TB */
1749 tcg_gen_exit_tb(0);
1750 break;
1751 case DISAS_TB_JUMP:
1752 /* nothing more to generate */
1753 break;
1754 }
1755 }
1756
1757 gen_tb_end(tb, num_insns);
1758 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1759 if (search_pc) {
1760 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1761 k++;
1762 while (k <= j) {
1763 tcg_ctx.gen_opc_instr_start[k++] = 0;
1764 }
1765 } else {
1766 tb->size = dc->pc - pc_start;
1767 tb->icount = num_insns;
1768 }
1769
1770 #ifdef DEBUG_DISAS
1771 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1772 qemu_log("\n");
1773 log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0);
1774 qemu_log("\nisize=%d osize=%td\n",
1775 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1776 tcg_ctx.gen_opc_buf);
1777 }
1778 #endif
1779 }
1780
1781 void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
1782 {
1783 gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 0);
1784 }
1785
1786 void gen_intermediate_code_pc(CPUOpenRISCState *env,
1787 struct TranslationBlock *tb)
1788 {
1789 gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 1);
1790 }
1791
1792 void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
1793 fprintf_function cpu_fprintf,
1794 int flags)
1795 {
1796 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
1797 CPUOpenRISCState *env = &cpu->env;
1798 int i;
1799
1800 cpu_fprintf(f, "PC=%08x\n", env->pc);
1801 for (i = 0; i < 32; ++i) {
1802 cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i],
1803 (i % 4) == 3 ? '\n' : ' ');
1804 }
1805 }
1806
1807 void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb,
1808 int pc_pos)
1809 {
1810 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1811 }
QEMU mirror