target-ppc/cpu.h

   1 /*
   2  *  PPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if !defined (__CPU_PPC_H__)
  21 #define __CPU_PPC_H__
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #include "cpu-defs.h"
  26
  27 //#define USE_OPEN_FIRMWARE
  28
  29 /***                          Sign extend constants                        ***/
  30 /* 8 to 32 bits */
  31 static inline int32_t s_ext8 (uint8_t value)
  32 {
  33     int8_t *tmp = &value;
  34
  35     return *tmp;
  36 }
  37
  38 /* 16 to 32 bits */
  39 static inline int32_t s_ext16 (uint16_t value)
  40 {
  41     int16_t *tmp = &value;
  42
  43     return *tmp;
  44 }
  45
  46 /* 24 to 32 bits */
  47 static inline int32_t s_ext24 (uint32_t value)
  48 {
  49     uint16_t utmp = (value >> 8) & 0xFFFF;
  50     int16_t *tmp = &utmp;
  51
  52     return (*tmp << 8) | (value & 0xFF);
  53 }
  54
  55 #include "config.h"
  56 #include <setjmp.h>
  57
  58 /* Instruction types */
  59 enum {
  60     PPC_NONE     = 0x0000,
  61     PPC_INTEGER  = 0x0001, /* CPU has integer operations instructions        */
  62     PPC_FLOAT    = 0x0002, /* CPU has floating point operations instructions */
  63     PPC_FLOW     = 0x0004, /* CPU has flow control instructions              */
  64     PPC_MEM      = 0x0008, /* CPU has virtual memory instructions            */
  65     PPC_RES      = 0x0010, /* CPU has ld/st with reservation instructions    */
  66     PPC_CACHE    = 0x0020, /* CPU has cache control instructions             */
  67     PPC_MISC     = 0x0040, /* CPU has spr/msr access instructions            */
  68     PPC_EXTERN   = 0x0080, /* CPU has external control instructions          */
  69     PPC_SEGMENT  = 0x0100, /* CPU has memory segment instructions            */
  70     PPC_CACHE_OPT= 0x0200,
  71     PPC_FLOAT_OPT= 0x0400,
  72     PPC_MEM_OPT  = 0x0800,
  73 };
  74
  75 #define PPC_COMMON  (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |           \
  76                      PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
  77 /* PPC 740/745/750/755 (aka G3) has external access instructions */
  78 #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
  79                  PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
  80
  81 /* Supervisor mode registers */
  82 /* Machine state register */
  83 #define MSR_POW 18
  84 #define MSR_ILE 16
  85 #define MSR_EE  15
  86 #define MSR_PR  14
  87 #define MSR_FP  13
  88 #define MSR_ME  12
  89 #define MSR_FE0 11
  90 #define MSR_SE  10
  91 #define MSR_BE  9
  92 #define MSR_FE1 8
  93 #define MSR_IP 6
  94 #define MSR_IR 5
  95 #define MSR_DR 4
  96 #define MSR_RI 1
  97 #define MSR_LE 0
  98 #define msr_pow env->msr[MSR_POW]
  99 #define msr_ile env->msr[MSR_ILE]
 100 #define msr_ee  env->msr[MSR_EE]
 101 #define msr_pr  env->msr[MSR_PR]
 102 #define msr_fp  env->msr[MSR_FP]
 103 #define msr_me  env->msr[MSR_ME]
 104 #define msr_fe0 env->msr[MSR_FE0]
 105 #define msr_se  env->msr[MSR_SE]
 106 #define msr_be  env->msr[MSR_BE]
 107 #define msr_fe1 env->msr[MSR_FE1]
 108 #define msr_ip  env->msr[MSR_IP]
 109 #define msr_ir  env->msr[MSR_IR]
 110 #define msr_dr  env->msr[MSR_DR]
 111 #define msr_ri  env->msr[MSR_RI]
 112 #define msr_le  env->msr[MSR_LE]
 113
 114 /* Segment registers */
 115 typedef struct CPUPPCState {
 116     /* general purpose registers */
 117     uint32_t gpr[32];
 118     /* floating point registers */
 119     double fpr[32];
 120     /* segment registers */
 121     uint32_t sdr1;
 122     uint32_t sr[16];
 123     /* XER */
 124     uint8_t xer[4];
 125     /* Reservation address */
 126     uint32_t reserve;
 127     /* machine state register */
 128     uint8_t msr[32];
 129     /* condition register */
 130     uint8_t crf[8];
 131     /* floating point status and control register */
 132     uint8_t fpscr[8];
 133     uint32_t nip;
 134     /* special purpose registers */
 135     uint32_t lr;
 136     uint32_t ctr;
 137     /* Time base */
 138     uint32_t tb[2];
 139     /* decrementer */
 140     uint32_t decr;
 141     /* BATs */
 142     uint32_t DBAT[2][8];
 143     uint32_t IBAT[2][8];
 144     /* all others */
 145     uint32_t spr[1024];
 146     /* qemu dedicated */
 147      /* temporary float registers */
 148     double ft0;
 149     double ft1;
 150     double ft2;
 151     int interrupt_request;
 152     jmp_buf jmp_env;
 153     int exception_index;
 154     int error_code;
 155     int access_type; /* when a memory exception occurs, the access
 156                         type is stored here */
 157 #if 0 /* TODO */
 158     uint32_t pending_exceptions; /* For external & decr exception,
 159                                   * that can be delayed */
 160 #else
 161     uint32_t exceptions; /* exception queue */
 162     uint32_t errors[32];
 163 #endif
 164     int user_mode_only; /* user mode only simulation */
 165     struct TranslationBlock *current_tb; /* currently executing TB */
 166     /* soft mmu support */
 167     /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
 168     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
 169     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
 170
 171     /* ice debug support */
 172     uint32_t breakpoints[MAX_BREAKPOINTS];
 173     int nb_breakpoints;
 174     int brkstate;
 175     int singlestep_enabled;
 176
 177     /* user data */
 178     void *opaque;
 179 } CPUPPCState;
 180
 181 CPUPPCState *cpu_ppc_init(void);
 182 int cpu_ppc_exec(CPUPPCState *s);
 183 void cpu_ppc_close(CPUPPCState *s);
 184 /* you can call this signal handler from your SIGBUS and SIGSEGV
 185    signal handlers to inform the virtual CPU of exceptions. non zero
 186    is returned if the signal was handled by the virtual CPU.  */
 187 struct siginfo;
 188 int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
 189                            void *puc);
 190
 191 void do_interrupt (CPUPPCState *env);
 192 void cpu_loop_exit(void);
 193
 194 void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
 195 void dump_stack (CPUPPCState *env);
 196
 197 uint32_t _load_xer (CPUPPCState *env);
 198 void _store_xer (CPUPPCState *env, uint32_t value);
 199 uint32_t _load_msr (CPUPPCState *env);
 200 void _store_msr (CPUPPCState *env, uint32_t value);
 201
 202 void PPC_init_hw (uint32_t mem_size,
 203                   uint32_t kernel_addr, uint32_t kernel_size,
 204                   uint32_t stack_addr, int boot_device,
 205                   const unsigned char *initrd_file);
 206
 207 #define TARGET_PAGE_BITS 12
 208 #include "cpu-all.h"
 209
 210 #define ugpr(n) (env->gpr[n])
 211 #define fprd(n) (env->fpr[n])
 212 #define fprs(n) ((float)env->fpr[n])
 213 #define fpru(n) ((uint32_t)env->fpr[n])
 214 #define fpri(n) ((int32_t)env->fpr[n])
 215
 216 #define SPR_ENCODE(sprn)                               \
 217 (((sprn) >> 5) | (((sprn) & 0x1F) << 5))
 218
 219 /* User mode SPR */
 220 #define spr(n) env->spr[n]
 221 #define XER_SO 31
 222 #define XER_OV 30
 223 #define XER_CA 29
 224 #define XER_BC 0
 225 #define xer_so env->xer[3]
 226 #define xer_ov env->xer[2]
 227 #define xer_ca env->xer[1]
 228 #define xer_bc env->xer[0]
 229
 230 #define XER    SPR_ENCODE(1)
 231 #define LR     SPR_ENCODE(8)
 232 #define CTR    SPR_ENCODE(9)
 233 /* VEA mode SPR */
 234 #define V_TBL  SPR_ENCODE(268)
 235 #define V_TBU  SPR_ENCODE(269)
 236 /* supervisor mode SPR */
 237 #define DSISR  SPR_ENCODE(18)
 238 #define DAR    SPR_ENCODE(19)
 239 #define DECR   SPR_ENCODE(22)
 240 #define SDR1   SPR_ENCODE(25)
 241 #define SRR0   SPR_ENCODE(26)
 242 #define SRR1   SPR_ENCODE(27)
 243 #define SPRG0  SPR_ENCODE(272)
 244 #define SPRG1  SPR_ENCODE(273)
 245 #define SPRG2  SPR_ENCODE(274)
 246 #define SPRG3  SPR_ENCODE(275)
 247 #define SPRG4  SPR_ENCODE(276)
 248 #define SPRG5  SPR_ENCODE(277)
 249 #define SPRG6  SPR_ENCODE(278)
 250 #define SPRG7  SPR_ENCODE(279)
 251 #define ASR    SPR_ENCODE(280)
 252 #define EAR    SPR_ENCODE(282)
 253 #define O_TBL  SPR_ENCODE(284)
 254 #define O_TBU  SPR_ENCODE(285)
 255 #define PVR    SPR_ENCODE(287)
 256 #define IBAT0U SPR_ENCODE(528)
 257 #define IBAT0L SPR_ENCODE(529)
 258 #define IBAT1U SPR_ENCODE(530)
 259 #define IBAT1L SPR_ENCODE(531)
 260 #define IBAT2U SPR_ENCODE(532)
 261 #define IBAT2L SPR_ENCODE(533)
 262 #define IBAT3U SPR_ENCODE(534)
 263 #define IBAT3L SPR_ENCODE(535)
 264 #define DBAT0U SPR_ENCODE(536)
 265 #define DBAT0L SPR_ENCODE(537)
 266 #define DBAT1U SPR_ENCODE(538)
 267 #define DBAT1L SPR_ENCODE(539)
 268 #define DBAT2U SPR_ENCODE(540)
 269 #define DBAT2L SPR_ENCODE(541)
 270 #define DBAT3U SPR_ENCODE(542)
 271 #define DBAT3L SPR_ENCODE(543)
 272 #define IBAT4U SPR_ENCODE(560)
 273 #define IBAT4L SPR_ENCODE(561)
 274 #define IBAT5U SPR_ENCODE(562)
 275 #define IBAT5L SPR_ENCODE(563)
 276 #define IBAT6U SPR_ENCODE(564)
 277 #define IBAT6L SPR_ENCODE(565)
 278 #define IBAT7U SPR_ENCODE(566)
 279 #define IBAT7L SPR_ENCODE(567)
 280 #define DBAT4U SPR_ENCODE(568)
 281 #define DBAT4L SPR_ENCODE(569)
 282 #define DBAT5U SPR_ENCODE(570)
 283 #define DBAT5L SPR_ENCODE(571)
 284 #define DBAT6U SPR_ENCODE(572)
 285 #define DBAT6L SPR_ENCODE(573)
 286 #define DBAT7U SPR_ENCODE(574)
 287 #define DBAT7L SPR_ENCODE(575)
 288 #define DABR   SPR_ENCODE(1013)
 289 #define DABR_MASK 0xFFFFFFF8
 290 #define FPECR  SPR_ENCODE(1022)
 291 #define PIR    SPR_ENCODE(1023)
 292
 293 #define TARGET_PAGE_BITS 12
 294 #include "cpu-all.h"
 295
 296 /* Memory access type :
 297  * may be needed for precise access rights control and precise exceptions.
 298  */
 299 enum {
 300     /* 1 bit to define user level / supervisor access */
 301     ACCESS_USER  = 0x00,
 302     ACCESS_SUPER = 0x01,
 303     /* Type of instruction that generated the access */
 304     ACCESS_CODE  = 0x10, /* Code fetch access                */
 305     ACCESS_INT   = 0x20, /* Integer load/store access        */
 306     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 307     ACCESS_RES   = 0x40, /* load/store with reservation      */
 308     ACCESS_EXT   = 0x50, /* external access                  */
 309     ACCESS_CACHE = 0x60, /* Cache manipulation               */
 310 };
 311
 312 /*****************************************************************************/
 313 /* Exceptions */
 314 enum {
 315     EXCP_NONE          = -1,
 316     /* PPC hardware exceptions : exception vector / 0x100 */
 317     EXCP_RESET         = 0x01, /* System reset                     */
 318     EXCP_MACHINE_CHECK = 0x02, /* Machine check exception          */
 319     EXCP_DSI           = 0x03, /* Impossible memory access         */
 320     EXCP_ISI           = 0x04, /* Impossible instruction fetch     */
 321     EXCP_EXTERNAL      = 0x05, /* External interruption            */
 322     EXCP_ALIGN         = 0x06, /* Alignment exception              */
 323     EXCP_PROGRAM       = 0x07, /* Program exception                */
 324     EXCP_NO_FP         = 0x08, /* No floating point                */
 325     EXCP_DECR          = 0x09, /* Decrementer exception            */
 326     EXCP_RESA          = 0x0A, /* Implementation specific          */
 327     EXCP_RESB          = 0x0B, /* Implementation specific          */
 328     EXCP_SYSCALL       = 0x0C, /* System call                      */
 329     EXCP_TRACE         = 0x0D, /* Trace exception (optional)       */
 330     EXCP_FP_ASSIST     = 0x0E, /* Floating-point assist (optional) */
 331     /* MPC740/745/750 & IBM 750 */
 332     EXCP_PERF          = 0x0F,  /* Performance monitor              */
 333     EXCP_IABR          = 0x13,  /* Instruction address breakpoint   */
 334     EXCP_SMI           = 0x14,  /* System management interrupt      */
 335     EXCP_THRM          = 0x15,  /* Thermal management interrupt     */
 336     /* MPC755 */
 337     EXCP_TLBMISS       = 0x10,  /* Instruction TLB miss             */
 338     EXCP_TLBMISS_DL    = 0x11,  /* Data TLB miss for load           */
 339     EXCP_TLBMISS_DS    = 0x12,  /* Data TLB miss for store          */
 340     EXCP_PPC_MAX       = 0x16,
 341     /* Qemu exception */
 342     EXCP_OFCALL        = 0x20,  /* Call open-firmware emulator      */
 343     EXCP_RTASCALL      = 0x21,  /* Call RTAS emulator               */
 344     /* Special cases where we want to stop translation */
 345     EXCP_MTMSR         = 0x104, /* mtmsr instruction:               */
 346                                 /* may change privilege level       */
 347     EXCP_BRANCH        = 0x108, /* branch instruction               */
 348     EXCP_RFI           = 0x10C, /* return from interrupt            */
 349     EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
 350 };
 351 /* Error codes */
 352 enum {
 353     /* Exception subtypes for EXCP_DSI                              */
 354     EXCP_DSI_TRANSLATE = 0x01,  /* Data address can't be translated */
 355     EXCP_DSI_NOTSUP    = 0x02,  /* Access type not supported        */
 356     EXCP_DSI_PROT      = 0x03,  /* Memory protection violation      */
 357     EXCP_DSI_EXTERNAL  = 0x04,  /* External access disabled         */
 358     EXCP_DSI_DABR      = 0x05,  /* Data address breakpoint          */
 359     /* flags for EXCP_DSI */
 360     EXCP_DSI_DIRECT    = 0x10,
 361     EXCP_DSI_STORE     = 0x20,
 362     EXCP_DSI_ECXW      = 0x40,
 363     /* Exception subtypes for EXCP_ISI                              */
 364     EXCP_ISI_TRANSLATE = 0x01,  /* Code address can't be translated */
 365     EXCP_ISI_NOEXEC    = 0x02,  /* Try to fetch from a data segment */
 366     EXCP_ISI_GUARD     = 0x03,  /* Fetch from guarded memory        */
 367     EXCP_ISI_PROT      = 0x04,  /* Memory protection violation      */
 368     EXCP_ISI_DIRECT    = 0x05,  /* Trying to fetch from             *
 369                                  * a direct store segment           */
 370     /* Exception subtypes for EXCP_ALIGN                            */
 371     EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
 372     EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
 373     EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
 374     EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
 375     EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
 376     EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
 377     /* Exception subtypes for EXCP_PROGRAM                          */
 378     /* FP exceptions */
 379     EXCP_FP            = 0x10,
 380     EXCP_FP_OX         = 0x01,  /* FP overflow                      */
 381     EXCP_FP_UX         = 0x02,  /* FP underflow                     */
 382     EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
 383     EXCP_FP_XX         = 0x04,  /* FP inexact                       */
 384     EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
 385     EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
 386     EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
 387     EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
 388     EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
 389     EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
 390     EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
 391     EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
 392     EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
 393     /* Invalid instruction */
 394     EXCP_INVAL         = 0x20,
 395     EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
 396     EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
 397     EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
 398     EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
 399     /* Privileged instruction */
 400     EXCP_PRIV          = 0x30,
 401     EXCP_PRIV_OPC      = 0x01,
 402     EXCP_PRIV_REG      = 0x02,
 403     /* Trap */
 404     EXCP_TRAP          = 0x40,
 405 };
 406
 407 /*****************************************************************************/
 408
 409 #endif /* !defined (__CPU_PPC_H__) */