target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if !defined (__CPU_PPC_H__)
  21 #define __CPU_PPC_H__
  22
  23 #include "config.h"
  24 #include <inttypes.h>
  25
  26 #if defined (TARGET_PPC64)
  27 typedef uint64_t ppc_gpr_t;
  28 #define TARGET_GPR_BITS  64
  29 #define TARGET_LONG_BITS 64
  30 #define REGX "%016" PRIx64
  31 #define TARGET_PAGE_BITS 12
  32 #elif defined(TARGET_PPCEMB)
  33 /* BookE have 36 bits physical address space */
  34 #define TARGET_PHYS_ADDR_BITS 64
  35 /* GPR are 64 bits: used by vector extension */
  36 typedef uint64_t ppc_gpr_t;
  37 #define TARGET_GPR_BITS  64
  38 #define TARGET_LONG_BITS 32
  39 #define REGX "%016" PRIx64
  40 #if defined(CONFIG_USER_ONLY)
  41 /* It looks like a lot of Linux programs assume page size
  42  * is 4kB long. This is evil, but we have to deal with it...
  43  */
  44 #define TARGET_PAGE_BITS 12
  45 #else
  46 /* Pages can be 1 kB small */
  47 #define TARGET_PAGE_BITS 10
  48 #endif
  49 #else
  50 #if (HOST_LONG_BITS >= 64)
  51 /* When using 64 bits temporary registers,
  52  * we can use 64 bits GPR with no extra cost
  53  * It's even an optimization as it will prevent
  54  * the compiler to do unuseful masking in the micro-ops.
  55  */
  56 typedef uint64_t ppc_gpr_t;
  57 #define TARGET_GPR_BITS  64
  58 #define REGX "%08" PRIx64
  59 #else
  60 typedef uint32_t ppc_gpr_t;
  61 #define TARGET_GPR_BITS  32
  62 #define REGX "%08" PRIx32
  63 #endif
  64 #define TARGET_LONG_BITS 32
  65 #define TARGET_PAGE_BITS 12
  66 #endif
  67
  68 #include "cpu-defs.h"
  69
  70 #define ADDRX TARGET_FMT_lx
  71 #define PADDRX TARGET_FMT_plx
  72
  73 #include <setjmp.h>
  74
  75 #include "softfloat.h"
  76
  77 #define TARGET_HAS_ICE 1
  78
  79 #if defined (TARGET_PPC64)
  80 #define ELF_MACHINE     EM_PPC64
  81 #else
  82 #define ELF_MACHINE     EM_PPC
  83 #endif
  84
  85 /*****************************************************************************/
  86 /* MMU model                                                                 */
  87 enum {
  88     POWERPC_MMU_UNKNOWN    = 0,
  89     /* Standard 32 bits PowerPC MMU                            */
  90     POWERPC_MMU_32B,
  91     /* PowerPC 601 MMU                                         */
  92     POWERPC_MMU_601,
  93     /* PowerPC 6xx MMU with software TLB                       */
  94     POWERPC_MMU_SOFT_6xx,
  95     /* PowerPC 74xx MMU with software TLB                      */
  96     POWERPC_MMU_SOFT_74xx,
  97     /* PowerPC 4xx MMU with software TLB                       */
  98     POWERPC_MMU_SOFT_4xx,
  99     /* PowerPC 4xx MMU with software TLB and zones protections */
 100     POWERPC_MMU_SOFT_4xx_Z,
 101     /* PowerPC 4xx MMU in real mode only                       */
 102     POWERPC_MMU_REAL_4xx,
 103     /* BookE MMU model                                         */
 104     POWERPC_MMU_BOOKE,
 105     /* BookE FSL MMU model                                     */
 106     POWERPC_MMU_BOOKE_FSL,
 107 #if defined(TARGET_PPC64)
 108     /* 64 bits PowerPC MMU                                     */
 109     POWERPC_MMU_64B,
 110 #endif /* defined(TARGET_PPC64) */
 111 };
 112
 113 /*****************************************************************************/
 114 /* Exception model                                                           */
 115 enum {
 116     POWERPC_EXCP_UNKNOWN   = 0,
 117     /* Standard PowerPC exception model */
 118     POWERPC_EXCP_STD,
 119     /* PowerPC 40x exception model      */
 120     POWERPC_EXCP_40x,
 121     /* PowerPC 601 exception model      */
 122     POWERPC_EXCP_601,
 123     /* PowerPC 602 exception model      */
 124     POWERPC_EXCP_602,
 125     /* PowerPC 603 exception model      */
 126     POWERPC_EXCP_603,
 127     /* PowerPC 603e exception model     */
 128     POWERPC_EXCP_603E,
 129     /* PowerPC G2 exception model       */
 130     POWERPC_EXCP_G2,
 131     /* PowerPC 604 exception model      */
 132     POWERPC_EXCP_604,
 133     /* PowerPC 7x0 exception model      */
 134     POWERPC_EXCP_7x0,
 135     /* PowerPC 7x5 exception model      */
 136     POWERPC_EXCP_7x5,
 137     /* PowerPC 74xx exception model     */
 138     POWERPC_EXCP_74xx,
 139     /* BookE exception model            */
 140     POWERPC_EXCP_BOOKE,
 141 #if defined(TARGET_PPC64)
 142     /* PowerPC 970 exception model      */
 143     POWERPC_EXCP_970,
 144 #endif /* defined(TARGET_PPC64) */
 145 };
 146
 147 /*****************************************************************************/
 148 /* Exception vectors definitions                                             */
 149 enum {
 150     POWERPC_EXCP_NONE    = -1,
 151     /* The 64 first entries are used by the PowerPC embedded specification   */
 152     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
 153     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
 154     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
 155     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
 156     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
 157     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
 158     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 159     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 160     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 161     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 162     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 163     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 164     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 165     POWERPC_EXCP_DTLB     = 13, /* Data TLB error                            */
 166     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB error                     */
 167     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 168     /* Vectors 16 to 31 are reserved                                         */
 169 #if defined(TARGET_PPCEMB)
 170     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 171     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 172     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 173     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 174     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 175     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 176 #endif /* defined(TARGET_PPCEMB) */
 177     /* Vectors 38 to 63 are reserved                                         */
 178     /* Exceptions defined in the PowerPC server specification                */
 179     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 180 #if defined(TARGET_PPC64) /* PowerPC 64 */
 181     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 182     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 183 #endif /* defined(TARGET_PPC64) */
 184 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 185     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 186 #endif /* defined(TARGET_PPC64H) */
 187     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 188 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 189     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 190     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 191     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 192     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 193 #endif /* defined(TARGET_PPC64H) */
 194     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 195     /* 40x specific exceptions                                               */
 196     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 197     /* 601 specific exceptions                                               */
 198     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 199     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 200     /* 602 specific exceptions                                               */
 201     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 202     /* 602/603 specific exceptions                                           */
 203     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB error               */
 204     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 205     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 206     /* Exceptions available on most PowerPC                                  */
 207     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 208     POWERPC_EXCP_IABR     = 82, /* Instruction address breakpoint            */
 209     POWERPC_EXCP_SMI      = 83, /* System management interrupt               */
 210     POWERPC_EXCP_PERFM    = 84, /* Embedded performance monitor interrupt    */
 211     /* 7xx/74xx specific exceptions                                          */
 212     POWERPC_EXCP_THERM    = 85, /* Thermal interrupt                         */
 213     /* 74xx specific exceptions                                              */
 214     POWERPC_EXCP_VPUA     = 86, /* Vector assist exception                   */
 215     /* 970FX specific exceptions                                             */
 216     POWERPC_EXCP_SOFTP    = 87, /* Soft patch exception                      */
 217     POWERPC_EXCP_MAINT    = 88, /* Maintenance exception                     */
 218     /* EOL                                                                   */
 219     POWERPC_EXCP_NB       = 96,
 220     /* Qemu exceptions: used internally during code translation              */
 221     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 222     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 223     /* Qemu exceptions: special cases we want to stop translation            */
 224     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 225     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 226 };
 227
 228
 229 /* Exceptions error codes                                                    */
 230 enum {
 231     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 232     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 233     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 234     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 235     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 236     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 237     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 238     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 239     /* FP exceptions                                                         */
 240     POWERPC_EXCP_FP            = 0x10,
 241     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 242     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 243     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 244     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 245     POWERPC_EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op                */
 246     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 247     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 248     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 249     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 250     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 251     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 252     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 253     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 254     /* Invalid instruction                                                   */
 255     POWERPC_EXCP_INVAL         = 0x20,
 256     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 257     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 258     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 259     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 260     /* Privileged instruction                                                */
 261     POWERPC_EXCP_PRIV          = 0x30,
 262     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 263     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 264     /* Trap                                                                  */
 265     POWERPC_EXCP_TRAP          = 0x40,
 266 };
 267
 268 /*****************************************************************************/
 269 /* Input pins model                                                          */
 270 enum {
 271     PPC_FLAGS_INPUT_UNKNOWN = 0,
 272     /* PowerPC 6xx bus                  */
 273     PPC_FLAGS_INPUT_6xx,
 274     /* BookE bus                        */
 275     PPC_FLAGS_INPUT_BookE,
 276     /* PowerPC 405 bus                  */
 277     PPC_FLAGS_INPUT_405,
 278     /* PowerPC 970 bus                  */
 279     PPC_FLAGS_INPUT_970,
 280     /* PowerPC 401 bus                  */
 281     PPC_FLAGS_INPUT_401,
 282 };
 283
 284 #define PPC_INPUT(env) (env->bus_model)
 285
 286 /*****************************************************************************/
 287 typedef struct ppc_def_t ppc_def_t;
 288 typedef struct opc_handler_t opc_handler_t;
 289
 290 /*****************************************************************************/
 291 /* Types used to describe some PowerPC registers */
 292 typedef struct CPUPPCState CPUPPCState;
 293 typedef struct ppc_tb_t ppc_tb_t;
 294 typedef struct ppc_spr_t ppc_spr_t;
 295 typedef struct ppc_dcr_t ppc_dcr_t;
 296 typedef struct ppc_avr_t ppc_avr_t;
 297 typedef union ppc_tlb_t ppc_tlb_t;
 298
 299 /* SPR access micro-ops generations callbacks */
 300 struct ppc_spr_t {
 301     void (*uea_read)(void *opaque, int spr_num);
 302     void (*uea_write)(void *opaque, int spr_num);
 303 #if !defined(CONFIG_USER_ONLY)
 304     void (*oea_read)(void *opaque, int spr_num);
 305     void (*oea_write)(void *opaque, int spr_num);
 306 #if defined(TARGET_PPC64H)
 307     void (*hea_read)(void *opaque, int spr_num);
 308     void (*hea_write)(void *opaque, int spr_num);
 309 #endif
 310 #endif
 311     const unsigned char *name;
 312 };
 313
 314 /* Altivec registers (128 bits) */
 315 struct ppc_avr_t {
 316     uint32_t u[4];
 317 };
 318
 319 /* Software TLB cache */
 320 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 321 struct ppc6xx_tlb_t {
 322     target_ulong pte0;
 323     target_ulong pte1;
 324     target_ulong EPN;
 325 };
 326
 327 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 328 struct ppcemb_tlb_t {
 329     target_phys_addr_t RPN;
 330     target_ulong EPN;
 331     target_ulong PID;
 332     target_ulong size;
 333     uint32_t prot;
 334     uint32_t attr; /* Storage attributes */
 335 };
 336
 337 union ppc_tlb_t {
 338     ppc6xx_tlb_t tlb6;
 339     ppcemb_tlb_t tlbe;
 340 };
 341
 342 /*****************************************************************************/
 343 /* Machine state register bits definition                                    */
 344 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 345 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 346 #define MSR_HV   60 /* hypervisor state                               hflags */
 347 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 348 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 349 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 350 #define MSR_VR   25 /* altivec available                            x hflags */
 351 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 352 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 353 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 354 #define MSR_KEY  19 /* key bit on 603e                                       */
 355 #define MSR_POW  18 /* Power management                             x        */
 356 #define MSR_WE   18 /* Wait state enable on embedded PowerPC        x        */
 357 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 358 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 359 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 360 #define MSR_EE   15 /* External interrupt enable                             */
 361 #define MSR_PR   14 /* Problem state                                  hflags */
 362 #define MSR_FP   13 /* Floating point available                       hflags */
 363 #define MSR_ME   12 /* Machine check interrupt enable                        */
 364 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 365 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 366 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 367 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 368 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 369 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 370 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 371 #define MSR_AL   7  /* AL bit on POWER                                       */
 372 #define MSR_IP   6  /* Interrupt prefix                                      */
 373 #define MSR_IR   5  /* Instruction relocate                                  */
 374 #define MSR_DR   4  /* Data relocate                                         */
 375 #define MSR_PE   3  /* Protection enable on 403                     x        */
 376 #define MSR_EP   3  /* Exception prefix on 601                      x        */
 377 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 378 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 379 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 380 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 381 #define msr_sf   env->msr[MSR_SF]
 382 #define msr_isf  env->msr[MSR_ISF]
 383 #define msr_hv   env->msr[MSR_HV]
 384 #define msr_cm   env->msr[MSR_CM]
 385 #define msr_icm  env->msr[MSR_ICM]
 386 #define msr_ucle env->msr[MSR_UCLE]
 387 #define msr_vr   env->msr[MSR_VR]
 388 #define msr_spe  env->msr[MSR_SPE]
 389 #define msr_ap   env->msr[MSR_AP]
 390 #define msr_sa   env->msr[MSR_SA]
 391 #define msr_key  env->msr[MSR_KEY]
 392 #define msr_pow  env->msr[MSR_POW]
 393 #define msr_we   env->msr[MSR_WE]
 394 #define msr_tgpr env->msr[MSR_TGPR]
 395 #define msr_ce   env->msr[MSR_CE]
 396 #define msr_ile  env->msr[MSR_ILE]
 397 #define msr_ee   env->msr[MSR_EE]
 398 #define msr_pr   env->msr[MSR_PR]
 399 #define msr_fp   env->msr[MSR_FP]
 400 #define msr_me   env->msr[MSR_ME]
 401 #define msr_fe0  env->msr[MSR_FE0]
 402 #define msr_se   env->msr[MSR_SE]
 403 #define msr_dwe  env->msr[MSR_DWE]
 404 #define msr_uble env->msr[MSR_UBLE]
 405 #define msr_be   env->msr[MSR_BE]
 406 #define msr_de   env->msr[MSR_DE]
 407 #define msr_fe1  env->msr[MSR_FE1]
 408 #define msr_al   env->msr[MSR_AL]
 409 #define msr_ip   env->msr[MSR_IP]
 410 #define msr_ir   env->msr[MSR_IR]
 411 #define msr_dr   env->msr[MSR_DR]
 412 #define msr_pe   env->msr[MSR_PE]
 413 #define msr_ep   env->msr[MSR_EP]
 414 #define msr_px   env->msr[MSR_PX]
 415 #define msr_pmm  env->msr[MSR_PMM]
 416 #define msr_ri   env->msr[MSR_RI]
 417 #define msr_le   env->msr[MSR_LE]
 418
 419 enum {
 420     /* Beware that MSR bits are given using IBM standard (ie MSB is 0 !)     */
 421     POWERPC_FLAG_NONE = 0x00000000,
 422     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 423     POWERPC_FLAG_SPE  = 0x00000001,
 424     POWERPC_FLAG_VRE  = 0x00000002,
 425     /* Flag for MSR bit 18 may not be needed...                              */
 426     POWERPC_FLAG_POW  = 0x00000004,
 427     POWERPC_FLAG_WE   = 0x00000008,
 428     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 429     POWERPC_FLAG_TGPR = 0x00000010,
 430     POWERPC_FLAG_CE   = 0x00000020,
 431     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 432     POWERPC_FLAG_SE   = 0x00000040,
 433     POWERPC_FLAG_DWE  = 0x00000080,
 434     POWERPC_FLAG_UBLE = 0x00000100,
 435     /* Flag for MSR bit 9 signification (BE/DE)                              */
 436     POWERPC_FLAG_BE   = 0x00000200,
 437     POWERPC_FLAG_DE   = 0x00000400,
 438     /* Flag for MSR bit 3 signification (PE/EP)                              */
 439     POWERPC_FLAG_PE   = 0x00000800,
 440     POWERPC_FLAG_EP   = 0x00001000,
 441     /* Flag for MSR but 2 signification (PX/PMM)                             */
 442     POWERPC_FLAG_PX   = 0x00002000,
 443     POWERPC_FLAG_PMM  = 0x00004000,
 444 };
 445
 446 /*****************************************************************************/
 447 /* The whole PowerPC CPU context */
 448 struct CPUPPCState {
 449     /* First are the most commonly used resources
 450      * during translated code execution
 451      */
 452 #if TARGET_GPR_BITS > HOST_LONG_BITS
 453     /* temporary fixed-point registers
 454      * used to emulate 64 bits target on 32 bits hosts
 455      */
 456     ppc_gpr_t t0, t1, t2;
 457 #endif
 458     ppc_avr_t t0_avr, t1_avr, t2_avr;
 459
 460     /* general purpose registers */
 461     ppc_gpr_t gpr[32];
 462     /* LR */
 463     target_ulong lr;
 464     /* CTR */
 465     target_ulong ctr;
 466     /* condition register */
 467     uint8_t crf[8];
 468     /* XER */
 469     /* XXX: We use only 5 fields, but we want to keep the structure aligned */
 470     uint8_t xer[8];
 471     /* Reservation address */
 472     target_ulong reserve;
 473
 474     /* Those ones are used in supervisor mode only */
 475     /* machine state register */
 476     uint8_t msr[64];
 477     /* temporary general purpose registers */
 478     ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
 479
 480     /* Floating point execution context */
 481     /* temporary float registers */
 482     float64 ft0;
 483     float64 ft1;
 484     float64 ft2;
 485     float_status fp_status;
 486     /* floating point registers */
 487     float64 fpr[32];
 488     /* floating point status and control register */
 489     uint8_t fpscr[8];
 490
 491     CPU_COMMON
 492
 493     int halted; /* TRUE if the CPU is in suspend state */
 494
 495     int access_type; /* when a memory exception occurs, the access
 496                         type is stored here */
 497
 498     /* MMU context */
 499     /* Address space register */
 500     target_ulong asr;
 501     /* segment registers */
 502     target_ulong sdr1;
 503     target_ulong sr[16];
 504     /* BATs */
 505     int nb_BATs;
 506     target_ulong DBAT[2][8];
 507     target_ulong IBAT[2][8];
 508
 509     /* Other registers */
 510     /* Special purpose registers */
 511     target_ulong spr[1024];
 512     /* Altivec registers */
 513     ppc_avr_t avr[32];
 514     uint32_t vscr;
 515     /* SPE registers */
 516     ppc_gpr_t spe_acc;
 517     float_status spe_status;
 518     uint32_t spe_fscr;
 519
 520     /* Internal devices resources */
 521     /* Time base and decrementer */
 522     ppc_tb_t *tb_env;
 523     /* Device control registers */
 524     ppc_dcr_t *dcr_env;
 525
 526     /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
 527     int nb_tlb;      /* Total number of TLB                                  */
 528     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
 529     int nb_ways;     /* Number of ways in the TLB set                        */
 530     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
 531     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
 532     int nb_pids;     /* Number of available PID registers                    */
 533     ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
 534     /* 403 dedicated access protection registers */
 535     target_ulong pb[4];
 536     /* PowerPC 64 SLB area */
 537     int slb_nr;
 538
 539     int dcache_line_size;
 540     int icache_line_size;
 541
 542     /* Those resources are used during exception processing */
 543     /* CPU model definition */
 544     target_ulong msr_mask;
 545     uint8_t mmu_model;
 546     uint8_t excp_model;
 547     uint8_t bus_model;
 548     uint8_t pad;
 549     int bfd_mach;
 550     uint32_t flags;
 551
 552     int exception_index;
 553     int error_code;
 554     int interrupt_request;
 555     uint32_t pending_interrupts;
 556 #if !defined(CONFIG_USER_ONLY)
 557     /* This is the IRQ controller, which is implementation dependant
 558      * and only relevant when emulating a complete machine.
 559      */
 560     uint32_t irq_input_state;
 561     void **irq_inputs;
 562     /* Exception vectors */
 563     target_ulong excp_vectors[POWERPC_EXCP_NB];
 564     target_ulong excp_prefix;
 565     target_ulong ivor_mask;
 566     target_ulong ivpr_mask;
 567     target_ulong hreset_vector;
 568 #endif
 569
 570     /* Those resources are used only during code translation */
 571     /* Next instruction pointer */
 572     target_ulong nip;
 573     /* SPR translation callbacks */
 574     ppc_spr_t spr_cb[1024];
 575     /* opcode handlers */
 576     opc_handler_t *opcodes[0x40];
 577
 578     /* Those resources are used only in Qemu core */
 579     jmp_buf jmp_env;
 580     int user_mode_only; /* user mode only simulation */
 581     target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
 582
 583     /* Power management */
 584     int power_mode;
 585
 586     /* temporary hack to handle OSI calls (only used if non NULL) */
 587     int (*osi_call)(struct CPUPPCState *env);
 588 };
 589
 590 /* Context used internally during MMU translations */
 591 typedef struct mmu_ctx_t mmu_ctx_t;
 592 struct mmu_ctx_t {
 593     target_phys_addr_t raddr;      /* Real address              */
 594     int prot;                      /* Protection bits           */
 595     target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
 596     target_ulong ptem;             /* Virtual segment ID | API  */
 597     int key;                       /* Access key                */
 598 };
 599
 600 /*****************************************************************************/
 601 CPUPPCState *cpu_ppc_init (void);
 602 int cpu_ppc_exec (CPUPPCState *s);
 603 void cpu_ppc_close (CPUPPCState *s);
 604 /* you can call this signal handler from your SIGBUS and SIGSEGV
 605    signal handlers to inform the virtual CPU of exceptions. non zero
 606    is returned if the signal was handled by the virtual CPU.  */
 607 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
 608                             void *puc);
 609
 610 void do_interrupt (CPUPPCState *env);
 611 void ppc_hw_interrupt (CPUPPCState *env);
 612 void cpu_loop_exit (void);
 613
 614 void dump_stack (CPUPPCState *env);
 615
 616 #if !defined(CONFIG_USER_ONLY)
 617 target_ulong do_load_ibatu (CPUPPCState *env, int nr);
 618 target_ulong do_load_ibatl (CPUPPCState *env, int nr);
 619 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
 620 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
 621 target_ulong do_load_dbatu (CPUPPCState *env, int nr);
 622 target_ulong do_load_dbatl (CPUPPCState *env, int nr);
 623 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
 624 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
 625 target_ulong do_load_sdr1 (CPUPPCState *env);
 626 void do_store_sdr1 (CPUPPCState *env, target_ulong value);
 627 #if defined(TARGET_PPC64)
 628 target_ulong ppc_load_asr (CPUPPCState *env);
 629 void ppc_store_asr (CPUPPCState *env, target_ulong value);
 630 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
 631 void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
 632 #endif /* defined(TARGET_PPC64) */
 633 #if 0 // Unused
 634 target_ulong do_load_sr (CPUPPCState *env, int srnum);
 635 #endif
 636 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
 637 #endif /* !defined(CONFIG_USER_ONLY) */
 638 target_ulong ppc_load_xer (CPUPPCState *env);
 639 void ppc_store_xer (CPUPPCState *env, target_ulong value);
 640 target_ulong do_load_msr (CPUPPCState *env);
 641 int do_store_msr (CPUPPCState *env, target_ulong value);
 642 #if defined(TARGET_PPC64)
 643 int ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
 644 #endif
 645
 646 void do_compute_hflags (CPUPPCState *env);
 647 void cpu_ppc_reset (void *opaque);
 648 CPUPPCState *cpu_ppc_init (void);
 649 void cpu_ppc_close(CPUPPCState *env);
 650
 651 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
 652 int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
 653 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 654 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
 655
 656 /* Time-base and decrementer management */
 657 #ifndef NO_CPU_IO_DEFS
 658 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
 659 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
 660 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
 661 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
 662 uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
 663 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
 664 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
 665 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
 666 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
 667 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
 668 #if defined(TARGET_PPC64H)
 669 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
 670 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
 671 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
 672 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
 673 #endif
 674 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
 675 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
 676 #if !defined(CONFIG_USER_ONLY)
 677 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
 678 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
 679 target_ulong load_40x_pit (CPUPPCState *env);
 680 void store_40x_pit (CPUPPCState *env, target_ulong val);
 681 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
 682 void store_40x_sler (CPUPPCState *env, uint32_t val);
 683 void store_booke_tcr (CPUPPCState *env, target_ulong val);
 684 void store_booke_tsr (CPUPPCState *env, target_ulong val);
 685 void ppc_tlb_invalidate_all (CPUPPCState *env);
 686 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
 687 #if defined(TARGET_PPC64)
 688 void ppc_slb_invalidate_all (CPUPPCState *env);
 689 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
 690 #endif
 691 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
 692 #endif
 693 #endif
 694
 695 /* Device control registers */
 696 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
 697 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
 698
 699 #define CPUState CPUPPCState
 700 #define cpu_init cpu_ppc_init
 701 #define cpu_exec cpu_ppc_exec
 702 #define cpu_gen_code cpu_ppc_gen_code
 703 #define cpu_signal_handler cpu_ppc_signal_handler
 704
 705 #include "cpu-all.h"
 706
 707 /*****************************************************************************/
 708 /* Registers definitions */
 709 #define XER_SO 31
 710 #define XER_OV 30
 711 #define XER_CA 29
 712 #define XER_CMP 8
 713 #define XER_BC  0
 714 #define xer_so  env->xer[4]
 715 #define xer_ov  env->xer[6]
 716 #define xer_ca  env->xer[2]
 717 #define xer_cmp env->xer[1]
 718 #define xer_bc  env->xer[0]
 719
 720 /* SPR definitions */
 721 #define SPR_MQ           (0x000)
 722 #define SPR_XER          (0x001)
 723 #define SPR_601_VRTCU    (0x004)
 724 #define SPR_601_VRTCL    (0x005)
 725 #define SPR_601_UDECR    (0x006)
 726 #define SPR_LR           (0x008)
 727 #define SPR_CTR          (0x009)
 728 #define SPR_DSISR        (0x012)
 729 #define SPR_DAR          (0x013) /* DAE for PowerPC 601 */
 730 #define SPR_601_RTCU     (0x014)
 731 #define SPR_601_RTCL     (0x015)
 732 #define SPR_DECR         (0x016)
 733 #define SPR_SDR1         (0x019)
 734 #define SPR_SRR0         (0x01A)
 735 #define SPR_SRR1         (0x01B)
 736 #define SPR_AMR          (0x01D)
 737 #define SPR_BOOKE_PID    (0x030)
 738 #define SPR_BOOKE_DECAR  (0x036)
 739 #define SPR_BOOKE_CSRR0  (0x03A)
 740 #define SPR_BOOKE_CSRR1  (0x03B)
 741 #define SPR_BOOKE_DEAR   (0x03D)
 742 #define SPR_BOOKE_ESR    (0x03E)
 743 #define SPR_BOOKE_IVPR   (0x03F)
 744 #define SPR_8xx_EIE      (0x050)
 745 #define SPR_8xx_EID      (0x051)
 746 #define SPR_8xx_NRE      (0x052)
 747 #define SPR_CTRL         (0x088)
 748 #define SPR_58x_CMPA     (0x090)
 749 #define SPR_58x_CMPB     (0x091)
 750 #define SPR_58x_CMPC     (0x092)
 751 #define SPR_58x_CMPD     (0x093)
 752 #define SPR_58x_ICR      (0x094)
 753 #define SPR_58x_DER      (0x094)
 754 #define SPR_58x_COUNTA   (0x096)
 755 #define SPR_58x_COUNTB   (0x097)
 756 #define SPR_UCTRL        (0x098)
 757 #define SPR_58x_CMPE     (0x098)
 758 #define SPR_58x_CMPF     (0x099)
 759 #define SPR_58x_CMPG     (0x09A)
 760 #define SPR_58x_CMPH     (0x09B)
 761 #define SPR_58x_LCTRL1   (0x09C)
 762 #define SPR_58x_LCTRL2   (0x09D)
 763 #define SPR_58x_ICTRL    (0x09E)
 764 #define SPR_58x_BAR      (0x09F)
 765 #define SPR_VRSAVE       (0x100)
 766 #define SPR_USPRG0       (0x100)
 767 #define SPR_USPRG1       (0x101)
 768 #define SPR_USPRG2       (0x102)
 769 #define SPR_USPRG3       (0x103)
 770 #define SPR_USPRG4       (0x104)
 771 #define SPR_USPRG5       (0x105)
 772 #define SPR_USPRG6       (0x106)
 773 #define SPR_USPRG7       (0x107)
 774 #define SPR_VTBL         (0x10C)
 775 #define SPR_VTBU         (0x10D)
 776 #define SPR_SPRG0        (0x110)
 777 #define SPR_SPRG1        (0x111)
 778 #define SPR_SPRG2        (0x112)
 779 #define SPR_SPRG3        (0x113)
 780 #define SPR_SPRG4        (0x114)
 781 #define SPR_SCOMC        (0x114)
 782 #define SPR_SPRG5        (0x115)
 783 #define SPR_SCOMD        (0x115)
 784 #define SPR_SPRG6        (0x116)
 785 #define SPR_SPRG7        (0x117)
 786 #define SPR_ASR          (0x118)
 787 #define SPR_EAR          (0x11A)
 788 #define SPR_TBL          (0x11C)
 789 #define SPR_TBU          (0x11D)
 790 #define SPR_TBU40        (0x11E)
 791 #define SPR_SVR          (0x11E)
 792 #define SPR_BOOKE_PIR    (0x11E)
 793 #define SPR_PVR          (0x11F)
 794 #define SPR_HSPRG0       (0x130)
 795 #define SPR_BOOKE_DBSR   (0x130)
 796 #define SPR_HSPRG1       (0x131)
 797 #define SPR_HDSISR       (0x132)
 798 #define SPR_HDAR         (0x133)
 799 #define SPR_BOOKE_DBCR0  (0x134)
 800 #define SPR_IBCR         (0x135)
 801 #define SPR_PURR         (0x135)
 802 #define SPR_BOOKE_DBCR1  (0x135)
 803 #define SPR_DBCR         (0x136)
 804 #define SPR_HDEC         (0x136)
 805 #define SPR_BOOKE_DBCR2  (0x136)
 806 #define SPR_HIOR         (0x137)
 807 #define SPR_MBAR         (0x137)
 808 #define SPR_RMOR         (0x138)
 809 #define SPR_BOOKE_IAC1   (0x138)
 810 #define SPR_HRMOR        (0x139)
 811 #define SPR_BOOKE_IAC2   (0x139)
 812 #define SPR_HSRR0        (0x13A)
 813 #define SPR_BOOKE_IAC3   (0x13A)
 814 #define SPR_HSRR1        (0x13B)
 815 #define SPR_BOOKE_IAC4   (0x13B)
 816 #define SPR_LPCR         (0x13C)
 817 #define SPR_BOOKE_DAC1   (0x13C)
 818 #define SPR_LPIDR        (0x13D)
 819 #define SPR_DABR2        (0x13D)
 820 #define SPR_BOOKE_DAC2   (0x13D)
 821 #define SPR_BOOKE_DVC1   (0x13E)
 822 #define SPR_BOOKE_DVC2   (0x13F)
 823 #define SPR_BOOKE_TSR    (0x150)
 824 #define SPR_BOOKE_TCR    (0x154)
 825 #define SPR_BOOKE_IVOR0  (0x190)
 826 #define SPR_BOOKE_IVOR1  (0x191)
 827 #define SPR_BOOKE_IVOR2  (0x192)
 828 #define SPR_BOOKE_IVOR3  (0x193)
 829 #define SPR_BOOKE_IVOR4  (0x194)
 830 #define SPR_BOOKE_IVOR5  (0x195)
 831 #define SPR_BOOKE_IVOR6  (0x196)
 832 #define SPR_BOOKE_IVOR7  (0x197)
 833 #define SPR_BOOKE_IVOR8  (0x198)
 834 #define SPR_BOOKE_IVOR9  (0x199)
 835 #define SPR_BOOKE_IVOR10 (0x19A)
 836 #define SPR_BOOKE_IVOR11 (0x19B)
 837 #define SPR_BOOKE_IVOR12 (0x19C)
 838 #define SPR_BOOKE_IVOR13 (0x19D)
 839 #define SPR_BOOKE_IVOR14 (0x19E)
 840 #define SPR_BOOKE_IVOR15 (0x19F)
 841 #define SPR_BOOKE_SPEFSCR (0x200)
 842 #define SPR_E500_BBEAR   (0x201)
 843 #define SPR_E500_BBTAR   (0x202)
 844 #define SPR_ATBL         (0x20E)
 845 #define SPR_ATBU         (0x20F)
 846 #define SPR_IBAT0U       (0x210)
 847 #define SPR_BOOKE_IVOR32 (0x210)
 848 #define SPR_IBAT0L       (0x211)
 849 #define SPR_BOOKE_IVOR33 (0x211)
 850 #define SPR_IBAT1U       (0x212)
 851 #define SPR_BOOKE_IVOR34 (0x212)
 852 #define SPR_IBAT1L       (0x213)
 853 #define SPR_BOOKE_IVOR35 (0x213)
 854 #define SPR_IBAT2U       (0x214)
 855 #define SPR_BOOKE_IVOR36 (0x214)
 856 #define SPR_IBAT2L       (0x215)
 857 #define SPR_E500_L1CFG0  (0x215)
 858 #define SPR_BOOKE_IVOR37 (0x215)
 859 #define SPR_IBAT3U       (0x216)
 860 #define SPR_E500_L1CFG1  (0x216)
 861 #define SPR_IBAT3L       (0x217)
 862 #define SPR_DBAT0U       (0x218)
 863 #define SPR_DBAT0L       (0x219)
 864 #define SPR_DBAT1U       (0x21A)
 865 #define SPR_DBAT1L       (0x21B)
 866 #define SPR_DBAT2U       (0x21C)
 867 #define SPR_DBAT2L       (0x21D)
 868 #define SPR_DBAT3U       (0x21E)
 869 #define SPR_DBAT3L       (0x21F)
 870 #define SPR_IBAT4U       (0x230)
 871 #define SPR_IBAT4L       (0x231)
 872 #define SPR_IBAT5U       (0x232)
 873 #define SPR_IBAT5L       (0x233)
 874 #define SPR_IBAT6U       (0x234)
 875 #define SPR_IBAT6L       (0x235)
 876 #define SPR_IBAT7U       (0x236)
 877 #define SPR_IBAT7L       (0x237)
 878 #define SPR_DBAT4U       (0x238)
 879 #define SPR_DBAT4L       (0x239)
 880 #define SPR_DBAT5U       (0x23A)
 881 #define SPR_BOOKE_MCSRR0 (0x23A)
 882 #define SPR_DBAT5L       (0x23B)
 883 #define SPR_BOOKE_MCSRR1 (0x23B)
 884 #define SPR_DBAT6U       (0x23C)
 885 #define SPR_BOOKE_MCSR   (0x23C)
 886 #define SPR_DBAT6L       (0x23D)
 887 #define SPR_E500_MCAR    (0x23D)
 888 #define SPR_DBAT7U       (0x23E)
 889 #define SPR_BOOKE_DSRR0  (0x23E)
 890 #define SPR_DBAT7L       (0x23F)
 891 #define SPR_BOOKE_DSRR1  (0x23F)
 892 #define SPR_BOOKE_SPRG8  (0x25C)
 893 #define SPR_BOOKE_SPRG9  (0x25D)
 894 #define SPR_BOOKE_MAS0   (0x270)
 895 #define SPR_BOOKE_MAS1   (0x271)
 896 #define SPR_BOOKE_MAS2   (0x272)
 897 #define SPR_BOOKE_MAS3   (0x273)
 898 #define SPR_BOOKE_MAS4   (0x274)
 899 #define SPR_BOOKE_MAS6   (0x276)
 900 #define SPR_BOOKE_PID1   (0x279)
 901 #define SPR_BOOKE_PID2   (0x27A)
 902 #define SPR_BOOKE_TLB0CFG (0x2B0)
 903 #define SPR_BOOKE_TLB1CFG (0x2B1)
 904 #define SPR_BOOKE_TLB2CFG (0x2B2)
 905 #define SPR_BOOKE_TLB3CFG (0x2B3)
 906 #define SPR_BOOKE_EPR    (0x2BE)
 907 #define SPR_PERF0        (0x300)
 908 #define SPR_PERF1        (0x301)
 909 #define SPR_PERF2        (0x302)
 910 #define SPR_PERF3        (0x303)
 911 #define SPR_PERF4        (0x304)
 912 #define SPR_PERF5        (0x305)
 913 #define SPR_PERF6        (0x306)
 914 #define SPR_PERF7        (0x307)
 915 #define SPR_PERF8        (0x308)
 916 #define SPR_PERF9        (0x309)
 917 #define SPR_PERFA        (0x30A)
 918 #define SPR_PERFB        (0x30B)
 919 #define SPR_PERFC        (0x30C)
 920 #define SPR_PERFD        (0x30D)
 921 #define SPR_PERFE        (0x30E)
 922 #define SPR_PERFF        (0x30F)
 923 #define SPR_UPERF0       (0x310)
 924 #define SPR_UPERF1       (0x311)
 925 #define SPR_UPERF2       (0x312)
 926 #define SPR_UPERF3       (0x313)
 927 #define SPR_UPERF4       (0x314)
 928 #define SPR_UPERF5       (0x315)
 929 #define SPR_UPERF6       (0x316)
 930 #define SPR_UPERF7       (0x317)
 931 #define SPR_UPERF8       (0x318)
 932 #define SPR_UPERF9       (0x319)
 933 #define SPR_UPERFA       (0x31A)
 934 #define SPR_UPERFB       (0x31B)
 935 #define SPR_UPERFC       (0x31C)
 936 #define SPR_UPERFD       (0x31D)
 937 #define SPR_UPERFE       (0x31E)
 938 #define SPR_UPERFF       (0x31F)
 939 #define SPR_440_INV0     (0x370)
 940 #define SPR_440_INV1     (0x371)
 941 #define SPR_440_INV2     (0x372)
 942 #define SPR_440_INV3     (0x373)
 943 #define SPR_440_ITV0     (0x374)
 944 #define SPR_440_ITV1     (0x375)
 945 #define SPR_440_ITV2     (0x376)
 946 #define SPR_440_ITV3     (0x377)
 947 #define SPR_440_CCR1     (0x378)
 948 #define SPR_DCRIPR       (0x37B)
 949 #define SPR_PPR          (0x380)
 950 #define SPR_440_DNV0     (0x390)
 951 #define SPR_440_DNV1     (0x391)
 952 #define SPR_440_DNV2     (0x392)
 953 #define SPR_440_DNV3     (0x393)
 954 #define SPR_440_DTV0     (0x394)
 955 #define SPR_440_DTV1     (0x395)
 956 #define SPR_440_DTV2     (0x396)
 957 #define SPR_440_DTV3     (0x397)
 958 #define SPR_440_DVLIM    (0x398)
 959 #define SPR_440_IVLIM    (0x399)
 960 #define SPR_440_RSTCFG   (0x39B)
 961 #define SPR_BOOKE_DCDBTRL (0x39C)
 962 #define SPR_BOOKE_DCDBTRH (0x39D)
 963 #define SPR_BOOKE_ICDBTRL (0x39E)
 964 #define SPR_BOOKE_ICDBTRH (0x39F)
 965 #define SPR_UMMCR2       (0x3A0)
 966 #define SPR_UPMC5        (0x3A1)
 967 #define SPR_UPMC6        (0x3A2)
 968 #define SPR_UBAMR        (0x3A7)
 969 #define SPR_UMMCR0       (0x3A8)
 970 #define SPR_UPMC1        (0x3A9)
 971 #define SPR_UPMC2        (0x3AA)
 972 #define SPR_USIAR        (0x3AB)
 973 #define SPR_UMMCR1       (0x3AC)
 974 #define SPR_UPMC3        (0x3AD)
 975 #define SPR_UPMC4        (0x3AE)
 976 #define SPR_USDA         (0x3AF)
 977 #define SPR_40x_ZPR      (0x3B0)
 978 #define SPR_BOOKE_MAS7   (0x3B0)
 979 #define SPR_620_PMR0     (0x3B0)
 980 #define SPR_MMCR2        (0x3B0)
 981 #define SPR_PMC5         (0x3B1)
 982 #define SPR_40x_PID      (0x3B1)
 983 #define SPR_620_PMR1     (0x3B1)
 984 #define SPR_PMC6         (0x3B2)
 985 #define SPR_440_MMUCR    (0x3B2)
 986 #define SPR_620_PMR2     (0x3B2)
 987 #define SPR_4xx_CCR0     (0x3B3)
 988 #define SPR_BOOKE_EPLC   (0x3B3)
 989 #define SPR_620_PMR3     (0x3B3)
 990 #define SPR_405_IAC3     (0x3B4)
 991 #define SPR_BOOKE_EPSC   (0x3B4)
 992 #define SPR_620_PMR4     (0x3B4)
 993 #define SPR_405_IAC4     (0x3B5)
 994 #define SPR_620_PMR5     (0x3B5)
 995 #define SPR_405_DVC1     (0x3B6)
 996 #define SPR_620_PMR6     (0x3B6)
 997 #define SPR_405_DVC2     (0x3B7)
 998 #define SPR_620_PMR7     (0x3B7)
 999 #define SPR_BAMR         (0x3B7)
1000 #define SPR_MMCR0        (0x3B8)
1001 #define SPR_620_PMR8     (0x3B8)
1002 #define SPR_PMC1         (0x3B9)
1003 #define SPR_40x_SGR      (0x3B9)
1004 #define SPR_620_PMR9     (0x3B9)
1005 #define SPR_PMC2         (0x3BA)
1006 #define SPR_40x_DCWR     (0x3BA)
1007 #define SPR_620_PMRA     (0x3BA)
1008 #define SPR_SIAR         (0x3BB)
1009 #define SPR_405_SLER     (0x3BB)
1010 #define SPR_620_PMRB     (0x3BB)
1011 #define SPR_MMCR1        (0x3BC)
1012 #define SPR_405_SU0R     (0x3BC)
1013 #define SPR_620_PMRC     (0x3BC)
1014 #define SPR_401_SKR      (0x3BC)
1015 #define SPR_PMC3         (0x3BD)
1016 #define SPR_405_DBCR1    (0x3BD)
1017 #define SPR_620_PMRD     (0x3BD)
1018 #define SPR_PMC4         (0x3BE)
1019 #define SPR_620_PMRE     (0x3BE)
1020 #define SPR_SDA          (0x3BF)
1021 #define SPR_620_PMRF     (0x3BF)
1022 #define SPR_403_VTBL     (0x3CC)
1023 #define SPR_403_VTBU     (0x3CD)
1024 #define SPR_DMISS        (0x3D0)
1025 #define SPR_DCMP         (0x3D1)
1026 #define SPR_HASH1        (0x3D2)
1027 #define SPR_HASH2        (0x3D3)
1028 #define SPR_BOOKE_ICDBDR (0x3D3)
1029 #define SPR_TLBMISS      (0x3D4)
1030 #define SPR_IMISS        (0x3D4)
1031 #define SPR_40x_ESR      (0x3D4)
1032 #define SPR_PTEHI        (0x3D5)
1033 #define SPR_ICMP         (0x3D5)
1034 #define SPR_40x_DEAR     (0x3D5)
1035 #define SPR_PTELO        (0x3D6)
1036 #define SPR_RPA          (0x3D6)
1037 #define SPR_40x_EVPR     (0x3D6)
1038 #define SPR_L3PM         (0x3D7)
1039 #define SPR_403_CDBCR    (0x3D7)
1040 #define SPR_L3OHCR       (0x3D8)
1041 #define SPR_TCR          (0x3D8)
1042 #define SPR_40x_TSR      (0x3D8)
1043 #define SPR_IBR          (0x3DA)
1044 #define SPR_40x_TCR      (0x3DA)
1045 #define SPR_ESASRR       (0x3DB)
1046 #define SPR_40x_PIT      (0x3DB)
1047 #define SPR_403_TBL      (0x3DC)
1048 #define SPR_403_TBU      (0x3DD)
1049 #define SPR_SEBR         (0x3DE)
1050 #define SPR_40x_SRR2     (0x3DE)
1051 #define SPR_SER          (0x3DF)
1052 #define SPR_40x_SRR3     (0x3DF)
1053 #define SPR_L3ITCR0      (0x3E8)
1054 #define SPR_L3ITCR1      (0x3E9)
1055 #define SPR_L3ITCR2      (0x3EA)
1056 #define SPR_L3ITCR3      (0x3EB)
1057 #define SPR_HID0         (0x3F0)
1058 #define SPR_40x_DBSR     (0x3F0)
1059 #define SPR_HID1         (0x3F1)
1060 #define SPR_IABR         (0x3F2)
1061 #define SPR_40x_DBCR0    (0x3F2)
1062 #define SPR_601_HID2     (0x3F2)
1063 #define SPR_E500_L1CSR0  (0x3F2)
1064 #define SPR_ICTRL        (0x3F3)
1065 #define SPR_HID2         (0x3F3)
1066 #define SPR_E500_L1CSR1  (0x3F3)
1067 #define SPR_440_DBDR     (0x3F3)
1068 #define SPR_LDSTDB       (0x3F4)
1069 #define SPR_40x_IAC1     (0x3F4)
1070 #define SPR_MMUCSR0      (0x3F4)
1071 #define SPR_DABR         (0x3F5)
1072 #define DABR_MASK (~(target_ulong)0x7)
1073 #define SPR_E500_BUCSR   (0x3F5)
1074 #define SPR_40x_IAC2     (0x3F5)
1075 #define SPR_601_HID5     (0x3F5)
1076 #define SPR_40x_DAC1     (0x3F6)
1077 #define SPR_MSSCR0       (0x3F6)
1078 #define SPR_970_HID5     (0x3F6)
1079 #define SPR_MSSSR0       (0x3F7)
1080 #define SPR_DABRX        (0x3F7)
1081 #define SPR_40x_DAC2     (0x3F7)
1082 #define SPR_MMUCFG       (0x3F7)
1083 #define SPR_LDSTCR       (0x3F8)
1084 #define SPR_L2PMCR       (0x3F8)
1085 #define SPR_750_HID2     (0x3F8)
1086 #define SPR_620_HID8     (0x3F8)
1087 #define SPR_L2CR         (0x3F9)
1088 #define SPR_620_HID9     (0x3F9)
1089 #define SPR_L3CR         (0x3FA)
1090 #define SPR_IABR2        (0x3FA)
1091 #define SPR_40x_DCCR     (0x3FA)
1092 #define SPR_ICTC         (0x3FB)
1093 #define SPR_40x_ICCR     (0x3FB)
1094 #define SPR_THRM1        (0x3FC)
1095 #define SPR_403_PBL1     (0x3FC)
1096 #define SPR_SP           (0x3FD)
1097 #define SPR_THRM2        (0x3FD)
1098 #define SPR_403_PBU1     (0x3FD)
1099 #define SPR_604_HID13    (0x3FD)
1100 #define SPR_LT           (0x3FE)
1101 #define SPR_THRM3        (0x3FE)
1102 #define SPR_FPECR        (0x3FE)
1103 #define SPR_403_PBL2     (0x3FE)
1104 #define SPR_PIR          (0x3FF)
1105 #define SPR_403_PBU2     (0x3FF)
1106 #define SPR_601_HID15    (0x3FF)
1107 #define SPR_604_HID15    (0x3FF)
1108 #define SPR_E500_SVR     (0x3FF)
1109
1110 /*****************************************************************************/
1111 /* Memory access type :
1112  * may be needed for precise access rights control and precise exceptions.
1113  */
1114 enum {
1115     /* 1 bit to define user level / supervisor access */
1116     ACCESS_USER  = 0x00,
1117     ACCESS_SUPER = 0x01,
1118     /* Type of instruction that generated the access */
1119     ACCESS_CODE  = 0x10, /* Code fetch access                */
1120     ACCESS_INT   = 0x20, /* Integer load/store access        */
1121     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1122     ACCESS_RES   = 0x40, /* load/store with reservation      */
1123     ACCESS_EXT   = 0x50, /* external access                  */
1124     ACCESS_CACHE = 0x60, /* Cache manipulation               */
1125 };
1126
1127 /* Hardware interruption sources:
1128  * all those exception can be raised simulteaneously
1129  */
1130 /* Input pins definitions */
1131 enum {
1132     /* 6xx bus input pins */
1133     PPC6xx_INPUT_HRESET     = 0,
1134     PPC6xx_INPUT_SRESET     = 1,
1135     PPC6xx_INPUT_CKSTP_IN   = 2,
1136     PPC6xx_INPUT_MCP        = 3,
1137     PPC6xx_INPUT_SMI        = 4,
1138     PPC6xx_INPUT_INT        = 5,
1139 };
1140
1141 enum {
1142     /* Embedded PowerPC input pins */
1143     PPCBookE_INPUT_HRESET     = 0,
1144     PPCBookE_INPUT_SRESET     = 1,
1145     PPCBookE_INPUT_CKSTP_IN   = 2,
1146     PPCBookE_INPUT_MCP        = 3,
1147     PPCBookE_INPUT_SMI        = 4,
1148     PPCBookE_INPUT_INT        = 5,
1149     PPCBookE_INPUT_CINT       = 6,
1150 };
1151
1152 enum {
1153     /* PowerPC 40x input pins */
1154     PPC40x_INPUT_RESET_CORE = 0,
1155     PPC40x_INPUT_RESET_CHIP = 1,
1156     PPC40x_INPUT_RESET_SYS  = 2,
1157     PPC40x_INPUT_CINT       = 3,
1158     PPC40x_INPUT_INT        = 4,
1159     PPC40x_INPUT_HALT       = 5,
1160     PPC40x_INPUT_DEBUG      = 6,
1161     PPC40x_INPUT_NB,
1162 };
1163
1164 #if defined(TARGET_PPC64)
1165 enum {
1166     /* PowerPC 620 (and probably others) input pins */
1167     PPC620_INPUT_HRESET     = 0,
1168     PPC620_INPUT_SRESET     = 1,
1169     PPC620_INPUT_CKSTP      = 2,
1170     PPC620_INPUT_TBEN       = 3,
1171     PPC620_INPUT_WAKEUP     = 4,
1172     PPC620_INPUT_MCP        = 5,
1173     PPC620_INPUT_SMI        = 6,
1174     PPC620_INPUT_INT        = 7,
1175 };
1176
1177 enum {
1178     /* PowerPC 970 input pins */
1179     PPC970_INPUT_HRESET     = 0,
1180     PPC970_INPUT_SRESET     = 1,
1181     PPC970_INPUT_CKSTP      = 2,
1182     PPC970_INPUT_TBEN       = 3,
1183     PPC970_INPUT_MCP        = 4,
1184     PPC970_INPUT_INT        = 5,
1185     PPC970_INPUT_THINT      = 6,
1186 };
1187 #endif
1188
1189 /* Hardware exceptions definitions */
1190 enum {
1191     /* External hardware exception sources */
1192     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
1193     PPC_INTERRUPT_MCK       = 1,  /* Machine check exception              */
1194     PPC_INTERRUPT_EXT       = 2,  /* External interrupt                   */
1195     PPC_INTERRUPT_SMI       = 3,  /* System management interrupt          */
1196     PPC_INTERRUPT_CEXT      = 4,  /* Critical external interrupt          */
1197     PPC_INTERRUPT_DEBUG     = 5,  /* External debug exception             */
1198     PPC_INTERRUPT_THERM     = 6,  /* Thermal exception                    */
1199     /* Internal hardware exception sources */
1200     PPC_INTERRUPT_DECR      = 7,  /* Decrementer exception                */
1201     PPC_INTERRUPT_HDECR     = 8,  /* Hypervisor decrementer exception     */
1202     PPC_INTERRUPT_PIT       = 9,  /* Programmable inteval timer interrupt */
1203     PPC_INTERRUPT_FIT       = 10, /* Fixed interval timer interrupt       */
1204     PPC_INTERRUPT_WDT       = 11, /* Watchdog timer interrupt             */
1205     PPC_INTERRUPT_CDOORBELL = 12, /* Critical doorbell interrupt          */
1206     PPC_INTERRUPT_DOORBELL  = 13, /* Doorbell interrupt                   */
1207     PPC_INTERRUPT_PERFM     = 14, /* Performance monitor interrupt        */
1208 };
1209
1210 /*****************************************************************************/
1211
1212 #endif /* !defined (__CPU_PPC_H__) */