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cpu: move exec-all.h inclusion out of cpu.h
[mirror_qemu.git] / target-ppc / cpu.h
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "qemu-common.h"
23
24 //#define PPC_EMULATE_32BITS_HYPV
25
26 #if defined (TARGET_PPC64)
27 /* PowerPC 64 definitions */
28 #define TARGET_LONG_BITS 64
29 #define TARGET_PAGE_BITS 12
30
31 #define TARGET_IS_BIENDIAN 1
32
33 /* Note that the official physical address space bits is 62-M where M
34 is implementation dependent. I've not looked up M for the set of
35 cpus we emulate at the system level. */
36 #define TARGET_PHYS_ADDR_SPACE_BITS 62
37
38 /* Note that the PPC environment architecture talks about 80 bit virtual
39 addresses, with segmentation. Obviously that's not all visible to a
40 single process, which is all we're concerned with here. */
41 #ifdef TARGET_ABI32
42 # define TARGET_VIRT_ADDR_SPACE_BITS 32
43 #else
44 # define TARGET_VIRT_ADDR_SPACE_BITS 64
45 #endif
46
47 #define TARGET_PAGE_BITS_64K 16
48 #define TARGET_PAGE_BITS_16M 24
49
50 #else /* defined (TARGET_PPC64) */
51 /* PowerPC 32 definitions */
52 #define TARGET_LONG_BITS 32
53
54 #if defined(TARGET_PPCEMB)
55 /* Specific definitions for PowerPC embedded */
56 /* BookE have 36 bits physical address space */
57 #if defined(CONFIG_USER_ONLY)
58 /* It looks like a lot of Linux programs assume page size
59 * is 4kB long. This is evil, but we have to deal with it...
60 */
61 #define TARGET_PAGE_BITS 12
62 #else /* defined(CONFIG_USER_ONLY) */
63 /* Pages can be 1 kB small */
64 #define TARGET_PAGE_BITS 10
65 #endif /* defined(CONFIG_USER_ONLY) */
66 #else /* defined(TARGET_PPCEMB) */
67 /* "standard" PowerPC 32 definitions */
68 #define TARGET_PAGE_BITS 12
69 #endif /* defined(TARGET_PPCEMB) */
70
71 #define TARGET_PHYS_ADDR_SPACE_BITS 36
72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
73
74 #endif /* defined (TARGET_PPC64) */
75
76 #define CPUArchState struct CPUPPCState
77
78 #include "exec/cpu-defs.h"
79 #include "cpu-qom.h"
80 #include "fpu/softfloat.h"
81
82 #if defined (TARGET_PPC64)
83 #define PPC_ELF_MACHINE EM_PPC64
84 #else
85 #define PPC_ELF_MACHINE EM_PPC
86 #endif
87
88 /*****************************************************************************/
89 /* Exception vectors definitions */
90 enum {
91 POWERPC_EXCP_NONE = -1,
92 /* The 64 first entries are used by the PowerPC embedded specification */
93 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
94 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
95 POWERPC_EXCP_DSI = 2, /* Data storage exception */
96 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
97 POWERPC_EXCP_EXTERNAL = 4, /* External input */
98 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
99 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
100 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
101 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
102 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
103 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
104 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
105 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
106 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
107 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
108 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
109 /* Vectors 16 to 31 are reserved */
110 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
111 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
112 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
113 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
114 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
115 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
116 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
117 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
118 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
119 /* Vectors 42 to 63 are reserved */
120 /* Exceptions defined in the PowerPC server specification */
121 POWERPC_EXCP_RESET = 64, /* System reset exception */
122 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
123 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
124 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
125 POWERPC_EXCP_TRACE = 68, /* Trace exception */
126 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
127 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
128 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
129 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
130 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
131 /* 40x specific exceptions */
132 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
133 /* 601 specific exceptions */
134 POWERPC_EXCP_IO = 75, /* IO error exception */
135 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
136 /* 602 specific exceptions */
137 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
138 /* 602/603 specific exceptions */
139 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
140 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
141 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
142 /* Exceptions available on most PowerPC */
143 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
144 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
145 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
146 POWERPC_EXCP_SMI = 84, /* System management interrupt */
147 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
148 /* 7xx/74xx specific exceptions */
149 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
150 /* 74xx specific exceptions */
151 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
152 /* 970FX specific exceptions */
153 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
154 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
155 /* Freescale embedded cores specific exceptions */
156 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
157 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
158 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
159 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
160 /* VSX Unavailable (Power ISA 2.06 and later) */
161 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
162 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
163 /* EOL */
164 POWERPC_EXCP_NB = 96,
165 /* QEMU exceptions: used internally during code translation */
166 POWERPC_EXCP_STOP = 0x200, /* stop translation */
167 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
168 /* QEMU exceptions: special cases we want to stop translation */
169 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
170 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
171 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
172 };
173
174 /* Exceptions error codes */
175 enum {
176 /* Exception subtypes for POWERPC_EXCP_ALIGN */
177 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
178 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
179 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
180 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
181 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
182 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
183 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
184 /* FP exceptions */
185 POWERPC_EXCP_FP = 0x10,
186 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
187 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
188 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
189 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
190 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
191 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
192 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
193 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
194 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
195 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
196 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
197 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
198 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
199 /* Invalid instruction */
200 POWERPC_EXCP_INVAL = 0x20,
201 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
202 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
203 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
204 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
205 /* Privileged instruction */
206 POWERPC_EXCP_PRIV = 0x30,
207 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
208 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
209 /* Trap */
210 POWERPC_EXCP_TRAP = 0x40,
211 };
212
213 #define PPC_INPUT(env) (env->bus_model)
214
215 /*****************************************************************************/
216 typedef struct opc_handler_t opc_handler_t;
217
218 /*****************************************************************************/
219 /* Types used to describe some PowerPC registers */
220 typedef struct DisasContext DisasContext;
221 typedef struct ppc_spr_t ppc_spr_t;
222 typedef union ppc_avr_t ppc_avr_t;
223 typedef union ppc_tlb_t ppc_tlb_t;
224
225 /* SPR access micro-ops generations callbacks */
226 struct ppc_spr_t {
227 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
228 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
229 #if !defined(CONFIG_USER_ONLY)
230 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
231 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
232 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
233 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
234 #endif
235 const char *name;
236 target_ulong default_value;
237 #ifdef CONFIG_KVM
238 /* We (ab)use the fact that all the SPRs will have ids for the
239 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
240 * don't sync this */
241 uint64_t one_reg_id;
242 #endif
243 };
244
245 /* Altivec registers (128 bits) */
246 union ppc_avr_t {
247 float32 f[4];
248 uint8_t u8[16];
249 uint16_t u16[8];
250 uint32_t u32[4];
251 int8_t s8[16];
252 int16_t s16[8];
253 int32_t s32[4];
254 uint64_t u64[2];
255 int64_t s64[2];
256 #ifdef CONFIG_INT128
257 __uint128_t u128;
258 #endif
259 };
260
261 #if !defined(CONFIG_USER_ONLY)
262 /* Software TLB cache */
263 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
264 struct ppc6xx_tlb_t {
265 target_ulong pte0;
266 target_ulong pte1;
267 target_ulong EPN;
268 };
269
270 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
271 struct ppcemb_tlb_t {
272 uint64_t RPN;
273 target_ulong EPN;
274 target_ulong PID;
275 target_ulong size;
276 uint32_t prot;
277 uint32_t attr; /* Storage attributes */
278 };
279
280 typedef struct ppcmas_tlb_t {
281 uint32_t mas8;
282 uint32_t mas1;
283 uint64_t mas2;
284 uint64_t mas7_3;
285 } ppcmas_tlb_t;
286
287 union ppc_tlb_t {
288 ppc6xx_tlb_t *tlb6;
289 ppcemb_tlb_t *tlbe;
290 ppcmas_tlb_t *tlbm;
291 };
292
293 /* possible TLB variants */
294 #define TLB_NONE 0
295 #define TLB_6XX 1
296 #define TLB_EMB 2
297 #define TLB_MAS 3
298 #endif
299
300 #define SDR_32_HTABORG 0xFFFF0000UL
301 #define SDR_32_HTABMASK 0x000001FFUL
302
303 #if defined(TARGET_PPC64)
304 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
305 #define SDR_64_HTABSIZE 0x000000000000001FULL
306 #endif /* defined(TARGET_PPC64 */
307
308 typedef struct ppc_slb_t ppc_slb_t;
309 struct ppc_slb_t {
310 uint64_t esid;
311 uint64_t vsid;
312 const struct ppc_one_seg_page_size *sps;
313 };
314
315 #define MAX_SLB_ENTRIES 64
316 #define SEGMENT_SHIFT_256M 28
317 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
318
319 #define SEGMENT_SHIFT_1T 40
320 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
321
322
323 /*****************************************************************************/
324 /* Machine state register bits definition */
325 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
326 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
327 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
328 #define MSR_SHV 60 /* hypervisor state hflags */
329 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
330 #define MSR_TS1 33
331 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
332 #define MSR_CM 31 /* Computation mode for BookE hflags */
333 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
334 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
335 #define MSR_GS 28 /* guest state for BookE */
336 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
337 #define MSR_VR 25 /* altivec available x hflags */
338 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
339 #define MSR_AP 23 /* Access privilege state on 602 hflags */
340 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
341 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
342 #define MSR_KEY 19 /* key bit on 603e */
343 #define MSR_POW 18 /* Power management */
344 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
345 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
346 #define MSR_ILE 16 /* Interrupt little-endian mode */
347 #define MSR_EE 15 /* External interrupt enable */
348 #define MSR_PR 14 /* Problem state hflags */
349 #define MSR_FP 13 /* Floating point available hflags */
350 #define MSR_ME 12 /* Machine check interrupt enable */
351 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
352 #define MSR_SE 10 /* Single-step trace enable x hflags */
353 #define MSR_DWE 10 /* Debug wait enable on 405 x */
354 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
355 #define MSR_BE 9 /* Branch trace enable x hflags */
356 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
357 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
358 #define MSR_AL 7 /* AL bit on POWER */
359 #define MSR_EP 6 /* Exception prefix on 601 */
360 #define MSR_IR 5 /* Instruction relocate */
361 #define MSR_DR 4 /* Data relocate */
362 #define MSR_PE 3 /* Protection enable on 403 */
363 #define MSR_PX 2 /* Protection exclusive on 403 x */
364 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
365 #define MSR_RI 1 /* Recoverable interrupt 1 */
366 #define MSR_LE 0 /* Little-endian mode 1 hflags */
367
368 /* LPCR bits */
369 #define LPCR_VPM0 (1ull << (63 - 0))
370 #define LPCR_VPM1 (1ull << (63 - 1))
371 #define LPCR_ISL (1ull << (63 - 2))
372 #define LPCR_KBV (1ull << (63 - 3))
373 #define LPCR_ILE (1ull << (63 - 38))
374 #define LPCR_MER (1ull << (63 - 52))
375 #define LPCR_LPES0 (1ull << (63 - 60))
376 #define LPCR_LPES1 (1ull << (63 - 61))
377 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
378 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
379
380 #define msr_sf ((env->msr >> MSR_SF) & 1)
381 #define msr_isf ((env->msr >> MSR_ISF) & 1)
382 #define msr_shv ((env->msr >> MSR_SHV) & 1)
383 #define msr_cm ((env->msr >> MSR_CM) & 1)
384 #define msr_icm ((env->msr >> MSR_ICM) & 1)
385 #define msr_thv ((env->msr >> MSR_THV) & 1)
386 #define msr_gs ((env->msr >> MSR_GS) & 1)
387 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
388 #define msr_vr ((env->msr >> MSR_VR) & 1)
389 #define msr_spe ((env->msr >> MSR_SPE) & 1)
390 #define msr_ap ((env->msr >> MSR_AP) & 1)
391 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
392 #define msr_sa ((env->msr >> MSR_SA) & 1)
393 #define msr_key ((env->msr >> MSR_KEY) & 1)
394 #define msr_pow ((env->msr >> MSR_POW) & 1)
395 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
396 #define msr_ce ((env->msr >> MSR_CE) & 1)
397 #define msr_ile ((env->msr >> MSR_ILE) & 1)
398 #define msr_ee ((env->msr >> MSR_EE) & 1)
399 #define msr_pr ((env->msr >> MSR_PR) & 1)
400 #define msr_fp ((env->msr >> MSR_FP) & 1)
401 #define msr_me ((env->msr >> MSR_ME) & 1)
402 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
403 #define msr_se ((env->msr >> MSR_SE) & 1)
404 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
405 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
406 #define msr_be ((env->msr >> MSR_BE) & 1)
407 #define msr_de ((env->msr >> MSR_DE) & 1)
408 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
409 #define msr_al ((env->msr >> MSR_AL) & 1)
410 #define msr_ep ((env->msr >> MSR_EP) & 1)
411 #define msr_ir ((env->msr >> MSR_IR) & 1)
412 #define msr_dr ((env->msr >> MSR_DR) & 1)
413 #define msr_pe ((env->msr >> MSR_PE) & 1)
414 #define msr_px ((env->msr >> MSR_PX) & 1)
415 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
416 #define msr_ri ((env->msr >> MSR_RI) & 1)
417 #define msr_le ((env->msr >> MSR_LE) & 1)
418 #define msr_ts ((env->msr >> MSR_TS1) & 3)
419 #define msr_tm ((env->msr >> MSR_TM) & 1)
420
421 /* Hypervisor bit is more specific */
422 #if defined(TARGET_PPC64)
423 #define MSR_HVB (1ULL << MSR_SHV)
424 #define msr_hv msr_shv
425 #else
426 #if defined(PPC_EMULATE_32BITS_HYPV)
427 #define MSR_HVB (1ULL << MSR_THV)
428 #define msr_hv msr_thv
429 #else
430 #define MSR_HVB (0ULL)
431 #define msr_hv (0)
432 #endif
433 #endif
434
435 /* Facility Status and Control (FSCR) bits */
436 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
437 #define FSCR_TAR (63 - 55) /* Target Address Register */
438 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
439 #define FSCR_IC_MASK (0xFFULL)
440 #define FSCR_IC_POS (63 - 7)
441 #define FSCR_IC_DSCR_SPR3 2
442 #define FSCR_IC_PMU 3
443 #define FSCR_IC_BHRB 4
444 #define FSCR_IC_TM 5
445 #define FSCR_IC_EBB 7
446 #define FSCR_IC_TAR 8
447
448 /* Exception state register bits definition */
449 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
450 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
451 #define ESR_PTR (1 << (63 - 38)) /* Trap */
452 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
453 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
454 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
455 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
456 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
457 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
458 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
459 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
460 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
461 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
462 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
463 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
464 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
465
466 /* Transaction EXception And Summary Register bits */
467 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
468 #define TEXASR_DISALLOWED (63 - 8)
469 #define TEXASR_NESTING_OVERFLOW (63 - 9)
470 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
471 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
472 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
473 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
474 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
475 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
476 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
477 #define TEXASR_ABORT (63 - 31)
478 #define TEXASR_SUSPENDED (63 - 32)
479 #define TEXASR_PRIVILEGE_HV (63 - 34)
480 #define TEXASR_PRIVILEGE_PR (63 - 35)
481 #define TEXASR_FAILURE_SUMMARY (63 - 36)
482 #define TEXASR_TFIAR_EXACT (63 - 37)
483 #define TEXASR_ROT (63 - 38)
484 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
485
486 enum {
487 POWERPC_FLAG_NONE = 0x00000000,
488 /* Flag for MSR bit 25 signification (VRE/SPE) */
489 POWERPC_FLAG_SPE = 0x00000001,
490 POWERPC_FLAG_VRE = 0x00000002,
491 /* Flag for MSR bit 17 signification (TGPR/CE) */
492 POWERPC_FLAG_TGPR = 0x00000004,
493 POWERPC_FLAG_CE = 0x00000008,
494 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
495 POWERPC_FLAG_SE = 0x00000010,
496 POWERPC_FLAG_DWE = 0x00000020,
497 POWERPC_FLAG_UBLE = 0x00000040,
498 /* Flag for MSR bit 9 signification (BE/DE) */
499 POWERPC_FLAG_BE = 0x00000080,
500 POWERPC_FLAG_DE = 0x00000100,
501 /* Flag for MSR bit 2 signification (PX/PMM) */
502 POWERPC_FLAG_PX = 0x00000200,
503 POWERPC_FLAG_PMM = 0x00000400,
504 /* Flag for special features */
505 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
506 POWERPC_FLAG_RTC_CLK = 0x00010000,
507 POWERPC_FLAG_BUS_CLK = 0x00020000,
508 /* Has CFAR */
509 POWERPC_FLAG_CFAR = 0x00040000,
510 /* Has VSX */
511 POWERPC_FLAG_VSX = 0x00080000,
512 /* Has Transaction Memory (ISA 2.07) */
513 POWERPC_FLAG_TM = 0x00100000,
514 };
515
516 /*****************************************************************************/
517 /* Floating point status and control register */
518 #define FPSCR_FX 31 /* Floating-point exception summary */
519 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
520 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
521 #define FPSCR_OX 28 /* Floating-point overflow exception */
522 #define FPSCR_UX 27 /* Floating-point underflow exception */
523 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
524 #define FPSCR_XX 25 /* Floating-point inexact exception */
525 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
526 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
527 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
528 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
529 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
530 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
531 #define FPSCR_FR 18 /* Floating-point fraction rounded */
532 #define FPSCR_FI 17 /* Floating-point fraction inexact */
533 #define FPSCR_C 16 /* Floating-point result class descriptor */
534 #define FPSCR_FL 15 /* Floating-point less than or negative */
535 #define FPSCR_FG 14 /* Floating-point greater than or negative */
536 #define FPSCR_FE 13 /* Floating-point equal or zero */
537 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
538 #define FPSCR_FPCC 12 /* Floating-point condition code */
539 #define FPSCR_FPRF 12 /* Floating-point result flags */
540 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
541 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
542 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
543 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
544 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
545 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
546 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
547 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
548 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
549 #define FPSCR_RN1 1
550 #define FPSCR_RN 0 /* Floating-point rounding control */
551 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
552 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
553 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
554 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
555 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
556 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
557 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
558 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
559 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
560 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
561 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
562 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
563 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
564 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
565 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
566 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
567 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
568 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
569 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
570 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
571 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
572 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
573 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
574 /* Invalid operation exception summary */
575 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
576 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
577 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
578 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
579 (1 << FPSCR_VXCVI)))
580 /* exception summary */
581 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
582 /* enabled exception summary */
583 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
584 0x1F)
585
586 #define FP_FX (1ull << FPSCR_FX)
587 #define FP_FEX (1ull << FPSCR_FEX)
588 #define FP_VX (1ull << FPSCR_VX)
589 #define FP_OX (1ull << FPSCR_OX)
590 #define FP_UX (1ull << FPSCR_UX)
591 #define FP_ZX (1ull << FPSCR_ZX)
592 #define FP_XX (1ull << FPSCR_XX)
593 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
594 #define FP_VXISI (1ull << FPSCR_VXISI)
595 #define FP_VXIDI (1ull << FPSCR_VXIDI)
596 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
597 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
598 #define FP_VXVC (1ull << FPSCR_VXVC)
599 #define FP_FR (1ull << FSPCR_FR)
600 #define FP_FI (1ull << FPSCR_FI)
601 #define FP_C (1ull << FPSCR_C)
602 #define FP_FL (1ull << FPSCR_FL)
603 #define FP_FG (1ull << FPSCR_FG)
604 #define FP_FE (1ull << FPSCR_FE)
605 #define FP_FU (1ull << FPSCR_FU)
606 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
607 #define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
608 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
609 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
610 #define FP_VXCVI (1ull << FPSCR_VXCVI)
611 #define FP_VE (1ull << FPSCR_VE)
612 #define FP_OE (1ull << FPSCR_OE)
613 #define FP_UE (1ull << FPSCR_UE)
614 #define FP_ZE (1ull << FPSCR_ZE)
615 #define FP_XE (1ull << FPSCR_XE)
616 #define FP_NI (1ull << FPSCR_NI)
617 #define FP_RN1 (1ull << FPSCR_RN1)
618 #define FP_RN (1ull << FPSCR_RN)
619
620 /* the exception bits which can be cleared by mcrfs - includes FX */
621 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
622 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
623 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
624 FP_VXSQRT | FP_VXCVI)
625
626 /*****************************************************************************/
627 /* Vector status and control register */
628 #define VSCR_NJ 16 /* Vector non-java */
629 #define VSCR_SAT 0 /* Vector saturation */
630 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
631 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
632
633 /*****************************************************************************/
634 /* BookE e500 MMU registers */
635
636 #define MAS0_NV_SHIFT 0
637 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
638
639 #define MAS0_WQ_SHIFT 12
640 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
641 /* Write TLB entry regardless of reservation */
642 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
643 /* Write TLB entry only already in use */
644 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
645 /* Clear TLB entry */
646 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
647
648 #define MAS0_HES_SHIFT 14
649 #define MAS0_HES (1 << MAS0_HES_SHIFT)
650
651 #define MAS0_ESEL_SHIFT 16
652 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
653
654 #define MAS0_TLBSEL_SHIFT 28
655 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
656 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
657 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
658 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
659 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
660
661 #define MAS0_ATSEL_SHIFT 31
662 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
663 #define MAS0_ATSEL_TLB 0
664 #define MAS0_ATSEL_LRAT MAS0_ATSEL
665
666 #define MAS1_TSIZE_SHIFT 7
667 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
668
669 #define MAS1_TS_SHIFT 12
670 #define MAS1_TS (1 << MAS1_TS_SHIFT)
671
672 #define MAS1_IND_SHIFT 13
673 #define MAS1_IND (1 << MAS1_IND_SHIFT)
674
675 #define MAS1_TID_SHIFT 16
676 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
677
678 #define MAS1_IPROT_SHIFT 30
679 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
680
681 #define MAS1_VALID_SHIFT 31
682 #define MAS1_VALID 0x80000000
683
684 #define MAS2_EPN_SHIFT 12
685 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
686
687 #define MAS2_ACM_SHIFT 6
688 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
689
690 #define MAS2_VLE_SHIFT 5
691 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
692
693 #define MAS2_W_SHIFT 4
694 #define MAS2_W (1 << MAS2_W_SHIFT)
695
696 #define MAS2_I_SHIFT 3
697 #define MAS2_I (1 << MAS2_I_SHIFT)
698
699 #define MAS2_M_SHIFT 2
700 #define MAS2_M (1 << MAS2_M_SHIFT)
701
702 #define MAS2_G_SHIFT 1
703 #define MAS2_G (1 << MAS2_G_SHIFT)
704
705 #define MAS2_E_SHIFT 0
706 #define MAS2_E (1 << MAS2_E_SHIFT)
707
708 #define MAS3_RPN_SHIFT 12
709 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
710
711 #define MAS3_U0 0x00000200
712 #define MAS3_U1 0x00000100
713 #define MAS3_U2 0x00000080
714 #define MAS3_U3 0x00000040
715 #define MAS3_UX 0x00000020
716 #define MAS3_SX 0x00000010
717 #define MAS3_UW 0x00000008
718 #define MAS3_SW 0x00000004
719 #define MAS3_UR 0x00000002
720 #define MAS3_SR 0x00000001
721 #define MAS3_SPSIZE_SHIFT 1
722 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
723
724 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
725 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
726 #define MAS4_TIDSELD_MASK 0x00030000
727 #define MAS4_TIDSELD_PID0 0x00000000
728 #define MAS4_TIDSELD_PID1 0x00010000
729 #define MAS4_TIDSELD_PID2 0x00020000
730 #define MAS4_TIDSELD_PIDZ 0x00030000
731 #define MAS4_INDD 0x00008000 /* Default IND */
732 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
733 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
734 #define MAS4_ACMD 0x00000040
735 #define MAS4_VLED 0x00000020
736 #define MAS4_WD 0x00000010
737 #define MAS4_ID 0x00000008
738 #define MAS4_MD 0x00000004
739 #define MAS4_GD 0x00000002
740 #define MAS4_ED 0x00000001
741 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
742 #define MAS4_WIMGED_SHIFT 0
743
744 #define MAS5_SGS 0x80000000
745 #define MAS5_SLPID_MASK 0x00000fff
746
747 #define MAS6_SPID0 0x3fff0000
748 #define MAS6_SPID1 0x00007ffe
749 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
750 #define MAS6_SAS 0x00000001
751 #define MAS6_SPID MAS6_SPID0
752 #define MAS6_SIND 0x00000002 /* Indirect page */
753 #define MAS6_SIND_SHIFT 1
754 #define MAS6_SPID_MASK 0x3fff0000
755 #define MAS6_SPID_SHIFT 16
756 #define MAS6_ISIZE_MASK 0x00000f80
757 #define MAS6_ISIZE_SHIFT 7
758
759 #define MAS7_RPN 0xffffffff
760
761 #define MAS8_TGS 0x80000000
762 #define MAS8_VF 0x40000000
763 #define MAS8_TLBPID 0x00000fff
764
765 /* Bit definitions for MMUCFG */
766 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
767 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
768 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
769 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
770 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
771 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
772 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
773 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
774 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
775
776 /* Bit definitions for MMUCSR0 */
777 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
778 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
779 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
780 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
781 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
782 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
783 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
784 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
785 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
786 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
787
788 /* TLBnCFG encoding */
789 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
790 #define TLBnCFG_HES 0x00002000 /* HW select supported */
791 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
792 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
793 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
794 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
795 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
796 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
797 #define TLBnCFG_MINSIZE_SHIFT 20
798 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
799 #define TLBnCFG_MAXSIZE_SHIFT 16
800 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
801 #define TLBnCFG_ASSOC_SHIFT 24
802
803 /* TLBnPS encoding */
804 #define TLBnPS_4K 0x00000004
805 #define TLBnPS_8K 0x00000008
806 #define TLBnPS_16K 0x00000010
807 #define TLBnPS_32K 0x00000020
808 #define TLBnPS_64K 0x00000040
809 #define TLBnPS_128K 0x00000080
810 #define TLBnPS_256K 0x00000100
811 #define TLBnPS_512K 0x00000200
812 #define TLBnPS_1M 0x00000400
813 #define TLBnPS_2M 0x00000800
814 #define TLBnPS_4M 0x00001000
815 #define TLBnPS_8M 0x00002000
816 #define TLBnPS_16M 0x00004000
817 #define TLBnPS_32M 0x00008000
818 #define TLBnPS_64M 0x00010000
819 #define TLBnPS_128M 0x00020000
820 #define TLBnPS_256M 0x00040000
821 #define TLBnPS_512M 0x00080000
822 #define TLBnPS_1G 0x00100000
823 #define TLBnPS_2G 0x00200000
824 #define TLBnPS_4G 0x00400000
825 #define TLBnPS_8G 0x00800000
826 #define TLBnPS_16G 0x01000000
827 #define TLBnPS_32G 0x02000000
828 #define TLBnPS_64G 0x04000000
829 #define TLBnPS_128G 0x08000000
830 #define TLBnPS_256G 0x10000000
831
832 /* tlbilx action encoding */
833 #define TLBILX_T_ALL 0
834 #define TLBILX_T_TID 1
835 #define TLBILX_T_FULLMATCH 3
836 #define TLBILX_T_CLASS0 4
837 #define TLBILX_T_CLASS1 5
838 #define TLBILX_T_CLASS2 6
839 #define TLBILX_T_CLASS3 7
840
841 /* BookE 2.06 helper defines */
842
843 #define BOOKE206_FLUSH_TLB0 (1 << 0)
844 #define BOOKE206_FLUSH_TLB1 (1 << 1)
845 #define BOOKE206_FLUSH_TLB2 (1 << 2)
846 #define BOOKE206_FLUSH_TLB3 (1 << 3)
847
848 /* number of possible TLBs */
849 #define BOOKE206_MAX_TLBN 4
850
851 /*****************************************************************************/
852 /* Embedded.Processor Control */
853
854 #define DBELL_TYPE_SHIFT 27
855 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
856 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
857 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
858 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
859 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
860 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
861
862 #define DBELL_BRDCAST (1 << 26)
863 #define DBELL_LPIDTAG_SHIFT 14
864 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
865 #define DBELL_PIRTAG_MASK 0x3fff
866
867 /*****************************************************************************/
868 /* Segment page size information, used by recent hash MMUs
869 * The format of this structure mirrors kvm_ppc_smmu_info
870 */
871
872 #define PPC_PAGE_SIZES_MAX_SZ 8
873
874 struct ppc_one_page_size {
875 uint32_t page_shift; /* Page shift (or 0) */
876 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
877 };
878
879 struct ppc_one_seg_page_size {
880 uint32_t page_shift; /* Base page shift of segment (or 0) */
881 uint32_t slb_enc; /* SLB encoding for BookS */
882 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
883 };
884
885 struct ppc_segment_page_sizes {
886 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
887 };
888
889
890 /*****************************************************************************/
891 /* The whole PowerPC CPU context */
892 #define NB_MMU_MODES 3
893
894 #define PPC_CPU_OPCODES_LEN 0x40
895 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
896
897 struct CPUPPCState {
898 /* First are the most commonly used resources
899 * during translated code execution
900 */
901 /* general purpose registers */
902 target_ulong gpr[32];
903 /* Storage for GPR MSB, used by the SPE extension */
904 target_ulong gprh[32];
905 /* LR */
906 target_ulong lr;
907 /* CTR */
908 target_ulong ctr;
909 /* condition register */
910 uint32_t crf[8];
911 #if defined(TARGET_PPC64)
912 /* CFAR */
913 target_ulong cfar;
914 #endif
915 /* XER (with SO, OV, CA split out) */
916 target_ulong xer;
917 target_ulong so;
918 target_ulong ov;
919 target_ulong ca;
920 /* Reservation address */
921 target_ulong reserve_addr;
922 /* Reservation value */
923 target_ulong reserve_val;
924 target_ulong reserve_val2;
925 /* Reservation store address */
926 target_ulong reserve_ea;
927 /* Reserved store source register and size */
928 target_ulong reserve_info;
929
930 /* Those ones are used in supervisor mode only */
931 /* machine state register */
932 target_ulong msr;
933 /* temporary general purpose registers */
934 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
935
936 /* Floating point execution context */
937 float_status fp_status;
938 /* floating point registers */
939 float64 fpr[32];
940 /* floating point status and control register */
941 target_ulong fpscr;
942
943 /* Next instruction pointer */
944 target_ulong nip;
945
946 int access_type; /* when a memory exception occurs, the access
947 type is stored here */
948
949 CPU_COMMON
950
951 /* MMU context - only relevant for full system emulation */
952 #if !defined(CONFIG_USER_ONLY)
953 #if defined(TARGET_PPC64)
954 /* PowerPC 64 SLB area */
955 ppc_slb_t slb[MAX_SLB_ENTRIES];
956 int32_t slb_nr;
957 #endif
958 /* segment registers */
959 hwaddr htab_base;
960 /* mask used to normalize hash value to PTEG index */
961 hwaddr htab_mask;
962 target_ulong sr[32];
963 /* externally stored hash table */
964 uint8_t *external_htab;
965 /* BATs */
966 uint32_t nb_BATs;
967 target_ulong DBAT[2][8];
968 target_ulong IBAT[2][8];
969 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
970 int32_t nb_tlb; /* Total number of TLB */
971 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
972 int nb_ways; /* Number of ways in the TLB set */
973 int last_way; /* Last used way used to allocate TLB in a LRU way */
974 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
975 int nb_pids; /* Number of available PID registers */
976 int tlb_type; /* Type of TLB we're dealing with */
977 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
978 /* 403 dedicated access protection registers */
979 target_ulong pb[4];
980 bool tlb_dirty; /* Set to non-zero when modifying TLB */
981 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
982 #endif
983
984 /* Other registers */
985 /* Special purpose registers */
986 target_ulong spr[1024];
987 ppc_spr_t spr_cb[1024];
988 /* Altivec registers */
989 ppc_avr_t avr[32];
990 uint32_t vscr;
991 /* VSX registers */
992 uint64_t vsr[32];
993 /* SPE registers */
994 uint64_t spe_acc;
995 uint32_t spe_fscr;
996 /* SPE and Altivec can share a status since they will never be used
997 * simultaneously */
998 float_status vec_status;
999
1000 /* Internal devices resources */
1001 /* Time base and decrementer */
1002 ppc_tb_t *tb_env;
1003 /* Device control registers */
1004 ppc_dcr_t *dcr_env;
1005
1006 int dcache_line_size;
1007 int icache_line_size;
1008
1009 /* Those resources are used during exception processing */
1010 /* CPU model definition */
1011 target_ulong msr_mask;
1012 powerpc_mmu_t mmu_model;
1013 powerpc_excp_t excp_model;
1014 powerpc_input_t bus_model;
1015 int bfd_mach;
1016 uint32_t flags;
1017 uint64_t insns_flags;
1018 uint64_t insns_flags2;
1019 #if defined(TARGET_PPC64)
1020 struct ppc_segment_page_sizes sps;
1021 bool ci_large_pages;
1022 #endif
1023
1024 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1025 uint64_t vpa_addr;
1026 uint64_t slb_shadow_addr, slb_shadow_size;
1027 uint64_t dtl_addr, dtl_size;
1028 #endif /* TARGET_PPC64 */
1029
1030 int error_code;
1031 uint32_t pending_interrupts;
1032 #if !defined(CONFIG_USER_ONLY)
1033 /* This is the IRQ controller, which is implementation dependent
1034 * and only relevant when emulating a complete machine.
1035 */
1036 uint32_t irq_input_state;
1037 void **irq_inputs;
1038 /* Exception vectors */
1039 target_ulong excp_vectors[POWERPC_EXCP_NB];
1040 target_ulong excp_prefix;
1041 target_ulong ivor_mask;
1042 target_ulong ivpr_mask;
1043 target_ulong hreset_vector;
1044 hwaddr mpic_iack;
1045 /* true when the external proxy facility mode is enabled */
1046 bool mpic_proxy;
1047 #endif
1048
1049 /* Those resources are used only during code translation */
1050 /* opcode handlers */
1051 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1052
1053 /* Those resources are used only in QEMU core */
1054 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1055 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1056 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1057
1058 /* Power management */
1059 int (*check_pow)(CPUPPCState *env);
1060
1061 #if !defined(CONFIG_USER_ONLY)
1062 void *load_info; /* Holds boot loading state. */
1063 #endif
1064
1065 /* booke timers */
1066
1067 /* Specifies bit locations of the Time Base used to signal a fixed timer
1068 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1069 *
1070 * 0 selects the least significant bit.
1071 * 63 selects the most significant bit.
1072 */
1073 uint8_t fit_period[4];
1074 uint8_t wdt_period[4];
1075
1076 /* Transactional memory state */
1077 target_ulong tm_gpr[32];
1078 ppc_avr_t tm_vsr[64];
1079 uint64_t tm_cr;
1080 uint64_t tm_lr;
1081 uint64_t tm_ctr;
1082 uint64_t tm_fpscr;
1083 uint64_t tm_amr;
1084 uint64_t tm_ppr;
1085 uint64_t tm_vrsave;
1086 uint32_t tm_vscr;
1087 uint64_t tm_dscr;
1088 uint64_t tm_tar;
1089 };
1090
1091 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1092 do { \
1093 env->fit_period[0] = (a_); \
1094 env->fit_period[1] = (b_); \
1095 env->fit_period[2] = (c_); \
1096 env->fit_period[3] = (d_); \
1097 } while (0)
1098
1099 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1100 do { \
1101 env->wdt_period[0] = (a_); \
1102 env->wdt_period[1] = (b_); \
1103 env->wdt_period[2] = (c_); \
1104 env->wdt_period[3] = (d_); \
1105 } while (0)
1106
1107 /**
1108 * PowerPCCPU:
1109 * @env: #CPUPPCState
1110 * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
1111 * @max_compat: Maximal supported logical PVR from the command line
1112 * @cpu_version: Current logical PVR, zero if in "raw" mode
1113 *
1114 * A PowerPC CPU.
1115 */
1116 struct PowerPCCPU {
1117 /*< private >*/
1118 CPUState parent_obj;
1119 /*< public >*/
1120
1121 CPUPPCState env;
1122 int cpu_dt_id;
1123 uint32_t max_compat;
1124 uint32_t cpu_version;
1125 };
1126
1127 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1128 {
1129 return container_of(env, PowerPCCPU, env);
1130 }
1131
1132 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1133
1134 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1135
1136 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1137 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1138
1139 void ppc_cpu_do_interrupt(CPUState *cpu);
1140 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1141 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1142 int flags);
1143 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1144 fprintf_function cpu_fprintf, int flags);
1145 int ppc_cpu_get_monitor_def(CPUState *cs, const char *name,
1146 uint64_t *pval);
1147 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1148 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1149 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1150 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1151 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1152 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1153 int cpuid, void *opaque);
1154 #ifndef CONFIG_USER_ONLY
1155 void ppc_cpu_do_system_reset(CPUState *cs);
1156 extern const struct VMStateDescription vmstate_ppc_cpu;
1157 #endif
1158
1159 /*****************************************************************************/
1160 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1161 void ppc_translate_init(void);
1162 void gen_update_current_nip(void *opaque);
1163 int cpu_ppc_exec (CPUState *s);
1164 /* you can call this signal handler from your SIGBUS and SIGSEGV
1165 signal handlers to inform the virtual CPU of exceptions. non zero
1166 is returned if the signal was handled by the virtual CPU. */
1167 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1168 void *puc);
1169 #if defined(CONFIG_USER_ONLY)
1170 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1171 int mmu_idx);
1172 #endif
1173
1174 #if !defined(CONFIG_USER_ONLY)
1175 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1176 #endif /* !defined(CONFIG_USER_ONLY) */
1177 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1178
1179 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1180 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1181 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
1182
1183 /* Time-base and decrementer management */
1184 #ifndef NO_CPU_IO_DEFS
1185 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1186 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1187 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1188 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1189 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1190 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1191 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1192 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1193 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1194 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1195 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1196 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1197 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1198 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1199 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1200 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1201 #if !defined(CONFIG_USER_ONLY)
1202 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1203 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1204 target_ulong load_40x_pit (CPUPPCState *env);
1205 void store_40x_pit (CPUPPCState *env, target_ulong val);
1206 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1207 void store_40x_sler (CPUPPCState *env, uint32_t val);
1208 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1209 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1210 void ppc_tlb_invalidate_all (CPUPPCState *env);
1211 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1212 void cpu_ppc_set_papr(PowerPCCPU *cpu);
1213 #endif
1214 #endif
1215
1216 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1217
1218 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1219 {
1220 uint64_t gprv;
1221
1222 gprv = env->gpr[gprn];
1223 if (env->flags & POWERPC_FLAG_SPE) {
1224 /* If the CPU implements the SPE extension, we have to get the
1225 * high bits of the GPR from the gprh storage area
1226 */
1227 gprv &= 0xFFFFFFFFULL;
1228 gprv |= (uint64_t)env->gprh[gprn] << 32;
1229 }
1230
1231 return gprv;
1232 }
1233
1234 /* Device control registers */
1235 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1236 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1237
1238 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1239
1240 #define cpu_exec cpu_ppc_exec
1241 #define cpu_signal_handler cpu_ppc_signal_handler
1242 #define cpu_list ppc_cpu_list
1243
1244 /* MMU modes definitions */
1245 #define MMU_MODE0_SUFFIX _user
1246 #define MMU_MODE1_SUFFIX _kernel
1247 #define MMU_MODE2_SUFFIX _hypv
1248 #define MMU_USER_IDX 0
1249 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1250 {
1251 return env->mmu_idx;
1252 }
1253
1254 #include "exec/cpu-all.h"
1255
1256 /*****************************************************************************/
1257 /* CRF definitions */
1258 #define CRF_LT 3
1259 #define CRF_GT 2
1260 #define CRF_EQ 1
1261 #define CRF_SO 0
1262 #define CRF_CH (1 << CRF_LT)
1263 #define CRF_CL (1 << CRF_GT)
1264 #define CRF_CH_OR_CL (1 << CRF_EQ)
1265 #define CRF_CH_AND_CL (1 << CRF_SO)
1266
1267 /* XER definitions */
1268 #define XER_SO 31
1269 #define XER_OV 30
1270 #define XER_CA 29
1271 #define XER_CMP 8
1272 #define XER_BC 0
1273 #define xer_so (env->so)
1274 #define xer_ov (env->ov)
1275 #define xer_ca (env->ca)
1276 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1277 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1278
1279 /* SPR definitions */
1280 #define SPR_MQ (0x000)
1281 #define SPR_XER (0x001)
1282 #define SPR_601_VRTCU (0x004)
1283 #define SPR_601_VRTCL (0x005)
1284 #define SPR_601_UDECR (0x006)
1285 #define SPR_LR (0x008)
1286 #define SPR_CTR (0x009)
1287 #define SPR_UAMR (0x00C)
1288 #define SPR_DSCR (0x011)
1289 #define SPR_DSISR (0x012)
1290 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1291 #define SPR_601_RTCU (0x014)
1292 #define SPR_601_RTCL (0x015)
1293 #define SPR_DECR (0x016)
1294 #define SPR_SDR1 (0x019)
1295 #define SPR_SRR0 (0x01A)
1296 #define SPR_SRR1 (0x01B)
1297 #define SPR_CFAR (0x01C)
1298 #define SPR_AMR (0x01D)
1299 #define SPR_ACOP (0x01F)
1300 #define SPR_BOOKE_PID (0x030)
1301 #define SPR_BOOKS_PID (0x030)
1302 #define SPR_BOOKE_DECAR (0x036)
1303 #define SPR_BOOKE_CSRR0 (0x03A)
1304 #define SPR_BOOKE_CSRR1 (0x03B)
1305 #define SPR_BOOKE_DEAR (0x03D)
1306 #define SPR_IAMR (0x03D)
1307 #define SPR_BOOKE_ESR (0x03E)
1308 #define SPR_BOOKE_IVPR (0x03F)
1309 #define SPR_MPC_EIE (0x050)
1310 #define SPR_MPC_EID (0x051)
1311 #define SPR_MPC_NRI (0x052)
1312 #define SPR_TFHAR (0x080)
1313 #define SPR_TFIAR (0x081)
1314 #define SPR_TEXASR (0x082)
1315 #define SPR_TEXASRU (0x083)
1316 #define SPR_UCTRL (0x088)
1317 #define SPR_MPC_CMPA (0x090)
1318 #define SPR_MPC_CMPB (0x091)
1319 #define SPR_MPC_CMPC (0x092)
1320 #define SPR_MPC_CMPD (0x093)
1321 #define SPR_MPC_ECR (0x094)
1322 #define SPR_MPC_DER (0x095)
1323 #define SPR_MPC_COUNTA (0x096)
1324 #define SPR_MPC_COUNTB (0x097)
1325 #define SPR_CTRL (0x098)
1326 #define SPR_MPC_CMPE (0x098)
1327 #define SPR_MPC_CMPF (0x099)
1328 #define SPR_FSCR (0x099)
1329 #define SPR_MPC_CMPG (0x09A)
1330 #define SPR_MPC_CMPH (0x09B)
1331 #define SPR_MPC_LCTRL1 (0x09C)
1332 #define SPR_MPC_LCTRL2 (0x09D)
1333 #define SPR_UAMOR (0x09D)
1334 #define SPR_MPC_ICTRL (0x09E)
1335 #define SPR_MPC_BAR (0x09F)
1336 #define SPR_PSPB (0x09F)
1337 #define SPR_DAWR (0x0B4)
1338 #define SPR_RPR (0x0BA)
1339 #define SPR_CIABR (0x0BB)
1340 #define SPR_DAWRX (0x0BC)
1341 #define SPR_HFSCR (0x0BE)
1342 #define SPR_VRSAVE (0x100)
1343 #define SPR_USPRG0 (0x100)
1344 #define SPR_USPRG1 (0x101)
1345 #define SPR_USPRG2 (0x102)
1346 #define SPR_USPRG3 (0x103)
1347 #define SPR_USPRG4 (0x104)
1348 #define SPR_USPRG5 (0x105)
1349 #define SPR_USPRG6 (0x106)
1350 #define SPR_USPRG7 (0x107)
1351 #define SPR_VTBL (0x10C)
1352 #define SPR_VTBU (0x10D)
1353 #define SPR_SPRG0 (0x110)
1354 #define SPR_SPRG1 (0x111)
1355 #define SPR_SPRG2 (0x112)
1356 #define SPR_SPRG3 (0x113)
1357 #define SPR_SPRG4 (0x114)
1358 #define SPR_SCOMC (0x114)
1359 #define SPR_SPRG5 (0x115)
1360 #define SPR_SCOMD (0x115)
1361 #define SPR_SPRG6 (0x116)
1362 #define SPR_SPRG7 (0x117)
1363 #define SPR_ASR (0x118)
1364 #define SPR_EAR (0x11A)
1365 #define SPR_TBL (0x11C)
1366 #define SPR_TBU (0x11D)
1367 #define SPR_TBU40 (0x11E)
1368 #define SPR_SVR (0x11E)
1369 #define SPR_BOOKE_PIR (0x11E)
1370 #define SPR_PVR (0x11F)
1371 #define SPR_HSPRG0 (0x130)
1372 #define SPR_BOOKE_DBSR (0x130)
1373 #define SPR_HSPRG1 (0x131)
1374 #define SPR_HDSISR (0x132)
1375 #define SPR_HDAR (0x133)
1376 #define SPR_BOOKE_EPCR (0x133)
1377 #define SPR_SPURR (0x134)
1378 #define SPR_BOOKE_DBCR0 (0x134)
1379 #define SPR_IBCR (0x135)
1380 #define SPR_PURR (0x135)
1381 #define SPR_BOOKE_DBCR1 (0x135)
1382 #define SPR_DBCR (0x136)
1383 #define SPR_HDEC (0x136)
1384 #define SPR_BOOKE_DBCR2 (0x136)
1385 #define SPR_HIOR (0x137)
1386 #define SPR_MBAR (0x137)
1387 #define SPR_RMOR (0x138)
1388 #define SPR_BOOKE_IAC1 (0x138)
1389 #define SPR_HRMOR (0x139)
1390 #define SPR_BOOKE_IAC2 (0x139)
1391 #define SPR_HSRR0 (0x13A)
1392 #define SPR_BOOKE_IAC3 (0x13A)
1393 #define SPR_HSRR1 (0x13B)
1394 #define SPR_BOOKE_IAC4 (0x13B)
1395 #define SPR_BOOKE_DAC1 (0x13C)
1396 #define SPR_MMCRH (0x13C)
1397 #define SPR_DABR2 (0x13D)
1398 #define SPR_BOOKE_DAC2 (0x13D)
1399 #define SPR_TFMR (0x13D)
1400 #define SPR_BOOKE_DVC1 (0x13E)
1401 #define SPR_LPCR (0x13E)
1402 #define SPR_BOOKE_DVC2 (0x13F)
1403 #define SPR_LPIDR (0x13F)
1404 #define SPR_BOOKE_TSR (0x150)
1405 #define SPR_HMER (0x150)
1406 #define SPR_HMEER (0x151)
1407 #define SPR_PCR (0x152)
1408 #define SPR_BOOKE_LPIDR (0x152)
1409 #define SPR_BOOKE_TCR (0x154)
1410 #define SPR_BOOKE_TLB0PS (0x158)
1411 #define SPR_BOOKE_TLB1PS (0x159)
1412 #define SPR_BOOKE_TLB2PS (0x15A)
1413 #define SPR_BOOKE_TLB3PS (0x15B)
1414 #define SPR_AMOR (0x15D)
1415 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1416 #define SPR_BOOKE_IVOR0 (0x190)
1417 #define SPR_BOOKE_IVOR1 (0x191)
1418 #define SPR_BOOKE_IVOR2 (0x192)
1419 #define SPR_BOOKE_IVOR3 (0x193)
1420 #define SPR_BOOKE_IVOR4 (0x194)
1421 #define SPR_BOOKE_IVOR5 (0x195)
1422 #define SPR_BOOKE_IVOR6 (0x196)
1423 #define SPR_BOOKE_IVOR7 (0x197)
1424 #define SPR_BOOKE_IVOR8 (0x198)
1425 #define SPR_BOOKE_IVOR9 (0x199)
1426 #define SPR_BOOKE_IVOR10 (0x19A)
1427 #define SPR_BOOKE_IVOR11 (0x19B)
1428 #define SPR_BOOKE_IVOR12 (0x19C)
1429 #define SPR_BOOKE_IVOR13 (0x19D)
1430 #define SPR_BOOKE_IVOR14 (0x19E)
1431 #define SPR_BOOKE_IVOR15 (0x19F)
1432 #define SPR_BOOKE_IVOR38 (0x1B0)
1433 #define SPR_BOOKE_IVOR39 (0x1B1)
1434 #define SPR_BOOKE_IVOR40 (0x1B2)
1435 #define SPR_BOOKE_IVOR41 (0x1B3)
1436 #define SPR_BOOKE_IVOR42 (0x1B4)
1437 #define SPR_BOOKE_GIVOR2 (0x1B8)
1438 #define SPR_BOOKE_GIVOR3 (0x1B9)
1439 #define SPR_BOOKE_GIVOR4 (0x1BA)
1440 #define SPR_BOOKE_GIVOR8 (0x1BB)
1441 #define SPR_BOOKE_GIVOR13 (0x1BC)
1442 #define SPR_BOOKE_GIVOR14 (0x1BD)
1443 #define SPR_TIR (0x1BE)
1444 #define SPR_BOOKE_SPEFSCR (0x200)
1445 #define SPR_Exxx_BBEAR (0x201)
1446 #define SPR_Exxx_BBTAR (0x202)
1447 #define SPR_Exxx_L1CFG0 (0x203)
1448 #define SPR_Exxx_L1CFG1 (0x204)
1449 #define SPR_Exxx_NPIDR (0x205)
1450 #define SPR_ATBL (0x20E)
1451 #define SPR_ATBU (0x20F)
1452 #define SPR_IBAT0U (0x210)
1453 #define SPR_BOOKE_IVOR32 (0x210)
1454 #define SPR_RCPU_MI_GRA (0x210)
1455 #define SPR_IBAT0L (0x211)
1456 #define SPR_BOOKE_IVOR33 (0x211)
1457 #define SPR_IBAT1U (0x212)
1458 #define SPR_BOOKE_IVOR34 (0x212)
1459 #define SPR_IBAT1L (0x213)
1460 #define SPR_BOOKE_IVOR35 (0x213)
1461 #define SPR_IBAT2U (0x214)
1462 #define SPR_BOOKE_IVOR36 (0x214)
1463 #define SPR_IBAT2L (0x215)
1464 #define SPR_BOOKE_IVOR37 (0x215)
1465 #define SPR_IBAT3U (0x216)
1466 #define SPR_IBAT3L (0x217)
1467 #define SPR_DBAT0U (0x218)
1468 #define SPR_RCPU_L2U_GRA (0x218)
1469 #define SPR_DBAT0L (0x219)
1470 #define SPR_DBAT1U (0x21A)
1471 #define SPR_DBAT1L (0x21B)
1472 #define SPR_DBAT2U (0x21C)
1473 #define SPR_DBAT2L (0x21D)
1474 #define SPR_DBAT3U (0x21E)
1475 #define SPR_DBAT3L (0x21F)
1476 #define SPR_IBAT4U (0x230)
1477 #define SPR_RPCU_BBCMCR (0x230)
1478 #define SPR_MPC_IC_CST (0x230)
1479 #define SPR_Exxx_CTXCR (0x230)
1480 #define SPR_IBAT4L (0x231)
1481 #define SPR_MPC_IC_ADR (0x231)
1482 #define SPR_Exxx_DBCR3 (0x231)
1483 #define SPR_IBAT5U (0x232)
1484 #define SPR_MPC_IC_DAT (0x232)
1485 #define SPR_Exxx_DBCNT (0x232)
1486 #define SPR_IBAT5L (0x233)
1487 #define SPR_IBAT6U (0x234)
1488 #define SPR_IBAT6L (0x235)
1489 #define SPR_IBAT7U (0x236)
1490 #define SPR_IBAT7L (0x237)
1491 #define SPR_DBAT4U (0x238)
1492 #define SPR_RCPU_L2U_MCR (0x238)
1493 #define SPR_MPC_DC_CST (0x238)
1494 #define SPR_Exxx_ALTCTXCR (0x238)
1495 #define SPR_DBAT4L (0x239)
1496 #define SPR_MPC_DC_ADR (0x239)
1497 #define SPR_DBAT5U (0x23A)
1498 #define SPR_BOOKE_MCSRR0 (0x23A)
1499 #define SPR_MPC_DC_DAT (0x23A)
1500 #define SPR_DBAT5L (0x23B)
1501 #define SPR_BOOKE_MCSRR1 (0x23B)
1502 #define SPR_DBAT6U (0x23C)
1503 #define SPR_BOOKE_MCSR (0x23C)
1504 #define SPR_DBAT6L (0x23D)
1505 #define SPR_Exxx_MCAR (0x23D)
1506 #define SPR_DBAT7U (0x23E)
1507 #define SPR_BOOKE_DSRR0 (0x23E)
1508 #define SPR_DBAT7L (0x23F)
1509 #define SPR_BOOKE_DSRR1 (0x23F)
1510 #define SPR_BOOKE_SPRG8 (0x25C)
1511 #define SPR_BOOKE_SPRG9 (0x25D)
1512 #define SPR_BOOKE_MAS0 (0x270)
1513 #define SPR_BOOKE_MAS1 (0x271)
1514 #define SPR_BOOKE_MAS2 (0x272)
1515 #define SPR_BOOKE_MAS3 (0x273)
1516 #define SPR_BOOKE_MAS4 (0x274)
1517 #define SPR_BOOKE_MAS5 (0x275)
1518 #define SPR_BOOKE_MAS6 (0x276)
1519 #define SPR_BOOKE_PID1 (0x279)
1520 #define SPR_BOOKE_PID2 (0x27A)
1521 #define SPR_MPC_DPDR (0x280)
1522 #define SPR_MPC_IMMR (0x288)
1523 #define SPR_BOOKE_TLB0CFG (0x2B0)
1524 #define SPR_BOOKE_TLB1CFG (0x2B1)
1525 #define SPR_BOOKE_TLB2CFG (0x2B2)
1526 #define SPR_BOOKE_TLB3CFG (0x2B3)
1527 #define SPR_BOOKE_EPR (0x2BE)
1528 #define SPR_PERF0 (0x300)
1529 #define SPR_RCPU_MI_RBA0 (0x300)
1530 #define SPR_MPC_MI_CTR (0x300)
1531 #define SPR_POWER_USIER (0x300)
1532 #define SPR_PERF1 (0x301)
1533 #define SPR_RCPU_MI_RBA1 (0x301)
1534 #define SPR_POWER_UMMCR2 (0x301)
1535 #define SPR_PERF2 (0x302)
1536 #define SPR_RCPU_MI_RBA2 (0x302)
1537 #define SPR_MPC_MI_AP (0x302)
1538 #define SPR_POWER_UMMCRA (0x302)
1539 #define SPR_PERF3 (0x303)
1540 #define SPR_RCPU_MI_RBA3 (0x303)
1541 #define SPR_MPC_MI_EPN (0x303)
1542 #define SPR_POWER_UPMC1 (0x303)
1543 #define SPR_PERF4 (0x304)
1544 #define SPR_POWER_UPMC2 (0x304)
1545 #define SPR_PERF5 (0x305)
1546 #define SPR_MPC_MI_TWC (0x305)
1547 #define SPR_POWER_UPMC3 (0x305)
1548 #define SPR_PERF6 (0x306)
1549 #define SPR_MPC_MI_RPN (0x306)
1550 #define SPR_POWER_UPMC4 (0x306)
1551 #define SPR_PERF7 (0x307)
1552 #define SPR_POWER_UPMC5 (0x307)
1553 #define SPR_PERF8 (0x308)
1554 #define SPR_RCPU_L2U_RBA0 (0x308)
1555 #define SPR_MPC_MD_CTR (0x308)
1556 #define SPR_POWER_UPMC6 (0x308)
1557 #define SPR_PERF9 (0x309)
1558 #define SPR_RCPU_L2U_RBA1 (0x309)
1559 #define SPR_MPC_MD_CASID (0x309)
1560 #define SPR_970_UPMC7 (0X309)
1561 #define SPR_PERFA (0x30A)
1562 #define SPR_RCPU_L2U_RBA2 (0x30A)
1563 #define SPR_MPC_MD_AP (0x30A)
1564 #define SPR_970_UPMC8 (0X30A)
1565 #define SPR_PERFB (0x30B)
1566 #define SPR_RCPU_L2U_RBA3 (0x30B)
1567 #define SPR_MPC_MD_EPN (0x30B)
1568 #define SPR_POWER_UMMCR0 (0X30B)
1569 #define SPR_PERFC (0x30C)
1570 #define SPR_MPC_MD_TWB (0x30C)
1571 #define SPR_POWER_USIAR (0X30C)
1572 #define SPR_PERFD (0x30D)
1573 #define SPR_MPC_MD_TWC (0x30D)
1574 #define SPR_POWER_USDAR (0X30D)
1575 #define SPR_PERFE (0x30E)
1576 #define SPR_MPC_MD_RPN (0x30E)
1577 #define SPR_POWER_UMMCR1 (0X30E)
1578 #define SPR_PERFF (0x30F)
1579 #define SPR_MPC_MD_TW (0x30F)
1580 #define SPR_UPERF0 (0x310)
1581 #define SPR_POWER_SIER (0x310)
1582 #define SPR_UPERF1 (0x311)
1583 #define SPR_POWER_MMCR2 (0x311)
1584 #define SPR_UPERF2 (0x312)
1585 #define SPR_POWER_MMCRA (0X312)
1586 #define SPR_UPERF3 (0x313)
1587 #define SPR_POWER_PMC1 (0X313)
1588 #define SPR_UPERF4 (0x314)
1589 #define SPR_POWER_PMC2 (0X314)
1590 #define SPR_UPERF5 (0x315)
1591 #define SPR_POWER_PMC3 (0X315)
1592 #define SPR_UPERF6 (0x316)
1593 #define SPR_POWER_PMC4 (0X316)
1594 #define SPR_UPERF7 (0x317)
1595 #define SPR_POWER_PMC5 (0X317)
1596 #define SPR_UPERF8 (0x318)
1597 #define SPR_POWER_PMC6 (0X318)
1598 #define SPR_UPERF9 (0x319)
1599 #define SPR_970_PMC7 (0X319)
1600 #define SPR_UPERFA (0x31A)
1601 #define SPR_970_PMC8 (0X31A)
1602 #define SPR_UPERFB (0x31B)
1603 #define SPR_POWER_MMCR0 (0X31B)
1604 #define SPR_UPERFC (0x31C)
1605 #define SPR_POWER_SIAR (0X31C)
1606 #define SPR_UPERFD (0x31D)
1607 #define SPR_POWER_SDAR (0X31D)
1608 #define SPR_UPERFE (0x31E)
1609 #define SPR_POWER_MMCR1 (0X31E)
1610 #define SPR_UPERFF (0x31F)
1611 #define SPR_RCPU_MI_RA0 (0x320)
1612 #define SPR_MPC_MI_DBCAM (0x320)
1613 #define SPR_BESCRS (0x320)
1614 #define SPR_RCPU_MI_RA1 (0x321)
1615 #define SPR_MPC_MI_DBRAM0 (0x321)
1616 #define SPR_BESCRSU (0x321)
1617 #define SPR_RCPU_MI_RA2 (0x322)
1618 #define SPR_MPC_MI_DBRAM1 (0x322)
1619 #define SPR_BESCRR (0x322)
1620 #define SPR_RCPU_MI_RA3 (0x323)
1621 #define SPR_BESCRRU (0x323)
1622 #define SPR_EBBHR (0x324)
1623 #define SPR_EBBRR (0x325)
1624 #define SPR_BESCR (0x326)
1625 #define SPR_RCPU_L2U_RA0 (0x328)
1626 #define SPR_MPC_MD_DBCAM (0x328)
1627 #define SPR_RCPU_L2U_RA1 (0x329)
1628 #define SPR_MPC_MD_DBRAM0 (0x329)
1629 #define SPR_RCPU_L2U_RA2 (0x32A)
1630 #define SPR_MPC_MD_DBRAM1 (0x32A)
1631 #define SPR_RCPU_L2U_RA3 (0x32B)
1632 #define SPR_TAR (0x32F)
1633 #define SPR_IC (0x350)
1634 #define SPR_VTB (0x351)
1635 #define SPR_MMCRC (0x353)
1636 #define SPR_440_INV0 (0x370)
1637 #define SPR_440_INV1 (0x371)
1638 #define SPR_440_INV2 (0x372)
1639 #define SPR_440_INV3 (0x373)
1640 #define SPR_440_ITV0 (0x374)
1641 #define SPR_440_ITV1 (0x375)
1642 #define SPR_440_ITV2 (0x376)
1643 #define SPR_440_ITV3 (0x377)
1644 #define SPR_440_CCR1 (0x378)
1645 #define SPR_TACR (0x378)
1646 #define SPR_TCSCR (0x379)
1647 #define SPR_CSIGR (0x37a)
1648 #define SPR_DCRIPR (0x37B)
1649 #define SPR_POWER_SPMC1 (0x37C)
1650 #define SPR_POWER_SPMC2 (0x37D)
1651 #define SPR_POWER_MMCRS (0x37E)
1652 #define SPR_WORT (0x37F)
1653 #define SPR_PPR (0x380)
1654 #define SPR_750_GQR0 (0x390)
1655 #define SPR_440_DNV0 (0x390)
1656 #define SPR_750_GQR1 (0x391)
1657 #define SPR_440_DNV1 (0x391)
1658 #define SPR_750_GQR2 (0x392)
1659 #define SPR_440_DNV2 (0x392)
1660 #define SPR_750_GQR3 (0x393)
1661 #define SPR_440_DNV3 (0x393)
1662 #define SPR_750_GQR4 (0x394)
1663 #define SPR_440_DTV0 (0x394)
1664 #define SPR_750_GQR5 (0x395)
1665 #define SPR_440_DTV1 (0x395)
1666 #define SPR_750_GQR6 (0x396)
1667 #define SPR_440_DTV2 (0x396)
1668 #define SPR_750_GQR7 (0x397)
1669 #define SPR_440_DTV3 (0x397)
1670 #define SPR_750_THRM4 (0x398)
1671 #define SPR_750CL_HID2 (0x398)
1672 #define SPR_440_DVLIM (0x398)
1673 #define SPR_750_WPAR (0x399)
1674 #define SPR_440_IVLIM (0x399)
1675 #define SPR_TSCR (0x399)
1676 #define SPR_750_DMAU (0x39A)
1677 #define SPR_750_DMAL (0x39B)
1678 #define SPR_440_RSTCFG (0x39B)
1679 #define SPR_BOOKE_DCDBTRL (0x39C)
1680 #define SPR_BOOKE_DCDBTRH (0x39D)
1681 #define SPR_BOOKE_ICDBTRL (0x39E)
1682 #define SPR_BOOKE_ICDBTRH (0x39F)
1683 #define SPR_74XX_UMMCR2 (0x3A0)
1684 #define SPR_7XX_UPMC5 (0x3A1)
1685 #define SPR_7XX_UPMC6 (0x3A2)
1686 #define SPR_UBAMR (0x3A7)
1687 #define SPR_7XX_UMMCR0 (0x3A8)
1688 #define SPR_7XX_UPMC1 (0x3A9)
1689 #define SPR_7XX_UPMC2 (0x3AA)
1690 #define SPR_7XX_USIAR (0x3AB)
1691 #define SPR_7XX_UMMCR1 (0x3AC)
1692 #define SPR_7XX_UPMC3 (0x3AD)
1693 #define SPR_7XX_UPMC4 (0x3AE)
1694 #define SPR_USDA (0x3AF)
1695 #define SPR_40x_ZPR (0x3B0)
1696 #define SPR_BOOKE_MAS7 (0x3B0)
1697 #define SPR_74XX_MMCR2 (0x3B0)
1698 #define SPR_7XX_PMC5 (0x3B1)
1699 #define SPR_40x_PID (0x3B1)
1700 #define SPR_7XX_PMC6 (0x3B2)
1701 #define SPR_440_MMUCR (0x3B2)
1702 #define SPR_4xx_CCR0 (0x3B3)
1703 #define SPR_BOOKE_EPLC (0x3B3)
1704 #define SPR_405_IAC3 (0x3B4)
1705 #define SPR_BOOKE_EPSC (0x3B4)
1706 #define SPR_405_IAC4 (0x3B5)
1707 #define SPR_405_DVC1 (0x3B6)
1708 #define SPR_405_DVC2 (0x3B7)
1709 #define SPR_BAMR (0x3B7)
1710 #define SPR_7XX_MMCR0 (0x3B8)
1711 #define SPR_7XX_PMC1 (0x3B9)
1712 #define SPR_40x_SGR (0x3B9)
1713 #define SPR_7XX_PMC2 (0x3BA)
1714 #define SPR_40x_DCWR (0x3BA)
1715 #define SPR_7XX_SIAR (0x3BB)
1716 #define SPR_405_SLER (0x3BB)
1717 #define SPR_7XX_MMCR1 (0x3BC)
1718 #define SPR_405_SU0R (0x3BC)
1719 #define SPR_401_SKR (0x3BC)
1720 #define SPR_7XX_PMC3 (0x3BD)
1721 #define SPR_405_DBCR1 (0x3BD)
1722 #define SPR_7XX_PMC4 (0x3BE)
1723 #define SPR_SDA (0x3BF)
1724 #define SPR_403_VTBL (0x3CC)
1725 #define SPR_403_VTBU (0x3CD)
1726 #define SPR_DMISS (0x3D0)
1727 #define SPR_DCMP (0x3D1)
1728 #define SPR_HASH1 (0x3D2)
1729 #define SPR_HASH2 (0x3D3)
1730 #define SPR_BOOKE_ICDBDR (0x3D3)
1731 #define SPR_TLBMISS (0x3D4)
1732 #define SPR_IMISS (0x3D4)
1733 #define SPR_40x_ESR (0x3D4)
1734 #define SPR_PTEHI (0x3D5)
1735 #define SPR_ICMP (0x3D5)
1736 #define SPR_40x_DEAR (0x3D5)
1737 #define SPR_PTELO (0x3D6)
1738 #define SPR_RPA (0x3D6)
1739 #define SPR_40x_EVPR (0x3D6)
1740 #define SPR_L3PM (0x3D7)
1741 #define SPR_403_CDBCR (0x3D7)
1742 #define SPR_L3ITCR0 (0x3D8)
1743 #define SPR_TCR (0x3D8)
1744 #define SPR_40x_TSR (0x3D8)
1745 #define SPR_IBR (0x3DA)
1746 #define SPR_40x_TCR (0x3DA)
1747 #define SPR_ESASRR (0x3DB)
1748 #define SPR_40x_PIT (0x3DB)
1749 #define SPR_403_TBL (0x3DC)
1750 #define SPR_403_TBU (0x3DD)
1751 #define SPR_SEBR (0x3DE)
1752 #define SPR_40x_SRR2 (0x3DE)
1753 #define SPR_SER (0x3DF)
1754 #define SPR_40x_SRR3 (0x3DF)
1755 #define SPR_L3OHCR (0x3E8)
1756 #define SPR_L3ITCR1 (0x3E9)
1757 #define SPR_L3ITCR2 (0x3EA)
1758 #define SPR_L3ITCR3 (0x3EB)
1759 #define SPR_HID0 (0x3F0)
1760 #define SPR_40x_DBSR (0x3F0)
1761 #define SPR_HID1 (0x3F1)
1762 #define SPR_IABR (0x3F2)
1763 #define SPR_40x_DBCR0 (0x3F2)
1764 #define SPR_601_HID2 (0x3F2)
1765 #define SPR_Exxx_L1CSR0 (0x3F2)
1766 #define SPR_ICTRL (0x3F3)
1767 #define SPR_HID2 (0x3F3)
1768 #define SPR_750CL_HID4 (0x3F3)
1769 #define SPR_Exxx_L1CSR1 (0x3F3)
1770 #define SPR_440_DBDR (0x3F3)
1771 #define SPR_LDSTDB (0x3F4)
1772 #define SPR_750_TDCL (0x3F4)
1773 #define SPR_40x_IAC1 (0x3F4)
1774 #define SPR_MMUCSR0 (0x3F4)
1775 #define SPR_970_HID4 (0x3F4)
1776 #define SPR_DABR (0x3F5)
1777 #define DABR_MASK (~(target_ulong)0x7)
1778 #define SPR_Exxx_BUCSR (0x3F5)
1779 #define SPR_40x_IAC2 (0x3F5)
1780 #define SPR_601_HID5 (0x3F5)
1781 #define SPR_40x_DAC1 (0x3F6)
1782 #define SPR_MSSCR0 (0x3F6)
1783 #define SPR_970_HID5 (0x3F6)
1784 #define SPR_MSSSR0 (0x3F7)
1785 #define SPR_MSSCR1 (0x3F7)
1786 #define SPR_DABRX (0x3F7)
1787 #define SPR_40x_DAC2 (0x3F7)
1788 #define SPR_MMUCFG (0x3F7)
1789 #define SPR_LDSTCR (0x3F8)
1790 #define SPR_L2PMCR (0x3F8)
1791 #define SPR_750FX_HID2 (0x3F8)
1792 #define SPR_Exxx_L1FINV0 (0x3F8)
1793 #define SPR_L2CR (0x3F9)
1794 #define SPR_L3CR (0x3FA)
1795 #define SPR_750_TDCH (0x3FA)
1796 #define SPR_IABR2 (0x3FA)
1797 #define SPR_40x_DCCR (0x3FA)
1798 #define SPR_ICTC (0x3FB)
1799 #define SPR_40x_ICCR (0x3FB)
1800 #define SPR_THRM1 (0x3FC)
1801 #define SPR_403_PBL1 (0x3FC)
1802 #define SPR_SP (0x3FD)
1803 #define SPR_THRM2 (0x3FD)
1804 #define SPR_403_PBU1 (0x3FD)
1805 #define SPR_604_HID13 (0x3FD)
1806 #define SPR_LT (0x3FE)
1807 #define SPR_THRM3 (0x3FE)
1808 #define SPR_RCPU_FPECR (0x3FE)
1809 #define SPR_403_PBL2 (0x3FE)
1810 #define SPR_PIR (0x3FF)
1811 #define SPR_403_PBU2 (0x3FF)
1812 #define SPR_601_HID15 (0x3FF)
1813 #define SPR_604_HID15 (0x3FF)
1814 #define SPR_E500_SVR (0x3FF)
1815
1816 /* Disable MAS Interrupt Updates for Hypervisor */
1817 #define EPCR_DMIUH (1 << 22)
1818 /* Disable Guest TLB Management Instructions */
1819 #define EPCR_DGTMI (1 << 23)
1820 /* Guest Interrupt Computation Mode */
1821 #define EPCR_GICM (1 << 24)
1822 /* Interrupt Computation Mode */
1823 #define EPCR_ICM (1 << 25)
1824 /* Disable Embedded Hypervisor Debug */
1825 #define EPCR_DUVD (1 << 26)
1826 /* Instruction Storage Interrupt Directed to Guest State */
1827 #define EPCR_ISIGS (1 << 27)
1828 /* Data Storage Interrupt Directed to Guest State */
1829 #define EPCR_DSIGS (1 << 28)
1830 /* Instruction TLB Error Interrupt Directed to Guest State */
1831 #define EPCR_ITLBGS (1 << 29)
1832 /* Data TLB Error Interrupt Directed to Guest State */
1833 #define EPCR_DTLBGS (1 << 30)
1834 /* External Input Interrupt Directed to Guest State */
1835 #define EPCR_EXTGS (1 << 31)
1836
1837 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1838 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1839 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1840 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1841 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1842
1843 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1844 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1845 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1846 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1847 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1848
1849 /* HID0 bits */
1850 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1851 #define HID0_DOZE (1 << 23) /* pre-2.06 */
1852 #define HID0_NAP (1 << 22) /* pre-2.06 */
1853 #define HID0_HILE (1ull << (63 - 19)) /* POWER8 */
1854
1855 /*****************************************************************************/
1856 /* PowerPC Instructions types definitions */
1857 enum {
1858 PPC_NONE = 0x0000000000000000ULL,
1859 /* PowerPC base instructions set */
1860 PPC_INSNS_BASE = 0x0000000000000001ULL,
1861 /* integer operations instructions */
1862 #define PPC_INTEGER PPC_INSNS_BASE
1863 /* flow control instructions */
1864 #define PPC_FLOW PPC_INSNS_BASE
1865 /* virtual memory instructions */
1866 #define PPC_MEM PPC_INSNS_BASE
1867 /* ld/st with reservation instructions */
1868 #define PPC_RES PPC_INSNS_BASE
1869 /* spr/msr access instructions */
1870 #define PPC_MISC PPC_INSNS_BASE
1871 /* Deprecated instruction sets */
1872 /* Original POWER instruction set */
1873 PPC_POWER = 0x0000000000000002ULL,
1874 /* POWER2 instruction set extension */
1875 PPC_POWER2 = 0x0000000000000004ULL,
1876 /* Power RTC support */
1877 PPC_POWER_RTC = 0x0000000000000008ULL,
1878 /* Power-to-PowerPC bridge (601) */
1879 PPC_POWER_BR = 0x0000000000000010ULL,
1880 /* 64 bits PowerPC instruction set */
1881 PPC_64B = 0x0000000000000020ULL,
1882 /* New 64 bits extensions (PowerPC 2.0x) */
1883 PPC_64BX = 0x0000000000000040ULL,
1884 /* 64 bits hypervisor extensions */
1885 PPC_64H = 0x0000000000000080ULL,
1886 /* New wait instruction (PowerPC 2.0x) */
1887 PPC_WAIT = 0x0000000000000100ULL,
1888 /* Time base mftb instruction */
1889 PPC_MFTB = 0x0000000000000200ULL,
1890
1891 /* Fixed-point unit extensions */
1892 /* PowerPC 602 specific */
1893 PPC_602_SPEC = 0x0000000000000400ULL,
1894 /* isel instruction */
1895 PPC_ISEL = 0x0000000000000800ULL,
1896 /* popcntb instruction */
1897 PPC_POPCNTB = 0x0000000000001000ULL,
1898 /* string load / store */
1899 PPC_STRING = 0x0000000000002000ULL,
1900
1901 /* Floating-point unit extensions */
1902 /* Optional floating point instructions */
1903 PPC_FLOAT = 0x0000000000010000ULL,
1904 /* New floating-point extensions (PowerPC 2.0x) */
1905 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1906 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1907 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1908 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1909 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1910 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1911 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1912
1913 /* Vector/SIMD extensions */
1914 /* Altivec support */
1915 PPC_ALTIVEC = 0x0000000001000000ULL,
1916 /* PowerPC 2.03 SPE extension */
1917 PPC_SPE = 0x0000000002000000ULL,
1918 /* PowerPC 2.03 SPE single-precision floating-point extension */
1919 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1920 /* PowerPC 2.03 SPE double-precision floating-point extension */
1921 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1922
1923 /* Optional memory control instructions */
1924 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1925 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1926 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1927 /* sync instruction */
1928 PPC_MEM_SYNC = 0x0000000080000000ULL,
1929 /* eieio instruction */
1930 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1931
1932 /* Cache control instructions */
1933 PPC_CACHE = 0x0000000200000000ULL,
1934 /* icbi instruction */
1935 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1936 /* dcbz instruction */
1937 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1938 /* dcba instruction */
1939 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1940 /* Freescale cache locking instructions */
1941 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1942
1943 /* MMU related extensions */
1944 /* external control instructions */
1945 PPC_EXTERN = 0x0000010000000000ULL,
1946 /* segment register access instructions */
1947 PPC_SEGMENT = 0x0000020000000000ULL,
1948 /* PowerPC 6xx TLB management instructions */
1949 PPC_6xx_TLB = 0x0000040000000000ULL,
1950 /* PowerPC 74xx TLB management instructions */
1951 PPC_74xx_TLB = 0x0000080000000000ULL,
1952 /* PowerPC 40x TLB management instructions */
1953 PPC_40x_TLB = 0x0000100000000000ULL,
1954 /* segment register access instructions for PowerPC 64 "bridge" */
1955 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1956 /* SLB management */
1957 PPC_SLBI = 0x0000400000000000ULL,
1958
1959 /* Embedded PowerPC dedicated instructions */
1960 PPC_WRTEE = 0x0001000000000000ULL,
1961 /* PowerPC 40x exception model */
1962 PPC_40x_EXCP = 0x0002000000000000ULL,
1963 /* PowerPC 405 Mac instructions */
1964 PPC_405_MAC = 0x0004000000000000ULL,
1965 /* PowerPC 440 specific instructions */
1966 PPC_440_SPEC = 0x0008000000000000ULL,
1967 /* BookE (embedded) PowerPC specification */
1968 PPC_BOOKE = 0x0010000000000000ULL,
1969 /* mfapidi instruction */
1970 PPC_MFAPIDI = 0x0020000000000000ULL,
1971 /* tlbiva instruction */
1972 PPC_TLBIVA = 0x0040000000000000ULL,
1973 /* tlbivax instruction */
1974 PPC_TLBIVAX = 0x0080000000000000ULL,
1975 /* PowerPC 4xx dedicated instructions */
1976 PPC_4xx_COMMON = 0x0100000000000000ULL,
1977 /* PowerPC 40x ibct instructions */
1978 PPC_40x_ICBT = 0x0200000000000000ULL,
1979 /* rfmci is not implemented in all BookE PowerPC */
1980 PPC_RFMCI = 0x0400000000000000ULL,
1981 /* rfdi instruction */
1982 PPC_RFDI = 0x0800000000000000ULL,
1983 /* DCR accesses */
1984 PPC_DCR = 0x1000000000000000ULL,
1985 /* DCR extended accesse */
1986 PPC_DCRX = 0x2000000000000000ULL,
1987 /* user-mode DCR access, implemented in PowerPC 460 */
1988 PPC_DCRUX = 0x4000000000000000ULL,
1989 /* popcntw and popcntd instructions */
1990 PPC_POPCNTWD = 0x8000000000000000ULL,
1991
1992 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1993 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1994 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1995 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1996 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1997 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1998 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1999 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2000 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2001 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2002 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2003 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2004 | PPC_CACHE | PPC_CACHE_ICBI \
2005 | PPC_CACHE_DCBZ \
2006 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2007 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2008 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2009 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2010 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2011 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2012 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2013 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2014 | PPC_POPCNTWD)
2015
2016 /* extended type values */
2017
2018 /* BookE 2.06 PowerPC specification */
2019 PPC2_BOOKE206 = 0x0000000000000001ULL,
2020 /* VSX (extensions to Altivec / VMX) */
2021 PPC2_VSX = 0x0000000000000002ULL,
2022 /* Decimal Floating Point (DFP) */
2023 PPC2_DFP = 0x0000000000000004ULL,
2024 /* Embedded.Processor Control */
2025 PPC2_PRCNTL = 0x0000000000000008ULL,
2026 /* Byte-reversed, indexed, double-word load and store */
2027 PPC2_DBRX = 0x0000000000000010ULL,
2028 /* Book I 2.05 PowerPC specification */
2029 PPC2_ISA205 = 0x0000000000000020ULL,
2030 /* VSX additions in ISA 2.07 */
2031 PPC2_VSX207 = 0x0000000000000040ULL,
2032 /* ISA 2.06B bpermd */
2033 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2034 /* ISA 2.06B divide extended variants */
2035 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2036 /* ISA 2.06B larx/stcx. instructions */
2037 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2038 /* ISA 2.06B floating point integer conversion */
2039 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2040 /* ISA 2.06B floating point test instructions */
2041 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2042 /* ISA 2.07 bctar instruction */
2043 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2044 /* ISA 2.07 load/store quadword */
2045 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2046 /* ISA 2.07 Altivec */
2047 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2048 /* PowerISA 2.07 Book3s specification */
2049 PPC2_ISA207S = 0x0000000000008000ULL,
2050 /* Double precision floating point conversion for signed integer 64 */
2051 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2052 /* Transactional Memory (ISA 2.07, Book II) */
2053 PPC2_TM = 0x0000000000020000ULL,
2054
2055 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2056 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2057 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2058 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2059 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2060 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2061 PPC2_FP_CVT_S64 | PPC2_TM)
2062 };
2063
2064 /*****************************************************************************/
2065 /* Memory access type :
2066 * may be needed for precise access rights control and precise exceptions.
2067 */
2068 enum {
2069 /* 1 bit to define user level / supervisor access */
2070 ACCESS_USER = 0x00,
2071 ACCESS_SUPER = 0x01,
2072 /* Type of instruction that generated the access */
2073 ACCESS_CODE = 0x10, /* Code fetch access */
2074 ACCESS_INT = 0x20, /* Integer load/store access */
2075 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2076 ACCESS_RES = 0x40, /* load/store with reservation */
2077 ACCESS_EXT = 0x50, /* external access */
2078 ACCESS_CACHE = 0x60, /* Cache manipulation */
2079 };
2080
2081 /* Hardware interruption sources:
2082 * all those exception can be raised simulteaneously
2083 */
2084 /* Input pins definitions */
2085 enum {
2086 /* 6xx bus input pins */
2087 PPC6xx_INPUT_HRESET = 0,
2088 PPC6xx_INPUT_SRESET = 1,
2089 PPC6xx_INPUT_CKSTP_IN = 2,
2090 PPC6xx_INPUT_MCP = 3,
2091 PPC6xx_INPUT_SMI = 4,
2092 PPC6xx_INPUT_INT = 5,
2093 PPC6xx_INPUT_TBEN = 6,
2094 PPC6xx_INPUT_WAKEUP = 7,
2095 PPC6xx_INPUT_NB,
2096 };
2097
2098 enum {
2099 /* Embedded PowerPC input pins */
2100 PPCBookE_INPUT_HRESET = 0,
2101 PPCBookE_INPUT_SRESET = 1,
2102 PPCBookE_INPUT_CKSTP_IN = 2,
2103 PPCBookE_INPUT_MCP = 3,
2104 PPCBookE_INPUT_SMI = 4,
2105 PPCBookE_INPUT_INT = 5,
2106 PPCBookE_INPUT_CINT = 6,
2107 PPCBookE_INPUT_NB,
2108 };
2109
2110 enum {
2111 /* PowerPC E500 input pins */
2112 PPCE500_INPUT_RESET_CORE = 0,
2113 PPCE500_INPUT_MCK = 1,
2114 PPCE500_INPUT_CINT = 3,
2115 PPCE500_INPUT_INT = 4,
2116 PPCE500_INPUT_DEBUG = 6,
2117 PPCE500_INPUT_NB,
2118 };
2119
2120 enum {
2121 /* PowerPC 40x input pins */
2122 PPC40x_INPUT_RESET_CORE = 0,
2123 PPC40x_INPUT_RESET_CHIP = 1,
2124 PPC40x_INPUT_RESET_SYS = 2,
2125 PPC40x_INPUT_CINT = 3,
2126 PPC40x_INPUT_INT = 4,
2127 PPC40x_INPUT_HALT = 5,
2128 PPC40x_INPUT_DEBUG = 6,
2129 PPC40x_INPUT_NB,
2130 };
2131
2132 enum {
2133 /* RCPU input pins */
2134 PPCRCPU_INPUT_PORESET = 0,
2135 PPCRCPU_INPUT_HRESET = 1,
2136 PPCRCPU_INPUT_SRESET = 2,
2137 PPCRCPU_INPUT_IRQ0 = 3,
2138 PPCRCPU_INPUT_IRQ1 = 4,
2139 PPCRCPU_INPUT_IRQ2 = 5,
2140 PPCRCPU_INPUT_IRQ3 = 6,
2141 PPCRCPU_INPUT_IRQ4 = 7,
2142 PPCRCPU_INPUT_IRQ5 = 8,
2143 PPCRCPU_INPUT_IRQ6 = 9,
2144 PPCRCPU_INPUT_IRQ7 = 10,
2145 PPCRCPU_INPUT_NB,
2146 };
2147
2148 #if defined(TARGET_PPC64)
2149 enum {
2150 /* PowerPC 970 input pins */
2151 PPC970_INPUT_HRESET = 0,
2152 PPC970_INPUT_SRESET = 1,
2153 PPC970_INPUT_CKSTP = 2,
2154 PPC970_INPUT_TBEN = 3,
2155 PPC970_INPUT_MCP = 4,
2156 PPC970_INPUT_INT = 5,
2157 PPC970_INPUT_THINT = 6,
2158 PPC970_INPUT_NB,
2159 };
2160
2161 enum {
2162 /* POWER7 input pins */
2163 POWER7_INPUT_INT = 0,
2164 /* POWER7 probably has other inputs, but we don't care about them
2165 * for any existing machine. We can wire these up when we need
2166 * them */
2167 POWER7_INPUT_NB,
2168 };
2169 #endif
2170
2171 /* Hardware exceptions definitions */
2172 enum {
2173 /* External hardware exception sources */
2174 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2175 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2176 PPC_INTERRUPT_MCK, /* Machine check exception */
2177 PPC_INTERRUPT_EXT, /* External interrupt */
2178 PPC_INTERRUPT_SMI, /* System management interrupt */
2179 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2180 PPC_INTERRUPT_DEBUG, /* External debug exception */
2181 PPC_INTERRUPT_THERM, /* Thermal exception */
2182 /* Internal hardware exception sources */
2183 PPC_INTERRUPT_DECR, /* Decrementer exception */
2184 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2185 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2186 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2187 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2188 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2189 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2190 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2191 };
2192
2193 /* Processor Compatibility mask (PCR) */
2194 enum {
2195 PCR_COMPAT_2_05 = 1ull << (63-62),
2196 PCR_COMPAT_2_06 = 1ull << (63-61),
2197 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2198 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2199 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2200 };
2201
2202 /* HMER/HMEER */
2203 enum {
2204 HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
2205 HMER_PROC_RECV_DONE = 1ull << (63 - 2),
2206 HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2207 HMER_TFAC_ERROR = 1ull << (63 - 4),
2208 HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
2209 HMER_XSCOM_FAIL = 1ull << (63 - 8),
2210 HMER_XSCOM_DONE = 1ull << (63 - 9),
2211 HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
2212 HMER_WARN_RISE = 1ull << (63 - 14),
2213 HMER_WARN_FALL = 1ull << (63 - 15),
2214 HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
2215 HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
2216 HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
2217 HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
2218 HMER_XSCOM_STATUS_LSH = (63 - 23),
2219 };
2220
2221 /* Alternate Interrupt Location (AIL) */
2222 enum {
2223 AIL_NONE = 0,
2224 AIL_RESERVED = 1,
2225 AIL_0001_8000 = 2,
2226 AIL_C000_0000_0000_4000 = 3,
2227 };
2228
2229 /*****************************************************************************/
2230
2231 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2232 {
2233 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2234 }
2235
2236 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2237 {
2238 env->so = (xer >> XER_SO) & 1;
2239 env->ov = (xer >> XER_OV) & 1;
2240 env->ca = (xer >> XER_CA) & 1;
2241 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2242 }
2243
2244 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2245 target_ulong *cs_base, uint32_t *flags)
2246 {
2247 *pc = env->nip;
2248 *cs_base = 0;
2249 *flags = env->hflags;
2250 }
2251
2252 #if !defined(CONFIG_USER_ONLY)
2253 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2254 {
2255 uintptr_t tlbml = (uintptr_t)tlbm;
2256 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2257
2258 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2259 }
2260
2261 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2262 {
2263 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2264 int r = tlbncfg & TLBnCFG_N_ENTRY;
2265 return r;
2266 }
2267
2268 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2269 {
2270 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2271 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2272 return r;
2273 }
2274
2275 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2276 {
2277 int id = booke206_tlbm_id(env, tlbm);
2278 int end = 0;
2279 int i;
2280
2281 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2282 end += booke206_tlb_size(env, i);
2283 if (id < end) {
2284 return i;
2285 }
2286 }
2287
2288 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2289 return 0;
2290 }
2291
2292 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2293 {
2294 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2295 int tlbid = booke206_tlbm_id(env, tlb);
2296 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2297 }
2298
2299 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2300 target_ulong ea, int way)
2301 {
2302 int r;
2303 uint32_t ways = booke206_tlb_ways(env, tlbn);
2304 int ways_bits = ctz32(ways);
2305 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2306 int i;
2307
2308 way &= ways - 1;
2309 ea >>= MAS2_EPN_SHIFT;
2310 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2311 r = (ea << ways_bits) | way;
2312
2313 if (r >= booke206_tlb_size(env, tlbn)) {
2314 return NULL;
2315 }
2316
2317 /* bump up to tlbn index */
2318 for (i = 0; i < tlbn; i++) {
2319 r += booke206_tlb_size(env, i);
2320 }
2321
2322 return &env->tlb.tlbm[r];
2323 }
2324
2325 /* returns bitmap of supported page sizes for a given TLB */
2326 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2327 {
2328 bool mav2 = false;
2329 uint32_t ret = 0;
2330
2331 if (mav2) {
2332 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2333 } else {
2334 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2335 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2336 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2337 int i;
2338 for (i = min; i <= max; i++) {
2339 ret |= (1 << (i << 1));
2340 }
2341 }
2342
2343 return ret;
2344 }
2345
2346 #endif
2347
2348 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2349 {
2350 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2351 return msr & (1ULL << MSR_CM);
2352 }
2353
2354 return msr & (1ULL << MSR_SF);
2355 }
2356
2357 /**
2358 * Check whether register rx is in the range between start and
2359 * start + nregs (as needed by the LSWX and LSWI instructions)
2360 */
2361 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2362 {
2363 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2364 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2365 }
2366
2367 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2368
2369 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2370
2371 /**
2372 * ppc_get_vcpu_dt_id:
2373 * @cs: a PowerPCCPU struct.
2374 *
2375 * Returns a device-tree ID for a CPU.
2376 */
2377 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2378
2379 /**
2380 * ppc_get_vcpu_by_dt_id:
2381 * @cpu_dt_id: a device tree id
2382 *
2383 * Searches for a CPU by @cpu_dt_id.
2384 *
2385 * Returns: a PowerPCCPU struct
2386 */
2387 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2388
2389 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2390 #endif /* !defined (__CPU_PPC_H__) */
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