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1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include <inttypes.h>
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 /* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37 /* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40 #ifdef TARGET_ABI32
41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
42 #else
43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
44 #endif
45
46 #else /* defined (TARGET_PPC64) */
47 /* PowerPC 32 definitions */
48 #define TARGET_LONG_BITS 32
49
50 #if defined(TARGET_PPCEMB)
51 /* Specific definitions for PowerPC embedded */
52 /* BookE have 36 bits physical address space */
53 #if defined(CONFIG_USER_ONLY)
54 /* It looks like a lot of Linux programs assume page size
55 * is 4kB long. This is evil, but we have to deal with it...
56 */
57 #define TARGET_PAGE_BITS 12
58 #else /* defined(CONFIG_USER_ONLY) */
59 /* Pages can be 1 kB small */
60 #define TARGET_PAGE_BITS 10
61 #endif /* defined(CONFIG_USER_ONLY) */
62 #else /* defined(TARGET_PPCEMB) */
63 /* "standard" PowerPC 32 definitions */
64 #define TARGET_PAGE_BITS 12
65 #endif /* defined(TARGET_PPCEMB) */
66
67 #define TARGET_PHYS_ADDR_SPACE_BITS 32
68 #define TARGET_VIRT_ADDR_SPACE_BITS 32
69
70 #endif /* defined (TARGET_PPC64) */
71
72 #define CPUState struct CPUPPCState
73
74 #include "cpu-defs.h"
75
76 #include <setjmp.h>
77
78 #include "softfloat.h"
79
80 #define TARGET_HAS_ICE 1
81
82 #if defined (TARGET_PPC64)
83 #define ELF_MACHINE EM_PPC64
84 #else
85 #define ELF_MACHINE EM_PPC
86 #endif
87
88 /*****************************************************************************/
89 /* MMU model */
90 typedef enum powerpc_mmu_t powerpc_mmu_t;
91 enum powerpc_mmu_t {
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93 /* Standard 32 bits PowerPC MMU */
94 POWERPC_MMU_32B = 0x00000001,
95 /* PowerPC 6xx MMU with software TLB */
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97 /* PowerPC 74xx MMU with software TLB */
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99 /* PowerPC 4xx MMU with software TLB */
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101 /* PowerPC 4xx MMU with software TLB and zones protections */
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103 /* PowerPC MMU in real mode only */
104 POWERPC_MMU_REAL = 0x00000006,
105 /* Freescale MPC8xx MMU model */
106 POWERPC_MMU_MPC8xx = 0x00000007,
107 /* BookE MMU model */
108 POWERPC_MMU_BOOKE = 0x00000008,
109 /* BookE FSL MMU model */
110 POWERPC_MMU_BOOKE_FSL = 0x00000009,
111 /* PowerPC 601 MMU model (specific BATs format) */
112 POWERPC_MMU_601 = 0x0000000A,
113 #if defined(TARGET_PPC64)
114 #define POWERPC_MMU_64 0x00010000
115 /* 64 bits PowerPC MMU */
116 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
117 /* 620 variant (no segment exceptions) */
118 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
119 #endif /* defined(TARGET_PPC64) */
120 };
121
122 /*****************************************************************************/
123 /* Exception model */
124 typedef enum powerpc_excp_t powerpc_excp_t;
125 enum powerpc_excp_t {
126 POWERPC_EXCP_UNKNOWN = 0,
127 /* Standard PowerPC exception model */
128 POWERPC_EXCP_STD,
129 /* PowerPC 40x exception model */
130 POWERPC_EXCP_40x,
131 /* PowerPC 601 exception model */
132 POWERPC_EXCP_601,
133 /* PowerPC 602 exception model */
134 POWERPC_EXCP_602,
135 /* PowerPC 603 exception model */
136 POWERPC_EXCP_603,
137 /* PowerPC 603e exception model */
138 POWERPC_EXCP_603E,
139 /* PowerPC G2 exception model */
140 POWERPC_EXCP_G2,
141 /* PowerPC 604 exception model */
142 POWERPC_EXCP_604,
143 /* PowerPC 7x0 exception model */
144 POWERPC_EXCP_7x0,
145 /* PowerPC 7x5 exception model */
146 POWERPC_EXCP_7x5,
147 /* PowerPC 74xx exception model */
148 POWERPC_EXCP_74xx,
149 /* BookE exception model */
150 POWERPC_EXCP_BOOKE,
151 #if defined(TARGET_PPC64)
152 /* PowerPC 970 exception model */
153 POWERPC_EXCP_970,
154 #endif /* defined(TARGET_PPC64) */
155 };
156
157 /*****************************************************************************/
158 /* Exception vectors definitions */
159 enum {
160 POWERPC_EXCP_NONE = -1,
161 /* The 64 first entries are used by the PowerPC embedded specification */
162 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
163 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
164 POWERPC_EXCP_DSI = 2, /* Data storage exception */
165 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
166 POWERPC_EXCP_EXTERNAL = 4, /* External input */
167 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
168 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
169 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
170 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
171 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
172 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
173 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
174 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
175 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
176 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
177 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
178 /* Vectors 16 to 31 are reserved */
179 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
180 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
181 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
182 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
183 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
184 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
185 /* Vectors 38 to 63 are reserved */
186 /* Exceptions defined in the PowerPC server specification */
187 POWERPC_EXCP_RESET = 64, /* System reset exception */
188 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
189 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
190 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
191 POWERPC_EXCP_TRACE = 68, /* Trace exception */
192 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
193 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
194 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
195 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
196 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
197 /* 40x specific exceptions */
198 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
199 /* 601 specific exceptions */
200 POWERPC_EXCP_IO = 75, /* IO error exception */
201 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
202 /* 602 specific exceptions */
203 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
204 /* 602/603 specific exceptions */
205 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
206 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
207 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
208 /* Exceptions available on most PowerPC */
209 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
210 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
211 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
212 POWERPC_EXCP_SMI = 84, /* System management interrupt */
213 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
214 /* 7xx/74xx specific exceptions */
215 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
216 /* 74xx specific exceptions */
217 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
218 /* 970FX specific exceptions */
219 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
220 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
221 /* Freescale embeded cores specific exceptions */
222 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
223 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
224 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
225 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
226 /* EOL */
227 POWERPC_EXCP_NB = 96,
228 /* Qemu exceptions: used internally during code translation */
229 POWERPC_EXCP_STOP = 0x200, /* stop translation */
230 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
231 /* Qemu exceptions: special cases we want to stop translation */
232 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
233 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
234 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
235 };
236
237 /* Exceptions error codes */
238 enum {
239 /* Exception subtypes for POWERPC_EXCP_ALIGN */
240 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
241 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
242 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
243 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
244 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
245 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
246 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
247 /* FP exceptions */
248 POWERPC_EXCP_FP = 0x10,
249 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
250 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
251 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
252 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
253 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
254 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
255 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
256 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
257 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
258 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
259 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
260 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
261 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
262 /* Invalid instruction */
263 POWERPC_EXCP_INVAL = 0x20,
264 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
265 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
266 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
267 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
268 /* Privileged instruction */
269 POWERPC_EXCP_PRIV = 0x30,
270 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
271 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
272 /* Trap */
273 POWERPC_EXCP_TRAP = 0x40,
274 };
275
276 /*****************************************************************************/
277 /* Input pins model */
278 typedef enum powerpc_input_t powerpc_input_t;
279 enum powerpc_input_t {
280 PPC_FLAGS_INPUT_UNKNOWN = 0,
281 /* PowerPC 6xx bus */
282 PPC_FLAGS_INPUT_6xx,
283 /* BookE bus */
284 PPC_FLAGS_INPUT_BookE,
285 /* PowerPC 405 bus */
286 PPC_FLAGS_INPUT_405,
287 /* PowerPC 970 bus */
288 PPC_FLAGS_INPUT_970,
289 /* PowerPC 401 bus */
290 PPC_FLAGS_INPUT_401,
291 /* Freescale RCPU bus */
292 PPC_FLAGS_INPUT_RCPU,
293 };
294
295 #define PPC_INPUT(env) (env->bus_model)
296
297 /*****************************************************************************/
298 typedef struct ppc_def_t ppc_def_t;
299 typedef struct opc_handler_t opc_handler_t;
300
301 /*****************************************************************************/
302 /* Types used to describe some PowerPC registers */
303 typedef struct CPUPPCState CPUPPCState;
304 typedef struct ppc_tb_t ppc_tb_t;
305 typedef struct ppc_spr_t ppc_spr_t;
306 typedef struct ppc_dcr_t ppc_dcr_t;
307 typedef union ppc_avr_t ppc_avr_t;
308 typedef union ppc_tlb_t ppc_tlb_t;
309
310 /* SPR access micro-ops generations callbacks */
311 struct ppc_spr_t {
312 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
313 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
314 #if !defined(CONFIG_USER_ONLY)
315 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
316 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
317 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
318 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
319 #endif
320 const char *name;
321 };
322
323 /* Altivec registers (128 bits) */
324 union ppc_avr_t {
325 float32 f[4];
326 uint8_t u8[16];
327 uint16_t u16[8];
328 uint32_t u32[4];
329 int8_t s8[16];
330 int16_t s16[8];
331 int32_t s32[4];
332 uint64_t u64[2];
333 };
334
335 /* Software TLB cache */
336 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
337 struct ppc6xx_tlb_t {
338 target_ulong pte0;
339 target_ulong pte1;
340 target_ulong EPN;
341 };
342
343 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
344 struct ppcemb_tlb_t {
345 target_phys_addr_t RPN;
346 target_ulong EPN;
347 target_ulong PID;
348 target_ulong size;
349 uint32_t prot;
350 uint32_t attr; /* Storage attributes */
351 };
352
353 union ppc_tlb_t {
354 ppc6xx_tlb_t tlb6;
355 ppcemb_tlb_t tlbe;
356 };
357
358 typedef struct ppc_slb_t ppc_slb_t;
359 struct ppc_slb_t {
360 uint64_t tmp64;
361 uint32_t tmp;
362 };
363
364 /*****************************************************************************/
365 /* Machine state register bits definition */
366 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
367 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
368 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
369 #define MSR_SHV 60 /* hypervisor state hflags */
370 #define MSR_CM 31 /* Computation mode for BookE hflags */
371 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
372 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
373 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
374 #define MSR_VR 25 /* altivec available x hflags */
375 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
376 #define MSR_AP 23 /* Access privilege state on 602 hflags */
377 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
378 #define MSR_KEY 19 /* key bit on 603e */
379 #define MSR_POW 18 /* Power management */
380 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
381 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
382 #define MSR_ILE 16 /* Interrupt little-endian mode */
383 #define MSR_EE 15 /* External interrupt enable */
384 #define MSR_PR 14 /* Problem state hflags */
385 #define MSR_FP 13 /* Floating point available hflags */
386 #define MSR_ME 12 /* Machine check interrupt enable */
387 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
388 #define MSR_SE 10 /* Single-step trace enable x hflags */
389 #define MSR_DWE 10 /* Debug wait enable on 405 x */
390 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
391 #define MSR_BE 9 /* Branch trace enable x hflags */
392 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
393 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
394 #define MSR_AL 7 /* AL bit on POWER */
395 #define MSR_EP 6 /* Exception prefix on 601 */
396 #define MSR_IR 5 /* Instruction relocate */
397 #define MSR_DR 4 /* Data relocate */
398 #define MSR_PE 3 /* Protection enable on 403 */
399 #define MSR_PX 2 /* Protection exclusive on 403 x */
400 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
401 #define MSR_RI 1 /* Recoverable interrupt 1 */
402 #define MSR_LE 0 /* Little-endian mode 1 hflags */
403
404 #define msr_sf ((env->msr >> MSR_SF) & 1)
405 #define msr_isf ((env->msr >> MSR_ISF) & 1)
406 #define msr_shv ((env->msr >> MSR_SHV) & 1)
407 #define msr_cm ((env->msr >> MSR_CM) & 1)
408 #define msr_icm ((env->msr >> MSR_ICM) & 1)
409 #define msr_thv ((env->msr >> MSR_THV) & 1)
410 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
411 #define msr_vr ((env->msr >> MSR_VR) & 1)
412 #define msr_spe ((env->msr >> MSR_SPE) & 1)
413 #define msr_ap ((env->msr >> MSR_AP) & 1)
414 #define msr_sa ((env->msr >> MSR_SA) & 1)
415 #define msr_key ((env->msr >> MSR_KEY) & 1)
416 #define msr_pow ((env->msr >> MSR_POW) & 1)
417 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
418 #define msr_ce ((env->msr >> MSR_CE) & 1)
419 #define msr_ile ((env->msr >> MSR_ILE) & 1)
420 #define msr_ee ((env->msr >> MSR_EE) & 1)
421 #define msr_pr ((env->msr >> MSR_PR) & 1)
422 #define msr_fp ((env->msr >> MSR_FP) & 1)
423 #define msr_me ((env->msr >> MSR_ME) & 1)
424 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
425 #define msr_se ((env->msr >> MSR_SE) & 1)
426 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
427 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
428 #define msr_be ((env->msr >> MSR_BE) & 1)
429 #define msr_de ((env->msr >> MSR_DE) & 1)
430 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
431 #define msr_al ((env->msr >> MSR_AL) & 1)
432 #define msr_ep ((env->msr >> MSR_EP) & 1)
433 #define msr_ir ((env->msr >> MSR_IR) & 1)
434 #define msr_dr ((env->msr >> MSR_DR) & 1)
435 #define msr_pe ((env->msr >> MSR_PE) & 1)
436 #define msr_px ((env->msr >> MSR_PX) & 1)
437 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
438 #define msr_ri ((env->msr >> MSR_RI) & 1)
439 #define msr_le ((env->msr >> MSR_LE) & 1)
440 /* Hypervisor bit is more specific */
441 #if defined(TARGET_PPC64)
442 #define MSR_HVB (1ULL << MSR_SHV)
443 #define msr_hv msr_shv
444 #else
445 #if defined(PPC_EMULATE_32BITS_HYPV)
446 #define MSR_HVB (1ULL << MSR_THV)
447 #define msr_hv msr_thv
448 #else
449 #define MSR_HVB (0ULL)
450 #define msr_hv (0)
451 #endif
452 #endif
453
454 enum {
455 POWERPC_FLAG_NONE = 0x00000000,
456 /* Flag for MSR bit 25 signification (VRE/SPE) */
457 POWERPC_FLAG_SPE = 0x00000001,
458 POWERPC_FLAG_VRE = 0x00000002,
459 /* Flag for MSR bit 17 signification (TGPR/CE) */
460 POWERPC_FLAG_TGPR = 0x00000004,
461 POWERPC_FLAG_CE = 0x00000008,
462 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
463 POWERPC_FLAG_SE = 0x00000010,
464 POWERPC_FLAG_DWE = 0x00000020,
465 POWERPC_FLAG_UBLE = 0x00000040,
466 /* Flag for MSR bit 9 signification (BE/DE) */
467 POWERPC_FLAG_BE = 0x00000080,
468 POWERPC_FLAG_DE = 0x00000100,
469 /* Flag for MSR bit 2 signification (PX/PMM) */
470 POWERPC_FLAG_PX = 0x00000200,
471 POWERPC_FLAG_PMM = 0x00000400,
472 /* Flag for special features */
473 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
474 POWERPC_FLAG_RTC_CLK = 0x00010000,
475 POWERPC_FLAG_BUS_CLK = 0x00020000,
476 };
477
478 /*****************************************************************************/
479 /* Floating point status and control register */
480 #define FPSCR_FX 31 /* Floating-point exception summary */
481 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
482 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
483 #define FPSCR_OX 28 /* Floating-point overflow exception */
484 #define FPSCR_UX 27 /* Floating-point underflow exception */
485 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
486 #define FPSCR_XX 25 /* Floating-point inexact exception */
487 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
488 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
489 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
490 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
491 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
492 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
493 #define FPSCR_FR 18 /* Floating-point fraction rounded */
494 #define FPSCR_FI 17 /* Floating-point fraction inexact */
495 #define FPSCR_C 16 /* Floating-point result class descriptor */
496 #define FPSCR_FL 15 /* Floating-point less than or negative */
497 #define FPSCR_FG 14 /* Floating-point greater than or negative */
498 #define FPSCR_FE 13 /* Floating-point equal or zero */
499 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
500 #define FPSCR_FPCC 12 /* Floating-point condition code */
501 #define FPSCR_FPRF 12 /* Floating-point result flags */
502 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
503 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
504 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
505 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
506 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
507 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
508 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
509 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
510 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
511 #define FPSCR_RN1 1
512 #define FPSCR_RN 0 /* Floating-point rounding control */
513 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
514 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
515 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
516 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
517 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
518 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
519 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
520 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
521 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
522 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
523 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
524 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
525 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
526 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
527 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
528 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
529 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
530 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
531 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
532 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
533 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
534 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
535 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
536 /* Invalid operation exception summary */
537 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
538 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
539 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
540 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
541 (1 << FPSCR_VXCVI)))
542 /* exception summary */
543 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
544 /* enabled exception summary */
545 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
546 0x1F)
547
548 /*****************************************************************************/
549 /* Vector status and control register */
550 #define VSCR_NJ 16 /* Vector non-java */
551 #define VSCR_SAT 0 /* Vector saturation */
552 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
553 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
554
555 /*****************************************************************************/
556 /* The whole PowerPC CPU context */
557 #define NB_MMU_MODES 3
558
559 struct CPUPPCState {
560 /* First are the most commonly used resources
561 * during translated code execution
562 */
563 /* general purpose registers */
564 target_ulong gpr[32];
565 #if !defined(TARGET_PPC64)
566 /* Storage for GPR MSB, used by the SPE extension */
567 target_ulong gprh[32];
568 #endif
569 /* LR */
570 target_ulong lr;
571 /* CTR */
572 target_ulong ctr;
573 /* condition register */
574 uint32_t crf[8];
575 /* XER */
576 target_ulong xer;
577 /* Reservation address */
578 target_ulong reserve_addr;
579 /* Reservation value */
580 target_ulong reserve_val;
581 /* Reservation store address */
582 target_ulong reserve_ea;
583 /* Reserved store source register and size */
584 target_ulong reserve_info;
585
586 /* Those ones are used in supervisor mode only */
587 /* machine state register */
588 target_ulong msr;
589 /* temporary general purpose registers */
590 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
591
592 /* Floating point execution context */
593 float_status fp_status;
594 /* floating point registers */
595 float64 fpr[32];
596 /* floating point status and control register */
597 uint32_t fpscr;
598
599 /* Next instruction pointer */
600 target_ulong nip;
601
602 int access_type; /* when a memory exception occurs, the access
603 type is stored here */
604
605 CPU_COMMON
606
607 /* MMU context - only relevant for full system emulation */
608 #if !defined(CONFIG_USER_ONLY)
609 #if defined(TARGET_PPC64)
610 /* Address space register */
611 target_ulong asr;
612 /* PowerPC 64 SLB area */
613 ppc_slb_t slb[64];
614 int slb_nr;
615 #endif
616 /* segment registers */
617 target_ulong sdr1;
618 target_ulong sr[32];
619 /* BATs */
620 int nb_BATs;
621 target_ulong DBAT[2][8];
622 target_ulong IBAT[2][8];
623 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
624 int nb_tlb; /* Total number of TLB */
625 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
626 int nb_ways; /* Number of ways in the TLB set */
627 int last_way; /* Last used way used to allocate TLB in a LRU way */
628 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
629 int nb_pids; /* Number of available PID registers */
630 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
631 /* 403 dedicated access protection registers */
632 target_ulong pb[4];
633 #endif
634
635 /* Other registers */
636 /* Special purpose registers */
637 target_ulong spr[1024];
638 ppc_spr_t spr_cb[1024];
639 /* Altivec registers */
640 ppc_avr_t avr[32];
641 uint32_t vscr;
642 /* SPE registers */
643 uint64_t spe_acc;
644 uint32_t spe_fscr;
645 /* SPE and Altivec can share a status since they will never be used
646 * simultaneously */
647 float_status vec_status;
648
649 /* Internal devices resources */
650 /* Time base and decrementer */
651 ppc_tb_t *tb_env;
652 /* Device control registers */
653 ppc_dcr_t *dcr_env;
654
655 int dcache_line_size;
656 int icache_line_size;
657
658 /* Those resources are used during exception processing */
659 /* CPU model definition */
660 target_ulong msr_mask;
661 powerpc_mmu_t mmu_model;
662 powerpc_excp_t excp_model;
663 powerpc_input_t bus_model;
664 int bfd_mach;
665 uint32_t flags;
666 uint64_t insns_flags;
667
668 int error_code;
669 uint32_t pending_interrupts;
670 #if !defined(CONFIG_USER_ONLY)
671 /* This is the IRQ controller, which is implementation dependant
672 * and only relevant when emulating a complete machine.
673 */
674 uint32_t irq_input_state;
675 void **irq_inputs;
676 /* Exception vectors */
677 target_ulong excp_vectors[POWERPC_EXCP_NB];
678 target_ulong excp_prefix;
679 target_ulong hreset_excp_prefix;
680 target_ulong ivor_mask;
681 target_ulong ivpr_mask;
682 target_ulong hreset_vector;
683 #endif
684
685 /* Those resources are used only during code translation */
686 /* opcode handlers */
687 opc_handler_t *opcodes[0x40];
688
689 /* Those resources are used only in Qemu core */
690 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
691 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
692 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
693
694 /* Power management */
695 int power_mode;
696 int (*check_pow)(CPUPPCState *env);
697
698 /* temporary hack to handle OSI calls (only used if non NULL) */
699 int (*osi_call)(struct CPUPPCState *env);
700 };
701
702 /* Context used internally during MMU translations */
703 typedef struct mmu_ctx_t mmu_ctx_t;
704 struct mmu_ctx_t {
705 target_phys_addr_t raddr; /* Real address */
706 target_phys_addr_t eaddr; /* Effective address */
707 int prot; /* Protection bits */
708 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
709 target_ulong ptem; /* Virtual segment ID | API */
710 int key; /* Access key */
711 int nx; /* Non-execute area */
712 };
713
714 /*****************************************************************************/
715 CPUPPCState *cpu_ppc_init (const char *cpu_model);
716 void ppc_translate_init(void);
717 int cpu_ppc_exec (CPUPPCState *s);
718 void cpu_ppc_close (CPUPPCState *s);
719 /* you can call this signal handler from your SIGBUS and SIGSEGV
720 signal handlers to inform the virtual CPU of exceptions. non zero
721 is returned if the signal was handled by the virtual CPU. */
722 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
723 void *puc);
724 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
725 int mmu_idx, int is_softmmu);
726 #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
727 int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
728 int rw, int access_type);
729 void do_interrupt (CPUPPCState *env);
730 void ppc_hw_interrupt (CPUPPCState *env);
731
732 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
733
734 #if !defined(CONFIG_USER_ONLY)
735 void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
736 target_ulong pte0, target_ulong pte1);
737 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
738 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
739 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
740 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
741 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
742 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
743 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
744 #if defined(TARGET_PPC64)
745 void ppc_store_asr (CPUPPCState *env, target_ulong value);
746 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
747 target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
748 void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
749 #endif /* defined(TARGET_PPC64) */
750 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
751 #endif /* !defined(CONFIG_USER_ONLY) */
752 void ppc_store_msr (CPUPPCState *env, target_ulong value);
753
754 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
755
756 const ppc_def_t *cpu_ppc_find_by_name (const char *name);
757 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
758
759 /* Time-base and decrementer management */
760 #ifndef NO_CPU_IO_DEFS
761 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
762 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
763 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
764 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
765 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
766 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
767 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
768 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
769 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
770 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
771 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
772 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
773 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
774 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
775 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
776 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
777 #if !defined(CONFIG_USER_ONLY)
778 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
779 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
780 target_ulong load_40x_pit (CPUPPCState *env);
781 void store_40x_pit (CPUPPCState *env, target_ulong val);
782 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
783 void store_40x_sler (CPUPPCState *env, uint32_t val);
784 void store_booke_tcr (CPUPPCState *env, target_ulong val);
785 void store_booke_tsr (CPUPPCState *env, target_ulong val);
786 void ppc_tlb_invalidate_all (CPUPPCState *env);
787 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
788 #if defined(TARGET_PPC64)
789 void ppc_slb_invalidate_all (CPUPPCState *env);
790 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
791 #endif
792 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
793 #endif
794 #endif
795
796 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
797 {
798 uint64_t gprv;
799
800 gprv = env->gpr[gprn];
801 #if !defined(TARGET_PPC64)
802 if (env->flags & POWERPC_FLAG_SPE) {
803 /* If the CPU implements the SPE extension, we have to get the
804 * high bits of the GPR from the gprh storage area
805 */
806 gprv &= 0xFFFFFFFFULL;
807 gprv |= (uint64_t)env->gprh[gprn] << 32;
808 }
809 #endif
810
811 return gprv;
812 }
813
814 /* Device control registers */
815 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
816 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
817
818 #define cpu_init cpu_ppc_init
819 #define cpu_exec cpu_ppc_exec
820 #define cpu_gen_code cpu_ppc_gen_code
821 #define cpu_signal_handler cpu_ppc_signal_handler
822 #define cpu_list ppc_cpu_list
823
824 #define CPU_SAVE_VERSION 4
825
826 /* MMU modes definitions */
827 #define MMU_MODE0_SUFFIX _user
828 #define MMU_MODE1_SUFFIX _kernel
829 #define MMU_MODE2_SUFFIX _hypv
830 #define MMU_USER_IDX 0
831 static inline int cpu_mmu_index (CPUState *env)
832 {
833 return env->mmu_idx;
834 }
835
836 #if defined(CONFIG_USER_ONLY)
837 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
838 {
839 if (newsp)
840 env->gpr[1] = newsp;
841 env->gpr[3] = 0;
842 }
843 #endif
844
845 #include "cpu-all.h"
846 #include "exec-all.h"
847
848 /*****************************************************************************/
849 /* CRF definitions */
850 #define CRF_LT 3
851 #define CRF_GT 2
852 #define CRF_EQ 1
853 #define CRF_SO 0
854 #define CRF_CH (1 << CRF_LT)
855 #define CRF_CL (1 << CRF_GT)
856 #define CRF_CH_OR_CL (1 << CRF_EQ)
857 #define CRF_CH_AND_CL (1 << CRF_SO)
858
859 /* XER definitions */
860 #define XER_SO 31
861 #define XER_OV 30
862 #define XER_CA 29
863 #define XER_CMP 8
864 #define XER_BC 0
865 #define xer_so ((env->xer >> XER_SO) & 1)
866 #define xer_ov ((env->xer >> XER_OV) & 1)
867 #define xer_ca ((env->xer >> XER_CA) & 1)
868 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
869 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
870
871 /* SPR definitions */
872 #define SPR_MQ (0x000)
873 #define SPR_XER (0x001)
874 #define SPR_601_VRTCU (0x004)
875 #define SPR_601_VRTCL (0x005)
876 #define SPR_601_UDECR (0x006)
877 #define SPR_LR (0x008)
878 #define SPR_CTR (0x009)
879 #define SPR_DSISR (0x012)
880 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
881 #define SPR_601_RTCU (0x014)
882 #define SPR_601_RTCL (0x015)
883 #define SPR_DECR (0x016)
884 #define SPR_SDR1 (0x019)
885 #define SPR_SRR0 (0x01A)
886 #define SPR_SRR1 (0x01B)
887 #define SPR_AMR (0x01D)
888 #define SPR_BOOKE_PID (0x030)
889 #define SPR_BOOKE_DECAR (0x036)
890 #define SPR_BOOKE_CSRR0 (0x03A)
891 #define SPR_BOOKE_CSRR1 (0x03B)
892 #define SPR_BOOKE_DEAR (0x03D)
893 #define SPR_BOOKE_ESR (0x03E)
894 #define SPR_BOOKE_IVPR (0x03F)
895 #define SPR_MPC_EIE (0x050)
896 #define SPR_MPC_EID (0x051)
897 #define SPR_MPC_NRI (0x052)
898 #define SPR_CTRL (0x088)
899 #define SPR_MPC_CMPA (0x090)
900 #define SPR_MPC_CMPB (0x091)
901 #define SPR_MPC_CMPC (0x092)
902 #define SPR_MPC_CMPD (0x093)
903 #define SPR_MPC_ECR (0x094)
904 #define SPR_MPC_DER (0x095)
905 #define SPR_MPC_COUNTA (0x096)
906 #define SPR_MPC_COUNTB (0x097)
907 #define SPR_UCTRL (0x098)
908 #define SPR_MPC_CMPE (0x098)
909 #define SPR_MPC_CMPF (0x099)
910 #define SPR_MPC_CMPG (0x09A)
911 #define SPR_MPC_CMPH (0x09B)
912 #define SPR_MPC_LCTRL1 (0x09C)
913 #define SPR_MPC_LCTRL2 (0x09D)
914 #define SPR_MPC_ICTRL (0x09E)
915 #define SPR_MPC_BAR (0x09F)
916 #define SPR_VRSAVE (0x100)
917 #define SPR_USPRG0 (0x100)
918 #define SPR_USPRG1 (0x101)
919 #define SPR_USPRG2 (0x102)
920 #define SPR_USPRG3 (0x103)
921 #define SPR_USPRG4 (0x104)
922 #define SPR_USPRG5 (0x105)
923 #define SPR_USPRG6 (0x106)
924 #define SPR_USPRG7 (0x107)
925 #define SPR_VTBL (0x10C)
926 #define SPR_VTBU (0x10D)
927 #define SPR_SPRG0 (0x110)
928 #define SPR_SPRG1 (0x111)
929 #define SPR_SPRG2 (0x112)
930 #define SPR_SPRG3 (0x113)
931 #define SPR_SPRG4 (0x114)
932 #define SPR_SCOMC (0x114)
933 #define SPR_SPRG5 (0x115)
934 #define SPR_SCOMD (0x115)
935 #define SPR_SPRG6 (0x116)
936 #define SPR_SPRG7 (0x117)
937 #define SPR_ASR (0x118)
938 #define SPR_EAR (0x11A)
939 #define SPR_TBL (0x11C)
940 #define SPR_TBU (0x11D)
941 #define SPR_TBU40 (0x11E)
942 #define SPR_SVR (0x11E)
943 #define SPR_BOOKE_PIR (0x11E)
944 #define SPR_PVR (0x11F)
945 #define SPR_HSPRG0 (0x130)
946 #define SPR_BOOKE_DBSR (0x130)
947 #define SPR_HSPRG1 (0x131)
948 #define SPR_HDSISR (0x132)
949 #define SPR_HDAR (0x133)
950 #define SPR_BOOKE_DBCR0 (0x134)
951 #define SPR_IBCR (0x135)
952 #define SPR_PURR (0x135)
953 #define SPR_BOOKE_DBCR1 (0x135)
954 #define SPR_DBCR (0x136)
955 #define SPR_HDEC (0x136)
956 #define SPR_BOOKE_DBCR2 (0x136)
957 #define SPR_HIOR (0x137)
958 #define SPR_MBAR (0x137)
959 #define SPR_RMOR (0x138)
960 #define SPR_BOOKE_IAC1 (0x138)
961 #define SPR_HRMOR (0x139)
962 #define SPR_BOOKE_IAC2 (0x139)
963 #define SPR_HSRR0 (0x13A)
964 #define SPR_BOOKE_IAC3 (0x13A)
965 #define SPR_HSRR1 (0x13B)
966 #define SPR_BOOKE_IAC4 (0x13B)
967 #define SPR_LPCR (0x13C)
968 #define SPR_BOOKE_DAC1 (0x13C)
969 #define SPR_LPIDR (0x13D)
970 #define SPR_DABR2 (0x13D)
971 #define SPR_BOOKE_DAC2 (0x13D)
972 #define SPR_BOOKE_DVC1 (0x13E)
973 #define SPR_BOOKE_DVC2 (0x13F)
974 #define SPR_BOOKE_TSR (0x150)
975 #define SPR_BOOKE_TCR (0x154)
976 #define SPR_BOOKE_IVOR0 (0x190)
977 #define SPR_BOOKE_IVOR1 (0x191)
978 #define SPR_BOOKE_IVOR2 (0x192)
979 #define SPR_BOOKE_IVOR3 (0x193)
980 #define SPR_BOOKE_IVOR4 (0x194)
981 #define SPR_BOOKE_IVOR5 (0x195)
982 #define SPR_BOOKE_IVOR6 (0x196)
983 #define SPR_BOOKE_IVOR7 (0x197)
984 #define SPR_BOOKE_IVOR8 (0x198)
985 #define SPR_BOOKE_IVOR9 (0x199)
986 #define SPR_BOOKE_IVOR10 (0x19A)
987 #define SPR_BOOKE_IVOR11 (0x19B)
988 #define SPR_BOOKE_IVOR12 (0x19C)
989 #define SPR_BOOKE_IVOR13 (0x19D)
990 #define SPR_BOOKE_IVOR14 (0x19E)
991 #define SPR_BOOKE_IVOR15 (0x19F)
992 #define SPR_BOOKE_SPEFSCR (0x200)
993 #define SPR_Exxx_BBEAR (0x201)
994 #define SPR_Exxx_BBTAR (0x202)
995 #define SPR_Exxx_L1CFG0 (0x203)
996 #define SPR_Exxx_NPIDR (0x205)
997 #define SPR_ATBL (0x20E)
998 #define SPR_ATBU (0x20F)
999 #define SPR_IBAT0U (0x210)
1000 #define SPR_BOOKE_IVOR32 (0x210)
1001 #define SPR_RCPU_MI_GRA (0x210)
1002 #define SPR_IBAT0L (0x211)
1003 #define SPR_BOOKE_IVOR33 (0x211)
1004 #define SPR_IBAT1U (0x212)
1005 #define SPR_BOOKE_IVOR34 (0x212)
1006 #define SPR_IBAT1L (0x213)
1007 #define SPR_BOOKE_IVOR35 (0x213)
1008 #define SPR_IBAT2U (0x214)
1009 #define SPR_BOOKE_IVOR36 (0x214)
1010 #define SPR_IBAT2L (0x215)
1011 #define SPR_BOOKE_IVOR37 (0x215)
1012 #define SPR_IBAT3U (0x216)
1013 #define SPR_IBAT3L (0x217)
1014 #define SPR_DBAT0U (0x218)
1015 #define SPR_RCPU_L2U_GRA (0x218)
1016 #define SPR_DBAT0L (0x219)
1017 #define SPR_DBAT1U (0x21A)
1018 #define SPR_DBAT1L (0x21B)
1019 #define SPR_DBAT2U (0x21C)
1020 #define SPR_DBAT2L (0x21D)
1021 #define SPR_DBAT3U (0x21E)
1022 #define SPR_DBAT3L (0x21F)
1023 #define SPR_IBAT4U (0x230)
1024 #define SPR_RPCU_BBCMCR (0x230)
1025 #define SPR_MPC_IC_CST (0x230)
1026 #define SPR_Exxx_CTXCR (0x230)
1027 #define SPR_IBAT4L (0x231)
1028 #define SPR_MPC_IC_ADR (0x231)
1029 #define SPR_Exxx_DBCR3 (0x231)
1030 #define SPR_IBAT5U (0x232)
1031 #define SPR_MPC_IC_DAT (0x232)
1032 #define SPR_Exxx_DBCNT (0x232)
1033 #define SPR_IBAT5L (0x233)
1034 #define SPR_IBAT6U (0x234)
1035 #define SPR_IBAT6L (0x235)
1036 #define SPR_IBAT7U (0x236)
1037 #define SPR_IBAT7L (0x237)
1038 #define SPR_DBAT4U (0x238)
1039 #define SPR_RCPU_L2U_MCR (0x238)
1040 #define SPR_MPC_DC_CST (0x238)
1041 #define SPR_Exxx_ALTCTXCR (0x238)
1042 #define SPR_DBAT4L (0x239)
1043 #define SPR_MPC_DC_ADR (0x239)
1044 #define SPR_DBAT5U (0x23A)
1045 #define SPR_BOOKE_MCSRR0 (0x23A)
1046 #define SPR_MPC_DC_DAT (0x23A)
1047 #define SPR_DBAT5L (0x23B)
1048 #define SPR_BOOKE_MCSRR1 (0x23B)
1049 #define SPR_DBAT6U (0x23C)
1050 #define SPR_BOOKE_MCSR (0x23C)
1051 #define SPR_DBAT6L (0x23D)
1052 #define SPR_Exxx_MCAR (0x23D)
1053 #define SPR_DBAT7U (0x23E)
1054 #define SPR_BOOKE_DSRR0 (0x23E)
1055 #define SPR_DBAT7L (0x23F)
1056 #define SPR_BOOKE_DSRR1 (0x23F)
1057 #define SPR_BOOKE_SPRG8 (0x25C)
1058 #define SPR_BOOKE_SPRG9 (0x25D)
1059 #define SPR_BOOKE_MAS0 (0x270)
1060 #define SPR_BOOKE_MAS1 (0x271)
1061 #define SPR_BOOKE_MAS2 (0x272)
1062 #define SPR_BOOKE_MAS3 (0x273)
1063 #define SPR_BOOKE_MAS4 (0x274)
1064 #define SPR_BOOKE_MAS5 (0x275)
1065 #define SPR_BOOKE_MAS6 (0x276)
1066 #define SPR_BOOKE_PID1 (0x279)
1067 #define SPR_BOOKE_PID2 (0x27A)
1068 #define SPR_MPC_DPDR (0x280)
1069 #define SPR_MPC_IMMR (0x288)
1070 #define SPR_BOOKE_TLB0CFG (0x2B0)
1071 #define SPR_BOOKE_TLB1CFG (0x2B1)
1072 #define SPR_BOOKE_TLB2CFG (0x2B2)
1073 #define SPR_BOOKE_TLB3CFG (0x2B3)
1074 #define SPR_BOOKE_EPR (0x2BE)
1075 #define SPR_PERF0 (0x300)
1076 #define SPR_RCPU_MI_RBA0 (0x300)
1077 #define SPR_MPC_MI_CTR (0x300)
1078 #define SPR_PERF1 (0x301)
1079 #define SPR_RCPU_MI_RBA1 (0x301)
1080 #define SPR_PERF2 (0x302)
1081 #define SPR_RCPU_MI_RBA2 (0x302)
1082 #define SPR_MPC_MI_AP (0x302)
1083 #define SPR_PERF3 (0x303)
1084 #define SPR_620_PMC1R (0x303)
1085 #define SPR_RCPU_MI_RBA3 (0x303)
1086 #define SPR_MPC_MI_EPN (0x303)
1087 #define SPR_PERF4 (0x304)
1088 #define SPR_620_PMC2R (0x304)
1089 #define SPR_PERF5 (0x305)
1090 #define SPR_MPC_MI_TWC (0x305)
1091 #define SPR_PERF6 (0x306)
1092 #define SPR_MPC_MI_RPN (0x306)
1093 #define SPR_PERF7 (0x307)
1094 #define SPR_PERF8 (0x308)
1095 #define SPR_RCPU_L2U_RBA0 (0x308)
1096 #define SPR_MPC_MD_CTR (0x308)
1097 #define SPR_PERF9 (0x309)
1098 #define SPR_RCPU_L2U_RBA1 (0x309)
1099 #define SPR_MPC_MD_CASID (0x309)
1100 #define SPR_PERFA (0x30A)
1101 #define SPR_RCPU_L2U_RBA2 (0x30A)
1102 #define SPR_MPC_MD_AP (0x30A)
1103 #define SPR_PERFB (0x30B)
1104 #define SPR_620_MMCR0R (0x30B)
1105 #define SPR_RCPU_L2U_RBA3 (0x30B)
1106 #define SPR_MPC_MD_EPN (0x30B)
1107 #define SPR_PERFC (0x30C)
1108 #define SPR_MPC_MD_TWB (0x30C)
1109 #define SPR_PERFD (0x30D)
1110 #define SPR_MPC_MD_TWC (0x30D)
1111 #define SPR_PERFE (0x30E)
1112 #define SPR_MPC_MD_RPN (0x30E)
1113 #define SPR_PERFF (0x30F)
1114 #define SPR_MPC_MD_TW (0x30F)
1115 #define SPR_UPERF0 (0x310)
1116 #define SPR_UPERF1 (0x311)
1117 #define SPR_UPERF2 (0x312)
1118 #define SPR_UPERF3 (0x313)
1119 #define SPR_620_PMC1W (0x313)
1120 #define SPR_UPERF4 (0x314)
1121 #define SPR_620_PMC2W (0x314)
1122 #define SPR_UPERF5 (0x315)
1123 #define SPR_UPERF6 (0x316)
1124 #define SPR_UPERF7 (0x317)
1125 #define SPR_UPERF8 (0x318)
1126 #define SPR_UPERF9 (0x319)
1127 #define SPR_UPERFA (0x31A)
1128 #define SPR_UPERFB (0x31B)
1129 #define SPR_620_MMCR0W (0x31B)
1130 #define SPR_UPERFC (0x31C)
1131 #define SPR_UPERFD (0x31D)
1132 #define SPR_UPERFE (0x31E)
1133 #define SPR_UPERFF (0x31F)
1134 #define SPR_RCPU_MI_RA0 (0x320)
1135 #define SPR_MPC_MI_DBCAM (0x320)
1136 #define SPR_RCPU_MI_RA1 (0x321)
1137 #define SPR_MPC_MI_DBRAM0 (0x321)
1138 #define SPR_RCPU_MI_RA2 (0x322)
1139 #define SPR_MPC_MI_DBRAM1 (0x322)
1140 #define SPR_RCPU_MI_RA3 (0x323)
1141 #define SPR_RCPU_L2U_RA0 (0x328)
1142 #define SPR_MPC_MD_DBCAM (0x328)
1143 #define SPR_RCPU_L2U_RA1 (0x329)
1144 #define SPR_MPC_MD_DBRAM0 (0x329)
1145 #define SPR_RCPU_L2U_RA2 (0x32A)
1146 #define SPR_MPC_MD_DBRAM1 (0x32A)
1147 #define SPR_RCPU_L2U_RA3 (0x32B)
1148 #define SPR_440_INV0 (0x370)
1149 #define SPR_440_INV1 (0x371)
1150 #define SPR_440_INV2 (0x372)
1151 #define SPR_440_INV3 (0x373)
1152 #define SPR_440_ITV0 (0x374)
1153 #define SPR_440_ITV1 (0x375)
1154 #define SPR_440_ITV2 (0x376)
1155 #define SPR_440_ITV3 (0x377)
1156 #define SPR_440_CCR1 (0x378)
1157 #define SPR_DCRIPR (0x37B)
1158 #define SPR_PPR (0x380)
1159 #define SPR_750_GQR0 (0x390)
1160 #define SPR_440_DNV0 (0x390)
1161 #define SPR_750_GQR1 (0x391)
1162 #define SPR_440_DNV1 (0x391)
1163 #define SPR_750_GQR2 (0x392)
1164 #define SPR_440_DNV2 (0x392)
1165 #define SPR_750_GQR3 (0x393)
1166 #define SPR_440_DNV3 (0x393)
1167 #define SPR_750_GQR4 (0x394)
1168 #define SPR_440_DTV0 (0x394)
1169 #define SPR_750_GQR5 (0x395)
1170 #define SPR_440_DTV1 (0x395)
1171 #define SPR_750_GQR6 (0x396)
1172 #define SPR_440_DTV2 (0x396)
1173 #define SPR_750_GQR7 (0x397)
1174 #define SPR_440_DTV3 (0x397)
1175 #define SPR_750_THRM4 (0x398)
1176 #define SPR_750CL_HID2 (0x398)
1177 #define SPR_440_DVLIM (0x398)
1178 #define SPR_750_WPAR (0x399)
1179 #define SPR_440_IVLIM (0x399)
1180 #define SPR_750_DMAU (0x39A)
1181 #define SPR_750_DMAL (0x39B)
1182 #define SPR_440_RSTCFG (0x39B)
1183 #define SPR_BOOKE_DCDBTRL (0x39C)
1184 #define SPR_BOOKE_DCDBTRH (0x39D)
1185 #define SPR_BOOKE_ICDBTRL (0x39E)
1186 #define SPR_BOOKE_ICDBTRH (0x39F)
1187 #define SPR_UMMCR2 (0x3A0)
1188 #define SPR_UPMC5 (0x3A1)
1189 #define SPR_UPMC6 (0x3A2)
1190 #define SPR_UBAMR (0x3A7)
1191 #define SPR_UMMCR0 (0x3A8)
1192 #define SPR_UPMC1 (0x3A9)
1193 #define SPR_UPMC2 (0x3AA)
1194 #define SPR_USIAR (0x3AB)
1195 #define SPR_UMMCR1 (0x3AC)
1196 #define SPR_UPMC3 (0x3AD)
1197 #define SPR_UPMC4 (0x3AE)
1198 #define SPR_USDA (0x3AF)
1199 #define SPR_40x_ZPR (0x3B0)
1200 #define SPR_BOOKE_MAS7 (0x3B0)
1201 #define SPR_620_PMR0 (0x3B0)
1202 #define SPR_MMCR2 (0x3B0)
1203 #define SPR_PMC5 (0x3B1)
1204 #define SPR_40x_PID (0x3B1)
1205 #define SPR_620_PMR1 (0x3B1)
1206 #define SPR_PMC6 (0x3B2)
1207 #define SPR_440_MMUCR (0x3B2)
1208 #define SPR_620_PMR2 (0x3B2)
1209 #define SPR_4xx_CCR0 (0x3B3)
1210 #define SPR_BOOKE_EPLC (0x3B3)
1211 #define SPR_620_PMR3 (0x3B3)
1212 #define SPR_405_IAC3 (0x3B4)
1213 #define SPR_BOOKE_EPSC (0x3B4)
1214 #define SPR_620_PMR4 (0x3B4)
1215 #define SPR_405_IAC4 (0x3B5)
1216 #define SPR_620_PMR5 (0x3B5)
1217 #define SPR_405_DVC1 (0x3B6)
1218 #define SPR_620_PMR6 (0x3B6)
1219 #define SPR_405_DVC2 (0x3B7)
1220 #define SPR_620_PMR7 (0x3B7)
1221 #define SPR_BAMR (0x3B7)
1222 #define SPR_MMCR0 (0x3B8)
1223 #define SPR_620_PMR8 (0x3B8)
1224 #define SPR_PMC1 (0x3B9)
1225 #define SPR_40x_SGR (0x3B9)
1226 #define SPR_620_PMR9 (0x3B9)
1227 #define SPR_PMC2 (0x3BA)
1228 #define SPR_40x_DCWR (0x3BA)
1229 #define SPR_620_PMRA (0x3BA)
1230 #define SPR_SIAR (0x3BB)
1231 #define SPR_405_SLER (0x3BB)
1232 #define SPR_620_PMRB (0x3BB)
1233 #define SPR_MMCR1 (0x3BC)
1234 #define SPR_405_SU0R (0x3BC)
1235 #define SPR_620_PMRC (0x3BC)
1236 #define SPR_401_SKR (0x3BC)
1237 #define SPR_PMC3 (0x3BD)
1238 #define SPR_405_DBCR1 (0x3BD)
1239 #define SPR_620_PMRD (0x3BD)
1240 #define SPR_PMC4 (0x3BE)
1241 #define SPR_620_PMRE (0x3BE)
1242 #define SPR_SDA (0x3BF)
1243 #define SPR_620_PMRF (0x3BF)
1244 #define SPR_403_VTBL (0x3CC)
1245 #define SPR_403_VTBU (0x3CD)
1246 #define SPR_DMISS (0x3D0)
1247 #define SPR_DCMP (0x3D1)
1248 #define SPR_HASH1 (0x3D2)
1249 #define SPR_HASH2 (0x3D3)
1250 #define SPR_BOOKE_ICDBDR (0x3D3)
1251 #define SPR_TLBMISS (0x3D4)
1252 #define SPR_IMISS (0x3D4)
1253 #define SPR_40x_ESR (0x3D4)
1254 #define SPR_PTEHI (0x3D5)
1255 #define SPR_ICMP (0x3D5)
1256 #define SPR_40x_DEAR (0x3D5)
1257 #define SPR_PTELO (0x3D6)
1258 #define SPR_RPA (0x3D6)
1259 #define SPR_40x_EVPR (0x3D6)
1260 #define SPR_L3PM (0x3D7)
1261 #define SPR_403_CDBCR (0x3D7)
1262 #define SPR_L3ITCR0 (0x3D8)
1263 #define SPR_TCR (0x3D8)
1264 #define SPR_40x_TSR (0x3D8)
1265 #define SPR_IBR (0x3DA)
1266 #define SPR_40x_TCR (0x3DA)
1267 #define SPR_ESASRR (0x3DB)
1268 #define SPR_40x_PIT (0x3DB)
1269 #define SPR_403_TBL (0x3DC)
1270 #define SPR_403_TBU (0x3DD)
1271 #define SPR_SEBR (0x3DE)
1272 #define SPR_40x_SRR2 (0x3DE)
1273 #define SPR_SER (0x3DF)
1274 #define SPR_40x_SRR3 (0x3DF)
1275 #define SPR_L3OHCR (0x3E8)
1276 #define SPR_L3ITCR1 (0x3E9)
1277 #define SPR_L3ITCR2 (0x3EA)
1278 #define SPR_L3ITCR3 (0x3EB)
1279 #define SPR_HID0 (0x3F0)
1280 #define SPR_40x_DBSR (0x3F0)
1281 #define SPR_HID1 (0x3F1)
1282 #define SPR_IABR (0x3F2)
1283 #define SPR_40x_DBCR0 (0x3F2)
1284 #define SPR_601_HID2 (0x3F2)
1285 #define SPR_Exxx_L1CSR0 (0x3F2)
1286 #define SPR_ICTRL (0x3F3)
1287 #define SPR_HID2 (0x3F3)
1288 #define SPR_750CL_HID4 (0x3F3)
1289 #define SPR_Exxx_L1CSR1 (0x3F3)
1290 #define SPR_440_DBDR (0x3F3)
1291 #define SPR_LDSTDB (0x3F4)
1292 #define SPR_750_TDCL (0x3F4)
1293 #define SPR_40x_IAC1 (0x3F4)
1294 #define SPR_MMUCSR0 (0x3F4)
1295 #define SPR_DABR (0x3F5)
1296 #define DABR_MASK (~(target_ulong)0x7)
1297 #define SPR_Exxx_BUCSR (0x3F5)
1298 #define SPR_40x_IAC2 (0x3F5)
1299 #define SPR_601_HID5 (0x3F5)
1300 #define SPR_40x_DAC1 (0x3F6)
1301 #define SPR_MSSCR0 (0x3F6)
1302 #define SPR_970_HID5 (0x3F6)
1303 #define SPR_MSSSR0 (0x3F7)
1304 #define SPR_MSSCR1 (0x3F7)
1305 #define SPR_DABRX (0x3F7)
1306 #define SPR_40x_DAC2 (0x3F7)
1307 #define SPR_MMUCFG (0x3F7)
1308 #define SPR_LDSTCR (0x3F8)
1309 #define SPR_L2PMCR (0x3F8)
1310 #define SPR_750FX_HID2 (0x3F8)
1311 #define SPR_620_BUSCSR (0x3F8)
1312 #define SPR_Exxx_L1FINV0 (0x3F8)
1313 #define SPR_L2CR (0x3F9)
1314 #define SPR_620_L2CR (0x3F9)
1315 #define SPR_L3CR (0x3FA)
1316 #define SPR_750_TDCH (0x3FA)
1317 #define SPR_IABR2 (0x3FA)
1318 #define SPR_40x_DCCR (0x3FA)
1319 #define SPR_620_L2SR (0x3FA)
1320 #define SPR_ICTC (0x3FB)
1321 #define SPR_40x_ICCR (0x3FB)
1322 #define SPR_THRM1 (0x3FC)
1323 #define SPR_403_PBL1 (0x3FC)
1324 #define SPR_SP (0x3FD)
1325 #define SPR_THRM2 (0x3FD)
1326 #define SPR_403_PBU1 (0x3FD)
1327 #define SPR_604_HID13 (0x3FD)
1328 #define SPR_LT (0x3FE)
1329 #define SPR_THRM3 (0x3FE)
1330 #define SPR_RCPU_FPECR (0x3FE)
1331 #define SPR_403_PBL2 (0x3FE)
1332 #define SPR_PIR (0x3FF)
1333 #define SPR_403_PBU2 (0x3FF)
1334 #define SPR_601_HID15 (0x3FF)
1335 #define SPR_604_HID15 (0x3FF)
1336 #define SPR_E500_SVR (0x3FF)
1337
1338 /*****************************************************************************/
1339 /* PowerPC Instructions types definitions */
1340 enum {
1341 PPC_NONE = 0x0000000000000000ULL,
1342 /* PowerPC base instructions set */
1343 PPC_INSNS_BASE = 0x0000000000000001ULL,
1344 /* integer operations instructions */
1345 #define PPC_INTEGER PPC_INSNS_BASE
1346 /* flow control instructions */
1347 #define PPC_FLOW PPC_INSNS_BASE
1348 /* virtual memory instructions */
1349 #define PPC_MEM PPC_INSNS_BASE
1350 /* ld/st with reservation instructions */
1351 #define PPC_RES PPC_INSNS_BASE
1352 /* spr/msr access instructions */
1353 #define PPC_MISC PPC_INSNS_BASE
1354 /* Deprecated instruction sets */
1355 /* Original POWER instruction set */
1356 PPC_POWER = 0x0000000000000002ULL,
1357 /* POWER2 instruction set extension */
1358 PPC_POWER2 = 0x0000000000000004ULL,
1359 /* Power RTC support */
1360 PPC_POWER_RTC = 0x0000000000000008ULL,
1361 /* Power-to-PowerPC bridge (601) */
1362 PPC_POWER_BR = 0x0000000000000010ULL,
1363 /* 64 bits PowerPC instruction set */
1364 PPC_64B = 0x0000000000000020ULL,
1365 /* New 64 bits extensions (PowerPC 2.0x) */
1366 PPC_64BX = 0x0000000000000040ULL,
1367 /* 64 bits hypervisor extensions */
1368 PPC_64H = 0x0000000000000080ULL,
1369 /* New wait instruction (PowerPC 2.0x) */
1370 PPC_WAIT = 0x0000000000000100ULL,
1371 /* Time base mftb instruction */
1372 PPC_MFTB = 0x0000000000000200ULL,
1373
1374 /* Fixed-point unit extensions */
1375 /* PowerPC 602 specific */
1376 PPC_602_SPEC = 0x0000000000000400ULL,
1377 /* isel instruction */
1378 PPC_ISEL = 0x0000000000000800ULL,
1379 /* popcntb instruction */
1380 PPC_POPCNTB = 0x0000000000001000ULL,
1381 /* string load / store */
1382 PPC_STRING = 0x0000000000002000ULL,
1383
1384 /* Floating-point unit extensions */
1385 /* Optional floating point instructions */
1386 PPC_FLOAT = 0x0000000000010000ULL,
1387 /* New floating-point extensions (PowerPC 2.0x) */
1388 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1389 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1390 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1391 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1392 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1393 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1394 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1395
1396 /* Vector/SIMD extensions */
1397 /* Altivec support */
1398 PPC_ALTIVEC = 0x0000000001000000ULL,
1399 /* PowerPC 2.03 SPE extension */
1400 PPC_SPE = 0x0000000002000000ULL,
1401 /* PowerPC 2.03 SPE single-precision floating-point extension */
1402 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1403 /* PowerPC 2.03 SPE double-precision floating-point extension */
1404 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1405
1406 /* Optional memory control instructions */
1407 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1408 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1409 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1410 /* sync instruction */
1411 PPC_MEM_SYNC = 0x0000000080000000ULL,
1412 /* eieio instruction */
1413 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1414
1415 /* Cache control instructions */
1416 PPC_CACHE = 0x0000000200000000ULL,
1417 /* icbi instruction */
1418 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1419 /* dcbz instruction with fixed cache line size */
1420 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1421 /* dcbz instruction with tunable cache line size */
1422 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1423 /* dcba instruction */
1424 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1425 /* Freescale cache locking instructions */
1426 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1427
1428 /* MMU related extensions */
1429 /* external control instructions */
1430 PPC_EXTERN = 0x0000010000000000ULL,
1431 /* segment register access instructions */
1432 PPC_SEGMENT = 0x0000020000000000ULL,
1433 /* PowerPC 6xx TLB management instructions */
1434 PPC_6xx_TLB = 0x0000040000000000ULL,
1435 /* PowerPC 74xx TLB management instructions */
1436 PPC_74xx_TLB = 0x0000080000000000ULL,
1437 /* PowerPC 40x TLB management instructions */
1438 PPC_40x_TLB = 0x0000100000000000ULL,
1439 /* segment register access instructions for PowerPC 64 "bridge" */
1440 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1441 /* SLB management */
1442 PPC_SLBI = 0x0000400000000000ULL,
1443
1444 /* Embedded PowerPC dedicated instructions */
1445 PPC_WRTEE = 0x0001000000000000ULL,
1446 /* PowerPC 40x exception model */
1447 PPC_40x_EXCP = 0x0002000000000000ULL,
1448 /* PowerPC 405 Mac instructions */
1449 PPC_405_MAC = 0x0004000000000000ULL,
1450 /* PowerPC 440 specific instructions */
1451 PPC_440_SPEC = 0x0008000000000000ULL,
1452 /* BookE (embedded) PowerPC specification */
1453 PPC_BOOKE = 0x0010000000000000ULL,
1454 /* mfapidi instruction */
1455 PPC_MFAPIDI = 0x0020000000000000ULL,
1456 /* tlbiva instruction */
1457 PPC_TLBIVA = 0x0040000000000000ULL,
1458 /* tlbivax instruction */
1459 PPC_TLBIVAX = 0x0080000000000000ULL,
1460 /* PowerPC 4xx dedicated instructions */
1461 PPC_4xx_COMMON = 0x0100000000000000ULL,
1462 /* PowerPC 40x ibct instructions */
1463 PPC_40x_ICBT = 0x0200000000000000ULL,
1464 /* rfmci is not implemented in all BookE PowerPC */
1465 PPC_RFMCI = 0x0400000000000000ULL,
1466 /* rfdi instruction */
1467 PPC_RFDI = 0x0800000000000000ULL,
1468 /* DCR accesses */
1469 PPC_DCR = 0x1000000000000000ULL,
1470 /* DCR extended accesse */
1471 PPC_DCRX = 0x2000000000000000ULL,
1472 /* user-mode DCR access, implemented in PowerPC 460 */
1473 PPC_DCRUX = 0x4000000000000000ULL,
1474 };
1475
1476 /*****************************************************************************/
1477 /* Memory access type :
1478 * may be needed for precise access rights control and precise exceptions.
1479 */
1480 enum {
1481 /* 1 bit to define user level / supervisor access */
1482 ACCESS_USER = 0x00,
1483 ACCESS_SUPER = 0x01,
1484 /* Type of instruction that generated the access */
1485 ACCESS_CODE = 0x10, /* Code fetch access */
1486 ACCESS_INT = 0x20, /* Integer load/store access */
1487 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1488 ACCESS_RES = 0x40, /* load/store with reservation */
1489 ACCESS_EXT = 0x50, /* external access */
1490 ACCESS_CACHE = 0x60, /* Cache manipulation */
1491 };
1492
1493 /* Hardware interruption sources:
1494 * all those exception can be raised simulteaneously
1495 */
1496 /* Input pins definitions */
1497 enum {
1498 /* 6xx bus input pins */
1499 PPC6xx_INPUT_HRESET = 0,
1500 PPC6xx_INPUT_SRESET = 1,
1501 PPC6xx_INPUT_CKSTP_IN = 2,
1502 PPC6xx_INPUT_MCP = 3,
1503 PPC6xx_INPUT_SMI = 4,
1504 PPC6xx_INPUT_INT = 5,
1505 PPC6xx_INPUT_TBEN = 6,
1506 PPC6xx_INPUT_WAKEUP = 7,
1507 PPC6xx_INPUT_NB,
1508 };
1509
1510 enum {
1511 /* Embedded PowerPC input pins */
1512 PPCBookE_INPUT_HRESET = 0,
1513 PPCBookE_INPUT_SRESET = 1,
1514 PPCBookE_INPUT_CKSTP_IN = 2,
1515 PPCBookE_INPUT_MCP = 3,
1516 PPCBookE_INPUT_SMI = 4,
1517 PPCBookE_INPUT_INT = 5,
1518 PPCBookE_INPUT_CINT = 6,
1519 PPCBookE_INPUT_NB,
1520 };
1521
1522 enum {
1523 /* PowerPC E500 input pins */
1524 PPCE500_INPUT_RESET_CORE = 0,
1525 PPCE500_INPUT_MCK = 1,
1526 PPCE500_INPUT_CINT = 3,
1527 PPCE500_INPUT_INT = 4,
1528 PPCE500_INPUT_DEBUG = 6,
1529 PPCE500_INPUT_NB,
1530 };
1531
1532 enum {
1533 /* PowerPC 40x input pins */
1534 PPC40x_INPUT_RESET_CORE = 0,
1535 PPC40x_INPUT_RESET_CHIP = 1,
1536 PPC40x_INPUT_RESET_SYS = 2,
1537 PPC40x_INPUT_CINT = 3,
1538 PPC40x_INPUT_INT = 4,
1539 PPC40x_INPUT_HALT = 5,
1540 PPC40x_INPUT_DEBUG = 6,
1541 PPC40x_INPUT_NB,
1542 };
1543
1544 enum {
1545 /* RCPU input pins */
1546 PPCRCPU_INPUT_PORESET = 0,
1547 PPCRCPU_INPUT_HRESET = 1,
1548 PPCRCPU_INPUT_SRESET = 2,
1549 PPCRCPU_INPUT_IRQ0 = 3,
1550 PPCRCPU_INPUT_IRQ1 = 4,
1551 PPCRCPU_INPUT_IRQ2 = 5,
1552 PPCRCPU_INPUT_IRQ3 = 6,
1553 PPCRCPU_INPUT_IRQ4 = 7,
1554 PPCRCPU_INPUT_IRQ5 = 8,
1555 PPCRCPU_INPUT_IRQ6 = 9,
1556 PPCRCPU_INPUT_IRQ7 = 10,
1557 PPCRCPU_INPUT_NB,
1558 };
1559
1560 #if defined(TARGET_PPC64)
1561 enum {
1562 /* PowerPC 970 input pins */
1563 PPC970_INPUT_HRESET = 0,
1564 PPC970_INPUT_SRESET = 1,
1565 PPC970_INPUT_CKSTP = 2,
1566 PPC970_INPUT_TBEN = 3,
1567 PPC970_INPUT_MCP = 4,
1568 PPC970_INPUT_INT = 5,
1569 PPC970_INPUT_THINT = 6,
1570 PPC970_INPUT_NB,
1571 };
1572 #endif
1573
1574 /* Hardware exceptions definitions */
1575 enum {
1576 /* External hardware exception sources */
1577 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1578 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1579 PPC_INTERRUPT_MCK, /* Machine check exception */
1580 PPC_INTERRUPT_EXT, /* External interrupt */
1581 PPC_INTERRUPT_SMI, /* System management interrupt */
1582 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1583 PPC_INTERRUPT_DEBUG, /* External debug exception */
1584 PPC_INTERRUPT_THERM, /* Thermal exception */
1585 /* Internal hardware exception sources */
1586 PPC_INTERRUPT_DECR, /* Decrementer exception */
1587 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1588 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1589 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1590 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1591 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1592 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1593 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
1594 };
1595
1596 /*****************************************************************************/
1597
1598 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
1599 {
1600 env->nip = tb->pc;
1601 }
1602
1603 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1604 target_ulong *cs_base, int *flags)
1605 {
1606 *pc = env->nip;
1607 *cs_base = 0;
1608 *flags = env->hflags;
1609 }
1610
1611 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
1612 {
1613 #if defined(TARGET_PPC64)
1614 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
1615 binaries on PPC64 yet. */
1616 env->gpr[13] = newtls;
1617 #else
1618 env->gpr[2] = newtls;
1619 #endif
1620 }
1621
1622 #endif /* !defined (__CPU_PPC_H__) */
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