target-ppc/excp_helper.c

   1 /*
   2  *  PowerPC exception emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #include "helper_regs.h"
  26
  27 //#define DEBUG_OP
  28 //#define DEBUG_SOFTWARE_TLB
  29 //#define DEBUG_EXCEPTIONS
  30
  31 #ifdef DEBUG_EXCEPTIONS
  32 #  define LOG_EXCP(...) qemu_log(__VA_ARGS__)
  33 #else
  34 #  define LOG_EXCP(...) do { } while (0)
  35 #endif
  36
  37 /*****************************************************************************/
  38 /* PowerPC Hypercall emulation */
  39
  40 void (*cpu_ppc_hypercall)(PowerPCCPU *);
  41
  42 /*****************************************************************************/
  43 /* Exception processing */
  44 #if defined(CONFIG_USER_ONLY)
  45 void ppc_cpu_do_interrupt(CPUState *cs)
  46 {
  47     PowerPCCPU *cpu = POWERPC_CPU(cs);
  48     CPUPPCState *env = &cpu->env;
  49
  50     cs->exception_index = POWERPC_EXCP_NONE;
  51     env->error_code = 0;
  52 }
  53
  54 static void ppc_hw_interrupt(CPUPPCState *env)
  55 {
  56     CPUState *cs = CPU(ppc_env_get_cpu(env));
  57
  58     cs->exception_index = POWERPC_EXCP_NONE;
  59     env->error_code = 0;
  60 }
  61 #else /* defined(CONFIG_USER_ONLY) */
  62 static inline void dump_syscall(CPUPPCState *env)
  63 {
  64     qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
  65                   " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
  66                   " nip=" TARGET_FMT_lx "\n",
  67                   ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
  68                   ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
  69                   ppc_dump_gpr(env, 6), env->nip);
  70 }
  71
  72 /* Note that this function should be greatly optimized
  73  * when called with a constant excp, from ppc_hw_interrupt
  74  */
  75 static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
  76 {
  77     CPUState *cs = CPU(cpu);
  78     CPUPPCState *env = &cpu->env;
  79     target_ulong msr, new_msr, vector;
  80     int srr0, srr1, asrr0, asrr1, lev, ail;
  81     bool lpes0;
  82
  83     qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
  84                   " => %08x (%02x)\n", env->nip, excp, env->error_code);
  85
  86     /* new srr1 value excluding must-be-zero bits */
  87     if (excp_model == POWERPC_EXCP_BOOKE) {
  88         msr = env->msr;
  89     } else {
  90         msr = env->msr & ~0x783f0000ULL;
  91     }
  92
  93     /* new interrupt handler msr preserves existing HV and ME unless
  94      * explicitly overriden
  95      */
  96     new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
  97
  98     /* target registers */
  99     srr0 = SPR_SRR0;
 100     srr1 = SPR_SRR1;
 101     asrr0 = -1;
 102     asrr1 = -1;
 103
 104     /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */
 105     if (env->in_pm_state) {
 106         env->in_pm_state = false;
 107
 108         /* Pretend to be returning from doze always as we don't lose state */
 109         msr |= (0x1ull << (63 - 47));
 110
 111         /* Non-machine check are routed to 0x100 with a wakeup cause
 112          * encoded in SRR1
 113          */
 114         if (excp != POWERPC_EXCP_MCHECK) {
 115             switch (excp) {
 116             case POWERPC_EXCP_RESET:
 117                 msr |= 0x4ull << (63 - 45);
 118                 break;
 119             case POWERPC_EXCP_EXTERNAL:
 120                 msr |= 0x8ull << (63 - 45);
 121                 break;
 122             case POWERPC_EXCP_DECR:
 123                 msr |= 0x6ull << (63 - 45);
 124                 break;
 125             case POWERPC_EXCP_SDOOR:
 126                 msr |= 0x5ull << (63 - 45);
 127                 break;
 128             case POWERPC_EXCP_SDOOR_HV:
 129                 msr |= 0x3ull << (63 - 45);
 130                 break;
 131             case POWERPC_EXCP_HV_MAINT:
 132                 msr |= 0xaull << (63 - 45);
 133                 break;
 134             default:
 135                 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
 136                           excp);
 137             }
 138             excp = POWERPC_EXCP_RESET;
 139         }
 140     }
 141
 142     /* Exception targetting modifiers
 143      *
 144      * LPES0 is supported on POWER7/8
 145      * LPES1 is not supported (old iSeries mode)
 146      *
 147      * On anything else, we behave as if LPES0 is 1
 148      * (externals don't alter MSR:HV)
 149      *
 150      * AIL is initialized here but can be cleared by
 151      * selected exceptions
 152      */
 153 #if defined(TARGET_PPC64)
 154     if (excp_model == POWERPC_EXCP_POWER7 ||
 155         excp_model == POWERPC_EXCP_POWER8) {
 156         lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 157         if (excp_model == POWERPC_EXCP_POWER8) {
 158             ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
 159         } else {
 160             ail = 0;
 161         }
 162     } else
 163 #endif /* defined(TARGET_PPC64) */
 164     {
 165         lpes0 = true;
 166         ail = 0;
 167     }
 168
 169     /* Hypervisor emulation assistance interrupt only exists on server
 170      * arch 2.05 server or later. We also don't want to generate it if
 171      * we don't have HVB in msr_mask (PAPR mode).
 172      */
 173     if (excp == POWERPC_EXCP_HV_EMU
 174 #if defined(TARGET_PPC64)
 175         && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB))
 176 #endif /* defined(TARGET_PPC64) */
 177
 178     ) {
 179         excp = POWERPC_EXCP_PROGRAM;
 180     }
 181
 182     switch (excp) {
 183     case POWERPC_EXCP_NONE:
 184         /* Should never happen */
 185         return;
 186     case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
 187         switch (excp_model) {
 188         case POWERPC_EXCP_40x:
 189             srr0 = SPR_40x_SRR2;
 190             srr1 = SPR_40x_SRR3;
 191             break;
 192         case POWERPC_EXCP_BOOKE:
 193             srr0 = SPR_BOOKE_CSRR0;
 194             srr1 = SPR_BOOKE_CSRR1;
 195             break;
 196         case POWERPC_EXCP_G2:
 197             break;
 198         default:
 199             goto excp_invalid;
 200         }
 201         break;
 202     case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
 203         if (msr_me == 0) {
 204             /* Machine check exception is not enabled.
 205              * Enter checkstop state.
 206              */
 207             fprintf(stderr, "Machine check while not allowed. "
 208                     "Entering checkstop state\n");
 209             if (qemu_log_separate()) {
 210                 qemu_log("Machine check while not allowed. "
 211                         "Entering checkstop state\n");
 212             }
 213             cs->halted = 1;
 214             cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 215         }
 216         new_msr |= (target_ulong)MSR_HVB;
 217         ail = 0;
 218
 219         /* machine check exceptions don't have ME set */
 220         new_msr &= ~((target_ulong)1 << MSR_ME);
 221
 222         /* XXX: should also have something loaded in DAR / DSISR */
 223         switch (excp_model) {
 224         case POWERPC_EXCP_40x:
 225             srr0 = SPR_40x_SRR2;
 226             srr1 = SPR_40x_SRR3;
 227             break;
 228         case POWERPC_EXCP_BOOKE:
 229             /* FIXME: choose one or the other based on CPU type */
 230             srr0 = SPR_BOOKE_MCSRR0;
 231             srr1 = SPR_BOOKE_MCSRR1;
 232             asrr0 = SPR_BOOKE_CSRR0;
 233             asrr1 = SPR_BOOKE_CSRR1;
 234             break;
 235         default:
 236             break;
 237         }
 238         break;
 239     case POWERPC_EXCP_DSI:       /* Data storage exception                   */
 240         LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
 241                  "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
 242         break;
 243     case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
 244         LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
 245                  "\n", msr, env->nip);
 246         msr |= env->error_code;
 247         break;
 248     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
 249         cs = CPU(cpu);
 250
 251         if (!lpes0) {
 252             new_msr |= (target_ulong)MSR_HVB;
 253             new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 254             srr0 = SPR_HSRR0;
 255             srr1 = SPR_HSRR1;
 256         }
 257         if (env->mpic_proxy) {
 258             /* IACK the IRQ on delivery */
 259             env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
 260         }
 261         break;
 262     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
 263         /* XXX: this is false */
 264         /* Get rS/rD and rA from faulting opcode */
 265         /* Broken for LE mode */
 266         env->spr[SPR_DSISR] |= (cpu_ldl_code(env, env->nip)
 267                                 & 0x03FF0000) >> 16;
 268         break;
 269     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
 270         switch (env->error_code & ~0xF) {
 271         case POWERPC_EXCP_FP:
 272             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
 273                 LOG_EXCP("Ignore floating point exception\n");
 274                 cs->exception_index = POWERPC_EXCP_NONE;
 275                 env->error_code = 0;
 276                 return;
 277             }
 278
 279             /* FP exceptions always have NIP pointing to the faulting
 280              * instruction, so always use store_next and claim we are
 281              * precise in the MSR.
 282              */
 283             msr |= 0x00100000;
 284             break;
 285         case POWERPC_EXCP_INVAL:
 286             LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
 287             msr |= 0x00080000;
 288             env->spr[SPR_BOOKE_ESR] = ESR_PIL;
 289             break;
 290         case POWERPC_EXCP_PRIV:
 291             msr |= 0x00040000;
 292             env->spr[SPR_BOOKE_ESR] = ESR_PPR;
 293             break;
 294         case POWERPC_EXCP_TRAP:
 295             msr |= 0x00020000;
 296             env->spr[SPR_BOOKE_ESR] = ESR_PTR;
 297             break;
 298         default:
 299             /* Should never occur */
 300             cpu_abort(cs, "Invalid program exception %d. Aborting\n",
 301                       env->error_code);
 302             break;
 303         }
 304         break;
 305     case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
 306         dump_syscall(env);
 307         lev = env->error_code;
 308
 309         /* We need to correct the NIP which in this case is supposed
 310          * to point to the next instruction
 311          */
 312         env->nip += 4;
 313
 314         /* "PAPR mode" built-in hypercall emulation */
 315         if ((lev == 1) && cpu_ppc_hypercall) {
 316             cpu_ppc_hypercall(cpu);
 317             return;
 318         }
 319         if (lev == 1) {
 320             new_msr |= (target_ulong)MSR_HVB;
 321         }
 322         break;
 323     case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
 324     case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
 325     case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
 326         break;
 327     case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
 328         /* FIT on 4xx */
 329         LOG_EXCP("FIT exception\n");
 330         break;
 331     case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
 332         LOG_EXCP("WDT exception\n");
 333         switch (excp_model) {
 334         case POWERPC_EXCP_BOOKE:
 335             srr0 = SPR_BOOKE_CSRR0;
 336             srr1 = SPR_BOOKE_CSRR1;
 337             break;
 338         default:
 339             break;
 340         }
 341         break;
 342     case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
 343     case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
 344         break;
 345     case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
 346         switch (excp_model) {
 347         case POWERPC_EXCP_BOOKE:
 348             /* FIXME: choose one or the other based on CPU type */
 349             srr0 = SPR_BOOKE_DSRR0;
 350             srr1 = SPR_BOOKE_DSRR1;
 351             asrr0 = SPR_BOOKE_CSRR0;
 352             asrr1 = SPR_BOOKE_CSRR1;
 353             break;
 354         default:
 355             break;
 356         }
 357         /* XXX: TODO */
 358         cpu_abort(cs, "Debug exception is not implemented yet !\n");
 359         break;
 360     case POWERPC_EXCP_SPEU:      /* SPE/embedded floating-point unavailable  */
 361         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 362         break;
 363     case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
 364         /* XXX: TODO */
 365         cpu_abort(cs, "Embedded floating point data exception "
 366                   "is not implemented yet !\n");
 367         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 368         break;
 369     case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
 370         /* XXX: TODO */
 371         cpu_abort(cs, "Embedded floating point round exception "
 372                   "is not implemented yet !\n");
 373         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 374         break;
 375     case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
 376         /* XXX: TODO */
 377         cpu_abort(cs,
 378                   "Performance counter exception is not implemented yet !\n");
 379         break;
 380     case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
 381         break;
 382     case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
 383         srr0 = SPR_BOOKE_CSRR0;
 384         srr1 = SPR_BOOKE_CSRR1;
 385         break;
 386     case POWERPC_EXCP_RESET:     /* System reset exception                   */
 387         if (msr_pow) {
 388             /* indicate that we resumed from power save mode */
 389             msr |= 0x10000;
 390         } else {
 391             new_msr &= ~((target_ulong)1 << MSR_ME);
 392         }
 393
 394         new_msr |= (target_ulong)MSR_HVB;
 395         ail = 0;
 396         break;
 397     case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
 398     case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
 399     case POWERPC_EXCP_TRACE:     /* Trace exception                          */
 400         break;
 401     case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
 402     case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
 403     case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
 404     case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
 405     case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
 406     case POWERPC_EXCP_HV_EMU:
 407         srr0 = SPR_HSRR0;
 408         srr1 = SPR_HSRR1;
 409         new_msr |= (target_ulong)MSR_HVB;
 410         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 411         break;
 412     case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
 413     case POWERPC_EXCP_VSXU:       /* VSX unavailable exception               */
 414     case POWERPC_EXCP_FU:         /* Facility unavailable exception          */
 415         break;
 416     case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
 417         LOG_EXCP("PIT exception\n");
 418         break;
 419     case POWERPC_EXCP_IO:        /* IO error exception                       */
 420         /* XXX: TODO */
 421         cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
 422         break;
 423     case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
 424         /* XXX: TODO */
 425         cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
 426         break;
 427     case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
 428         /* XXX: TODO */
 429         cpu_abort(cs, "602 emulation trap exception "
 430                   "is not implemented yet !\n");
 431         break;
 432     case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
 433         switch (excp_model) {
 434         case POWERPC_EXCP_602:
 435         case POWERPC_EXCP_603:
 436         case POWERPC_EXCP_603E:
 437         case POWERPC_EXCP_G2:
 438             goto tlb_miss_tgpr;
 439         case POWERPC_EXCP_7x5:
 440             goto tlb_miss;
 441         case POWERPC_EXCP_74xx:
 442             goto tlb_miss_74xx;
 443         default:
 444             cpu_abort(cs, "Invalid instruction TLB miss exception\n");
 445             break;
 446         }
 447         break;
 448     case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
 449         switch (excp_model) {
 450         case POWERPC_EXCP_602:
 451         case POWERPC_EXCP_603:
 452         case POWERPC_EXCP_603E:
 453         case POWERPC_EXCP_G2:
 454             goto tlb_miss_tgpr;
 455         case POWERPC_EXCP_7x5:
 456             goto tlb_miss;
 457         case POWERPC_EXCP_74xx:
 458             goto tlb_miss_74xx;
 459         default:
 460             cpu_abort(cs, "Invalid data load TLB miss exception\n");
 461             break;
 462         }
 463         break;
 464     case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
 465         switch (excp_model) {
 466         case POWERPC_EXCP_602:
 467         case POWERPC_EXCP_603:
 468         case POWERPC_EXCP_603E:
 469         case POWERPC_EXCP_G2:
 470         tlb_miss_tgpr:
 471             /* Swap temporary saved registers with GPRs */
 472             if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
 473                 new_msr |= (target_ulong)1 << MSR_TGPR;
 474                 hreg_swap_gpr_tgpr(env);
 475             }
 476             goto tlb_miss;
 477         case POWERPC_EXCP_7x5:
 478         tlb_miss:
 479 #if defined(DEBUG_SOFTWARE_TLB)
 480             if (qemu_log_enabled()) {
 481                 const char *es;
 482                 target_ulong *miss, *cmp;
 483                 int en;
 484
 485                 if (excp == POWERPC_EXCP_IFTLB) {
 486                     es = "I";
 487                     en = 'I';
 488                     miss = &env->spr[SPR_IMISS];
 489                     cmp = &env->spr[SPR_ICMP];
 490                 } else {
 491                     if (excp == POWERPC_EXCP_DLTLB) {
 492                         es = "DL";
 493                     } else {
 494                         es = "DS";
 495                     }
 496                     en = 'D';
 497                     miss = &env->spr[SPR_DMISS];
 498                     cmp = &env->spr[SPR_DCMP];
 499                 }
 500                 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
 501                          TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
 502                          TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
 503                          env->spr[SPR_HASH1], env->spr[SPR_HASH2],
 504                          env->error_code);
 505             }
 506 #endif
 507             msr |= env->crf[0] << 28;
 508             msr |= env->error_code; /* key, D/I, S/L bits */
 509             /* Set way using a LRU mechanism */
 510             msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
 511             break;
 512         case POWERPC_EXCP_74xx:
 513         tlb_miss_74xx:
 514 #if defined(DEBUG_SOFTWARE_TLB)
 515             if (qemu_log_enabled()) {
 516                 const char *es;
 517                 target_ulong *miss, *cmp;
 518                 int en;
 519
 520                 if (excp == POWERPC_EXCP_IFTLB) {
 521                     es = "I";
 522                     en = 'I';
 523                     miss = &env->spr[SPR_TLBMISS];
 524                     cmp = &env->spr[SPR_PTEHI];
 525                 } else {
 526                     if (excp == POWERPC_EXCP_DLTLB) {
 527                         es = "DL";
 528                     } else {
 529                         es = "DS";
 530                     }
 531                     en = 'D';
 532                     miss = &env->spr[SPR_TLBMISS];
 533                     cmp = &env->spr[SPR_PTEHI];
 534                 }
 535                 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
 536                          TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
 537                          env->error_code);
 538             }
 539 #endif
 540             msr |= env->error_code; /* key bit */
 541             break;
 542         default:
 543             cpu_abort(cs, "Invalid data store TLB miss exception\n");
 544             break;
 545         }
 546         break;
 547     case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
 548         /* XXX: TODO */
 549         cpu_abort(cs, "Floating point assist exception "
 550                   "is not implemented yet !\n");
 551         break;
 552     case POWERPC_EXCP_DABR:      /* Data address breakpoint                  */
 553         /* XXX: TODO */
 554         cpu_abort(cs, "DABR exception is not implemented yet !\n");
 555         break;
 556     case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
 557         /* XXX: TODO */
 558         cpu_abort(cs, "IABR exception is not implemented yet !\n");
 559         break;
 560     case POWERPC_EXCP_SMI:       /* System management interrupt              */
 561         /* XXX: TODO */
 562         cpu_abort(cs, "SMI exception is not implemented yet !\n");
 563         break;
 564     case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
 565         /* XXX: TODO */
 566         cpu_abort(cs, "Thermal management exception "
 567                   "is not implemented yet !\n");
 568         break;
 569     case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
 570         /* XXX: TODO */
 571         cpu_abort(cs,
 572                   "Performance counter exception is not implemented yet !\n");
 573         break;
 574     case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
 575         /* XXX: TODO */
 576         cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
 577         break;
 578     case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
 579         /* XXX: TODO */
 580         cpu_abort(cs,
 581                   "970 soft-patch exception is not implemented yet !\n");
 582         break;
 583     case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
 584         /* XXX: TODO */
 585         cpu_abort(cs,
 586                   "970 maintenance exception is not implemented yet !\n");
 587         break;
 588     case POWERPC_EXCP_MEXTBR:    /* Maskable external breakpoint             */
 589         /* XXX: TODO */
 590         cpu_abort(cs, "Maskable external exception "
 591                   "is not implemented yet !\n");
 592         break;
 593     case POWERPC_EXCP_NMEXTBR:   /* Non maskable external breakpoint         */
 594         /* XXX: TODO */
 595         cpu_abort(cs, "Non maskable external exception "
 596                   "is not implemented yet !\n");
 597         break;
 598     default:
 599     excp_invalid:
 600         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
 601         break;
 602     }
 603
 604     /* Save PC */
 605     env->spr[srr0] = env->nip;
 606
 607     /* Save MSR */
 608     env->spr[srr1] = msr;
 609
 610     /* Sanity check */
 611     if (!(env->msr_mask & MSR_HVB) && (srr0 == SPR_HSRR0)) {
 612         cpu_abort(cs, "Trying to deliver HV exception %d with "
 613                   "no HV support\n", excp);
 614     }
 615
 616     /* If any alternate SRR register are defined, duplicate saved values */
 617     if (asrr0 != -1) {
 618         env->spr[asrr0] = env->spr[srr0];
 619     }
 620     if (asrr1 != -1) {
 621         env->spr[asrr1] = env->spr[srr1];
 622     }
 623
 624     /* Sort out endianness of interrupt, this differs depending on the
 625      * CPU, the HV mode, etc...
 626      */
 627 #ifdef TARGET_PPC64
 628     if (excp_model == POWERPC_EXCP_POWER7) {
 629         if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
 630             new_msr |= (target_ulong)1 << MSR_LE;
 631         }
 632     } else if (excp_model == POWERPC_EXCP_POWER8) {
 633         if (new_msr & MSR_HVB) {
 634             if (env->spr[SPR_HID0] & HID0_HILE) {
 635                 new_msr |= (target_ulong)1 << MSR_LE;
 636             }
 637         } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
 638             new_msr |= (target_ulong)1 << MSR_LE;
 639         }
 640     } else if (msr_ile) {
 641         new_msr |= (target_ulong)1 << MSR_LE;
 642     }
 643 #else
 644     if (msr_ile) {
 645         new_msr |= (target_ulong)1 << MSR_LE;
 646     }
 647 #endif
 648
 649     /* Jump to handler */
 650     vector = env->excp_vectors[excp];
 651     if (vector == (target_ulong)-1ULL) {
 652         cpu_abort(cs, "Raised an exception without defined vector %d\n",
 653                   excp);
 654     }
 655     vector |= env->excp_prefix;
 656
 657     /* AIL only works if there is no HV transition and we are running with
 658      * translations enabled
 659      */
 660     if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
 661         ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
 662         ail = 0;
 663     }
 664     /* Handle AIL */
 665     if (ail) {
 666         new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
 667         switch(ail) {
 668         case AIL_0001_8000:
 669             vector |= 0x18000;
 670             break;
 671         case AIL_C000_0000_0000_4000:
 672             vector |= 0xc000000000004000ull;
 673             break;
 674         default:
 675             cpu_abort(cs, "Invalid AIL combination %d\n", ail);
 676             break;
 677         }
 678     }
 679
 680 #if defined(TARGET_PPC64)
 681     if (excp_model == POWERPC_EXCP_BOOKE) {
 682         if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
 683             /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
 684             new_msr |= (target_ulong)1 << MSR_CM;
 685         } else {
 686             vector = (uint32_t)vector;
 687         }
 688     } else {
 689         if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
 690             vector = (uint32_t)vector;
 691         } else {
 692             new_msr |= (target_ulong)1 << MSR_SF;
 693         }
 694     }
 695 #endif
 696     /* We don't use hreg_store_msr here as already have treated
 697      * any special case that could occur. Just store MSR and update hflags
 698      *
 699      * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
 700      * will prevent setting of the HV bit which some exceptions might need
 701      * to do.
 702      */
 703     env->msr = new_msr & env->msr_mask;
 704     hreg_compute_hflags(env);
 705     env->nip = vector;
 706     /* Reset exception state */
 707     cs->exception_index = POWERPC_EXCP_NONE;
 708     env->error_code = 0;
 709
 710     /* Any interrupt is context synchronizing, check if TCG TLB
 711      * needs a delayed flush on ppc64
 712      */
 713     check_tlb_flush(env);
 714 }
 715
 716 void ppc_cpu_do_interrupt(CPUState *cs)
 717 {
 718     PowerPCCPU *cpu = POWERPC_CPU(cs);
 719     CPUPPCState *env = &cpu->env;
 720
 721     powerpc_excp(cpu, env->excp_model, cs->exception_index);
 722 }
 723
 724 static void ppc_hw_interrupt(CPUPPCState *env)
 725 {
 726     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 727 #if 0
 728     CPUState *cs = CPU(cpu);
 729
 730     qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
 731                   __func__, env, env->pending_interrupts,
 732                   cs->interrupt_request, (int)msr_me, (int)msr_ee);
 733 #endif
 734     /* External reset */
 735     if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
 736         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
 737         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
 738         return;
 739     }
 740     /* Machine check exception */
 741     if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
 742         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
 743         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK);
 744         return;
 745     }
 746 #if 0 /* TODO */
 747     /* External debug exception */
 748     if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
 749         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
 750         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG);
 751         return;
 752     }
 753 #endif
 754     /* Hypervisor decrementer exception */
 755     if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
 756         /* LPCR will be clear when not supported so this will work */
 757         bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
 758         if ((msr_ee != 0 || msr_hv == 0) && hdice) {
 759             /* HDEC clears on delivery */
 760             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
 761             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
 762             return;
 763         }
 764     }
 765     /* Extermal interrupt can ignore MSR:EE under some circumstances */
 766     if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
 767         bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 768         if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
 769             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
 770             return;
 771         }
 772     }
 773     if (msr_ce != 0) {
 774         /* External critical interrupt */
 775         if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
 776             /* Taking a critical external interrupt does not clear the external
 777              * critical interrupt status
 778              */
 779 #if 0
 780             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
 781 #endif
 782             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL);
 783             return;
 784         }
 785     }
 786     if (msr_ee != 0) {
 787         /* Watchdog timer on embedded PowerPC */
 788         if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
 789             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
 790             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT);
 791             return;
 792         }
 793         if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
 794             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
 795             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI);
 796             return;
 797         }
 798         /* Fixed interval timer on embedded PowerPC */
 799         if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
 800             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
 801             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT);
 802             return;
 803         }
 804         /* Programmable interval timer on embedded PowerPC */
 805         if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
 806             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
 807             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT);
 808             return;
 809         }
 810         /* Decrementer exception */
 811         if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
 812             if (ppc_decr_clear_on_delivery(env)) {
 813                 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
 814             }
 815             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR);
 816             return;
 817         }
 818         if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
 819             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
 820             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
 821             return;
 822         }
 823         if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
 824             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
 825             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM);
 826             return;
 827         }
 828         /* Thermal interrupt */
 829         if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
 830             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
 831             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
 832             return;
 833         }
 834     }
 835 }
 836
 837 void ppc_cpu_do_system_reset(CPUState *cs)
 838 {
 839     PowerPCCPU *cpu = POWERPC_CPU(cs);
 840     CPUPPCState *env = &cpu->env;
 841
 842     powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
 843 }
 844 #endif /* !CONFIG_USER_ONLY */
 845
 846 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 847 {
 848     PowerPCCPU *cpu = POWERPC_CPU(cs);
 849     CPUPPCState *env = &cpu->env;
 850
 851     if (interrupt_request & CPU_INTERRUPT_HARD) {
 852         ppc_hw_interrupt(env);
 853         if (env->pending_interrupts == 0) {
 854             cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
 855         }
 856         return true;
 857     }
 858     return false;
 859 }
 860
 861 #if defined(DEBUG_OP)
 862 static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
 863 {
 864     qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
 865              TARGET_FMT_lx "\n", RA, msr);
 866 }
 867 #endif
 868
 869 /*****************************************************************************/
 870 /* Exceptions processing helpers */
 871
 872 void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
 873                             uint32_t error_code, uintptr_t raddr)
 874 {
 875     CPUState *cs = CPU(ppc_env_get_cpu(env));
 876
 877     cs->exception_index = exception;
 878     env->error_code = error_code;
 879     cpu_loop_exit_restore(cs, raddr);
 880 }
 881
 882 void raise_exception_err(CPUPPCState *env, uint32_t exception,
 883                          uint32_t error_code)
 884 {
 885     raise_exception_err_ra(env, exception, error_code, 0);
 886 }
 887
 888 void raise_exception(CPUPPCState *env, uint32_t exception)
 889 {
 890     raise_exception_err_ra(env, exception, 0, 0);
 891 }
 892
 893 void raise_exception_ra(CPUPPCState *env, uint32_t exception,
 894                         uintptr_t raddr)
 895 {
 896     raise_exception_err_ra(env, exception, 0, raddr);
 897 }
 898
 899 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
 900                                 uint32_t error_code)
 901 {
 902     raise_exception_err_ra(env, exception, error_code, 0);
 903 }
 904
 905 void helper_raise_exception(CPUPPCState *env, uint32_t exception)
 906 {
 907     raise_exception_err_ra(env, exception, 0, 0);
 908 }
 909
 910 #if !defined(CONFIG_USER_ONLY)
 911 void helper_store_msr(CPUPPCState *env, target_ulong val)
 912 {
 913     uint32_t excp = hreg_store_msr(env, val, 0);
 914
 915     if (excp != 0) {
 916         CPUState *cs = CPU(ppc_env_get_cpu(env));
 917         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 918         raise_exception(env, excp);
 919     }
 920 }
 921
 922 #if defined(TARGET_PPC64)
 923 void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
 924 {
 925     CPUState *cs;
 926
 927     cs = CPU(ppc_env_get_cpu(env));
 928     cs->halted = 1;
 929     env->in_pm_state = true;
 930
 931     /* The architecture specifies that HDEC interrupts are
 932      * discarded in PM states
 933      */
 934     env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
 935
 936     /* Technically, nap doesn't set EE, but if we don't set it
 937      * then ppc_hw_interrupt() won't deliver. We could add some
 938      * other tests there based on LPCR but it's simpler to just
 939      * whack EE in. It will be cleared by the 0x100 at wakeup
 940      * anyway. It will still be observable by the guest in SRR1
 941      * but this doesn't seem to be a problem.
 942      */
 943     env->msr |= (1ull << MSR_EE);
 944     raise_exception(env, EXCP_HLT);
 945 }
 946 #endif /* defined(TARGET_PPC64) */
 947
 948 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
 949 {
 950     CPUState *cs = CPU(ppc_env_get_cpu(env));
 951
 952     /* MSR:POW cannot be set by any form of rfi */
 953     msr &= ~(1ULL << MSR_POW);
 954
 955 #if defined(TARGET_PPC64)
 956     /* Switching to 32-bit ? Crop the nip */
 957     if (!msr_is_64bit(env, msr)) {
 958         nip = (uint32_t)nip;
 959     }
 960 #else
 961     nip = (uint32_t)nip;
 962 #endif
 963     /* XXX: beware: this is false if VLE is supported */
 964     env->nip = nip & ~((target_ulong)0x00000003);
 965     hreg_store_msr(env, msr, 1);
 966 #if defined(DEBUG_OP)
 967     cpu_dump_rfi(env->nip, env->msr);
 968 #endif
 969     /* No need to raise an exception here,
 970      * as rfi is always the last insn of a TB
 971      */
 972     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 973
 974     /* Context synchronizing: check if TCG TLB needs flush */
 975     check_tlb_flush(env);
 976 }
 977
 978 void helper_rfi(CPUPPCState *env)
 979 {
 980     do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
 981 }
 982
 983 #define MSR_BOOK3S_MASK
 984 #if defined(TARGET_PPC64)
 985 void helper_rfid(CPUPPCState *env)
 986 {
 987     /* The architeture defines a number of rules for which bits
 988      * can change but in practice, we handle this in hreg_store_msr()
 989      * which will be called by do_rfi(), so there is no need to filter
 990      * here
 991      */
 992     do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
 993 }
 994
 995 void helper_hrfid(CPUPPCState *env)
 996 {
 997     do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
 998 }
 999 #endif
1000
1001 /*****************************************************************************/
1002 /* Embedded PowerPC specific helpers */
1003 void helper_40x_rfci(CPUPPCState *env)
1004 {
1005     do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
1006 }
1007
1008 void helper_rfci(CPUPPCState *env)
1009 {
1010     do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
1011 }
1012
1013 void helper_rfdi(CPUPPCState *env)
1014 {
1015     /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
1016     do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
1017 }
1018
1019 void helper_rfmci(CPUPPCState *env)
1020 {
1021     /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
1022     do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
1023 }
1024 #endif
1025
1026 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1027                uint32_t flags)
1028 {
1029     if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1030                   ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1031                   ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1032                   ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1033                   ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1034         raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1035     }
1036 }
1037
1038 #if defined(TARGET_PPC64)
1039 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1040                uint32_t flags)
1041 {
1042     if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1043                   ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1044                   ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1045                   ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1046                   ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
1047         raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1048     }
1049 }
1050 #endif
1051
1052 #if !defined(CONFIG_USER_ONLY)
1053 /*****************************************************************************/
1054 /* PowerPC 601 specific instructions (POWER bridge) */
1055
1056 void helper_rfsvc(CPUPPCState *env)
1057 {
1058     do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
1059 }
1060
1061 /* Embedded.Processor Control */
1062 static int dbell2irq(target_ulong rb)
1063 {
1064     int msg = rb & DBELL_TYPE_MASK;
1065     int irq = -1;
1066
1067     switch (msg) {
1068     case DBELL_TYPE_DBELL:
1069         irq = PPC_INTERRUPT_DOORBELL;
1070         break;
1071     case DBELL_TYPE_DBELL_CRIT:
1072         irq = PPC_INTERRUPT_CDOORBELL;
1073         break;
1074     case DBELL_TYPE_G_DBELL:
1075     case DBELL_TYPE_G_DBELL_CRIT:
1076     case DBELL_TYPE_G_DBELL_MC:
1077         /* XXX implement */
1078     default:
1079         break;
1080     }
1081
1082     return irq;
1083 }
1084
1085 void helper_msgclr(CPUPPCState *env, target_ulong rb)
1086 {
1087     int irq = dbell2irq(rb);
1088
1089     if (irq < 0) {
1090         return;
1091     }
1092
1093     env->pending_interrupts &= ~(1 << irq);
1094 }
1095
1096 void helper_msgsnd(target_ulong rb)
1097 {
1098     int irq = dbell2irq(rb);
1099     int pir = rb & DBELL_PIRTAG_MASK;
1100     CPUState *cs;
1101
1102     if (irq < 0) {
1103         return;
1104     }
1105
1106     CPU_FOREACH(cs) {
1107         PowerPCCPU *cpu = POWERPC_CPU(cs);
1108         CPUPPCState *cenv = &cpu->env;
1109
1110         if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
1111             cenv->pending_interrupts |= 1 << irq;
1112             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1113         }
1114     }
1115 }
1116 #endif