target-ppc/helper.c

   1 /*
   2  *  PPC emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "exec.h"
  21 #if defined (USE_OPEN_FIRMWARE)
  22 #include <time.h>
  23 #include "of.h"
  24 #endif
  25
  26 //#define DEBUG_MMU
  27 //#define DEBUG_BATS
  28 //#define DEBUG_EXCEPTIONS
  29
  30 /*****************************************************************************/
  31 /* PPC MMU emulation */
  32 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
  33                               int is_user, int is_softmmu);
  34
  35 /* Perform BAT hit & translation */
  36 static int get_bat (CPUState *env, uint32_t *real, int *prot,
  37                     uint32_t virtual, int rw, int type)
  38 {
  39     uint32_t *BATlt, *BATut, *BATu, *BATl;
  40     uint32_t base, BEPIl, BEPIu, bl;
  41     int i;
  42     int ret = -1;
  43
  44 #if defined (DEBUG_BATS)
  45     if (loglevel > 0) {
  46         fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
  47                type == ACCESS_CODE ? 'I' : 'D', virtual);
  48     }
  49 #endif
  50     switch (type) {
  51     case ACCESS_CODE:
  52         BATlt = env->IBAT[1];
  53         BATut = env->IBAT[0];
  54         break;
  55     default:
  56         BATlt = env->DBAT[1];
  57         BATut = env->DBAT[0];
  58         break;
  59     }
  60 #if defined (DEBUG_BATS)
  61     if (loglevel > 0) {
  62         fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
  63                type == ACCESS_CODE ? 'I' : 'D', virtual);
  64     }
  65 #endif
  66     base = virtual & 0xFFFC0000;
  67     for (i = 0; i < 4; i++) {
  68         BATu = &BATut[i];
  69         BATl = &BATlt[i];
  70         BEPIu = *BATu & 0xF0000000;
  71         BEPIl = *BATu & 0x0FFE0000;
  72         bl = (*BATu & 0x00001FFC) << 15;
  73 #if defined (DEBUG_BATS)
  74         if (loglevel > 0) {
  75             fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
  76                     __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
  77                     *BATu, *BATl);
  78         }
  79 #endif
  80         if ((virtual & 0xF0000000) == BEPIu &&
  81             ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
  82             /* BAT matches */
  83             if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
  84                 (msr_pr == 1 && (*BATu & 0x00000001))) {
  85                 /* Get physical address */
  86                 *real = (*BATl & 0xF0000000) |
  87                     ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
  88                     (virtual & 0x0001F000);
  89                 if (*BATl & 0x00000001)
  90                     *prot = PAGE_READ;
  91                 if (*BATl & 0x00000002)
  92                     *prot = PAGE_WRITE | PAGE_READ;
  93 #if defined (DEBUG_BATS)
  94                 if (loglevel > 0) {
  95                     fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
  96                             i, *real, *prot & PAGE_READ ? 'R' : '-',
  97                             *prot & PAGE_WRITE ? 'W' : '-');
  98                 }
  99 #endif
 100                 ret = 0;
 101                 break;
 102             }
 103         }
 104     }
 105     if (ret < 0) {
 106 #if defined (DEBUG_BATS)
 107         printf("no BAT match for 0x%08x:\n", virtual);
 108         for (i = 0; i < 4; i++) {
 109             BATu = &BATut[i];
 110             BATl = &BATlt[i];
 111             BEPIu = *BATu & 0xF0000000;
 112             BEPIl = *BATu & 0x0FFE0000;
 113             bl = (*BATu & 0x00001FFC) << 15;
 114             printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
 115                    "0x%08x 0x%08x 0x%08x\n",
 116                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
 117                    *BATu, *BATl, BEPIu, BEPIl, bl);
 118         }
 119 #endif
 120     }
 121     /* No hit */
 122     return ret;
 123 }
 124
 125 /* PTE table lookup */
 126 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
 127                      int h, int key, int rw)
 128 {
 129     uint32_t pte0, pte1, keep = 0, access = 0;
 130     int i, good = -1, store = 0;
 131     int ret = -1; /* No entry found */
 132
 133     for (i = 0; i < 8; i++) {
 134         pte0 = ldl_raw(phys_ram_base + base + (i * 8));
 135         pte1 =  ldl_raw(phys_ram_base + base + (i * 8) + 4);
 136 #if defined (DEBUG_MMU)
 137         if (loglevel > 0) {
 138             fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
 139                     "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
 140                     pte0 >> 31, h, (pte0 >> 6) & 1, va);
 141         }
 142 #endif
 143         /* Check validity and table match */
 144         if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
 145             /* Check vsid & api */
 146             if ((pte0 & 0x7FFFFFBF) == va) {
 147                 if (good == -1) {
 148                     good = i;
 149                     keep = pte1;
 150                 } else {
 151                     /* All matches should have equal RPN, WIMG & PP */
 152                     if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
 153                         if (loglevel > 0)
 154                             fprintf(logfile, "Bad RPN/WIMG/PP\n");
 155                         return -1;
 156                     }
 157                 }
 158                 /* Check access rights */
 159                 if (key == 0) {
 160                     access = PAGE_READ;
 161                     if ((pte1 & 0x00000003) != 0x3)
 162                         access |= PAGE_WRITE;
 163                 } else {
 164                     switch (pte1 & 0x00000003) {
 165                     case 0x0:
 166                         access = 0;
 167                         break;
 168                     case 0x1:
 169                     case 0x3:
 170                         access = PAGE_READ;
 171                         break;
 172                     case 0x2:
 173                         access = PAGE_READ | PAGE_WRITE;
 174                         break;
 175                     }
 176                 }
 177                 if (ret < 0) {
 178                     if ((rw == 0 && (access & PAGE_READ)) ||
 179                         (rw == 1 && (access & PAGE_WRITE))) {
 180 #if defined (DEBUG_MMU)
 181                         if (loglevel > 0)
 182                             fprintf(logfile, "PTE access granted !\n");
 183 #endif
 184                     good = i;
 185                     keep = pte1;
 186                     ret = 0;
 187                     } else {
 188                         /* Access right violation */
 189                         ret = -2;
 190 #if defined (DEBUG_MMU)
 191                         if (loglevel > 0)
 192                             fprintf(logfile, "PTE access rejected\n");
 193 #endif
 194                 }
 195                     *prot = access;
 196                 }
 197             }
 198         }
 199     }
 200     if (good != -1) {
 201         *RPN = keep & 0xFFFFF000;
 202 #if defined (DEBUG_MMU)
 203         if (loglevel > 0) {
 204             fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
 205                *RPN, *prot, ret);
 206         }
 207 #endif
 208         /* Update page flags */
 209         if (!(keep & 0x00000100)) {
 210             /* Access flag */
 211             keep |= 0x00000100;
 212             store = 1;
 213         }
 214             if (!(keep & 0x00000080)) {
 215             if (rw && ret == 0) {
 216                 /* Change flag */
 217                 keep |= 0x00000080;
 218                 store = 1;
 219             } else {
 220                 /* Force page fault for first write access */
 221                 *prot &= ~PAGE_WRITE;
 222             }
 223         }
 224         if (store) {
 225             stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
 226         }
 227     }
 228
 229     return ret;
 230 }
 231
 232 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
 233 {
 234     return (sdr1 & 0xFFFF0000) | (hash & mask);
 235 }
 236
 237 /* Perform segment based translation */
 238 static int get_segment (CPUState *env, uint32_t *real, int *prot,
 239                         uint32_t virtual, int rw, int type)
 240 {
 241     uint32_t pg_addr, sdr, ptem, vsid, pgidx;
 242     uint32_t hash, mask;
 243     uint32_t sr;
 244     int key;
 245     int ret = -1, ret2;
 246
 247     sr = env->sr[virtual >> 28];
 248 #if defined (DEBUG_MMU)
 249     if (loglevel > 0) {
 250         fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
 251                 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
 252                 virtual, virtual >> 28, sr, env->nip,
 253                 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
 254     }
 255 #endif
 256     key = (((sr & 0x20000000) && msr_pr == 1) ||
 257         ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
 258     if ((sr & 0x80000000) == 0) {
 259 #if defined (DEBUG_MMU)
 260         if (loglevel > 0)
 261             fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
 262                     key, sr & 0x10000000);
 263 #endif
 264         /* Check if instruction fetch is allowed, if needed */
 265         if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
 266             /* Page address translation */
 267             vsid = sr & 0x00FFFFFF;
 268             pgidx = (virtual >> 12) & 0xFFFF;
 269             sdr = env->sdr1;
 270             hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
 271             mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
 272             pg_addr = get_pgaddr(sdr, hash, mask);
 273             ptem = (vsid << 7) | (pgidx >> 10);
 274 #if defined (DEBUG_MMU)
 275             if (loglevel > 0) {
 276                 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
 277                         "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
 278                         pg_addr);
 279             }
 280 #endif
 281             /* Primary table lookup */
 282             ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
 283             if (ret < 0) {
 284                 /* Secondary table lookup */
 285                 hash = (~hash) & 0x01FFFFC0;
 286                 pg_addr = get_pgaddr(sdr, hash, mask);
 287 #if defined (DEBUG_MMU)
 288                 if (virtual != 0xEFFFFFFF && loglevel > 0) {
 289                     fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
 290                             "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
 291                             hash, pg_addr);
 292                 }
 293 #endif
 294                 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
 295                 if (ret2 != -1)
 296                     ret = ret2;
 297             }
 298         } else {
 299 #if defined (DEBUG_MMU)
 300             if (loglevel > 0)
 301                 fprintf(logfile, "No access allowed\n");
 302 #endif
 303             ret = -3;
 304         }
 305     } else {
 306 #if defined (DEBUG_MMU)
 307         if (loglevel > 0)
 308             fprintf(logfile, "direct store...\n");
 309 #endif
 310         /* Direct-store segment : absolutely *BUGGY* for now */
 311         switch (type) {
 312         case ACCESS_INT:
 313             /* Integer load/store : only access allowed */
 314             break;
 315         case ACCESS_CODE:
 316             /* No code fetch is allowed in direct-store areas */
 317             return -4;
 318         case ACCESS_FLOAT:
 319             /* Floating point load/store */
 320             return -4;
 321         case ACCESS_RES:
 322             /* lwarx, ldarx or srwcx. */
 323             return -4;
 324         case ACCESS_CACHE:
 325             /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
 326             /* Should make the instruction do no-op.
 327              * As it already do no-op, it's quite easy :-)
 328              */
 329             *real = virtual;
 330             return 0;
 331         case ACCESS_EXT:
 332             /* eciwx or ecowx */
 333             return -4;
 334         default:
 335             if (logfile) {
 336                 fprintf(logfile, "ERROR: instruction should not need "
 337                         "address translation\n");
 338             }
 339             printf("ERROR: instruction should not need "
 340                    "address translation\n");
 341             return -4;
 342         }
 343         if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
 344             *real = virtual;
 345             ret = 2;
 346         } else {
 347             ret = -2;
 348         }
 349     }
 350
 351     return ret;
 352 }
 353
 354 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
 355                           uint32_t address, int rw, int access_type)
 356 {
 357     int ret;
 358 #if 0
 359     if (loglevel > 0) {
 360         fprintf(logfile, "%s\n", __func__);
 361     }
 362 #endif
 363     if ((access_type == ACCESS_CODE && msr_ir == 0) ||
 364         (access_type != ACCESS_CODE && msr_dr == 0)) {
 365         /* No address translation */
 366         *physical = address & ~0xFFF;
 367         *prot = PAGE_READ | PAGE_WRITE;
 368         ret = 0;
 369     } else {
 370         /* Try to find a BAT */
 371         ret = get_bat(env, physical, prot, address, rw, access_type);
 372         if (ret < 0) {
 373             /* We didn't match any BAT entry */
 374             ret = get_segment(env, physical, prot, address, rw, access_type);
 375         }
 376     }
 377 #if 0
 378     if (loglevel > 0) {
 379         fprintf(logfile, "%s address %08x => %08x\n",
 380                 __func__, address, *physical);
 381     }
 382 #endif
 383     return ret;
 384 }
 385
 386 #if defined(CONFIG_USER_ONLY)
 387 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 388 {
 389     return addr;
 390 }
 391 #else
 392 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 393 {
 394     uint32_t phys_addr;
 395     int prot;
 396
 397     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 398         return -1;
 399     return phys_addr;
 400 }
 401 #endif
 402
 403 #if !defined(CONFIG_USER_ONLY)
 404
 405 #define MMUSUFFIX _mmu
 406 #define GETPC() (__builtin_return_address(0))
 407
 408 #define SHIFT 0
 409 #include "softmmu_template.h"
 410
 411 #define SHIFT 1
 412 #include "softmmu_template.h"
 413
 414 #define SHIFT 2
 415 #include "softmmu_template.h"
 416
 417 #define SHIFT 3
 418 #include "softmmu_template.h"
 419
 420 /* try to fill the TLB and return an exception if error. If retaddr is
 421    NULL, it means that the function was called in C code (i.e. not
 422    from generated code or from helper.c) */
 423 /* XXX: fix it to restore all registers */
 424 void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
 425 {
 426     TranslationBlock *tb;
 427     CPUState *saved_env;
 428     unsigned long pc;
 429     int ret;
 430
 431     /* XXX: hack to restore env in all cases, even if not called from
 432        generated code */
 433     saved_env = env;
 434     env = cpu_single_env;
 435 #if 0
 436     {
 437         unsigned long tlb_addrr, tlb_addrw;
 438         int index;
 439         index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 440         tlb_addrr = env->tlb_read[is_user][index].address;
 441         tlb_addrw = env->tlb_write[is_user][index].address;
 442         if (loglevel) {
 443             fprintf(logfile,
 444                     "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
 445                "(0x%08lx 0x%08lx)\n", __func__, env,
 446                &env->tlb_read[is_user][index], index, addr,
 447                tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
 448                tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
 449         }
 450     }
 451 #endif
 452     ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
 453     if (ret) {
 454         if (retaddr) {
 455             /* now we have a real cpu fault */
 456             pc = (unsigned long)retaddr;
 457             tb = tb_find_pc(pc);
 458             if (tb) {
 459                 /* the PC is inside the translated code. It means that we have
 460                    a virtual CPU fault */
 461                 cpu_restore_state(tb, env, pc, NULL);
 462             }
 463         }
 464         do_raise_exception_err(env->exception_index, env->error_code);
 465     }
 466 #if 0
 467     {
 468         unsigned long tlb_addrr, tlb_addrw;
 469         int index;
 470         index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 471         tlb_addrr = env->tlb_read[is_user][index].address;
 472         tlb_addrw = env->tlb_write[is_user][index].address;
 473         printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
 474                "(0x%08lx 0x%08lx)\n", __func__, env,
 475                &env->tlb_read[is_user][index], index, addr,
 476                tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
 477                tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
 478     }
 479 #endif
 480     env = saved_env;
 481 }
 482
 483 void cpu_ppc_init_mmu(CPUState *env)
 484 {
 485     /* Nothing to do: all translation are disabled */
 486 }
 487 #endif
 488
 489 /* Perform address translation */
 490 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
 491                               int is_user, int is_softmmu)
 492 {
 493     uint32_t physical;
 494     int prot;
 495     int exception = 0, error_code = 0;
 496     int access_type;
 497     int ret = 0;
 498
 499     if (rw == 2) {
 500         /* code access */
 501         rw = 0;
 502         access_type = ACCESS_CODE;
 503     } else {
 504         /* data access */
 505         /* XXX: put correct access by using cpu_restore_state()
 506            correctly */
 507         access_type = ACCESS_INT;
 508         //        access_type = env->access_type;
 509     }
 510     if (env->user_mode_only) {
 511         /* user mode only emulation */
 512         ret = -2;
 513         goto do_fault;
 514     }
 515     ret = get_physical_address(env, &physical, &prot,
 516                                address, rw, access_type);
 517     if (ret == 0) {
 518         ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
 519                            is_user, is_softmmu);
 520     } else if (ret < 0) {
 521     do_fault:
 522 #if defined (DEBUG_MMU)
 523         if (loglevel > 0)
 524             cpu_ppc_dump_state(env, logfile, 0);
 525 #endif
 526         if (access_type == ACCESS_CODE) {
 527             exception = EXCP_ISI;
 528             switch (ret) {
 529             case -1:
 530                 /* No matches in page tables */
 531                 error_code = EXCP_ISI_TRANSLATE;
 532                 break;
 533             case -2:
 534                 /* Access rights violation */
 535                 error_code = EXCP_ISI_PROT;
 536                 break;
 537             case -3:
 538                 /* No execute protection violation */
 539                 error_code = EXCP_ISI_NOEXEC;
 540                 break;
 541             case -4:
 542                 /* Direct store exception */
 543                 /* No code fetch is allowed in direct-store areas */
 544                 error_code = EXCP_ISI_DIRECT;
 545                 break;
 546             }
 547         } else {
 548             exception = EXCP_DSI;
 549             switch (ret) {
 550             case -1:
 551                 /* No matches in page tables */
 552                 error_code = EXCP_DSI_TRANSLATE;
 553                 break;
 554             case -2:
 555                 /* Access rights violation */
 556                 error_code = EXCP_DSI_PROT;
 557                 break;
 558             case -4:
 559                 /* Direct store exception */
 560                 switch (access_type) {
 561                 case ACCESS_FLOAT:
 562                     /* Floating point load/store */
 563                     exception = EXCP_ALIGN;
 564                     error_code = EXCP_ALIGN_FP;
 565                     break;
 566                 case ACCESS_RES:
 567                     /* lwarx, ldarx or srwcx. */
 568                     exception = EXCP_DSI;
 569                     error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
 570                     break;
 571                 case ACCESS_EXT:
 572                     /* eciwx or ecowx */
 573                     exception = EXCP_DSI;
 574                     error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
 575                         EXCP_DSI_ECXW;
 576                     break;
 577                 default:
 578                     printf("DSI: invalid exception (%d)\n", ret);
 579                     exception = EXCP_PROGRAM;
 580                     error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
 581                     break;
 582                 }
 583             }
 584             if (rw)
 585                 error_code |= EXCP_DSI_STORE;
 586             /* Store fault address */
 587             env->spr[DAR] = address;
 588         }
 589 #if 0
 590         printf("%s: set exception to %d %02x\n",
 591                __func__, exception, error_code);
 592 #endif
 593         env->exception_index = exception;
 594         env->error_code = error_code;
 595         ret = 1;
 596     }
 597     return ret;
 598 }
 599
 600 uint32_t _load_xer (CPUState *env)
 601 {
 602     return (xer_so << XER_SO) |
 603         (xer_ov << XER_OV) |
 604         (xer_ca << XER_CA) |
 605         (xer_bc << XER_BC);
 606 }
 607
 608 void _store_xer (CPUState *env, uint32_t value)
 609 {
 610     xer_so = (value >> XER_SO) & 0x01;
 611     xer_ov = (value >> XER_OV) & 0x01;
 612     xer_ca = (value >> XER_CA) & 0x01;
 613     xer_bc = (value >> XER_BC) & 0x1f;
 614 }
 615
 616 uint32_t _load_msr (CPUState *env)
 617 {
 618     return (msr_pow << MSR_POW) |
 619         (msr_ile << MSR_ILE) |
 620         (msr_ee << MSR_EE) |
 621         (msr_pr << MSR_PR) |
 622         (msr_fp << MSR_FP) |
 623         (msr_me << MSR_ME) |
 624         (msr_fe0 << MSR_FE0) |
 625         (msr_se << MSR_SE) |
 626         (msr_be << MSR_BE) |
 627         (msr_fe1 << MSR_FE1) |
 628         (msr_ip << MSR_IP) |
 629         (msr_ir << MSR_IR) |
 630         (msr_dr << MSR_DR) |
 631         (msr_ri << MSR_RI) |
 632         (msr_le << MSR_LE);
 633 }
 634
 635 void _store_msr (CPUState *env, uint32_t value)
 636 {
 637 #if 0 // TRY
 638     if (((value >> MSR_IR) & 0x01) != msr_ir ||
 639         ((value >> MSR_DR) & 0x01) != msr_dr)
 640     {
 641         /* Flush all tlb when changing translation mode or privilege level */
 642         tlb_flush(env, 1);
 643     }
 644 #endif
 645     msr_pow = (value >> MSR_POW) & 0x03;
 646     msr_ile = (value >> MSR_ILE) & 0x01;
 647     msr_ee = (value >> MSR_EE) & 0x01;
 648     msr_pr = (value >> MSR_PR) & 0x01;
 649     msr_fp = (value >> MSR_FP) & 0x01;
 650     msr_me = (value >> MSR_ME) & 0x01;
 651     msr_fe0 = (value >> MSR_FE0) & 0x01;
 652     msr_se = (value >> MSR_SE) & 0x01;
 653     msr_be = (value >> MSR_BE) & 0x01;
 654     msr_fe1 = (value >> MSR_FE1) & 0x01;
 655     msr_ip = (value >> MSR_IP) & 0x01;
 656     msr_ir = (value >> MSR_IR) & 0x01;
 657     msr_dr = (value >> MSR_DR) & 0x01;
 658     msr_ri = (value >> MSR_RI) & 0x01;
 659     msr_le = (value >> MSR_LE) & 0x01;
 660 }
 661
 662 void do_interrupt (CPUState *env)
 663 {
 664 #if defined (CONFIG_USER_ONLY)
 665     env->exception_index |= 0x100;
 666 #else
 667     uint32_t msr;
 668     int excp = env->exception_index;
 669
 670     msr = _load_msr(env);
 671 #if defined (DEBUG_EXCEPTIONS)
 672     if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
 673     {
 674         if (loglevel > 0) {
 675             fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
 676                     env->nip, excp << 8, env->error_code);
 677         }
 678         if (loglevel > 0)
 679             cpu_ppc_dump_state(env, logfile, 0);
 680     }
 681 #endif
 682     if (loglevel & CPU_LOG_INT) {
 683         fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
 684                 env->nip, excp << 8, env->error_code);
 685     }
 686     /* Generate informations in save/restore registers */
 687     switch (excp) {
 688     case EXCP_OFCALL:
 689 #if defined (USE_OPEN_FIRMWARE)
 690         env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
 691 #endif
 692         return;
 693     case EXCP_RTASCALL:
 694 #if defined (USE_OPEN_FIRMWARE)
 695         printf("RTAS call !\n");
 696         env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
 697         printf("RTAS call done\n");
 698 #endif
 699         return;
 700     case EXCP_NONE:
 701         /* Do nothing */
 702 #if defined (DEBUG_EXCEPTIONS)
 703         printf("%s: escape EXCP_NONE\n", __func__);
 704 #endif
 705         return;
 706     case EXCP_RESET:
 707         if (msr_ip)
 708             excp += 0xFFC00;
 709         goto store_next;
 710     case EXCP_MACHINE_CHECK:
 711         if (msr_me == 0) {
 712             cpu_abort(env, "Machine check exception while not allowed\n");
 713         }
 714         msr_me = 0;
 715         break;
 716     case EXCP_DSI:
 717         /* Store exception cause */
 718         /* data location address has been stored
 719          * when the fault has been detected
 720      */
 721         msr &= ~0xFFFF0000;
 722         env->spr[DSISR] = 0;
 723         if (env->error_code &  EXCP_DSI_TRANSLATE)
 724             env->spr[DSISR] |= 0x40000000;
 725         else if (env->error_code & EXCP_DSI_PROT)
 726             env->spr[DSISR] |= 0x08000000;
 727         else if (env->error_code & EXCP_DSI_NOTSUP) {
 728             env->spr[DSISR] |= 0x80000000;
 729             if (env->error_code & EXCP_DSI_DIRECT)
 730                 env->spr[DSISR] |= 0x04000000;
 731         }
 732         if (env->error_code & EXCP_DSI_STORE)
 733             env->spr[DSISR] |= 0x02000000;
 734         if ((env->error_code & 0xF) == EXCP_DSI_DABR)
 735             env->spr[DSISR] |= 0x00400000;
 736         if (env->error_code & EXCP_DSI_ECXW)
 737             env->spr[DSISR] |= 0x00100000;
 738 #if defined (DEBUG_EXCEPTIONS)
 739         if (loglevel) {
 740             fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
 741                     env->spr[DSISR], env->spr[DAR]);
 742         } else {
 743             printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
 744                    env->spr[DSISR], env->spr[DAR], env->nip);
 745         }
 746 #endif
 747         goto store_next;
 748     case EXCP_ISI:
 749         /* Store exception cause */
 750         msr &= ~0xFFFF0000;
 751         if (env->error_code == EXCP_ISI_TRANSLATE)
 752             msr |= 0x40000000;
 753         else if (env->error_code == EXCP_ISI_NOEXEC ||
 754                  env->error_code == EXCP_ISI_GUARD ||
 755                  env->error_code == EXCP_ISI_DIRECT)
 756             msr |= 0x10000000;
 757         else
 758             msr |= 0x08000000;
 759 #if defined (DEBUG_EXCEPTIONS)
 760         if (loglevel) {
 761             fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
 762                     msr, env->nip);
 763         } else {
 764             printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
 765                    msr, env->nip, env->spr[V_TBL]);
 766         }
 767 #endif
 768         goto store_next;
 769     case EXCP_EXTERNAL:
 770         if (msr_ee == 0) {
 771 #if defined (DEBUG_EXCEPTIONS)
 772             if (loglevel > 0) {
 773                 fprintf(logfile, "Skipping hardware interrupt\n");
 774     }
 775 #endif
 776             /* Requeue it */
 777             do_raise_exception(EXCP_EXTERNAL);
 778             return;
 779             }
 780         goto store_next;
 781     case EXCP_ALIGN:
 782         /* Store exception cause */
 783         /* Get rS/rD and rA from faulting opcode */
 784         env->spr[DSISR] |=
 785             (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
 786         /* data location address has been stored
 787          * when the fault has been detected
 788          */
 789         goto store_current;
 790     case EXCP_PROGRAM:
 791         msr &= ~0xFFFF0000;
 792         switch (env->error_code & ~0xF) {
 793         case EXCP_FP:
 794             if (msr_fe0 == 0 && msr_fe1 == 0) {
 795 #if defined (DEBUG_EXCEPTIONS)
 796                 printf("Ignore floating point exception\n");
 797 #endif
 798                 return;
 799         }
 800             msr |= 0x00100000;
 801             /* Set FX */
 802             env->fpscr[7] |= 0x8;
 803             /* Finally, update FEX */
 804             if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
 805                 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
 806                 env->fpscr[7] |= 0x4;
 807         break;
 808         case EXCP_INVAL:
 809             //      printf("Invalid instruction at 0x%08x\n", env->nip);
 810             msr |= 0x00080000;
 811         break;
 812         case EXCP_PRIV:
 813             msr |= 0x00040000;
 814         break;
 815         case EXCP_TRAP:
 816             msr |= 0x00020000;
 817             break;
 818         default:
 819             /* Should never occur */
 820         break;
 821     }
 822         msr |= 0x00010000;
 823         goto store_current;
 824     case EXCP_NO_FP:
 825         goto store_current;
 826     case EXCP_DECR:
 827         if (msr_ee == 0) {
 828             /* Requeue it */
 829             do_raise_exception(EXCP_DECR);
 830             return;
 831         }
 832         goto store_next;
 833     case EXCP_SYSCALL:
 834         if (loglevel & CPU_LOG_INT) {
 835             fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
 836                     env->gpr[0], env->gpr[3], env->gpr[4],
 837                     env->gpr[5], env->gpr[6]);
 838             if (env->gpr[0] == 4 && env->gpr[3] == 1) {
 839                 int len, addr, i;
 840                 uint8_t c;
 841
 842                 fprintf(logfile, "write: ");
 843                 addr = env->gpr[4];
 844                 len = env->gpr[5];
 845                 if (len > 64)
 846                     len = 64;
 847                 for(i = 0; i < len; i++) {
 848                     c = 0;
 849                     cpu_memory_rw_debug(env, addr + i, &c, 1, 0);
 850                     if (c < 32 || c > 126)
 851                         c = '.';
 852                     fprintf(logfile, "%c", c);
 853                 }
 854                 fprintf(logfile, "\n");
 855             }
 856         }
 857         goto store_next;
 858     case EXCP_TRACE:
 859         goto store_next;
 860     case EXCP_FP_ASSIST:
 861         goto store_next;
 862     case EXCP_MTMSR:
 863         /* Nothing to do */
 864         return;
 865     case EXCP_BRANCH:
 866         /* Nothing to do */
 867         return;
 868     case EXCP_RFI:
 869         /* Restore user-mode state */
 870         tb_flush(env);
 871 #if defined (DEBUG_EXCEPTIONS)
 872         if (msr_pr == 1)
 873             printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
 874 #endif
 875         return;
 876     store_current:
 877         /* SRR0 is set to current instruction */
 878         env->spr[SRR0] = (uint32_t)env->nip - 4;
 879         break;
 880     store_next:
 881         /* SRR0 is set to next instruction */
 882         env->spr[SRR0] = (uint32_t)env->nip;
 883         break;
 884     }
 885     env->spr[SRR1] = msr;
 886     /* reload MSR with correct bits */
 887     msr_pow = 0;
 888     msr_ee = 0;
 889     msr_pr = 0;
 890     msr_fp = 0;
 891     msr_fe0 = 0;
 892     msr_se = 0;
 893     msr_be = 0;
 894     msr_fe1 = 0;
 895     msr_ir = 0;
 896     msr_dr = 0;
 897     msr_ri = 0;
 898     msr_le = msr_ile;
 899     /* Jump to handler */
 900     env->nip = excp << 8;
 901     env->exception_index = EXCP_NONE;
 902     /* Invalidate all TLB as we may have changed translation mode */
 903     tlb_flush(env, 1);
 904     /* ensure that no TB jump will be modified as
 905        the program flow was changed */
 906 #ifdef __sparc__
 907     tmp_T0 = 0;
 908 #else
 909     T0 = 0;
 910 #endif
 911 #endif
 912     env->exception_index = -1;
 913 }