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Add reset callbacks for PowerPC CPU.
[mirror_qemu.git] / target-ppc / helper.c
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30
31 //#define DEBUG_MMU
32 //#define DEBUG_BATS
33 //#define DEBUG_SOFTWARE_TLB
34 //#define DEBUG_EXCEPTIONS
35 //#define FLUSH_ALL_TLBS
36
37 /*****************************************************************************/
38 /* PowerPC MMU emulation */
39
40 #if defined(CONFIG_USER_ONLY)
41 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
42 int is_user, int is_softmmu)
43 {
44 int exception, error_code;
45
46 if (rw == 2) {
47 exception = EXCP_ISI;
48 error_code = 0;
49 } else {
50 exception = EXCP_DSI;
51 error_code = 0;
52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
59
60 return 1;
61 }
62
63 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
64 {
65 return addr;
66 }
67 #else
68 /* Common routines used by software and hardware TLBs emulation */
69 static inline int pte_is_valid (target_ulong pte0)
70 {
71 return pte0 & 0x80000000 ? 1 : 0;
72 }
73
74 static inline void pte_invalidate (target_ulong *pte0)
75 {
76 *pte0 &= ~0x80000000;
77 }
78
79 #define PTE_PTEM_MASK 0x7FFFFFBF
80 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
81
82 static int pte_check (mmu_ctx_t *ctx,
83 target_ulong pte0, target_ulong pte1, int h, int rw)
84 {
85 int access, ret;
86
87 access = 0;
88 ret = -1;
89 /* Check validity and table match */
90 if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {
91 /* Check vsid & api */
92 if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
93 if (ctx->raddr != (target_ulong)-1) {
94 /* all matches should have equal RPN, WIMG & PP */
95 if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
96 if (loglevel > 0)
97 fprintf(logfile, "Bad RPN/WIMG/PP\n");
98 return -3;
99 }
100 }
101 /* Compute access rights */
102 if (ctx->key == 0) {
103 access = PAGE_READ;
104 if ((pte1 & 0x00000003) != 0x3)
105 access |= PAGE_WRITE;
106 } else {
107 switch (pte1 & 0x00000003) {
108 case 0x0:
109 access = 0;
110 break;
111 case 0x1:
112 case 0x3:
113 access = PAGE_READ;
114 break;
115 case 0x2:
116 access = PAGE_READ | PAGE_WRITE;
117 break;
118 }
119 }
120 /* Keep the matching PTE informations */
121 ctx->raddr = pte1;
122 ctx->prot = access;
123 if ((rw == 0 && (access & PAGE_READ)) ||
124 (rw == 1 && (access & PAGE_WRITE))) {
125 /* Access granted */
126 #if defined (DEBUG_MMU)
127 if (loglevel > 0)
128 fprintf(logfile, "PTE access granted !\n");
129 #endif
130 ret = 0;
131 } else {
132 /* Access right violation */
133 #if defined (DEBUG_MMU)
134 if (loglevel > 0)
135 fprintf(logfile, "PTE access rejected\n");
136 #endif
137 ret = -2;
138 }
139 }
140 }
141
142 return ret;
143 }
144
145 static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
146 int ret, int rw)
147 {
148 int store = 0;
149
150 /* Update page flags */
151 if (!(*pte1p & 0x00000100)) {
152 /* Update accessed flag */
153 *pte1p |= 0x00000100;
154 store = 1;
155 }
156 if (!(*pte1p & 0x00000080)) {
157 if (rw == 1 && ret == 0) {
158 /* Update changed flag */
159 *pte1p |= 0x00000080;
160 store = 1;
161 } else {
162 /* Force page fault for first write access */
163 ctx->prot &= ~PAGE_WRITE;
164 }
165 }
166
167 return store;
168 }
169
170 /* Software driven TLB helpers */
171 static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
172 int way, int is_code)
173 {
174 int nr;
175
176 /* Select TLB num in a way from address */
177 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
178 /* Select TLB way */
179 nr += env->tlb_per_way * way;
180 /* 6xx have separate TLBs for instructions and data */
181 if (is_code && env->id_tlbs == 1)
182 nr += env->nb_tlb;
183
184 return nr;
185 }
186
187 void ppc6xx_tlb_invalidate_all (CPUState *env)
188 {
189 ppc6xx_tlb_t *tlb;
190 int nr, max;
191
192 #if defined (DEBUG_SOFTWARE_TLB) && 0
193 if (loglevel != 0) {
194 fprintf(logfile, "Invalidate all TLBs\n");
195 }
196 #endif
197 /* Invalidate all defined software TLB */
198 max = env->nb_tlb;
199 if (env->id_tlbs == 1)
200 max *= 2;
201 for (nr = 0; nr < max; nr++) {
202 tlb = &env->tlb[nr].tlb6;
203 #if !defined(FLUSH_ALL_TLBS)
204 tlb_flush_page(env, tlb->EPN);
205 #endif
206 pte_invalidate(&tlb->pte0);
207 }
208 #if defined(FLUSH_ALL_TLBS)
209 tlb_flush(env, 1);
210 #endif
211 }
212
213 static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
214 target_ulong eaddr,
215 int is_code, int match_epn)
216 {
217 ppc6xx_tlb_t *tlb;
218 int way, nr;
219
220 #if !defined(FLUSH_ALL_TLBS)
221 /* Invalidate ITLB + DTLB, all ways */
222 for (way = 0; way < env->nb_ways; way++) {
223 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
224 tlb = &env->tlb[nr].tlb6;
225 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
226 #if defined (DEBUG_SOFTWARE_TLB)
227 if (loglevel != 0) {
228 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
229 nr, env->nb_tlb, eaddr);
230 }
231 #endif
232 pte_invalidate(&tlb->pte0);
233 tlb_flush_page(env, tlb->EPN);
234 }
235 }
236 #else
237 /* XXX: PowerPC specification say this is valid as well */
238 ppc6xx_tlb_invalidate_all(env);
239 #endif
240 }
241
242 void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
243 int is_code)
244 {
245 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
246 }
247
248 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
249 target_ulong pte0, target_ulong pte1)
250 {
251 ppc6xx_tlb_t *tlb;
252 int nr;
253
254 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
255 tlb = &env->tlb[nr].tlb6;
256 #if defined (DEBUG_SOFTWARE_TLB)
257 if (loglevel != 0) {
258 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
259 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
260 }
261 #endif
262 /* Invalidate any pending reference in Qemu for this virtual address */
263 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
264 tlb->pte0 = pte0;
265 tlb->pte1 = pte1;
266 tlb->EPN = EPN;
267 /* Store last way for LRU mechanism */
268 env->last_way = way;
269 }
270
271 static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
272 target_ulong eaddr, int rw, int access_type)
273 {
274 ppc6xx_tlb_t *tlb;
275 int nr, best, way;
276 int ret;
277
278 best = -1;
279 ret = -1; /* No TLB found */
280 for (way = 0; way < env->nb_ways; way++) {
281 nr = ppc6xx_tlb_getnum(env, eaddr, way,
282 access_type == ACCESS_CODE ? 1 : 0);
283 tlb = &env->tlb[nr].tlb6;
284 /* This test "emulates" the PTE index match for hardware TLBs */
285 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
286 #if defined (DEBUG_SOFTWARE_TLB)
287 if (loglevel != 0) {
288 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
289 "] <> " ADDRX "\n",
290 nr, env->nb_tlb,
291 pte_is_valid(tlb->pte0) ? "valid" : "inval",
292 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
293 }
294 #endif
295 continue;
296 }
297 #if defined (DEBUG_SOFTWARE_TLB)
298 if (loglevel != 0) {
299 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
300 " %c %c\n",
301 nr, env->nb_tlb,
302 pte_is_valid(tlb->pte0) ? "valid" : "inval",
303 tlb->EPN, eaddr, tlb->pte1,
304 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
305 }
306 #endif
307 switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
308 case -3:
309 /* TLB inconsistency */
310 return -1;
311 case -2:
312 /* Access violation */
313 ret = -2;
314 best = nr;
315 break;
316 case -1:
317 default:
318 /* No match */
319 break;
320 case 0:
321 /* access granted */
322 /* XXX: we should go on looping to check all TLBs consistency
323 * but we can speed-up the whole thing as the
324 * result would be undefined if TLBs are not consistent.
325 */
326 ret = 0;
327 best = nr;
328 goto done;
329 }
330 }
331 if (best != -1) {
332 done:
333 #if defined (DEBUG_SOFTWARE_TLB)
334 if (loglevel > 0) {
335 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
336 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
337 }
338 #endif
339 /* Update page flags */
340 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
341 }
342
343 return ret;
344 }
345
346 /* Perform BAT hit & translation */
347 static int get_bat (CPUState *env, mmu_ctx_t *ctx,
348 target_ulong virtual, int rw, int type)
349 {
350 target_ulong *BATlt, *BATut, *BATu, *BATl;
351 target_ulong base, BEPIl, BEPIu, bl;
352 int i;
353 int ret = -1;
354
355 #if defined (DEBUG_BATS)
356 if (loglevel > 0) {
357 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
358 type == ACCESS_CODE ? 'I' : 'D', virtual);
359 }
360 #endif
361 switch (type) {
362 case ACCESS_CODE:
363 BATlt = env->IBAT[1];
364 BATut = env->IBAT[0];
365 break;
366 default:
367 BATlt = env->DBAT[1];
368 BATut = env->DBAT[0];
369 break;
370 }
371 #if defined (DEBUG_BATS)
372 if (loglevel > 0) {
373 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
374 type == ACCESS_CODE ? 'I' : 'D', virtual);
375 }
376 #endif
377 base = virtual & 0xFFFC0000;
378 for (i = 0; i < 4; i++) {
379 BATu = &BATut[i];
380 BATl = &BATlt[i];
381 BEPIu = *BATu & 0xF0000000;
382 BEPIl = *BATu & 0x0FFE0000;
383 bl = (*BATu & 0x00001FFC) << 15;
384 #if defined (DEBUG_BATS)
385 if (loglevel > 0) {
386 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
387 " BATl 0x" ADDRX "\n",
388 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
389 *BATu, *BATl);
390 }
391 #endif
392 if ((virtual & 0xF0000000) == BEPIu &&
393 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
394 /* BAT matches */
395 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
396 (msr_pr == 1 && (*BATu & 0x00000001))) {
397 /* Get physical address */
398 ctx->raddr = (*BATl & 0xF0000000) |
399 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
400 (virtual & 0x0001F000);
401 if (*BATl & 0x00000001)
402 ctx->prot = PAGE_READ;
403 if (*BATl & 0x00000002)
404 ctx->prot = PAGE_WRITE | PAGE_READ;
405 #if defined (DEBUG_BATS)
406 if (loglevel > 0) {
407 fprintf(logfile, "BAT %d match: r 0x" ADDRX
408 " prot=%c%c\n",
409 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
410 ctx->prot & PAGE_WRITE ? 'W' : '-');
411 }
412 #endif
413 ret = 0;
414 break;
415 }
416 }
417 }
418 if (ret < 0) {
419 #if defined (DEBUG_BATS)
420 printf("no BAT match for 0x" ADDRX ":\n", virtual);
421 for (i = 0; i < 4; i++) {
422 BATu = &BATut[i];
423 BATl = &BATlt[i];
424 BEPIu = *BATu & 0xF0000000;
425 BEPIl = *BATu & 0x0FFE0000;
426 bl = (*BATu & 0x00001FFC) << 15;
427 printf("%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
428 " BATl 0x" ADDRX " \n\t"
429 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
430 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
431 *BATu, *BATl, BEPIu, BEPIl, bl);
432 }
433 #endif
434 }
435 /* No hit */
436 return ret;
437 }
438
439 /* PTE table lookup */
440 static int find_pte (mmu_ctx_t *ctx, int h, int rw)
441 {
442 target_ulong base, pte0, pte1;
443 int i, good = -1;
444 int ret;
445
446 ret = -1; /* No entry found */
447 base = ctx->pg_addr[h];
448 for (i = 0; i < 8; i++) {
449 pte0 = ldl_phys(base + (i * 8));
450 pte1 = ldl_phys(base + (i * 8) + 4);
451 #if defined (DEBUG_MMU)
452 if (loglevel > 0) {
453 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
454 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
455 base + (i * 8), pte0, pte1,
456 pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);
457 }
458 #endif
459 switch (pte_check(ctx, pte0, pte1, h, rw)) {
460 case -3:
461 /* PTE inconsistency */
462 return -1;
463 case -2:
464 /* Access violation */
465 ret = -2;
466 good = i;
467 break;
468 case -1:
469 default:
470 /* No PTE match */
471 break;
472 case 0:
473 /* access granted */
474 /* XXX: we should go on looping to check all PTEs consistency
475 * but if we can speed-up the whole thing as the
476 * result would be undefined if PTEs are not consistent.
477 */
478 ret = 0;
479 good = i;
480 goto done;
481 }
482 }
483 if (good != -1) {
484 done:
485 #if defined (DEBUG_MMU)
486 if (loglevel > 0) {
487 fprintf(logfile, "found PTE at addr 0x" ADDRX " prot=0x%01x "
488 "ret=%d\n",
489 ctx->raddr, ctx->prot, ret);
490 }
491 #endif
492 /* Update page flags */
493 pte1 = ctx->raddr;
494 if (pte_update_flags(ctx, &pte1, ret, rw) == 1)
495 stl_phys_notdirty(base + (good * 8) + 4, pte1);
496 }
497
498 return ret;
499 }
500
501 static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
502 target_phys_addr_t hash,
503 target_phys_addr_t mask)
504 {
505 return (sdr1 & 0xFFFF0000) | (hash & mask);
506 }
507
508 /* Perform segment based translation */
509 static int get_segment (CPUState *env, mmu_ctx_t *ctx,
510 target_ulong eaddr, int rw, int type)
511 {
512 target_phys_addr_t sdr, hash, mask;
513 target_ulong sr, vsid, pgidx;
514 int ret = -1, ret2;
515
516 sr = env->sr[eaddr >> 28];
517 #if defined (DEBUG_MMU)
518 if (loglevel > 0) {
519 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x"
520 ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
521 eaddr, eaddr >> 28, sr, env->nip,
522 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
523 }
524 #endif
525 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
526 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
527 if ((sr & 0x80000000) == 0) {
528 #if defined (DEBUG_MMU)
529 if (loglevel > 0)
530 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
531 ctx->key, sr & 0x10000000);
532 #endif
533 /* Check if instruction fetch is allowed, if needed */
534 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
535 /* Page address translation */
536 pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
537 vsid = sr & 0x00FFFFFF;
538 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
539 /* Primary table address */
540 sdr = env->sdr1;
541 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
542 ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
543 /* Secondary table address */
544 hash = (~hash) & 0x01FFFFC0;
545 ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
546 ctx->ptem = (vsid << 7) | (pgidx >> 10);
547 /* Initialize real address with an invalid value */
548 ctx->raddr = (target_ulong)-1;
549 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
550 /* Software TLB search */
551 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
552 } else {
553 #if defined (DEBUG_MMU)
554 if (loglevel > 0) {
555 fprintf(logfile, "0 sdr1=0x" ADDRX " vsid=0x%06x "
556 "api=0x%04x hash=0x%07x pg_addr=0x" ADDRX "\n",
557 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
558 }
559 #endif
560 /* Primary table lookup */
561 ret = find_pte(ctx, 0, rw);
562 if (ret < 0) {
563 /* Secondary table lookup */
564 #if defined (DEBUG_MMU)
565 if (eaddr != 0xEFFFFFFF && loglevel > 0) {
566 fprintf(logfile,
567 "1 sdr1=0x" ADDRX " vsid=0x%06x api=0x%04x "
568 "hash=0x%05x pg_addr=0x" ADDRX "\n",
569 sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
570 }
571 #endif
572 ret2 = find_pte(ctx, 1, rw);
573 if (ret2 != -1)
574 ret = ret2;
575 }
576 }
577 } else {
578 #if defined (DEBUG_MMU)
579 if (loglevel > 0)
580 fprintf(logfile, "No access allowed\n");
581 #endif
582 ret = -3;
583 }
584 } else {
585 #if defined (DEBUG_MMU)
586 if (loglevel > 0)
587 fprintf(logfile, "direct store...\n");
588 #endif
589 /* Direct-store segment : absolutely *BUGGY* for now */
590 switch (type) {
591 case ACCESS_INT:
592 /* Integer load/store : only access allowed */
593 break;
594 case ACCESS_CODE:
595 /* No code fetch is allowed in direct-store areas */
596 return -4;
597 case ACCESS_FLOAT:
598 /* Floating point load/store */
599 return -4;
600 case ACCESS_RES:
601 /* lwarx, ldarx or srwcx. */
602 return -4;
603 case ACCESS_CACHE:
604 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
605 /* Should make the instruction do no-op.
606 * As it already do no-op, it's quite easy :-)
607 */
608 ctx->raddr = eaddr;
609 return 0;
610 case ACCESS_EXT:
611 /* eciwx or ecowx */
612 return -4;
613 default:
614 if (logfile) {
615 fprintf(logfile, "ERROR: instruction should not need "
616 "address translation\n");
617 }
618 printf("ERROR: instruction should not need "
619 "address translation\n");
620 return -4;
621 }
622 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
623 ctx->raddr = eaddr;
624 ret = 2;
625 } else {
626 ret = -2;
627 }
628 }
629
630 return ret;
631 }
632
633 void ppc4xx_tlb_invalidate_all (CPUState *env)
634 {
635 ppcemb_tlb_t *tlb;
636 int i;
637
638 for (i = 0; i < env->nb_tlb; i++) {
639 tlb = &env->tlb[i].tlbe;
640 if (tlb->prot & PAGE_VALID) {
641 #if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
642 end = tlb->EPN + tlb->size;
643 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
644 tlb_flush_page(env, page);
645 #endif
646 tlb->prot &= ~PAGE_VALID;
647 }
648 }
649 tlb_flush(env, 1);
650 }
651
652 int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
653 target_ulong address, int rw, int access_type)
654 {
655 ppcemb_tlb_t *tlb;
656 target_phys_addr_t raddr;
657 target_ulong mask;
658 int i, ret, zsel, zpr;
659
660 ret = -6;
661 for (i = 0; i < env->nb_tlb; i++) {
662 tlb = &env->tlb[i].tlbe;
663 /* Check valid flag */
664 if (!(tlb->prot & PAGE_VALID)) {
665 if (loglevel)
666 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
667 continue;
668 }
669 mask = ~(tlb->size - 1);
670 if (loglevel) {
671 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
672 ADDRX " " ADDRX " %d\n",
673 __func__, i, address, (int)env->spr[SPR_40x_PID],
674 tlb->EPN, mask, (int)tlb->PID);
675 }
676 /* Check PID */
677 if (tlb->PID != 0 && tlb->PID != env->spr[SPR_40x_PID])
678 continue;
679 /* Check effective address */
680 if ((address & mask) != tlb->EPN)
681 continue;
682 raddr = (tlb->RPN & mask) | (address & ~mask);
683 zsel = (tlb->attr >> 4) & 0xF;
684 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
685 if (loglevel) {
686 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
687 __func__, i, zsel, zpr, rw, tlb->attr);
688 }
689 if (access_type == ACCESS_CODE) {
690 /* Check execute enable bit */
691 switch (zpr) {
692 case 0x0:
693 if (msr_pr) {
694 ret = -3;
695 ctx->prot = 0;
696 break;
697 }
698 /* No break here */
699 case 0x1:
700 case 0x2:
701 /* Check from TLB entry */
702 if (!(tlb->prot & PAGE_EXEC)) {
703 ret = -3;
704 } else {
705 if (tlb->prot & PAGE_WRITE)
706 ctx->prot = PAGE_READ | PAGE_WRITE;
707 else
708 ctx->prot = PAGE_READ;
709 ret = 0;
710 }
711 break;
712 case 0x3:
713 /* All accesses granted */
714 ret = 0;
715 ctx->prot = PAGE_READ | PAGE_WRITE;
716 break;
717 }
718 } else {
719 switch (zpr) {
720 case 0x0:
721 if (msr_pr) {
722 ret = -2;
723 ctx->prot = 0;
724 break;
725 }
726 /* No break here */
727 case 0x1:
728 case 0x2:
729 /* Check from TLB entry */
730 /* Check write protection bit */
731 if (rw && !(tlb->prot & PAGE_WRITE)) {
732 ret = -2;
733 } else {
734 ret = 2;
735 if (tlb->prot & PAGE_WRITE)
736 ctx->prot = PAGE_READ | PAGE_WRITE;
737 else
738 ctx->prot = PAGE_READ;
739 }
740 break;
741 case 0x3:
742 /* All accesses granted */
743 ret = 2;
744 ctx->prot = PAGE_READ | PAGE_WRITE;
745 break;
746 }
747 }
748 if (ret >= 0) {
749 ctx->raddr = raddr;
750 if (loglevel) {
751 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
752 " %d\n", __func__, address, ctx->raddr, ctx->prot);
753 }
754 return i;
755 }
756 }
757
758 return ret;
759 }
760
761 static int check_physical (CPUState *env, mmu_ctx_t *ctx,
762 target_ulong eaddr, int rw)
763 {
764 int in_plb, ret;
765
766 ctx->raddr = eaddr;
767 ctx->prot = PAGE_READ;
768 ret = 0;
769 if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {
770 /* 403 family add some particular protections,
771 * using PBL/PBU registers for accesses with no translation.
772 */
773 in_plb =
774 /* Check PLB validity */
775 (env->pb[0] < env->pb[1] &&
776 /* and address in plb area */
777 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
778 (env->pb[2] < env->pb[3] &&
779 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
780 if (in_plb ^ msr_px) {
781 /* Access in protected area */
782 if (rw == 1) {
783 /* Access is not allowed */
784 ret = -2;
785 }
786 } else {
787 /* Read-write access is allowed */
788 ctx->prot |= PAGE_WRITE;
789 }
790 } else {
791 ctx->prot |= PAGE_WRITE;
792 }
793
794 return ret;
795 }
796
797 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
798 int rw, int access_type, int check_BATs)
799 {
800 int ret;
801 #if 0
802 if (loglevel > 0) {
803 fprintf(logfile, "%s\n", __func__);
804 }
805 #endif
806 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
807 (access_type != ACCESS_CODE && msr_dr == 0)) {
808 /* No address translation */
809 ret = check_physical(env, ctx, eaddr, rw);
810 } else {
811 switch (PPC_MMU(env)) {
812 case PPC_FLAGS_MMU_32B:
813 case PPC_FLAGS_MMU_SOFT_6xx:
814 /* Try to find a BAT */
815 ret = -1;
816 if (check_BATs)
817 ret = get_bat(env, ctx, eaddr, rw, access_type);
818 if (ret < 0) {
819 /* We didn't match any BAT entry */
820 ret = get_segment(env, ctx, eaddr, rw, access_type);
821 }
822 break;
823 case PPC_FLAGS_MMU_SOFT_4xx:
824 ret = mmu4xx_get_physical_address(env, ctx, eaddr,
825 rw, access_type);
826 break;
827 default:
828 /* XXX: TODO */
829 cpu_abort(env, "MMU model not implemented\n");
830 return -1;
831 }
832 }
833 #if 0
834 if (loglevel > 0) {
835 fprintf(logfile, "%s address " ADDRX " => " ADDRX "\n",
836 __func__, eaddr, ctx->raddr);
837 }
838 #endif
839
840 return ret;
841 }
842
843 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
844 {
845 mmu_ctx_t ctx;
846
847 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
848 return -1;
849
850 return ctx.raddr & TARGET_PAGE_MASK;
851 }
852
853 /* Perform address translation */
854 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
855 int is_user, int is_softmmu)
856 {
857 mmu_ctx_t ctx;
858 int exception = 0, error_code = 0;
859 int access_type;
860 int ret = 0;
861
862 if (rw == 2) {
863 /* code access */
864 rw = 0;
865 access_type = ACCESS_CODE;
866 } else {
867 /* data access */
868 /* XXX: put correct access by using cpu_restore_state()
869 correctly */
870 access_type = ACCESS_INT;
871 // access_type = env->access_type;
872 }
873 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
874 if (ret == 0) {
875 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
876 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
877 is_user, is_softmmu);
878 } else if (ret < 0) {
879 #if defined (DEBUG_MMU)
880 if (loglevel > 0)
881 cpu_dump_state(env, logfile, fprintf, 0);
882 #endif
883 if (access_type == ACCESS_CODE) {
884 exception = EXCP_ISI;
885 switch (ret) {
886 case -1:
887 /* No matches in page tables or TLB */
888 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
889 exception = EXCP_I_TLBMISS;
890 env->spr[SPR_IMISS] = address;
891 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
892 error_code = 1 << 18;
893 goto tlb_miss;
894 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
895 exception = EXCP_40x_ITLBMISS;
896 error_code = 0;
897 env->spr[SPR_40x_DEAR] = address;
898 env->spr[SPR_40x_ESR] = 0x00000000;
899 } else {
900 error_code = 0x40000000;
901 }
902 break;
903 case -2:
904 /* Access rights violation */
905 error_code = 0x08000000;
906 break;
907 case -3:
908 /* No execute protection violation */
909 error_code = 0x10000000;
910 break;
911 case -4:
912 /* Direct store exception */
913 /* No code fetch is allowed in direct-store areas */
914 error_code = 0x10000000;
915 break;
916 case -5:
917 /* No match in segment table */
918 exception = EXCP_ISEG;
919 error_code = 0;
920 break;
921 }
922 } else {
923 exception = EXCP_DSI;
924 switch (ret) {
925 case -1:
926 /* No matches in page tables or TLB */
927 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
928 if (rw == 1) {
929 exception = EXCP_DS_TLBMISS;
930 error_code = 1 << 16;
931 } else {
932 exception = EXCP_DL_TLBMISS;
933 error_code = 0;
934 }
935 env->spr[SPR_DMISS] = address;
936 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
937 tlb_miss:
938 error_code |= ctx.key << 19;
939 env->spr[SPR_HASH1] = ctx.pg_addr[0];
940 env->spr[SPR_HASH2] = ctx.pg_addr[1];
941 /* Do not alter DAR nor DSISR */
942 goto out;
943 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
944 exception = EXCP_40x_DTLBMISS;
945 error_code = 0;
946 env->spr[SPR_40x_DEAR] = address;
947 if (rw)
948 env->spr[SPR_40x_ESR] = 0x00800000;
949 else
950 env->spr[SPR_40x_ESR] = 0x00000000;
951 } else {
952 error_code = 0x40000000;
953 }
954 break;
955 case -2:
956 /* Access rights violation */
957 error_code = 0x08000000;
958 break;
959 case -4:
960 /* Direct store exception */
961 switch (access_type) {
962 case ACCESS_FLOAT:
963 /* Floating point load/store */
964 exception = EXCP_ALIGN;
965 error_code = EXCP_ALIGN_FP;
966 break;
967 case ACCESS_RES:
968 /* lwarx, ldarx or srwcx. */
969 error_code = 0x04000000;
970 break;
971 case ACCESS_EXT:
972 /* eciwx or ecowx */
973 error_code = 0x04100000;
974 break;
975 default:
976 printf("DSI: invalid exception (%d)\n", ret);
977 exception = EXCP_PROGRAM;
978 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
979 break;
980 }
981 break;
982 case -5:
983 /* No match in segment table */
984 exception = EXCP_DSEG;
985 error_code = 0;
986 break;
987 }
988 if (exception == EXCP_DSI && rw == 1)
989 error_code |= 0x02000000;
990 /* Store fault address */
991 env->spr[SPR_DAR] = address;
992 env->spr[SPR_DSISR] = error_code;
993 }
994 out:
995 #if 0
996 printf("%s: set exception to %d %02x\n",
997 __func__, exception, error_code);
998 #endif
999 env->exception_index = exception;
1000 env->error_code = error_code;
1001 ret = 1;
1002 }
1003
1004 return ret;
1005 }
1006
1007 /*****************************************************************************/
1008 /* BATs management */
1009 #if !defined(FLUSH_ALL_TLBS)
1010 static inline void do_invalidate_BAT (CPUPPCState *env,
1011 target_ulong BATu, target_ulong mask)
1012 {
1013 target_ulong base, end, page;
1014
1015 base = BATu & ~0x0001FFFF;
1016 end = base + mask + 0x00020000;
1017 #if defined (DEBUG_BATS)
1018 if (loglevel != 0) {
1019 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1020 base, end, mask);
1021 }
1022 #endif
1023 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1024 tlb_flush_page(env, page);
1025 #if defined (DEBUG_BATS)
1026 if (loglevel != 0)
1027 fprintf(logfile, "Flush done\n");
1028 #endif
1029 }
1030 #endif
1031
1032 static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1033 target_ulong value)
1034 {
1035 #if defined (DEBUG_BATS)
1036 if (loglevel != 0) {
1037 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1038 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1039 }
1040 #endif
1041 }
1042
1043 target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1044 {
1045 return env->IBAT[0][nr];
1046 }
1047
1048 target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1049 {
1050 return env->IBAT[1][nr];
1051 }
1052
1053 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1054 {
1055 target_ulong mask;
1056
1057 dump_store_bat(env, 'I', 0, nr, value);
1058 if (env->IBAT[0][nr] != value) {
1059 mask = (value << 15) & 0x0FFE0000UL;
1060 #if !defined(FLUSH_ALL_TLBS)
1061 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1062 #endif
1063 /* When storing valid upper BAT, mask BEPI and BRPN
1064 * and invalidate all TLBs covered by this BAT
1065 */
1066 mask = (value << 15) & 0x0FFE0000UL;
1067 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1068 (value & ~0x0001FFFFUL & ~mask);
1069 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1070 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1071 #if !defined(FLUSH_ALL_TLBS)
1072 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1073 #else
1074 tlb_flush(env, 1);
1075 #endif
1076 }
1077 }
1078
1079 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1080 {
1081 dump_store_bat(env, 'I', 1, nr, value);
1082 env->IBAT[1][nr] = value;
1083 }
1084
1085 target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1086 {
1087 return env->DBAT[0][nr];
1088 }
1089
1090 target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1091 {
1092 return env->DBAT[1][nr];
1093 }
1094
1095 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1096 {
1097 target_ulong mask;
1098
1099 dump_store_bat(env, 'D', 0, nr, value);
1100 if (env->DBAT[0][nr] != value) {
1101 /* When storing valid upper BAT, mask BEPI and BRPN
1102 * and invalidate all TLBs covered by this BAT
1103 */
1104 mask = (value << 15) & 0x0FFE0000UL;
1105 #if !defined(FLUSH_ALL_TLBS)
1106 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1107 #endif
1108 mask = (value << 15) & 0x0FFE0000UL;
1109 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1110 (value & ~0x0001FFFFUL & ~mask);
1111 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1112 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1113 #if !defined(FLUSH_ALL_TLBS)
1114 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1115 #else
1116 tlb_flush(env, 1);
1117 #endif
1118 }
1119 }
1120
1121 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1122 {
1123 dump_store_bat(env, 'D', 1, nr, value);
1124 env->DBAT[1][nr] = value;
1125 }
1126
1127
1128 /*****************************************************************************/
1129 /* TLB management */
1130 void ppc_tlb_invalidate_all (CPUPPCState *env)
1131 {
1132 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
1133 ppc6xx_tlb_invalidate_all(env);
1134 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
1135 ppc4xx_tlb_invalidate_all(env);
1136 } else {
1137 tlb_flush(env, 1);
1138 }
1139 }
1140
1141 /*****************************************************************************/
1142 /* Special registers manipulation */
1143 #if defined(TARGET_PPC64)
1144 target_ulong ppc_load_asr (CPUPPCState *env)
1145 {
1146 return env->asr;
1147 }
1148
1149 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1150 {
1151 if (env->asr != value) {
1152 env->asr = value;
1153 tlb_flush(env, 1);
1154 }
1155 }
1156 #endif
1157
1158 target_ulong do_load_sdr1 (CPUPPCState *env)
1159 {
1160 return env->sdr1;
1161 }
1162
1163 void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1164 {
1165 #if defined (DEBUG_MMU)
1166 if (loglevel != 0) {
1167 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
1168 }
1169 #endif
1170 if (env->sdr1 != value) {
1171 env->sdr1 = value;
1172 tlb_flush(env, 1);
1173 }
1174 }
1175
1176 target_ulong do_load_sr (CPUPPCState *env, int srnum)
1177 {
1178 return env->sr[srnum];
1179 }
1180
1181 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1182 {
1183 #if defined (DEBUG_MMU)
1184 if (loglevel != 0) {
1185 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1186 __func__, srnum, value, env->sr[srnum]);
1187 }
1188 #endif
1189 if (env->sr[srnum] != value) {
1190 env->sr[srnum] = value;
1191 #if !defined(FLUSH_ALL_TLBS) && 0
1192 {
1193 target_ulong page, end;
1194 /* Invalidate 256 MB of virtual memory */
1195 page = (16 << 20) * srnum;
1196 end = page + (16 << 20);
1197 for (; page != end; page += TARGET_PAGE_SIZE)
1198 tlb_flush_page(env, page);
1199 }
1200 #else
1201 tlb_flush(env, 1);
1202 #endif
1203 }
1204 }
1205 #endif /* !defined (CONFIG_USER_ONLY) */
1206
1207 uint32_t ppc_load_xer (CPUPPCState *env)
1208 {
1209 return (xer_so << XER_SO) |
1210 (xer_ov << XER_OV) |
1211 (xer_ca << XER_CA) |
1212 (xer_bc << XER_BC) |
1213 (xer_cmp << XER_CMP);
1214 }
1215
1216 void ppc_store_xer (CPUPPCState *env, uint32_t value)
1217 {
1218 xer_so = (value >> XER_SO) & 0x01;
1219 xer_ov = (value >> XER_OV) & 0x01;
1220 xer_ca = (value >> XER_CA) & 0x01;
1221 xer_cmp = (value >> XER_CMP) & 0xFF;
1222 xer_bc = (value >> XER_BC) & 0x7F;
1223 }
1224
1225 /* Swap temporary saved registers with GPRs */
1226 static inline void swap_gpr_tgpr (CPUPPCState *env)
1227 {
1228 ppc_gpr_t tmp;
1229
1230 tmp = env->gpr[0];
1231 env->gpr[0] = env->tgpr[0];
1232 env->tgpr[0] = tmp;
1233 tmp = env->gpr[1];
1234 env->gpr[1] = env->tgpr[1];
1235 env->tgpr[1] = tmp;
1236 tmp = env->gpr[2];
1237 env->gpr[2] = env->tgpr[2];
1238 env->tgpr[2] = tmp;
1239 tmp = env->gpr[3];
1240 env->gpr[3] = env->tgpr[3];
1241 env->tgpr[3] = tmp;
1242 }
1243
1244 /* GDBstub can read and write MSR... */
1245 target_ulong do_load_msr (CPUPPCState *env)
1246 {
1247 return
1248 #if defined (TARGET_PPC64)
1249 ((target_ulong)msr_sf << MSR_SF) |
1250 ((target_ulong)msr_isf << MSR_ISF) |
1251 ((target_ulong)msr_hv << MSR_HV) |
1252 #endif
1253 ((target_ulong)msr_ucle << MSR_UCLE) |
1254 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1255 ((target_ulong)msr_ap << MSR_AP) |
1256 ((target_ulong)msr_sa << MSR_SA) |
1257 ((target_ulong)msr_key << MSR_KEY) |
1258 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1259 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1260 ((target_ulong)msr_ile << MSR_ILE) |
1261 ((target_ulong)msr_ee << MSR_EE) |
1262 ((target_ulong)msr_pr << MSR_PR) |
1263 ((target_ulong)msr_fp << MSR_FP) |
1264 ((target_ulong)msr_me << MSR_ME) |
1265 ((target_ulong)msr_fe0 << MSR_FE0) |
1266 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1267 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1268 ((target_ulong)msr_fe1 << MSR_FE1) |
1269 ((target_ulong)msr_al << MSR_AL) |
1270 ((target_ulong)msr_ip << MSR_IP) |
1271 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1272 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1273 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1274 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1275 ((target_ulong)msr_ri << MSR_RI) |
1276 ((target_ulong)msr_le << MSR_LE);
1277 }
1278
1279 void do_store_msr (CPUPPCState *env, target_ulong value)
1280 {
1281 int enter_pm;
1282
1283 value &= env->msr_mask;
1284 if (((value >> MSR_IR) & 1) != msr_ir ||
1285 ((value >> MSR_DR) & 1) != msr_dr) {
1286 /* Flush all tlb when changing translation mode */
1287 tlb_flush(env, 1);
1288 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1289 }
1290 #if 0
1291 if (loglevel != 0) {
1292 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1293 }
1294 #endif
1295 switch (PPC_EXCP(env)) {
1296 case PPC_FLAGS_EXCP_602:
1297 case PPC_FLAGS_EXCP_603:
1298 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1299 /* Swap temporary saved registers with GPRs */
1300 swap_gpr_tgpr(env);
1301 }
1302 break;
1303 default:
1304 break;
1305 }
1306 #if defined (TARGET_PPC64)
1307 msr_sf = (value >> MSR_SF) & 1;
1308 msr_isf = (value >> MSR_ISF) & 1;
1309 msr_hv = (value >> MSR_HV) & 1;
1310 #endif
1311 msr_ucle = (value >> MSR_UCLE) & 1;
1312 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1313 msr_ap = (value >> MSR_AP) & 1;
1314 msr_sa = (value >> MSR_SA) & 1;
1315 msr_key = (value >> MSR_KEY) & 1;
1316 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1317 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1318 msr_ile = (value >> MSR_ILE) & 1;
1319 msr_ee = (value >> MSR_EE) & 1;
1320 msr_pr = (value >> MSR_PR) & 1;
1321 msr_fp = (value >> MSR_FP) & 1;
1322 msr_me = (value >> MSR_ME) & 1;
1323 msr_fe0 = (value >> MSR_FE0) & 1;
1324 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1325 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1326 msr_fe1 = (value >> MSR_FE1) & 1;
1327 msr_al = (value >> MSR_AL) & 1;
1328 msr_ip = (value >> MSR_IP) & 1;
1329 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1330 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1331 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1332 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1333 msr_ri = (value >> MSR_RI) & 1;
1334 msr_le = (value >> MSR_LE) & 1;
1335 do_compute_hflags(env);
1336
1337 enter_pm = 0;
1338 switch (PPC_EXCP(env)) {
1339 case PPC_FLAGS_EXCP_603:
1340 /* Don't handle SLEEP mode: we should disable all clocks...
1341 * No dynamic power-management.
1342 */
1343 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1344 enter_pm = 1;
1345 break;
1346 case PPC_FLAGS_EXCP_604:
1347 if (msr_pow == 1)
1348 enter_pm = 1;
1349 break;
1350 case PPC_FLAGS_EXCP_7x0:
1351 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
1352 enter_pm = 1;
1353 break;
1354 default:
1355 break;
1356 }
1357 if (enter_pm) {
1358 /* power save: exit cpu loop */
1359 env->halted = 1;
1360 env->exception_index = EXCP_HLT;
1361 cpu_loop_exit();
1362 }
1363 }
1364
1365 #if defined(TARGET_PPC64)
1366 void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
1367 {
1368 do_store_msr(env,
1369 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
1370 }
1371 #endif
1372
1373 void do_compute_hflags (CPUPPCState *env)
1374 {
1375 /* Compute current hflags */
1376 env->hflags = (msr_cm << MSR_CM) | (msr_vr << MSR_VR) |
1377 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1378 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1379 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
1380 #if defined (TARGET_PPC64)
1381 /* No care here: PowerPC 64 MSR_SF means the same as MSR_CM for BookE */
1382 env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32));
1383 #endif
1384 }
1385
1386 /*****************************************************************************/
1387 /* Exception processing */
1388 #if defined (CONFIG_USER_ONLY)
1389 void do_interrupt (CPUState *env)
1390 {
1391 env->exception_index = -1;
1392 }
1393
1394 void ppc_hw_interrupt (CPUState *env)
1395 {
1396 env->exception_index = -1;
1397 }
1398 #else /* defined (CONFIG_USER_ONLY) */
1399 static void dump_syscall(CPUState *env)
1400 {
1401 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1402 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
1403 env->gpr[0], env->gpr[3], env->gpr[4],
1404 env->gpr[5], env->gpr[6], env->nip);
1405 }
1406
1407 void do_interrupt (CPUState *env)
1408 {
1409 target_ulong msr, *srr_0, *srr_1, *asrr_0, *asrr_1;
1410 int excp, idx;
1411
1412 excp = env->exception_index;
1413 msr = do_load_msr(env);
1414 /* The default is to use SRR0 & SRR1 to save the exception context */
1415 srr_0 = &env->spr[SPR_SRR0];
1416 srr_1 = &env->spr[SPR_SRR1];
1417 asrr_0 = NULL;
1418 asrr_1 = NULL;
1419 #if defined (DEBUG_EXCEPTIONS)
1420 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1421 if (loglevel != 0) {
1422 fprintf(logfile,
1423 "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1424 env->nip, excp, env->error_code);
1425 cpu_dump_state(env, logfile, fprintf, 0);
1426 }
1427 }
1428 #endif
1429 if (loglevel & CPU_LOG_INT) {
1430 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1431 env->nip, excp, env->error_code);
1432 }
1433 msr_pow = 0;
1434 idx = -1;
1435 /* Generate informations in save/restore registers */
1436 switch (excp) {
1437 /* Generic PowerPC exceptions */
1438 case EXCP_RESET: /* 0x0100 */
1439 switch (PPC_EXCP(env)) {
1440 case PPC_FLAGS_EXCP_40x:
1441 srr_0 = &env->spr[SPR_40x_SRR2];
1442 srr_1 = &env->spr[SPR_40x_SRR3];
1443 break;
1444 case PPC_FLAGS_EXCP_BOOKE:
1445 idx = 0;
1446 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1447 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1448 break;
1449 default:
1450 if (msr_ip)
1451 excp += 0xFFC00;
1452 excp |= 0xFFC00000;
1453 break;
1454 }
1455 goto store_next;
1456 case EXCP_MACHINE_CHECK: /* 0x0200 */
1457 switch (PPC_EXCP(env)) {
1458 case PPC_FLAGS_EXCP_40x:
1459 srr_0 = &env->spr[SPR_40x_SRR2];
1460 srr_1 = &env->spr[SPR_40x_SRR3];
1461 break;
1462 case PPC_FLAGS_EXCP_BOOKE:
1463 idx = 1;
1464 srr_0 = &env->spr[SPR_BOOKE_MCSRR0];
1465 srr_1 = &env->spr[SPR_BOOKE_MCSRR1];
1466 asrr_0 = &env->spr[SPR_BOOKE_CSRR0];
1467 asrr_1 = &env->spr[SPR_BOOKE_CSRR1];
1468 msr_ce = 0;
1469 break;
1470 default:
1471 break;
1472 }
1473 msr_me = 0;
1474 break;
1475 case EXCP_DSI: /* 0x0300 */
1476 /* Store exception cause */
1477 /* data location address has been stored
1478 * when the fault has been detected
1479 */
1480 idx = 2;
1481 msr &= ~0xFFFF0000;
1482 #if defined (DEBUG_EXCEPTIONS)
1483 if (loglevel) {
1484 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1485 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1486 }
1487 #endif
1488 goto store_next;
1489 case EXCP_ISI: /* 0x0400 */
1490 /* Store exception cause */
1491 idx = 3;
1492 msr &= ~0xFFFF0000;
1493 msr |= env->error_code;
1494 #if defined (DEBUG_EXCEPTIONS)
1495 if (loglevel != 0) {
1496 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
1497 "\n", msr, env->nip);
1498 }
1499 #endif
1500 goto store_next;
1501 case EXCP_EXTERNAL: /* 0x0500 */
1502 idx = 4;
1503 goto store_next;
1504 case EXCP_ALIGN: /* 0x0600 */
1505 if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
1506 /* Store exception cause */
1507 idx = 5;
1508 /* Get rS/rD and rA from faulting opcode */
1509 env->spr[SPR_DSISR] |=
1510 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1511 /* data location address has been stored
1512 * when the fault has been detected
1513 */
1514 } else {
1515 /* IO error exception on PowerPC 601 */
1516 /* XXX: TODO */
1517 cpu_abort(env,
1518 "601 IO error exception is not implemented yet !\n");
1519 }
1520 goto store_current;
1521 case EXCP_PROGRAM: /* 0x0700 */
1522 idx = 6;
1523 msr &= ~0xFFFF0000;
1524 switch (env->error_code & ~0xF) {
1525 case EXCP_FP:
1526 if (msr_fe0 == 0 && msr_fe1 == 0) {
1527 #if defined (DEBUG_EXCEPTIONS)
1528 if (loglevel) {
1529 fprintf(logfile, "Ignore floating point exception\n");
1530 }
1531 #endif
1532 return;
1533 }
1534 msr |= 0x00100000;
1535 /* Set FX */
1536 env->fpscr[7] |= 0x8;
1537 /* Finally, update FEX */
1538 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1539 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1540 env->fpscr[7] |= 0x4;
1541 break;
1542 case EXCP_INVAL:
1543 #if defined (DEBUG_EXCEPTIONS)
1544 if (loglevel) {
1545 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
1546 env->nip);
1547 }
1548 #endif
1549 msr |= 0x00080000;
1550 break;
1551 case EXCP_PRIV:
1552 msr |= 0x00040000;
1553 break;
1554 case EXCP_TRAP:
1555 idx = 15;
1556 msr |= 0x00020000;
1557 break;
1558 default:
1559 /* Should never occur */
1560 break;
1561 }
1562 msr |= 0x00010000;
1563 goto store_current;
1564 case EXCP_NO_FP: /* 0x0800 */
1565 idx = 7;
1566 msr &= ~0xFFFF0000;
1567 goto store_current;
1568 case EXCP_DECR:
1569 goto store_next;
1570 case EXCP_SYSCALL: /* 0x0C00 */
1571 idx = 8;
1572 /* NOTE: this is a temporary hack to support graphics OSI
1573 calls from the MOL driver */
1574 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1575 env->osi_call) {
1576 if (env->osi_call(env) != 0)
1577 return;
1578 }
1579 if (loglevel & CPU_LOG_INT) {
1580 dump_syscall(env);
1581 }
1582 goto store_next;
1583 case EXCP_TRACE: /* 0x0D00 */
1584 goto store_next;
1585 case EXCP_PERF: /* 0x0F00 */
1586 /* XXX: TODO */
1587 cpu_abort(env,
1588 "Performance counter exception is not implemented yet !\n");
1589 goto store_next;
1590 /* 32 bits PowerPC specific exceptions */
1591 case EXCP_FP_ASSIST: /* 0x0E00 */
1592 /* XXX: TODO */
1593 cpu_abort(env, "Floating point assist exception "
1594 "is not implemented yet !\n");
1595 goto store_next;
1596 /* 64 bits PowerPC exceptions */
1597 case EXCP_DSEG: /* 0x0380 */
1598 /* XXX: TODO */
1599 cpu_abort(env, "Data segment exception is not implemented yet !\n");
1600 goto store_next;
1601 case EXCP_ISEG: /* 0x0480 */
1602 /* XXX: TODO */
1603 cpu_abort(env,
1604 "Instruction segment exception is not implemented yet !\n");
1605 goto store_next;
1606 case EXCP_HDECR: /* 0x0980 */
1607 /* XXX: TODO */
1608 cpu_abort(env, "Hypervisor decrementer exception is not implemented "
1609 "yet !\n");
1610 goto store_next;
1611 /* Implementation specific exceptions */
1612 case 0x0A00:
1613 if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
1614 env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
1615 /* Critical interrupt on G2 */
1616 /* XXX: TODO */
1617 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1618 goto store_next;
1619 } else {
1620 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1621 }
1622 return;
1623 case 0x0F20:
1624 idx = 9;
1625 switch (PPC_EXCP(env)) {
1626 case PPC_FLAGS_EXCP_40x:
1627 /* APU unavailable on 405 */
1628 /* XXX: TODO */
1629 cpu_abort(env,
1630 "APU unavailable exception is not implemented yet !\n");
1631 goto store_next;
1632 case PPC_FLAGS_EXCP_74xx:
1633 /* Altivec unavailable */
1634 /* XXX: TODO */
1635 cpu_abort(env, "Altivec unavailable exception "
1636 "is not implemented yet !\n");
1637 goto store_next;
1638 default:
1639 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1640 break;
1641 }
1642 return;
1643 case 0x1000:
1644 idx = 10;
1645 switch (PPC_EXCP(env)) {
1646 case PPC_FLAGS_EXCP_40x:
1647 /* PIT on 4xx */
1648 msr &= ~0xFFFF0000;
1649 #if defined (DEBUG_EXCEPTIONS)
1650 if (loglevel != 0)
1651 fprintf(logfile, "PIT exception\n");
1652 #endif
1653 goto store_next;
1654 case PPC_FLAGS_EXCP_602:
1655 case PPC_FLAGS_EXCP_603:
1656 /* ITLBMISS on 602/603 */
1657 goto store_gprs;
1658 case PPC_FLAGS_EXCP_7x5:
1659 /* ITLBMISS on 745/755 */
1660 goto tlb_miss;
1661 default:
1662 cpu_abort(env, "Invalid exception 0x1000 !\n");
1663 break;
1664 }
1665 return;
1666 case 0x1010:
1667 idx = 11;
1668 switch (PPC_EXCP(env)) {
1669 case PPC_FLAGS_EXCP_40x:
1670 /* FIT on 4xx */
1671 msr &= ~0xFFFF0000;
1672 #if defined (DEBUG_EXCEPTIONS)
1673 if (loglevel != 0)
1674 fprintf(logfile, "FIT exception\n");
1675 #endif
1676 goto store_next;
1677 default:
1678 cpu_abort(env, "Invalid exception 0x1010 !\n");
1679 break;
1680 }
1681 return;
1682 case 0x1020:
1683 idx = 12;
1684 switch (PPC_EXCP(env)) {
1685 case PPC_FLAGS_EXCP_40x:
1686 /* Watchdog on 4xx */
1687 msr &= ~0xFFFF0000;
1688 #if defined (DEBUG_EXCEPTIONS)
1689 if (loglevel != 0)
1690 fprintf(logfile, "WDT exception\n");
1691 #endif
1692 goto store_next;
1693 case PPC_FLAGS_EXCP_BOOKE:
1694 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1695 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1696 break;
1697 default:
1698 cpu_abort(env, "Invalid exception 0x1020 !\n");
1699 break;
1700 }
1701 return;
1702 case 0x1100:
1703 idx = 13;
1704 switch (PPC_EXCP(env)) {
1705 case PPC_FLAGS_EXCP_40x:
1706 /* DTLBMISS on 4xx */
1707 msr &= ~0xFFFF0000;
1708 goto store_next;
1709 case PPC_FLAGS_EXCP_602:
1710 case PPC_FLAGS_EXCP_603:
1711 /* DLTLBMISS on 602/603 */
1712 goto store_gprs;
1713 case PPC_FLAGS_EXCP_7x5:
1714 /* DLTLBMISS on 745/755 */
1715 goto tlb_miss;
1716 default:
1717 cpu_abort(env, "Invalid exception 0x1100 !\n");
1718 break;
1719 }
1720 return;
1721 case 0x1200:
1722 idx = 14;
1723 switch (PPC_EXCP(env)) {
1724 case PPC_FLAGS_EXCP_40x:
1725 /* ITLBMISS on 4xx */
1726 msr &= ~0xFFFF0000;
1727 goto store_next;
1728 case PPC_FLAGS_EXCP_602:
1729 case PPC_FLAGS_EXCP_603:
1730 /* DSTLBMISS on 602/603 */
1731 store_gprs:
1732 /* Swap temporary saved registers with GPRs */
1733 swap_gpr_tgpr(env);
1734 msr_tgpr = 1;
1735 #if defined (DEBUG_SOFTWARE_TLB)
1736 if (loglevel != 0) {
1737 const unsigned char *es;
1738 target_ulong *miss, *cmp;
1739 int en;
1740 if (excp == 0x1000) {
1741 es = "I";
1742 en = 'I';
1743 miss = &env->spr[SPR_IMISS];
1744 cmp = &env->spr[SPR_ICMP];
1745 } else {
1746 if (excp == 0x1100)
1747 es = "DL";
1748 else
1749 es = "DS";
1750 en = 'D';
1751 miss = &env->spr[SPR_DMISS];
1752 cmp = &env->spr[SPR_DCMP];
1753 }
1754 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
1755 " H1 " ADDRX " H2 " ADDRX " " ADDRX "\n",
1756 es, en, *miss, en, *cmp,
1757 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
1758 env->error_code);
1759 }
1760 #endif
1761 goto tlb_miss;
1762 case PPC_FLAGS_EXCP_7x5:
1763 /* DSTLBMISS on 745/755 */
1764 tlb_miss:
1765 msr &= ~0xF83F0000;
1766 msr |= env->crf[0] << 28;
1767 msr |= env->error_code; /* key, D/I, S/L bits */
1768 /* Set way using a LRU mechanism */
1769 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
1770 goto store_next;
1771 default:
1772 cpu_abort(env, "Invalid exception 0x1200 !\n");
1773 break;
1774 }
1775 return;
1776 case 0x1300:
1777 switch (PPC_EXCP(env)) {
1778 case PPC_FLAGS_EXCP_601:
1779 case PPC_FLAGS_EXCP_602:
1780 case PPC_FLAGS_EXCP_603:
1781 case PPC_FLAGS_EXCP_604:
1782 case PPC_FLAGS_EXCP_7x0:
1783 case PPC_FLAGS_EXCP_7x5:
1784 /* IABR on 6xx/7xx */
1785 /* XXX: TODO */
1786 cpu_abort(env, "IABR exception is not implemented yet !\n");
1787 goto store_next;
1788 default:
1789 cpu_abort(env, "Invalid exception 0x1300 !\n");
1790 break;
1791 }
1792 return;
1793 case 0x1400:
1794 switch (PPC_EXCP(env)) {
1795 case PPC_FLAGS_EXCP_601:
1796 case PPC_FLAGS_EXCP_602:
1797 case PPC_FLAGS_EXCP_603:
1798 case PPC_FLAGS_EXCP_604:
1799 case PPC_FLAGS_EXCP_7x0:
1800 case PPC_FLAGS_EXCP_7x5:
1801 /* SMI on 6xx/7xx */
1802 /* XXX: TODO */
1803 cpu_abort(env, "SMI exception is not implemented yet !\n");
1804 goto store_next;
1805 default:
1806 cpu_abort(env, "Invalid exception 0x1400 !\n");
1807 break;
1808 }
1809 return;
1810 case 0x1500:
1811 switch (PPC_EXCP(env)) {
1812 case PPC_FLAGS_EXCP_602:
1813 /* Watchdog on 602 */
1814 /* XXX: TODO */
1815 cpu_abort(env,
1816 "602 watchdog exception is not implemented yet !\n");
1817 goto store_next;
1818 case PPC_FLAGS_EXCP_970:
1819 /* Soft patch exception on 970 */
1820 /* XXX: TODO */
1821 cpu_abort(env,
1822 "970 soft-patch exception is not implemented yet !\n");
1823 goto store_next;
1824 case PPC_FLAGS_EXCP_74xx:
1825 /* VPU assist on 74xx */
1826 /* XXX: TODO */
1827 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1828 goto store_next;
1829 default:
1830 cpu_abort(env, "Invalid exception 0x1500 !\n");
1831 break;
1832 }
1833 return;
1834 case 0x1600:
1835 switch (PPC_EXCP(env)) {
1836 case PPC_FLAGS_EXCP_602:
1837 /* Emulation trap on 602 */
1838 /* XXX: TODO */
1839 cpu_abort(env, "602 emulation trap exception "
1840 "is not implemented yet !\n");
1841 goto store_next;
1842 case PPC_FLAGS_EXCP_970:
1843 /* Maintenance exception on 970 */
1844 /* XXX: TODO */
1845 cpu_abort(env,
1846 "970 maintenance exception is not implemented yet !\n");
1847 goto store_next;
1848 default:
1849 cpu_abort(env, "Invalid exception 0x1600 !\n");
1850 break;
1851 }
1852 return;
1853 case 0x1700:
1854 switch (PPC_EXCP(env)) {
1855 case PPC_FLAGS_EXCP_7x0:
1856 case PPC_FLAGS_EXCP_7x5:
1857 /* Thermal management interrupt on G3 */
1858 /* XXX: TODO */
1859 cpu_abort(env, "G3 thermal management exception "
1860 "is not implemented yet !\n");
1861 goto store_next;
1862 case PPC_FLAGS_EXCP_970:
1863 /* VPU assist on 970 */
1864 /* XXX: TODO */
1865 cpu_abort(env,
1866 "970 VPU assist exception is not implemented yet !\n");
1867 goto store_next;
1868 default:
1869 cpu_abort(env, "Invalid exception 0x1700 !\n");
1870 break;
1871 }
1872 return;
1873 case 0x1800:
1874 switch (PPC_EXCP(env)) {
1875 case PPC_FLAGS_EXCP_970:
1876 /* Thermal exception on 970 */
1877 /* XXX: TODO */
1878 cpu_abort(env, "970 thermal management exception "
1879 "is not implemented yet !\n");
1880 goto store_next;
1881 default:
1882 cpu_abort(env, "Invalid exception 0x1800 !\n");
1883 break;
1884 }
1885 return;
1886 case 0x2000:
1887 switch (PPC_EXCP(env)) {
1888 case PPC_FLAGS_EXCP_40x:
1889 /* DEBUG on 4xx */
1890 /* XXX: TODO */
1891 cpu_abort(env, "40x debug exception is not implemented yet !\n");
1892 goto store_next;
1893 case PPC_FLAGS_EXCP_601:
1894 /* Run mode exception on 601 */
1895 /* XXX: TODO */
1896 cpu_abort(env,
1897 "601 run mode exception is not implemented yet !\n");
1898 goto store_next;
1899 case PPC_FLAGS_EXCP_BOOKE:
1900 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1901 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1902 break;
1903 default:
1904 cpu_abort(env, "Invalid exception 0x1800 !\n");
1905 break;
1906 }
1907 return;
1908 /* Other exceptions */
1909 /* Qemu internal exceptions:
1910 * we should never come here with those values: abort execution
1911 */
1912 default:
1913 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
1914 return;
1915 store_current:
1916 /* save current instruction location */
1917 *srr_0 = env->nip - 4;
1918 break;
1919 store_next:
1920 /* save next instruction location */
1921 *srr_0 = env->nip;
1922 break;
1923 }
1924 /* Save msr */
1925 *srr_1 = msr;
1926 if (asrr_0 != NULL)
1927 *asrr_0 = *srr_0;
1928 if (asrr_1 != NULL)
1929 *asrr_1 = *srr_1;
1930 /* If we disactivated any translation, flush TLBs */
1931 if (msr_ir || msr_dr) {
1932 tlb_flush(env, 1);
1933 }
1934 /* reload MSR with correct bits */
1935 msr_ee = 0;
1936 msr_pr = 0;
1937 msr_fp = 0;
1938 msr_fe0 = 0;
1939 msr_se = 0;
1940 msr_be = 0;
1941 msr_fe1 = 0;
1942 msr_ir = 0;
1943 msr_dr = 0;
1944 msr_ri = 0;
1945 msr_le = msr_ile;
1946 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_BOOKE) {
1947 msr_cm = msr_icm;
1948 if (idx == -1 || (idx >= 16 && idx < 32)) {
1949 cpu_abort(env, "Invalid exception index for excp %d %08x idx %d\n",
1950 excp, excp, idx);
1951 }
1952 #if defined(TARGET_PPC64)
1953 if (msr_cm)
1954 env->nip = (uint64_t)env->spr[SPR_BOOKE_IVPR];
1955 else
1956 #endif
1957 env->nip = (uint32_t)env->spr[SPR_BOOKE_IVPR];
1958 if (idx < 16)
1959 env->nip |= env->spr[SPR_BOOKE_IVOR0 + idx];
1960 else if (idx < 38)
1961 env->nip |= env->spr[SPR_BOOKE_IVOR32 + idx - 32];
1962 } else {
1963 msr_sf = msr_isf;
1964 env->nip = excp;
1965 }
1966 do_compute_hflags(env);
1967 /* Jump to handler */
1968 env->exception_index = EXCP_NONE;
1969 }
1970
1971 void ppc_hw_interrupt (CPUPPCState *env)
1972 {
1973 int raised = 0;
1974
1975 #if 1
1976 if (loglevel & CPU_LOG_INT) {
1977 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
1978 __func__, env, env->pending_interrupts,
1979 env->interrupt_request, msr_me, msr_ee);
1980 }
1981 #endif
1982 /* Raise it */
1983 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
1984 /* External reset / critical input */
1985 /* XXX: critical input should be handled another way.
1986 * This code is not correct !
1987 */
1988 env->exception_index = EXCP_RESET;
1989 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
1990 raised = 1;
1991 }
1992 if (raised == 0 && msr_me != 0) {
1993 /* Machine check exception */
1994 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
1995 env->exception_index = EXCP_MACHINE_CHECK;
1996 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
1997 raised = 1;
1998 }
1999 }
2000 if (raised == 0 && msr_ee != 0) {
2001 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2002 /* Hypervisor decrementer exception */
2003 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2004 env->exception_index = EXCP_HDECR;
2005 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2006 raised = 1;
2007 } else
2008 #endif
2009 /* Decrementer exception */
2010 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2011 env->exception_index = EXCP_DECR;
2012 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2013 raised = 1;
2014 /* Programmable interval timer on embedded PowerPC */
2015 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2016 env->exception_index = EXCP_40x_PIT;
2017 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2018 raised = 1;
2019 /* Fixed interval timer on embedded PowerPC */
2020 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2021 env->exception_index = EXCP_40x_FIT;
2022 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2023 raised = 1;
2024 /* Watchdog timer on embedded PowerPC */
2025 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2026 env->exception_index = EXCP_40x_WATCHDOG;
2027 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2028 raised = 1;
2029 /* External interrupt */
2030 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2031 env->exception_index = EXCP_EXTERNAL;
2032 /* Taking an external interrupt does not clear the external
2033 * interrupt status
2034 */
2035 #if 0
2036 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2037 #endif
2038 raised = 1;
2039 #if 0 // TODO
2040 /* Thermal interrupt */
2041 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2042 env->exception_index = EXCP_970_THRM;
2043 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2044 raised = 1;
2045 #endif
2046 }
2047 #if 0 // TODO
2048 /* External debug exception */
2049 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2050 env->exception_index = EXCP_xxx;
2051 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2052 raised = 1;
2053 #endif
2054 }
2055 if (raised != 0) {
2056 env->error_code = 0;
2057 do_interrupt(env);
2058 }
2059 }
2060 #endif /* !CONFIG_USER_ONLY */
2061
2062 void cpu_dump_EA (target_ulong EA)
2063 {
2064 FILE *f;
2065
2066 if (logfile) {
2067 f = logfile;
2068 } else {
2069 f = stdout;
2070 return;
2071 }
2072 fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA);
2073 }
2074
2075 void cpu_ppc_reset (void *opaque)
2076 {
2077 CPUPPCState *env;
2078
2079 env = opaque;
2080 #if defined (DO_SINGLE_STEP) && 0
2081 /* Single step trace mode */
2082 msr_se = 1;
2083 msr_be = 1;
2084 #endif
2085 msr_fp = 1; /* Allow floating point exceptions */
2086 msr_me = 1; /* Allow machine check exceptions */
2087 #if defined(TARGET_PPC64)
2088 msr_sf = 0; /* Boot in 32 bits mode */
2089 msr_cm = 0;
2090 #endif
2091 #if defined(CONFIG_USER_ONLY)
2092 msr_pr = 1;
2093 tlb_flush(env, 1);
2094 #else
2095 env->nip = 0xFFFFFFFC;
2096 ppc_tlb_invalidate_all(env);
2097 #endif
2098 do_compute_hflags(env);
2099 env->reserve = -1;
2100 }
2101
2102 CPUPPCState *cpu_ppc_init (void)
2103 {
2104 CPUPPCState *env;
2105
2106 env = qemu_mallocz(sizeof(CPUPPCState));
2107 if (!env)
2108 return NULL;
2109 cpu_exec_init(env);
2110 cpu_ppc_reset(env);
2111
2112 return env;
2113 }
2114
2115 void cpu_ppc_close (CPUPPCState *env)
2116 {
2117 /* Should also remove all opcode tables... */
2118 free(env);
2119 }
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