target-ppc/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "sysemu/kvm.h"
   4 #include "helper_regs.h"
   5
   6 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
   7 {
   8     PowerPCCPU *cpu = opaque;
   9     CPUPPCState *env = &cpu->env;
  10     unsigned int i, j;
  11     target_ulong sdr1;
  12     uint32_t fpscr;
  13     target_ulong xer;
  14
  15     for (i = 0; i < 32; i++)
  16         qemu_get_betls(f, &env->gpr[i]);
  17 #if !defined(TARGET_PPC64)
  18     for (i = 0; i < 32; i++)
  19         qemu_get_betls(f, &env->gprh[i]);
  20 #endif
  21     qemu_get_betls(f, &env->lr);
  22     qemu_get_betls(f, &env->ctr);
  23     for (i = 0; i < 8; i++)
  24         qemu_get_be32s(f, &env->crf[i]);
  25     qemu_get_betls(f, &xer);
  26     cpu_write_xer(env, xer);
  27     qemu_get_betls(f, &env->reserve_addr);
  28     qemu_get_betls(f, &env->msr);
  29     for (i = 0; i < 4; i++)
  30         qemu_get_betls(f, &env->tgpr[i]);
  31     for (i = 0; i < 32; i++) {
  32         union {
  33             float64 d;
  34             uint64_t l;
  35         } u;
  36         u.l = qemu_get_be64(f);
  37         env->fpr[i] = u.d;
  38     }
  39     qemu_get_be32s(f, &fpscr);
  40     env->fpscr = fpscr;
  41     qemu_get_sbe32s(f, &env->access_type);
  42 #if defined(TARGET_PPC64)
  43     qemu_get_betls(f, &env->spr[SPR_ASR]);
  44     qemu_get_sbe32s(f, &env->slb_nr);
  45 #endif
  46     qemu_get_betls(f, &sdr1);
  47     for (i = 0; i < 32; i++)
  48         qemu_get_betls(f, &env->sr[i]);
  49     for (i = 0; i < 2; i++)
  50         for (j = 0; j < 8; j++)
  51             qemu_get_betls(f, &env->DBAT[i][j]);
  52     for (i = 0; i < 2; i++)
  53         for (j = 0; j < 8; j++)
  54             qemu_get_betls(f, &env->IBAT[i][j]);
  55     qemu_get_sbe32s(f, &env->nb_tlb);
  56     qemu_get_sbe32s(f, &env->tlb_per_way);
  57     qemu_get_sbe32s(f, &env->nb_ways);
  58     qemu_get_sbe32s(f, &env->last_way);
  59     qemu_get_sbe32s(f, &env->id_tlbs);
  60     qemu_get_sbe32s(f, &env->nb_pids);
  61     if (env->tlb.tlb6) {
  62         // XXX assumes 6xx
  63         for (i = 0; i < env->nb_tlb; i++) {
  64             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  65             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  66             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  67         }
  68     }
  69     for (i = 0; i < 4; i++)
  70         qemu_get_betls(f, &env->pb[i]);
  71     for (i = 0; i < 1024; i++)
  72         qemu_get_betls(f, &env->spr[i]);
  73     if (!env->external_htab) {
  74         ppc_store_sdr1(env, sdr1);
  75     }
  76     qemu_get_be32s(f, &env->vscr);
  77     qemu_get_be64s(f, &env->spe_acc);
  78     qemu_get_be32s(f, &env->spe_fscr);
  79     qemu_get_betls(f, &env->msr_mask);
  80     qemu_get_be32s(f, &env->flags);
  81     qemu_get_sbe32s(f, &env->error_code);
  82     qemu_get_be32s(f, &env->pending_interrupts);
  83     qemu_get_be32s(f, &env->irq_input_state);
  84     for (i = 0; i < POWERPC_EXCP_NB; i++)
  85         qemu_get_betls(f, &env->excp_vectors[i]);
  86     qemu_get_betls(f, &env->excp_prefix);
  87     qemu_get_betls(f, &env->ivor_mask);
  88     qemu_get_betls(f, &env->ivpr_mask);
  89     qemu_get_betls(f, &env->hreset_vector);
  90     qemu_get_betls(f, &env->nip);
  91     qemu_get_betls(f, &env->hflags);
  92     qemu_get_betls(f, &env->hflags_nmsr);
  93     qemu_get_sbe32s(f, &env->mmu_idx);
  94     qemu_get_sbe32(f); /* Discard unused power_mode */
  95
  96     return 0;
  97 }
  98
  99 static int get_avr(QEMUFile *f, void *pv, size_t size)
 100 {
 101     ppc_avr_t *v = pv;
 102
 103     v->u64[0] = qemu_get_be64(f);
 104     v->u64[1] = qemu_get_be64(f);
 105
 106     return 0;
 107 }
 108
 109 static void put_avr(QEMUFile *f, void *pv, size_t size)
 110 {
 111     ppc_avr_t *v = pv;
 112
 113     qemu_put_be64(f, v->u64[0]);
 114     qemu_put_be64(f, v->u64[1]);
 115 }
 116
 117 static const VMStateInfo vmstate_info_avr = {
 118     .name = "avr",
 119     .get  = get_avr,
 120     .put  = put_avr,
 121 };
 122
 123 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 124     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 125
 126 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 127     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 128
 129 static void cpu_pre_save(void *opaque)
 130 {
 131     PowerPCCPU *cpu = opaque;
 132     CPUPPCState *env = &cpu->env;
 133     int i;
 134
 135     env->spr[SPR_LR] = env->lr;
 136     env->spr[SPR_CTR] = env->ctr;
 137     env->spr[SPR_XER] = env->xer;
 138 #if defined(TARGET_PPC64)
 139     env->spr[SPR_CFAR] = env->cfar;
 140 #endif
 141     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 142
 143     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 144         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 145         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 146         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 147         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 148     }
 149     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 150         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 151         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 152         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 153         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 154     }
 155 }
 156
 157 static int cpu_post_load(void *opaque, int version_id)
 158 {
 159     PowerPCCPU *cpu = opaque;
 160     CPUPPCState *env = &cpu->env;
 161     int i;
 162
 163     env->lr = env->spr[SPR_LR];
 164     env->ctr = env->spr[SPR_CTR];
 165     env->xer = env->spr[SPR_XER];
 166 #if defined(TARGET_PPC64)
 167     env->cfar = env->spr[SPR_CFAR];
 168 #endif
 169     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 170
 171     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 172         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 173         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 174         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 175         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 176     }
 177     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 178         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 179         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 180         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 181         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 182     }
 183
 184     if (!env->external_htab) {
 185         /* Restore htab_base and htab_mask variables */
 186         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 187     }
 188     hreg_compute_hflags(env);
 189     hreg_compute_mem_idx(env);
 190
 191     return 0;
 192 }
 193
 194 static bool fpu_needed(void *opaque)
 195 {
 196     PowerPCCPU *cpu = opaque;
 197
 198     return (cpu->env.insns_flags & PPC_FLOAT);
 199 }
 200
 201 static const VMStateDescription vmstate_fpu = {
 202     .name = "cpu/fpu",
 203     .version_id = 1,
 204     .minimum_version_id = 1,
 205     .fields = (VMStateField[]) {
 206         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 207         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 208         VMSTATE_END_OF_LIST()
 209     },
 210 };
 211
 212 static bool altivec_needed(void *opaque)
 213 {
 214     PowerPCCPU *cpu = opaque;
 215
 216     return (cpu->env.insns_flags & PPC_ALTIVEC);
 217 }
 218
 219 static const VMStateDescription vmstate_altivec = {
 220     .name = "cpu/altivec",
 221     .version_id = 1,
 222     .minimum_version_id = 1,
 223     .fields = (VMStateField[]) {
 224         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 225         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 226         VMSTATE_END_OF_LIST()
 227     },
 228 };
 229
 230 static bool vsx_needed(void *opaque)
 231 {
 232     PowerPCCPU *cpu = opaque;
 233
 234     return (cpu->env.insns_flags2 & PPC2_VSX);
 235 }
 236
 237 static const VMStateDescription vmstate_vsx = {
 238     .name = "cpu/vsx",
 239     .version_id = 1,
 240     .minimum_version_id = 1,
 241     .fields = (VMStateField[]) {
 242         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 243         VMSTATE_END_OF_LIST()
 244     },
 245 };
 246
 247 static bool sr_needed(void *opaque)
 248 {
 249 #ifdef TARGET_PPC64
 250     PowerPCCPU *cpu = opaque;
 251
 252     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 253 #else
 254     return true;
 255 #endif
 256 }
 257
 258 static const VMStateDescription vmstate_sr = {
 259     .name = "cpu/sr",
 260     .version_id = 1,
 261     .minimum_version_id = 1,
 262     .fields = (VMStateField[]) {
 263         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 264         VMSTATE_END_OF_LIST()
 265     },
 266 };
 267
 268 #ifdef TARGET_PPC64
 269 static int get_slbe(QEMUFile *f, void *pv, size_t size)
 270 {
 271     ppc_slb_t *v = pv;
 272
 273     v->esid = qemu_get_be64(f);
 274     v->vsid = qemu_get_be64(f);
 275
 276     return 0;
 277 }
 278
 279 static void put_slbe(QEMUFile *f, void *pv, size_t size)
 280 {
 281     ppc_slb_t *v = pv;
 282
 283     qemu_put_be64(f, v->esid);
 284     qemu_put_be64(f, v->vsid);
 285 }
 286
 287 static const VMStateInfo vmstate_info_slbe = {
 288     .name = "slbe",
 289     .get  = get_slbe,
 290     .put  = put_slbe,
 291 };
 292
 293 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 294     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 295
 296 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 297     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 298
 299 static bool slb_needed(void *opaque)
 300 {
 301     PowerPCCPU *cpu = opaque;
 302
 303     /* We don't support any of the old segment table based 64-bit CPUs */
 304     return (cpu->env.mmu_model & POWERPC_MMU_64);
 305 }
 306
 307 static const VMStateDescription vmstate_slb = {
 308     .name = "cpu/slb",
 309     .version_id = 1,
 310     .minimum_version_id = 1,
 311     .fields = (VMStateField[]) {
 312         VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
 313         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 314         VMSTATE_END_OF_LIST()
 315     }
 316 };
 317 #endif /* TARGET_PPC64 */
 318
 319 static const VMStateDescription vmstate_tlb6xx_entry = {
 320     .name = "cpu/tlb6xx_entry",
 321     .version_id = 1,
 322     .minimum_version_id = 1,
 323     .fields = (VMStateField[]) {
 324         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 325         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 326         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 327         VMSTATE_END_OF_LIST()
 328     },
 329 };
 330
 331 static bool tlb6xx_needed(void *opaque)
 332 {
 333     PowerPCCPU *cpu = opaque;
 334     CPUPPCState *env = &cpu->env;
 335
 336     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 337 }
 338
 339 static const VMStateDescription vmstate_tlb6xx = {
 340     .name = "cpu/tlb6xx",
 341     .version_id = 1,
 342     .minimum_version_id = 1,
 343     .fields = (VMStateField[]) {
 344         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 345         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 346                                             env.nb_tlb,
 347                                             vmstate_tlb6xx_entry,
 348                                             ppc6xx_tlb_t),
 349         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 350         VMSTATE_END_OF_LIST()
 351     }
 352 };
 353
 354 static const VMStateDescription vmstate_tlbemb_entry = {
 355     .name = "cpu/tlbemb_entry",
 356     .version_id = 1,
 357     .minimum_version_id = 1,
 358     .fields = (VMStateField[]) {
 359         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 360         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 361         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 362         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 363         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 364         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 365         VMSTATE_END_OF_LIST()
 366     },
 367 };
 368
 369 static bool tlbemb_needed(void *opaque)
 370 {
 371     PowerPCCPU *cpu = opaque;
 372     CPUPPCState *env = &cpu->env;
 373
 374     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 375 }
 376
 377 static bool pbr403_needed(void *opaque)
 378 {
 379     PowerPCCPU *cpu = opaque;
 380     uint32_t pvr = cpu->env.spr[SPR_PVR];
 381
 382     return (pvr & 0xffff0000) == 0x00200000;
 383 }
 384
 385 static const VMStateDescription vmstate_pbr403 = {
 386     .name = "cpu/pbr403",
 387     .version_id = 1,
 388     .minimum_version_id = 1,
 389     .fields = (VMStateField[]) {
 390         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 391         VMSTATE_END_OF_LIST()
 392     },
 393 };
 394
 395 static const VMStateDescription vmstate_tlbemb = {
 396     .name = "cpu/tlb6xx",
 397     .version_id = 1,
 398     .minimum_version_id = 1,
 399     .fields = (VMStateField[]) {
 400         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 401         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 402                                             env.nb_tlb,
 403                                             vmstate_tlbemb_entry,
 404                                             ppcemb_tlb_t),
 405         /* 403 protection registers */
 406         VMSTATE_END_OF_LIST()
 407     },
 408     .subsections = (VMStateSubsection []) {
 409         {
 410             .vmsd = &vmstate_pbr403,
 411             .needed = pbr403_needed,
 412         } , {
 413             /* empty */
 414         }
 415     }
 416 };
 417
 418 static const VMStateDescription vmstate_tlbmas_entry = {
 419     .name = "cpu/tlbmas_entry",
 420     .version_id = 1,
 421     .minimum_version_id = 1,
 422     .fields = (VMStateField[]) {
 423         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 424         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 425         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 426         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 427         VMSTATE_END_OF_LIST()
 428     },
 429 };
 430
 431 static bool tlbmas_needed(void *opaque)
 432 {
 433     PowerPCCPU *cpu = opaque;
 434     CPUPPCState *env = &cpu->env;
 435
 436     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 437 }
 438
 439 static const VMStateDescription vmstate_tlbmas = {
 440     .name = "cpu/tlbmas",
 441     .version_id = 1,
 442     .minimum_version_id = 1,
 443     .fields = (VMStateField[]) {
 444         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 445         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 446                                             env.nb_tlb,
 447                                             vmstate_tlbmas_entry,
 448                                             ppcmas_tlb_t),
 449         VMSTATE_END_OF_LIST()
 450     }
 451 };
 452
 453 const VMStateDescription vmstate_ppc_cpu = {
 454     .name = "cpu",
 455     .version_id = 5,
 456     .minimum_version_id = 5,
 457     .minimum_version_id_old = 4,
 458     .load_state_old = cpu_load_old,
 459     .pre_save = cpu_pre_save,
 460     .post_load = cpu_post_load,
 461     .fields = (VMStateField[]) {
 462         /* Verify we haven't changed the pvr */
 463         VMSTATE_UINTTL_EQUAL(env.spr[SPR_PVR], PowerPCCPU),
 464
 465         /* User mode architected state */
 466         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 467 #if !defined(TARGET_PPC64)
 468         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 469 #endif
 470         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 471         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 472
 473         /* SPRs */
 474         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 475         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 476
 477         /* Reservation */
 478         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 479
 480         /* Supervisor mode architected state */
 481         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 482
 483         /* Internal state */
 484         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 485         /* FIXME: access_type? */
 486
 487         /* Sanity checking */
 488         VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
 489         VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
 490         VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
 491         VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
 492         VMSTATE_END_OF_LIST()
 493     },
 494     .subsections = (VMStateSubsection []) {
 495         {
 496             .vmsd = &vmstate_fpu,
 497             .needed = fpu_needed,
 498         } , {
 499             .vmsd = &vmstate_altivec,
 500             .needed = altivec_needed,
 501         } , {
 502             .vmsd = &vmstate_vsx,
 503             .needed = vsx_needed,
 504         } , {
 505             .vmsd = &vmstate_sr,
 506             .needed = sr_needed,
 507         } , {
 508 #ifdef TARGET_PPC64
 509             .vmsd = &vmstate_slb,
 510             .needed = slb_needed,
 511         } , {
 512 #endif /* TARGET_PPC64 */
 513             .vmsd = &vmstate_tlb6xx,
 514             .needed = tlb6xx_needed,
 515         } , {
 516             .vmsd = &vmstate_tlbemb,
 517             .needed = tlbemb_needed,
 518         } , {
 519             .vmsd = &vmstate_tlbmas,
 520             .needed = tlbmas_needed,
 521         } , {
 522             /* empty */
 523         }
 524     }
 525 };