target-ppc/op_helper.c

   1 /*
   2  *  PPC emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <math.h>
  21 #include "exec.h"
  22
  23 #define MEMSUFFIX _raw
  24 #include "op_helper_mem.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #define MEMSUFFIX _user
  27 #include "op_helper_mem.h"
  28 #define MEMSUFFIX _kernel
  29 #include "op_helper_mem.h"
  30 #endif
  31
  32 /*****************************************************************************/
  33 /* Exceptions processing helpers */
  34 void cpu_loop_exit(void)
  35 {
  36     longjmp(env->jmp_env, 1);
  37 }
  38
  39 void do_raise_exception_err (uint32_t exception, int error_code)
  40 {
  41 #if 0
  42     printf("Raise exception %3x code : %d\n", exception, error_code);
  43 #endif
  44     switch (exception) {
  45     case EXCP_EXTERNAL:
  46     case EXCP_DECR:
  47         printf("DECREMENTER & EXTERNAL exceptions should be hard interrupts !\n");
  48         if (msr_ee == 0)
  49             return;
  50         break;
  51     case EXCP_PROGRAM:
  52         if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
  53             return;
  54         break;
  55     default:
  56         break;
  57 }
  58     env->exception_index = exception;
  59     env->error_code = error_code;
  60         cpu_loop_exit();
  61     }
  62
  63 void do_raise_exception (uint32_t exception)
  64 {
  65     do_raise_exception_err(exception, 0);
  66 }
  67
  68 /*****************************************************************************/
  69 /* Helpers for "fat" micro operations */
  70 /* Special registers load and store */
  71 void do_load_cr (void)
  72 {
  73     T0 = (env->crf[0] << 28) |
  74         (env->crf[1] << 24) |
  75         (env->crf[2] << 20) |
  76         (env->crf[3] << 16) |
  77         (env->crf[4] << 12) |
  78         (env->crf[5] << 8) |
  79         (env->crf[6] << 4) |
  80         (env->crf[7] << 0);
  81 }
  82
  83 void do_store_cr (uint32_t mask)
  84 {
  85     int i, sh;
  86
  87     for (i = 0, sh = 7; i < 8; i++, sh --) {
  88         if (mask & (1 << sh))
  89             env->crf[i] = (T0 >> (sh * 4)) & 0xF;
  90     }
  91 }
  92
  93 void do_load_xer (void)
  94 {
  95     T0 = (xer_so << XER_SO) |
  96         (xer_ov << XER_OV) |
  97         (xer_ca << XER_CA) |
  98         (xer_bc << XER_BC);
  99 }
 100
 101 void do_store_xer (void)
 102 {
 103     xer_so = (T0 >> XER_SO) & 0x01;
 104     xer_ov = (T0 >> XER_OV) & 0x01;
 105     xer_ca = (T0 >> XER_CA) & 0x01;
 106     xer_bc = (T0 >> XER_BC) & 0x1f;
 107 }
 108
 109 void do_load_msr (void)
 110 {
 111     T0 = (msr_pow << MSR_POW) |
 112         (msr_ile << MSR_ILE) |
 113         (msr_ee << MSR_EE) |
 114         (msr_pr << MSR_PR) |
 115         (msr_fp << MSR_FP) |
 116         (msr_me << MSR_ME) |
 117         (msr_fe0 << MSR_FE0) |
 118         (msr_se << MSR_SE) |
 119         (msr_be << MSR_BE) |
 120         (msr_fe1 << MSR_FE1) |
 121         (msr_ip << MSR_IP) |
 122         (msr_ir << MSR_IR) |
 123         (msr_dr << MSR_DR) |
 124         (msr_ri << MSR_RI) |
 125         (msr_le << MSR_LE);
 126 }
 127
 128 void do_store_msr (void)
 129 {
 130 #if 1 // TRY
 131     if (((T0 >> MSR_IR) & 0x01) != msr_ir ||
 132         ((T0 >> MSR_DR) & 0x01) != msr_dr ||
 133         ((T0 >> MSR_PR) & 0x01) != msr_pr)
 134     {
 135         do_tlbia();
 136     }
 137 #endif
 138     msr_pow = (T0 >> MSR_POW) & 0x03;
 139     msr_ile = (T0 >> MSR_ILE) & 0x01;
 140     msr_ee = (T0 >> MSR_EE) & 0x01;
 141     msr_pr = (T0 >> MSR_PR) & 0x01;
 142     msr_fp = (T0 >> MSR_FP) & 0x01;
 143     msr_me = (T0 >> MSR_ME) & 0x01;
 144     msr_fe0 = (T0 >> MSR_FE0) & 0x01;
 145     msr_se = (T0 >> MSR_SE) & 0x01;
 146     msr_be = (T0 >> MSR_BE) & 0x01;
 147     msr_fe1 = (T0 >> MSR_FE1) & 0x01;
 148     msr_ip = (T0 >> MSR_IP) & 0x01;
 149     msr_ir = (T0 >> MSR_IR) & 0x01;
 150     msr_dr = (T0 >> MSR_DR) & 0x01;
 151     msr_ri = (T0 >> MSR_RI) & 0x01;
 152     msr_le = (T0 >> MSR_LE) & 0x01;
 153 }
 154
 155 /* shift right arithmetic helper */
 156 void do_sraw (void)
 157 {
 158     int32_t ret;
 159
 160     xer_ca = 0;
 161     if (T1 & 0x20) {
 162         ret = (-1) * (T0 >> 31);
 163         if (ret < 0 && (T0 & ~0x80000000) != 0)
 164             xer_ca = 1;
 165 #if 1 // TRY
 166     } else if (T1 == 0) {
 167         ret = T0;
 168 #endif
 169     } else {
 170         ret = (int32_t)T0 >> (T1 & 0x1f);
 171         if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0)
 172             xer_ca = 1;
 173     }
 174     T0 = ret;
 175 }
 176
 177 /* Floating point operations helpers */
 178 void do_load_fpscr (void)
 179 {
 180     /* The 32 MSB of the target fpr are undefined.
 181      * They'll be zero...
 182      */
 183     union {
 184         double d;
 185         struct {
 186             uint32_t u[2];
 187         } s;
 188     } u;
 189     int i;
 190
 191     u.s.u[0] = 0;
 192     u.s.u[1] = 0;
 193     for (i = 0; i < 8; i++)
 194         u.s.u[1] |= env->fpscr[i] << (4 * i);
 195     FT0 = u.d;
 196 }
 197
 198 void do_store_fpscr (uint32_t mask)
 199 {
 200     /*
 201      * We use only the 32 LSB of the incoming fpr
 202      */
 203     union {
 204         double d;
 205         struct {
 206             uint32_t u[2];
 207         } s;
 208     } u;
 209     int i;
 210
 211     u.d = FT0;
 212     if (mask & 0x80)
 213         env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9);
 214     for (i = 1; i < 7; i++) {
 215         if (mask & (1 << (7 - i)))
 216             env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF;
 217     }
 218     /* TODO: update FEX & VX */
 219     /* Set rounding mode */
 220     switch (env->fpscr[0] & 0x3) {
 221     case 0:
 222         /* Best approximation (round to nearest) */
 223         fesetround(FE_TONEAREST);
 224         break;
 225     case 1:
 226         /* Smaller magnitude (round toward zero) */
 227         fesetround(FE_TOWARDZERO);
 228         break;
 229     case 2:
 230         /* Round toward +infinite */
 231         fesetround(FE_UPWARD);
 232         break;
 233     case 3:
 234         /* Round toward -infinite */
 235         fesetround(FE_DOWNWARD);
 236         break;
 237     }
 238 }
 239
 240 void do_fctiw (void)
 241 {
 242     union {
 243         double d;
 244         uint64_t i;
 245     } *p = (void *)&FT1;
 246
 247     if (FT0 > (double)0x7FFFFFFF)
 248         p->i = 0x7FFFFFFFULL << 32;
 249     else if (FT0 < -(double)0x80000000)
 250         p->i = 0x80000000ULL << 32;
 251     else
 252         p->i = 0;
 253     p->i |= (uint32_t)FT0;
 254     FT0 = p->d;
 255 }
 256
 257 void do_fctiwz (void)
 258 {
 259     union {
 260         double d;
 261         uint64_t i;
 262     } *p = (void *)&FT1;
 263     int cround = fegetround();
 264
 265     fesetround(FE_TOWARDZERO);
 266     if (FT0 > (double)0x7FFFFFFF)
 267         p->i = 0x7FFFFFFFULL << 32;
 268     else if (FT0 < -(double)0x80000000)
 269         p->i = 0x80000000ULL << 32;
 270     else
 271         p->i = 0;
 272     p->i |= (uint32_t)FT0;
 273     FT0 = p->d;
 274     fesetround(cround);
 275 }
 276
 277 void do_fnmadd (void)
 278 {
 279     FT0 = -((FT0 * FT1) + FT2);
 280 }
 281
 282 void do_fnmsub (void)
 283 {
 284     FT0 = -((FT0 * FT1) - FT2);
 285 }
 286
 287 void do_fnmadds (void)
 288 {
 289     FT0 = -((FTS0 * FTS1) + FTS2);
 290 }
 291
 292 void do_fnmsubs (void)
 293 {
 294     FT0 = -((FTS0 * FTS1) - FTS2);
 295 }
 296
 297 void do_fsqrt (void)
 298 {
 299     FT0 = sqrt(FT0);
 300 }
 301
 302 void do_fsqrts (void)
 303 {
 304     FT0 = (float)sqrt((float)FT0);
 305 }
 306
 307 void do_fres (void)
 308 {
 309     FT0 = 1.0 / FT0;
 310 }
 311
 312 void do_fsqrte (void)
 313 {
 314     FT0 = 1.0 / sqrt(FT0);
 315 }
 316
 317 void do_fsel (void)
 318 {
 319     if (FT0 >= 0)
 320         FT0 = FT2;
 321     else
 322         FT0 = FT1;
 323 }
 324
 325 void do_fcmpu (void)
 326 {
 327     if (isnan(FT0) || isnan(FT1)) {
 328         T0 = 0x01;
 329         env->fpscr[4] |= 0x1;
 330         env->fpscr[6] |= 0x1;
 331     } else if (FT0 < FT1) {
 332         T0 = 0x08;
 333     } else if (FT0 > FT1) {
 334         T0 = 0x04;
 335     } else {
 336         T0 = 0x02;
 337     }
 338     env->fpscr[3] = T0;
 339 }
 340
 341 void do_fcmpo (void)
 342 {
 343     env->fpscr[4] &= ~0x1;
 344     if (isnan(FT0) || isnan(FT1)) {
 345         T0 = 0x01;
 346         env->fpscr[4] |= 0x1;
 347         /* I don't know how to test "quiet" nan... */
 348         if (0 /* || ! quiet_nan(...) */) {
 349             env->fpscr[6] |= 0x1;
 350             if (!(env->fpscr[1] & 0x8))
 351                 env->fpscr[4] |= 0x8;
 352         } else {
 353             env->fpscr[4] |= 0x8;
 354         }
 355     } else if (FT0 < FT1) {
 356         T0 = 0x08;
 357     } else if (FT0 > FT1) {
 358         T0 = 0x04;
 359     } else {
 360         T0 = 0x02;
 361     }
 362     env->fpscr[3] = T0;
 363 }
 364
 365 void do_fabs (void)
 366 {
 367     FT0 = fabsl(FT0);
 368 }
 369
 370 void do_fnabs (void)
 371 {
 372     FT0 = -fabsl(FT0);
 373 }
 374
 375 /* Instruction cache invalidation helper */
 376 #define ICACHE_LINE_SIZE 32
 377
 378 void do_check_reservation (void)
 379 {
 380     if ((env->reserve & ~(ICACHE_LINE_SIZE - 1)) == T0)
 381         env->reserve = -1;
 382 }
 383
 384 void do_icbi (void)
 385 {
 386     /* Invalidate one cache line */
 387     T0 &= ~(ICACHE_LINE_SIZE - 1);
 388     tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE);
 389 }
 390
 391 /* TLB invalidation helpers */
 392 void do_tlbia (void)
 393 {
 394     tlb_flush(env, 1);
 395 }
 396
 397 void do_tlbie (void)
 398 {
 399     tlb_flush_page(env, T0);
 400 }
 401
 402 void do_store_sr (uint32_t srnum)
 403 {
 404 #if defined (DEBUG_OP)
 405     dump_store_sr(srnum);
 406 #endif
 407 #if 0 // TRY
 408     {
 409         uint32_t base, page;
 410
 411         base = srnum << 28;
 412         for (page = base; page != base + 0x100000000; page += 0x1000)
 413             tlb_flush_page(env, page);
 414     }
 415 #else
 416     tlb_flush(env, 1);
 417 #endif
 418     env->sr[srnum] = T0;
 419 }
 420
 421 /* For BATs, we may not invalidate any TLBs if the change is only on
 422  * protection bits for user mode.
 423  */
 424 void do_store_ibat (int ul, int nr)
 425 {
 426 #if defined (DEBUG_OP)
 427     dump_store_ibat(ul, nr);
 428 #endif
 429 #if 0 // TRY
 430     {
 431         uint32_t base, length, page;
 432
 433         base = env->IBAT[0][nr];
 434         length = (((base >> 2) & 0x000007FF) + 1) << 17;
 435         base &= 0xFFFC0000;
 436         for (page = base; page != base + length; page += 0x1000)
 437             tlb_flush_page(env, page);
 438     }
 439 #else
 440     tlb_flush(env, 1);
 441 #endif
 442     env->IBAT[ul][nr] = T0;
 443 }
 444
 445 void do_store_dbat (int ul, int nr)
 446 {
 447 #if defined (DEBUG_OP)
 448     dump_store_dbat(ul, nr);
 449 #endif
 450 #if 0 // TRY
 451     {
 452         uint32_t base, length, page;
 453         base = env->DBAT[0][nr];
 454         length = (((base >> 2) & 0x000007FF) + 1) << 17;
 455         base &= 0xFFFC0000;
 456         for (page = base; page != base + length; page += 0x1000)
 457             tlb_flush_page(env, page);
 458     }
 459 #else
 460     tlb_flush(env, 1);
 461 #endif
 462     env->DBAT[ul][nr] = T0;
 463 }
 464
 465 /*****************************************************************************/
 466 /* Special helpers for debug */
 467 void dump_state (void)
 468 {
 469     //    cpu_ppc_dump_state(env, stdout, 0);
 470 }
 471
 472 void dump_rfi (void)
 473 {
 474 #if 0
 475     printf("Return from interrupt => 0x%08x\n", env->nip);
 476     //    cpu_ppc_dump_state(env, stdout, 0);
 477 #endif
 478 }
 479
 480 void dump_store_sr (int srnum)
 481 {
 482 #if 0
 483     printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
 484 #endif
 485 }
 486
 487 static void _dump_store_bat (char ID, int ul, int nr)
 488 {
 489     printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
 490            ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip);
 491 }
 492
 493 void dump_store_ibat (int ul, int nr)
 494 {
 495     _dump_store_bat('I', ul, nr);
 496 }
 497
 498 void dump_store_dbat (int ul, int nr)
 499 {
 500     _dump_store_bat('D', ul, nr);
 501 }
 502
 503 void dump_store_tb (int ul)
 504 {
 505     printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0);
 506 }
 507
 508 void dump_update_tb(uint32_t param)
 509 {
 510 #if 0
 511     printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
 512 #endif
 513 }
 514