target-ppc/op_helper.c

   1 /*
   2  *  PowerPC emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "exec.h"
  21
  22 #include "op_helper.h"
  23
  24 #define MEMSUFFIX _raw
  25 #include "op_helper.h"
  26 #include "op_helper_mem.h"
  27 #if !defined(CONFIG_USER_ONLY)
  28 #define MEMSUFFIX _user
  29 #include "op_helper.h"
  30 #include "op_helper_mem.h"
  31 #define MEMSUFFIX _kernel
  32 #include "op_helper.h"
  33 #include "op_helper_mem.h"
  34 #endif
  35
  36 //#define DEBUG_OP
  37 //#define DEBUG_EXCEPTIONS
  38 //#define DEBUG_SOFTWARE_TLB
  39 //#define FLUSH_ALL_TLBS
  40
  41 /*****************************************************************************/
  42 /* Exceptions processing helpers */
  43 void cpu_loop_exit (void)
  44 {
  45     longjmp(env->jmp_env, 1);
  46 }
  47
  48 void do_raise_exception_err (uint32_t exception, int error_code)
  49 {
  50 #if 0
  51     printf("Raise exception %3x code : %d\n", exception, error_code);
  52 #endif
  53     switch (exception) {
  54     case EXCP_PROGRAM:
  55         if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
  56             return;
  57         break;
  58     default:
  59         break;
  60     }
  61     env->exception_index = exception;
  62     env->error_code = error_code;
  63     cpu_loop_exit();
  64 }
  65
  66 void do_raise_exception (uint32_t exception)
  67 {
  68     do_raise_exception_err(exception, 0);
  69 }
  70
  71 void cpu_dump_EA (target_ulong EA);
  72 void do_print_mem_EA (target_ulong EA)
  73 {
  74     cpu_dump_EA(EA);
  75 }
  76
  77 /*****************************************************************************/
  78 /* Registers load and stores */
  79 void do_load_cr (void)
  80 {
  81     T0 = (env->crf[0] << 28) |
  82         (env->crf[1] << 24) |
  83         (env->crf[2] << 20) |
  84         (env->crf[3] << 16) |
  85         (env->crf[4] << 12) |
  86         (env->crf[5] << 8) |
  87         (env->crf[6] << 4) |
  88         (env->crf[7] << 0);
  89 }
  90
  91 void do_store_cr (uint32_t mask)
  92 {
  93     int i, sh;
  94
  95     for (i = 0, sh = 7; i < 8; i++, sh --) {
  96         if (mask & (1 << sh))
  97             env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
  98     }
  99 }
 100
 101 void do_load_xer (void)
 102 {
 103     T0 = (xer_so << XER_SO) |
 104         (xer_ov << XER_OV) |
 105         (xer_ca << XER_CA) |
 106         (xer_bc << XER_BC) |
 107         (xer_cmp << XER_CMP);
 108 }
 109
 110 void do_store_xer (void)
 111 {
 112     xer_so = (T0 >> XER_SO) & 0x01;
 113     xer_ov = (T0 >> XER_OV) & 0x01;
 114     xer_ca = (T0 >> XER_CA) & 0x01;
 115     xer_cmp = (T0 >> XER_CMP) & 0xFF;
 116     xer_bc = (T0 >> XER_BC) & 0x7F;
 117 }
 118
 119 void do_load_fpscr (void)
 120 {
 121     /* The 32 MSB of the target fpr are undefined.
 122      * They'll be zero...
 123      */
 124     union {
 125         float64 d;
 126         struct {
 127             uint32_t u[2];
 128         } s;
 129     } u;
 130     int i;
 131
 132 #if defined(WORDS_BIGENDIAN)
 133 #define WORD0 0
 134 #define WORD1 1
 135 #else
 136 #define WORD0 1
 137 #define WORD1 0
 138 #endif
 139     u.s.u[WORD0] = 0;
 140     u.s.u[WORD1] = 0;
 141     for (i = 0; i < 8; i++)
 142         u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
 143     FT0 = u.d;
 144 }
 145
 146 void do_store_fpscr (uint32_t mask)
 147 {
 148     /*
 149      * We use only the 32 LSB of the incoming fpr
 150      */
 151     union {
 152         double d;
 153         struct {
 154             uint32_t u[2];
 155         } s;
 156     } u;
 157     int i, rnd_type;
 158
 159     u.d = FT0;
 160     if (mask & 0x80)
 161         env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
 162     for (i = 1; i < 7; i++) {
 163         if (mask & (1 << (7 - i)))
 164             env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
 165     }
 166     /* TODO: update FEX & VX */
 167     /* Set rounding mode */
 168     switch (env->fpscr[0] & 0x3) {
 169     case 0:
 170         /* Best approximation (round to nearest) */
 171         rnd_type = float_round_nearest_even;
 172         break;
 173     case 1:
 174         /* Smaller magnitude (round toward zero) */
 175         rnd_type = float_round_to_zero;
 176         break;
 177     case 2:
 178         /* Round toward +infinite */
 179         rnd_type = float_round_up;
 180         break;
 181     default:
 182     case 3:
 183         /* Round toward -infinite */
 184         rnd_type = float_round_down;
 185         break;
 186     }
 187     set_float_rounding_mode(rnd_type, &env->fp_status);
 188 }
 189
 190 target_ulong ppc_load_dump_spr (int sprn)
 191 {
 192     if (loglevel) {
 193         fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
 194                 sprn, sprn, env->spr[sprn]);
 195     }
 196
 197     return env->spr[sprn];
 198 }
 199
 200 void ppc_store_dump_spr (int sprn, target_ulong val)
 201 {
 202     if (loglevel) {
 203         fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
 204                 sprn, sprn, env->spr[sprn], val);
 205     }
 206     env->spr[sprn] = val;
 207 }
 208
 209 /*****************************************************************************/
 210 /* Fixed point operations helpers */
 211 #if defined(TARGET_PPC64)
 212 static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
 213 {
 214     *plow += a;
 215     /* carry test */
 216     if (*plow < a)
 217         (*phigh)++;
 218     *phigh += b;
 219 }
 220
 221 static void neg128 (uint64_t *plow, uint64_t *phigh)
 222 {
 223     *plow = ~ *plow;
 224     *phigh = ~ *phigh;
 225     add128(plow, phigh, 1, 0);
 226 }
 227
 228 static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
 229 {
 230     uint32_t a0, a1, b0, b1;
 231     uint64_t v;
 232
 233     a0 = a;
 234     a1 = a >> 32;
 235
 236     b0 = b;
 237     b1 = b >> 32;
 238
 239     v = (uint64_t)a0 * (uint64_t)b0;
 240     *plow = v;
 241     *phigh = 0;
 242
 243     v = (uint64_t)a0 * (uint64_t)b1;
 244     add128(plow, phigh, v << 32, v >> 32);
 245
 246     v = (uint64_t)a1 * (uint64_t)b0;
 247     add128(plow, phigh, v << 32, v >> 32);
 248
 249     v = (uint64_t)a1 * (uint64_t)b1;
 250     *phigh += v;
 251 #if defined(DEBUG_MULDIV)
 252     printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
 253            a, b, *phigh, *plow);
 254 #endif
 255 }
 256
 257 void do_mul64 (uint64_t *plow, uint64_t *phigh)
 258 {
 259     mul64(plow, phigh, T0, T1);
 260 }
 261
 262 static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
 263 {
 264     int sa, sb;
 265     sa = (a < 0);
 266     if (sa)
 267         a = -a;
 268     sb = (b < 0);
 269     if (sb)
 270         b = -b;
 271     mul64(plow, phigh, a, b);
 272     if (sa ^ sb) {
 273         neg128(plow, phigh);
 274     }
 275 }
 276
 277 void do_imul64 (uint64_t *plow, uint64_t *phigh)
 278 {
 279     imul64(plow, phigh, T0, T1);
 280 }
 281 #endif
 282
 283 void do_adde (void)
 284 {
 285     T2 = T0;
 286     T0 += T1 + xer_ca;
 287     if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
 288                  (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
 289         xer_ca = 0;
 290     } else {
 291         xer_ca = 1;
 292     }
 293 }
 294
 295 #if defined(TARGET_PPC64)
 296 void do_adde_64 (void)
 297 {
 298     T2 = T0;
 299     T0 += T1 + xer_ca;
 300     if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
 301                  (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
 302         xer_ca = 0;
 303     } else {
 304         xer_ca = 1;
 305     }
 306 }
 307 #endif
 308
 309 void do_addmeo (void)
 310 {
 311     T1 = T0;
 312     T0 += xer_ca + (-1);
 313     if (likely(!((uint32_t)T1 &
 314                  ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
 315         xer_ov = 0;
 316     } else {
 317         xer_so = 1;
 318         xer_ov = 1;
 319     }
 320     if (likely(T1 != 0))
 321         xer_ca = 1;
 322 }
 323
 324 #if defined(TARGET_PPC64)
 325 void do_addmeo_64 (void)
 326 {
 327     T1 = T0;
 328     T0 += xer_ca + (-1);
 329     if (likely(!((uint64_t)T1 &
 330                  ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
 331         xer_ov = 0;
 332     } else {
 333         xer_so = 1;
 334         xer_ov = 1;
 335     }
 336     if (likely(T1 != 0))
 337         xer_ca = 1;
 338 }
 339 #endif
 340
 341 void do_divwo (void)
 342 {
 343     if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
 344                  (int32_t)T1 == 0))) {
 345         xer_ov = 0;
 346         T0 = (int32_t)T0 / (int32_t)T1;
 347     } else {
 348         xer_so = 1;
 349         xer_ov = 1;
 350         T0 = (-1) * ((uint32_t)T0 >> 31);
 351     }
 352 }
 353
 354 #if defined(TARGET_PPC64)
 355 void do_divdo (void)
 356 {
 357     if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
 358                  (int64_t)T1 == 0))) {
 359         xer_ov = 0;
 360         T0 = (int64_t)T0 / (int64_t)T1;
 361     } else {
 362         xer_so = 1;
 363         xer_ov = 1;
 364         T0 = (-1ULL) * ((uint64_t)T0 >> 63);
 365     }
 366 }
 367 #endif
 368
 369 void do_divwuo (void)
 370 {
 371     if (likely((uint32_t)T1 != 0)) {
 372         xer_ov = 0;
 373         T0 = (uint32_t)T0 / (uint32_t)T1;
 374     } else {
 375         xer_so = 1;
 376         xer_ov = 1;
 377         T0 = 0;
 378     }
 379 }
 380
 381 #if defined(TARGET_PPC64)
 382 void do_divduo (void)
 383 {
 384     if (likely((uint64_t)T1 != 0)) {
 385         xer_ov = 0;
 386         T0 = (uint64_t)T0 / (uint64_t)T1;
 387     } else {
 388         xer_so = 1;
 389         xer_ov = 1;
 390         T0 = 0;
 391     }
 392 }
 393 #endif
 394
 395 void do_mullwo (void)
 396 {
 397     int64_t res = (int64_t)T0 * (int64_t)T1;
 398
 399     if (likely((int32_t)res == res)) {
 400         xer_ov = 0;
 401     } else {
 402         xer_ov = 1;
 403         xer_so = 1;
 404     }
 405     T0 = (int32_t)res;
 406 }
 407
 408 #if defined(TARGET_PPC64)
 409 void do_mulldo (void)
 410 {
 411     int64_t th;
 412     uint64_t tl;
 413
 414     do_imul64(&tl, &th);
 415     if (likely(th == 0)) {
 416         xer_ov = 0;
 417     } else {
 418         xer_ov = 1;
 419         xer_so = 1;
 420     }
 421     T0 = (int64_t)tl;
 422 }
 423 #endif
 424
 425 void do_nego (void)
 426 {
 427     if (likely((int32_t)T0 != INT32_MIN)) {
 428         xer_ov = 0;
 429         T0 = -(int32_t)T0;
 430     } else {
 431         xer_ov = 1;
 432         xer_so = 1;
 433     }
 434 }
 435
 436 #if defined(TARGET_PPC64)
 437 void do_nego_64 (void)
 438 {
 439     if (likely((int64_t)T0 != INT64_MIN)) {
 440         xer_ov = 0;
 441         T0 = -(int64_t)T0;
 442     } else {
 443         xer_ov = 1;
 444         xer_so = 1;
 445     }
 446 }
 447 #endif
 448
 449 void do_subfe (void)
 450 {
 451     T0 = T1 + ~T0 + xer_ca;
 452     if (likely((uint32_t)T0 >= (uint32_t)T1 &&
 453                (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
 454         xer_ca = 0;
 455     } else {
 456         xer_ca = 1;
 457     }
 458 }
 459
 460 #if defined(TARGET_PPC64)
 461 void do_subfe_64 (void)
 462 {
 463     T0 = T1 + ~T0 + xer_ca;
 464     if (likely((uint64_t)T0 >= (uint64_t)T1 &&
 465                (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
 466         xer_ca = 0;
 467     } else {
 468         xer_ca = 1;
 469     }
 470 }
 471 #endif
 472
 473 void do_subfmeo (void)
 474 {
 475     T1 = T0;
 476     T0 = ~T0 + xer_ca - 1;
 477     if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
 478                  (1UL << 31)))) {
 479         xer_ov = 0;
 480     } else {
 481         xer_so = 1;
 482         xer_ov = 1;
 483     }
 484     if (likely((uint32_t)T1 != UINT32_MAX))
 485         xer_ca = 1;
 486 }
 487
 488 #if defined(TARGET_PPC64)
 489 void do_subfmeo_64 (void)
 490 {
 491     T1 = T0;
 492     T0 = ~T0 + xer_ca - 1;
 493     if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
 494                  (1ULL << 63)))) {
 495         xer_ov = 0;
 496     } else {
 497         xer_so = 1;
 498         xer_ov = 1;
 499     }
 500     if (likely((uint64_t)T1 != UINT64_MAX))
 501         xer_ca = 1;
 502 }
 503 #endif
 504
 505 void do_subfzeo (void)
 506 {
 507     T1 = T0;
 508     T0 = ~T0 + xer_ca;
 509     if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
 510                  ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
 511         xer_ov = 0;
 512     } else {
 513         xer_ov = 1;
 514         xer_so = 1;
 515     }
 516     if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
 517         xer_ca = 0;
 518     } else {
 519         xer_ca = 1;
 520     }
 521 }
 522
 523 #if defined(TARGET_PPC64)
 524 void do_subfzeo_64 (void)
 525 {
 526     T1 = T0;
 527     T0 = ~T0 + xer_ca;
 528     if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
 529                  ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
 530         xer_ov = 0;
 531     } else {
 532         xer_ov = 1;
 533         xer_so = 1;
 534     }
 535     if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
 536         xer_ca = 0;
 537     } else {
 538         xer_ca = 1;
 539     }
 540 }
 541 #endif
 542
 543 /* shift right arithmetic helper */
 544 void do_sraw (void)
 545 {
 546     int32_t ret;
 547
 548     if (likely(!(T1 & 0x20UL))) {
 549         if (likely((uint32_t)T1 != 0)) {
 550             ret = (int32_t)T0 >> (T1 & 0x1fUL);
 551             if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
 552                 xer_ca = 0;
 553             } else {
 554                 xer_ca = 1;
 555             }
 556         } else {
 557             ret = T0;
 558             xer_ca = 0;
 559         }
 560     } else {
 561         ret = (-1) * ((uint32_t)T0 >> 31);
 562         if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
 563             xer_ca = 0;
 564         } else {
 565             xer_ca = 1;
 566         }
 567     }
 568     T0 = ret;
 569 }
 570
 571 #if defined(TARGET_PPC64)
 572 void do_srad (void)
 573 {
 574     int64_t ret;
 575
 576     if (likely(!(T1 & 0x40UL))) {
 577         if (likely((uint64_t)T1 != 0)) {
 578             ret = (int64_t)T0 >> (T1 & 0x3FUL);
 579             if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
 580                 xer_ca = 0;
 581             } else {
 582                 xer_ca = 1;
 583             }
 584         } else {
 585             ret = T0;
 586             xer_ca = 0;
 587         }
 588     } else {
 589         ret = (-1) * ((uint64_t)T0 >> 63);
 590         if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
 591             xer_ca = 0;
 592         } else {
 593             xer_ca = 1;
 594         }
 595     }
 596     T0 = ret;
 597 }
 598 #endif
 599
 600 static inline int popcnt (uint32_t val)
 601 {
 602     int i;
 603
 604     for (i = 0; val != 0;)
 605         val = val ^ (val - 1);
 606
 607     return i;
 608 }
 609
 610 void do_popcntb (void)
 611 {
 612     uint32_t ret;
 613     int i;
 614
 615     ret = 0;
 616     for (i = 0; i < 32; i += 8)
 617         ret |= popcnt((T0 >> i) & 0xFF) << i;
 618     T0 = ret;
 619 }
 620
 621 #if defined(TARGET_PPC64)
 622 void do_popcntb_64 (void)
 623 {
 624     uint64_t ret;
 625     int i;
 626
 627     ret = 0;
 628     for (i = 0; i < 64; i += 8)
 629         ret |= popcnt((T0 >> i) & 0xFF) << i;
 630     T0 = ret;
 631 }
 632 #endif
 633
 634 /*****************************************************************************/
 635 /* Floating point operations helpers */
 636 void do_fctiw (void)
 637 {
 638     union {
 639         double d;
 640         uint64_t i;
 641     } p;
 642
 643     p.i = float64_to_int32(FT0, &env->fp_status);
 644 #if USE_PRECISE_EMULATION
 645     /* XXX: higher bits are not supposed to be significant.
 646      *     to make tests easier, return the same as a real PowerPC 750 (aka G3)
 647      */
 648     p.i |= 0xFFF80000ULL << 32;
 649 #endif
 650     FT0 = p.d;
 651 }
 652
 653 void do_fctiwz (void)
 654 {
 655     union {
 656         double d;
 657         uint64_t i;
 658     } p;
 659
 660     p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
 661 #if USE_PRECISE_EMULATION
 662     /* XXX: higher bits are not supposed to be significant.
 663      *     to make tests easier, return the same as a real PowerPC 750 (aka G3)
 664      */
 665     p.i |= 0xFFF80000ULL << 32;
 666 #endif
 667     FT0 = p.d;
 668 }
 669
 670 #if defined(TARGET_PPC64)
 671 void do_fcfid (void)
 672 {
 673     union {
 674         double d;
 675         uint64_t i;
 676     } p;
 677
 678     p.d = FT0;
 679     FT0 = int64_to_float64(p.i, &env->fp_status);
 680 }
 681
 682 void do_fctid (void)
 683 {
 684     union {
 685         double d;
 686         uint64_t i;
 687     } p;
 688
 689     p.i = float64_to_int64(FT0, &env->fp_status);
 690     FT0 = p.d;
 691 }
 692
 693 void do_fctidz (void)
 694 {
 695     union {
 696         double d;
 697         uint64_t i;
 698     } p;
 699
 700     p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
 701     FT0 = p.d;
 702 }
 703
 704 #endif
 705
 706 #if USE_PRECISE_EMULATION
 707 void do_fmadd (void)
 708 {
 709 #ifdef FLOAT128
 710     float128 ft0_128, ft1_128;
 711
 712     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 713     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 714     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 715     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 716     ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 717     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 718 #else
 719     /* This is OK on x86 hosts */
 720     FT0 = (FT0 * FT1) + FT2;
 721 #endif
 722 }
 723
 724 void do_fmsub (void)
 725 {
 726 #ifdef FLOAT128
 727     float128 ft0_128, ft1_128;
 728
 729     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 730     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 731     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 732     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 733     ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 734     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 735 #else
 736     /* This is OK on x86 hosts */
 737     FT0 = (FT0 * FT1) - FT2;
 738 #endif
 739 }
 740 #endif /* USE_PRECISE_EMULATION */
 741
 742 void do_fnmadd (void)
 743 {
 744 #if USE_PRECISE_EMULATION
 745 #ifdef FLOAT128
 746     float128 ft0_128, ft1_128;
 747
 748     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 749     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 750     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 751     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 752     ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 753     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 754 #else
 755     /* This is OK on x86 hosts */
 756     FT0 = (FT0 * FT1) + FT2;
 757 #endif
 758 #else
 759     FT0 = float64_mul(FT0, FT1, &env->fp_status);
 760     FT0 = float64_add(FT0, FT2, &env->fp_status);
 761 #endif
 762     if (likely(!isnan(FT0)))
 763         FT0 = float64_chs(FT0);
 764 }
 765
 766 void do_fnmsub (void)
 767 {
 768 #if USE_PRECISE_EMULATION
 769 #ifdef FLOAT128
 770     float128 ft0_128, ft1_128;
 771
 772     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 773     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 774     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 775     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 776     ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 777     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 778 #else
 779     /* This is OK on x86 hosts */
 780     FT0 = (FT0 * FT1) - FT2;
 781 #endif
 782 #else
 783     FT0 = float64_mul(FT0, FT1, &env->fp_status);
 784     FT0 = float64_sub(FT0, FT2, &env->fp_status);
 785 #endif
 786     if (likely(!isnan(FT0)))
 787         FT0 = float64_chs(FT0);
 788 }
 789
 790 void do_fsqrt (void)
 791 {
 792     FT0 = float64_sqrt(FT0, &env->fp_status);
 793 }
 794
 795 void do_fres (void)
 796 {
 797     union {
 798         double d;
 799         uint64_t i;
 800     } p;
 801
 802     if (likely(isnormal(FT0))) {
 803 #if USE_PRECISE_EMULATION
 804         FT0 = float64_div(1.0, FT0, &env->fp_status);
 805         FT0 = float64_to_float32(FT0, &env->fp_status);
 806 #else
 807         FT0 = float32_div(1.0, FT0, &env->fp_status);
 808 #endif
 809     } else {
 810         p.d = FT0;
 811         if (p.i == 0x8000000000000000ULL) {
 812             p.i = 0xFFF0000000000000ULL;
 813         } else if (p.i == 0x0000000000000000ULL) {
 814             p.i = 0x7FF0000000000000ULL;
 815         } else if (isnan(FT0)) {
 816             p.i = 0x7FF8000000000000ULL;
 817         } else if (FT0 < 0.0) {
 818             p.i = 0x8000000000000000ULL;
 819         } else {
 820             p.i = 0x0000000000000000ULL;
 821         }
 822         FT0 = p.d;
 823     }
 824 }
 825
 826 void do_frsqrte (void)
 827 {
 828     union {
 829         double d;
 830         uint64_t i;
 831     } p;
 832
 833     if (likely(isnormal(FT0) && FT0 > 0.0)) {
 834         FT0 = float64_sqrt(FT0, &env->fp_status);
 835         FT0 = float32_div(1.0, FT0, &env->fp_status);
 836     } else {
 837         p.d = FT0;
 838         if (p.i == 0x8000000000000000ULL) {
 839             p.i = 0xFFF0000000000000ULL;
 840         } else if (p.i == 0x0000000000000000ULL) {
 841             p.i = 0x7FF0000000000000ULL;
 842         } else if (isnan(FT0)) {
 843             if (!(p.i & 0x0008000000000000ULL))
 844                 p.i |= 0x000FFFFFFFFFFFFFULL;
 845         } else if (FT0 < 0) {
 846             p.i = 0x7FF8000000000000ULL;
 847         } else {
 848             p.i = 0x0000000000000000ULL;
 849         }
 850         FT0 = p.d;
 851     }
 852 }
 853
 854 void do_fsel (void)
 855 {
 856     if (FT0 >= 0)
 857         FT0 = FT1;
 858     else
 859         FT0 = FT2;
 860 }
 861
 862 void do_fcmpu (void)
 863 {
 864     if (likely(!isnan(FT0) && !isnan(FT1))) {
 865         if (float64_lt(FT0, FT1, &env->fp_status)) {
 866             T0 = 0x08UL;
 867         } else if (!float64_le(FT0, FT1, &env->fp_status)) {
 868             T0 = 0x04UL;
 869         } else {
 870             T0 = 0x02UL;
 871         }
 872     } else {
 873         T0 = 0x01UL;
 874         env->fpscr[4] |= 0x1;
 875         env->fpscr[6] |= 0x1;
 876     }
 877     env->fpscr[3] = T0;
 878 }
 879
 880 void do_fcmpo (void)
 881 {
 882     env->fpscr[4] &= ~0x1;
 883     if (likely(!isnan(FT0) && !isnan(FT1))) {
 884         if (float64_lt(FT0, FT1, &env->fp_status)) {
 885             T0 = 0x08UL;
 886         } else if (!float64_le(FT0, FT1, &env->fp_status)) {
 887             T0 = 0x04UL;
 888         } else {
 889             T0 = 0x02UL;
 890         }
 891     } else {
 892         T0 = 0x01UL;
 893         env->fpscr[4] |= 0x1;
 894         if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
 895             /* Quiet NaN case */
 896             env->fpscr[6] |= 0x1;
 897             if (!(env->fpscr[1] & 0x8))
 898                 env->fpscr[4] |= 0x8;
 899         } else {
 900             env->fpscr[4] |= 0x8;
 901         }
 902     }
 903     env->fpscr[3] = T0;
 904 }
 905
 906 #if !defined (CONFIG_USER_ONLY)
 907 void do_rfi (void)
 908 {
 909 #if defined(TARGET_PPC64)
 910     if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
 911         env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
 912         do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 913     } else {
 914         env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
 915         ppc_store_msr_32(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 916     }
 917 #else
 918     env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
 919     do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 920 #endif
 921 #if defined (DEBUG_OP)
 922     dump_rfi();
 923 #endif
 924     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 925 }
 926
 927 #if defined(TARGET_PPC64)
 928 void do_rfid (void)
 929 {
 930     if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
 931         env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
 932         do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 933     } else {
 934         env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
 935         do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
 936     }
 937 #if defined (DEBUG_OP)
 938     dump_rfi();
 939 #endif
 940     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 941 }
 942 #endif
 943 #endif
 944
 945 void do_tw (int flags)
 946 {
 947     if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
 948                   ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
 949                   ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
 950                   ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
 951                   ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
 952         do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
 953     }
 954 }
 955
 956 #if defined(TARGET_PPC64)
 957 void do_td (int flags)
 958 {
 959     if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
 960                   ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
 961                   ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
 962                   ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
 963                   ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
 964         do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
 965 }
 966 #endif
 967
 968 /*****************************************************************************/
 969 /* PowerPC 601 specific instructions (POWER bridge) */
 970 void do_POWER_abso (void)
 971 {
 972     if ((uint32_t)T0 == INT32_MIN) {
 973         T0 = INT32_MAX;
 974         xer_ov = 1;
 975         xer_so = 1;
 976     } else {
 977         T0 = -T0;
 978         xer_ov = 0;
 979     }
 980 }
 981
 982 void do_POWER_clcs (void)
 983 {
 984     switch (T0) {
 985     case 0x0CUL:
 986         /* Instruction cache line size */
 987         T0 = ICACHE_LINE_SIZE;
 988         break;
 989     case 0x0DUL:
 990         /* Data cache line size */
 991         T0 = DCACHE_LINE_SIZE;
 992         break;
 993     case 0x0EUL:
 994         /* Minimum cache line size */
 995         T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
 996             ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
 997         break;
 998     case 0x0FUL:
 999         /* Maximum cache line size */
1000         T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
1001             ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
1002         break;
1003     default:
1004         /* Undefined */
1005         break;
1006     }
1007 }
1008
1009 void do_POWER_div (void)
1010 {
1011     uint64_t tmp;
1012
1013     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1014         T0 = (long)((-1) * (T0 >> 31));
1015         env->spr[SPR_MQ] = 0;
1016     } else {
1017         tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1018         env->spr[SPR_MQ] = tmp % T1;
1019         T0 = tmp / (int32_t)T1;
1020     }
1021 }
1022
1023 void do_POWER_divo (void)
1024 {
1025     int64_t tmp;
1026
1027     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1028         T0 = (long)((-1) * (T0 >> 31));
1029         env->spr[SPR_MQ] = 0;
1030         xer_ov = 1;
1031         xer_so = 1;
1032     } else {
1033         tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1034         env->spr[SPR_MQ] = tmp % T1;
1035         tmp /= (int32_t)T1;
1036         if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1037             xer_ov = 1;
1038             xer_so = 1;
1039         } else {
1040             xer_ov = 0;
1041         }
1042         T0 = tmp;
1043     }
1044 }
1045
1046 void do_POWER_divs (void)
1047 {
1048     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1049         T0 = (long)((-1) * (T0 >> 31));
1050         env->spr[SPR_MQ] = 0;
1051     } else {
1052         env->spr[SPR_MQ] = T0 % T1;
1053         T0 = (int32_t)T0 / (int32_t)T1;
1054     }
1055 }
1056
1057 void do_POWER_divso (void)
1058 {
1059     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1060         T0 = (long)((-1) * (T0 >> 31));
1061         env->spr[SPR_MQ] = 0;
1062         xer_ov = 1;
1063         xer_so = 1;
1064     } else {
1065         T0 = (int32_t)T0 / (int32_t)T1;
1066         env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1067         xer_ov = 0;
1068     }
1069 }
1070
1071 void do_POWER_dozo (void)
1072 {
1073     if ((int32_t)T1 > (int32_t)T0) {
1074         T2 = T0;
1075         T0 = T1 - T0;
1076         if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1077             ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1078             xer_so = 1;
1079             xer_ov = 1;
1080         } else {
1081             xer_ov = 0;
1082         }
1083     } else {
1084         T0 = 0;
1085         xer_ov = 0;
1086     }
1087 }
1088
1089 void do_POWER_maskg (void)
1090 {
1091     uint32_t ret;
1092
1093     if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1094         ret = -1;
1095     } else {
1096         ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
1097             (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
1098         if ((uint32_t)T0 > (uint32_t)T1)
1099             ret = ~ret;
1100     }
1101     T0 = ret;
1102 }
1103
1104 void do_POWER_mulo (void)
1105 {
1106     uint64_t tmp;
1107
1108     tmp = (uint64_t)T0 * (uint64_t)T1;
1109     env->spr[SPR_MQ] = tmp >> 32;
1110     T0 = tmp;
1111     if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1112         xer_ov = 1;
1113         xer_so = 1;
1114     } else {
1115         xer_ov = 0;
1116     }
1117 }
1118
1119 #if !defined (CONFIG_USER_ONLY)
1120 void do_POWER_rac (void)
1121 {
1122 #if 0
1123     mmu_ctx_t ctx;
1124
1125     /* We don't have to generate many instances of this instruction,
1126      * as rac is supervisor only.
1127      */
1128     if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
1129         T0 = ctx.raddr;
1130 #endif
1131 }
1132
1133 void do_POWER_rfsvc (void)
1134 {
1135     env->nip = env->lr & ~0x00000003UL;
1136     T0 = env->ctr & 0x0000FFFFUL;
1137     do_store_msr(env, T0);
1138 #if defined (DEBUG_OP)
1139     dump_rfi();
1140 #endif
1141     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1142 }
1143
1144 /* PowerPC 601 BAT management helper */
1145 void do_store_601_batu (int nr)
1146 {
1147     do_store_ibatu(env, nr, (uint32_t)T0);
1148     env->DBAT[0][nr] = env->IBAT[0][nr];
1149     env->DBAT[1][nr] = env->IBAT[1][nr];
1150 }
1151 #endif
1152
1153 /*****************************************************************************/
1154 /* 602 specific instructions */
1155 /* mfrom is the most crazy instruction ever seen, imho ! */
1156 /* Real implementation uses a ROM table. Do the same */
1157 #define USE_MFROM_ROM_TABLE
1158 void do_op_602_mfrom (void)
1159 {
1160     if (likely(T0 < 602)) {
1161 #if defined(USE_MFROM_ROM_TABLE)
1162 #include "mfrom_table.c"
1163         T0 = mfrom_ROM_table[T0];
1164 #else
1165         double d;
1166         /* Extremly decomposed:
1167          *                    -T0 / 256
1168          * T0 = 256 * log10(10          + 1.0) + 0.5
1169          */
1170         d = T0;
1171         d = float64_div(d, 256, &env->fp_status);
1172         d = float64_chs(d);
1173         d = exp10(d); // XXX: use float emulation function
1174         d = float64_add(d, 1.0, &env->fp_status);
1175         d = log10(d); // XXX: use float emulation function
1176         d = float64_mul(d, 256, &env->fp_status);
1177         d = float64_add(d, 0.5, &env->fp_status);
1178         T0 = float64_round_to_int(d, &env->fp_status);
1179 #endif
1180     } else {
1181         T0 = 0;
1182     }
1183 }
1184
1185 /*****************************************************************************/
1186 /* Embedded PowerPC specific helpers */
1187 void do_405_check_ov (void)
1188 {
1189     if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1190                !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1191         xer_ov = 0;
1192     } else {
1193         xer_ov = 1;
1194         xer_so = 1;
1195     }
1196 }
1197
1198 void do_405_check_sat (void)
1199 {
1200     if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1201                 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1202         /* Saturate result */
1203         if (T2 >> 31) {
1204             T0 = INT32_MIN;
1205         } else {
1206             T0 = INT32_MAX;
1207         }
1208     }
1209 }
1210
1211 #if !defined(CONFIG_USER_ONLY)
1212 void do_40x_rfci (void)
1213 {
1214     env->nip = env->spr[SPR_40x_SRR2];
1215     do_store_msr(env, env->spr[SPR_40x_SRR3] & ~0xFFFF0000);
1216 #if defined (DEBUG_OP)
1217     dump_rfi();
1218 #endif
1219     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1220 }
1221
1222 void do_rfci (void)
1223 {
1224 #if defined(TARGET_PPC64)
1225     if (env->spr[SPR_BOOKE_CSRR1] & (1 << MSR_CM)) {
1226         env->nip = (uint64_t)env->spr[SPR_BOOKE_CSRR0];
1227     } else
1228 #endif
1229     {
1230         env->nip = (uint32_t)env->spr[SPR_BOOKE_CSRR0];
1231     }
1232     do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_CSRR1] & ~0x3FFF0000);
1233 #if defined (DEBUG_OP)
1234     dump_rfi();
1235 #endif
1236     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1237 }
1238
1239 void do_rfdi (void)
1240 {
1241 #if defined(TARGET_PPC64)
1242     if (env->spr[SPR_BOOKE_DSRR1] & (1 << MSR_CM)) {
1243         env->nip = (uint64_t)env->spr[SPR_BOOKE_DSRR0];
1244     } else
1245 #endif
1246     {
1247         env->nip = (uint32_t)env->spr[SPR_BOOKE_DSRR0];
1248     }
1249     do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_DSRR1] & ~0x3FFF0000);
1250 #if defined (DEBUG_OP)
1251     dump_rfi();
1252 #endif
1253     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1254 }
1255
1256 void do_rfmci (void)
1257 {
1258 #if defined(TARGET_PPC64)
1259     if (env->spr[SPR_BOOKE_MCSRR1] & (1 << MSR_CM)) {
1260         env->nip = (uint64_t)env->spr[SPR_BOOKE_MCSRR0];
1261     } else
1262 #endif
1263     {
1264         env->nip = (uint32_t)env->spr[SPR_BOOKE_MCSRR0];
1265     }
1266     do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_MCSRR1] & ~0x3FFF0000);
1267 #if defined (DEBUG_OP)
1268     dump_rfi();
1269 #endif
1270     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1271 }
1272
1273 void do_load_dcr (void)
1274 {
1275     target_ulong val;
1276
1277     if (unlikely(env->dcr_env == NULL)) {
1278         if (loglevel) {
1279             fprintf(logfile, "No DCR environment\n");
1280         }
1281         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1282     } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1283         if (loglevel) {
1284             fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1285         }
1286         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1287     } else {
1288         T0 = val;
1289     }
1290 }
1291
1292 void do_store_dcr (void)
1293 {
1294     if (unlikely(env->dcr_env == NULL)) {
1295         if (loglevel) {
1296             fprintf(logfile, "No DCR environment\n");
1297         }
1298         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1299     } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1300         if (loglevel) {
1301             fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1302         }
1303         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1304     }
1305 }
1306
1307 void do_load_403_pb (int num)
1308 {
1309     T0 = env->pb[num];
1310 }
1311
1312 void do_store_403_pb (int num)
1313 {
1314     if (likely(env->pb[num] != T0)) {
1315         env->pb[num] = T0;
1316         /* Should be optimized */
1317         tlb_flush(env, 1);
1318     }
1319 }
1320 #endif
1321
1322 /* 440 specific */
1323 void do_440_dlmzb (void)
1324 {
1325     target_ulong mask;
1326     int i;
1327
1328     i = 1;
1329     for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1330         if ((T0 & mask) == 0)
1331             goto done;
1332         i++;
1333     }
1334     for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1335         if ((T1 & mask) == 0)
1336             break;
1337         i++;
1338     }
1339  done:
1340     T0 = i;
1341 }
1342
1343 #if defined(TARGET_PPCSPE)
1344 /* SPE extension helpers */
1345 /* Use a table to make this quicker */
1346 static uint8_t hbrev[16] = {
1347     0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1348     0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1349 };
1350
1351 static inline uint8_t byte_reverse (uint8_t val)
1352 {
1353     return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1354 }
1355
1356 static inline uint32_t word_reverse (uint32_t val)
1357 {
1358     return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1359         (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1360 }
1361
1362 #define MASKBITS 16 // Random value - to be fixed
1363 void do_brinc (void)
1364 {
1365     uint32_t a, b, d, mask;
1366
1367     mask = (uint32_t)(-1UL) >> MASKBITS;
1368     b = T1_64 & mask;
1369     a = T0_64 & mask;
1370     d = word_reverse(1 + word_reverse(a | ~mask));
1371     T0_64 = (T0_64 & ~mask) | (d & mask);
1372 }
1373
1374 #define DO_SPE_OP2(name)                                                      \
1375 void do_ev##name (void)                                                       \
1376 {                                                                             \
1377     T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) |         \
1378         (uint64_t)_do_e##name(T0_64, T1_64);                                  \
1379 }
1380
1381 #define DO_SPE_OP1(name)                                                      \
1382 void do_ev##name (void)                                                       \
1383 {                                                                             \
1384     T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) |                      \
1385         (uint64_t)_do_e##name(T0_64);                                         \
1386 }
1387
1388 /* Fixed-point vector arithmetic */
1389 static inline uint32_t _do_eabs (uint32_t val)
1390 {
1391     if (val != 0x80000000)
1392         val &= ~0x80000000;
1393
1394     return val;
1395 }
1396
1397 static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1398 {
1399     return op1 + op2;
1400 }
1401
1402 static inline int _do_ecntlsw (uint32_t val)
1403 {
1404     if (val & 0x80000000)
1405         return _do_cntlzw(~val);
1406     else
1407         return _do_cntlzw(val);
1408 }
1409
1410 static inline int _do_ecntlzw (uint32_t val)
1411 {
1412     return _do_cntlzw(val);
1413 }
1414
1415 static inline uint32_t _do_eneg (uint32_t val)
1416 {
1417     if (val != 0x80000000)
1418         val ^= 0x80000000;
1419
1420     return val;
1421 }
1422
1423 static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1424 {
1425     return rotl32(op1, op2);
1426 }
1427
1428 static inline uint32_t _do_erndw (uint32_t val)
1429 {
1430     return (val + 0x000080000000) & 0xFFFF0000;
1431 }
1432
1433 static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1434 {
1435     /* No error here: 6 bits are used */
1436     return op1 << (op2 & 0x3F);
1437 }
1438
1439 static inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1440 {
1441     /* No error here: 6 bits are used */
1442     return op1 >> (op2 & 0x3F);
1443 }
1444
1445 static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1446 {
1447     /* No error here: 6 bits are used */
1448     return op1 >> (op2 & 0x3F);
1449 }
1450
1451 static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1452 {
1453     return op2 - op1;
1454 }
1455
1456 /* evabs */
1457 DO_SPE_OP1(abs);
1458 /* evaddw */
1459 DO_SPE_OP2(addw);
1460 /* evcntlsw */
1461 DO_SPE_OP1(cntlsw);
1462 /* evcntlzw */
1463 DO_SPE_OP1(cntlzw);
1464 /* evneg */
1465 DO_SPE_OP1(neg);
1466 /* evrlw */
1467 DO_SPE_OP2(rlw);
1468 /* evrnd */
1469 DO_SPE_OP1(rndw);
1470 /* evslw */
1471 DO_SPE_OP2(slw);
1472 /* evsrws */
1473 DO_SPE_OP2(srws);
1474 /* evsrwu */
1475 DO_SPE_OP2(srwu);
1476 /* evsubfw */
1477 DO_SPE_OP2(subfw);
1478
1479 /* evsel is a little bit more complicated... */
1480 static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1481 {
1482     if (n)
1483         return op1;
1484     else
1485         return op2;
1486 }
1487
1488 void do_evsel (void)
1489 {
1490     T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1491         (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1492 }
1493
1494 /* Fixed-point vector comparisons */
1495 #define DO_SPE_CMP(name)                                                      \
1496 void do_ev##name (void)                                                       \
1497 {                                                                             \
1498     T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32,                   \
1499                                                T1_64 >> 32) << 32,            \
1500                          _do_e##name(T0_64, T1_64));                          \
1501 }
1502
1503 static inline uint32_t _do_evcmp_merge (int t0, int t1)
1504 {
1505     return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1506 }
1507 static inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
1508 {
1509     return op1 == op2 ? 1 : 0;
1510 }
1511
1512 static inline int _do_ecmpgts (int32_t op1, int32_t op2)
1513 {
1514     return op1 > op2 ? 1 : 0;
1515 }
1516
1517 static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
1518 {
1519     return op1 > op2 ? 1 : 0;
1520 }
1521
1522 static inline int _do_ecmplts (int32_t op1, int32_t op2)
1523 {
1524     return op1 < op2 ? 1 : 0;
1525 }
1526
1527 static inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
1528 {
1529     return op1 < op2 ? 1 : 0;
1530 }
1531
1532 /* evcmpeq */
1533 DO_SPE_CMP(cmpeq);
1534 /* evcmpgts */
1535 DO_SPE_CMP(cmpgts);
1536 /* evcmpgtu */
1537 DO_SPE_CMP(cmpgtu);
1538 /* evcmplts */
1539 DO_SPE_CMP(cmplts);
1540 /* evcmpltu */
1541 DO_SPE_CMP(cmpltu);
1542
1543 /* Single precision floating-point conversions from/to integer */
1544 static inline uint32_t _do_efscfsi (int32_t val)
1545 {
1546     union {
1547         uint32_t u;
1548         float32 f;
1549     } u;
1550
1551     u.f = int32_to_float32(val, &env->spe_status);
1552
1553     return u.u;
1554 }
1555
1556 static inline uint32_t _do_efscfui (uint32_t val)
1557 {
1558     union {
1559         uint32_t u;
1560         float32 f;
1561     } u;
1562
1563     u.f = uint32_to_float32(val, &env->spe_status);
1564
1565     return u.u;
1566 }
1567
1568 static inline int32_t _do_efsctsi (uint32_t val)
1569 {
1570     union {
1571         int32_t u;
1572         float32 f;
1573     } u;
1574
1575     u.u = val;
1576     /* NaN are not treated the same way IEEE 754 does */
1577     if (unlikely(isnan(u.f)))
1578         return 0;
1579
1580     return float32_to_int32(u.f, &env->spe_status);
1581 }
1582
1583 static inline uint32_t _do_efsctui (uint32_t val)
1584 {
1585     union {
1586         int32_t u;
1587         float32 f;
1588     } u;
1589
1590     u.u = val;
1591     /* NaN are not treated the same way IEEE 754 does */
1592     if (unlikely(isnan(u.f)))
1593         return 0;
1594
1595     return float32_to_uint32(u.f, &env->spe_status);
1596 }
1597
1598 static inline int32_t _do_efsctsiz (uint32_t val)
1599 {
1600     union {
1601         int32_t u;
1602         float32 f;
1603     } u;
1604
1605     u.u = val;
1606     /* NaN are not treated the same way IEEE 754 does */
1607     if (unlikely(isnan(u.f)))
1608         return 0;
1609
1610     return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1611 }
1612
1613 static inline uint32_t _do_efsctuiz (uint32_t val)
1614 {
1615     union {
1616         int32_t u;
1617         float32 f;
1618     } u;
1619
1620     u.u = val;
1621     /* NaN are not treated the same way IEEE 754 does */
1622     if (unlikely(isnan(u.f)))
1623         return 0;
1624
1625     return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1626 }
1627
1628 void do_efscfsi (void)
1629 {
1630     T0_64 = _do_efscfsi(T0_64);
1631 }
1632
1633 void do_efscfui (void)
1634 {
1635     T0_64 = _do_efscfui(T0_64);
1636 }
1637
1638 void do_efsctsi (void)
1639 {
1640     T0_64 = _do_efsctsi(T0_64);
1641 }
1642
1643 void do_efsctui (void)
1644 {
1645     T0_64 = _do_efsctui(T0_64);
1646 }
1647
1648 void do_efsctsiz (void)
1649 {
1650     T0_64 = _do_efsctsiz(T0_64);
1651 }
1652
1653 void do_efsctuiz (void)
1654 {
1655     T0_64 = _do_efsctuiz(T0_64);
1656 }
1657
1658 /* Single precision floating-point conversion to/from fractional */
1659 static inline uint32_t _do_efscfsf (uint32_t val)
1660 {
1661     union {
1662         uint32_t u;
1663         float32 f;
1664     } u;
1665     float32 tmp;
1666
1667     u.f = int32_to_float32(val, &env->spe_status);
1668     tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1669     u.f = float32_div(u.f, tmp, &env->spe_status);
1670
1671     return u.u;
1672 }
1673
1674 static inline uint32_t _do_efscfuf (uint32_t val)
1675 {
1676     union {
1677         uint32_t u;
1678         float32 f;
1679     } u;
1680     float32 tmp;
1681
1682     u.f = uint32_to_float32(val, &env->spe_status);
1683     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1684     u.f = float32_div(u.f, tmp, &env->spe_status);
1685
1686     return u.u;
1687 }
1688
1689 static inline int32_t _do_efsctsf (uint32_t val)
1690 {
1691     union {
1692         int32_t u;
1693         float32 f;
1694     } u;
1695     float32 tmp;
1696
1697     u.u = val;
1698     /* NaN are not treated the same way IEEE 754 does */
1699     if (unlikely(isnan(u.f)))
1700         return 0;
1701     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1702     u.f = float32_mul(u.f, tmp, &env->spe_status);
1703
1704     return float32_to_int32(u.f, &env->spe_status);
1705 }
1706
1707 static inline uint32_t _do_efsctuf (uint32_t val)
1708 {
1709     union {
1710         int32_t u;
1711         float32 f;
1712     } u;
1713     float32 tmp;
1714
1715     u.u = val;
1716     /* NaN are not treated the same way IEEE 754 does */
1717     if (unlikely(isnan(u.f)))
1718         return 0;
1719     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1720     u.f = float32_mul(u.f, tmp, &env->spe_status);
1721
1722     return float32_to_uint32(u.f, &env->spe_status);
1723 }
1724
1725 static inline int32_t _do_efsctsfz (uint32_t val)
1726 {
1727     union {
1728         int32_t u;
1729         float32 f;
1730     } u;
1731     float32 tmp;
1732
1733     u.u = val;
1734     /* NaN are not treated the same way IEEE 754 does */
1735     if (unlikely(isnan(u.f)))
1736         return 0;
1737     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1738     u.f = float32_mul(u.f, tmp, &env->spe_status);
1739
1740     return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1741 }
1742
1743 static inline uint32_t _do_efsctufz (uint32_t val)
1744 {
1745     union {
1746         int32_t u;
1747         float32 f;
1748     } u;
1749     float32 tmp;
1750
1751     u.u = val;
1752     /* NaN are not treated the same way IEEE 754 does */
1753     if (unlikely(isnan(u.f)))
1754         return 0;
1755     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1756     u.f = float32_mul(u.f, tmp, &env->spe_status);
1757
1758     return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1759 }
1760
1761 void do_efscfsf (void)
1762 {
1763     T0_64 = _do_efscfsf(T0_64);
1764 }
1765
1766 void do_efscfuf (void)
1767 {
1768     T0_64 = _do_efscfuf(T0_64);
1769 }
1770
1771 void do_efsctsf (void)
1772 {
1773     T0_64 = _do_efsctsf(T0_64);
1774 }
1775
1776 void do_efsctuf (void)
1777 {
1778     T0_64 = _do_efsctuf(T0_64);
1779 }
1780
1781 void do_efsctsfz (void)
1782 {
1783     T0_64 = _do_efsctsfz(T0_64);
1784 }
1785
1786 void do_efsctufz (void)
1787 {
1788     T0_64 = _do_efsctufz(T0_64);
1789 }
1790
1791 /* Double precision floating point helpers */
1792 static inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
1793 {
1794     /* XXX: TODO: test special values (NaN, infinites, ...) */
1795     return _do_efdtstlt(op1, op2);
1796 }
1797
1798 static inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
1799 {
1800     /* XXX: TODO: test special values (NaN, infinites, ...) */
1801     return _do_efdtstgt(op1, op2);
1802 }
1803
1804 static inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
1805 {
1806     /* XXX: TODO: test special values (NaN, infinites, ...) */
1807     return _do_efdtsteq(op1, op2);
1808 }
1809
1810 void do_efdcmplt (void)
1811 {
1812     T0 = _do_efdcmplt(T0_64, T1_64);
1813 }
1814
1815 void do_efdcmpgt (void)
1816 {
1817     T0 = _do_efdcmpgt(T0_64, T1_64);
1818 }
1819
1820 void do_efdcmpeq (void)
1821 {
1822     T0 = _do_efdcmpeq(T0_64, T1_64);
1823 }
1824
1825 /* Double precision floating-point conversion to/from integer */
1826 static inline uint64_t _do_efdcfsi (int64_t val)
1827 {
1828     union {
1829         uint64_t u;
1830         float64 f;
1831     } u;
1832
1833     u.f = int64_to_float64(val, &env->spe_status);
1834
1835     return u.u;
1836 }
1837
1838 static inline uint64_t _do_efdcfui (uint64_t val)
1839 {
1840     union {
1841         uint64_t u;
1842         float64 f;
1843     } u;
1844
1845     u.f = uint64_to_float64(val, &env->spe_status);
1846
1847     return u.u;
1848 }
1849
1850 static inline int64_t _do_efdctsi (uint64_t val)
1851 {
1852     union {
1853         int64_t u;
1854         float64 f;
1855     } u;
1856
1857     u.u = val;
1858     /* NaN are not treated the same way IEEE 754 does */
1859     if (unlikely(isnan(u.f)))
1860         return 0;
1861
1862     return float64_to_int64(u.f, &env->spe_status);
1863 }
1864
1865 static inline uint64_t _do_efdctui (uint64_t val)
1866 {
1867     union {
1868         int64_t u;
1869         float64 f;
1870     } u;
1871
1872     u.u = val;
1873     /* NaN are not treated the same way IEEE 754 does */
1874     if (unlikely(isnan(u.f)))
1875         return 0;
1876
1877     return float64_to_uint64(u.f, &env->spe_status);
1878 }
1879
1880 static inline int64_t _do_efdctsiz (uint64_t val)
1881 {
1882     union {
1883         int64_t u;
1884         float64 f;
1885     } u;
1886
1887     u.u = val;
1888     /* NaN are not treated the same way IEEE 754 does */
1889     if (unlikely(isnan(u.f)))
1890         return 0;
1891
1892     return float64_to_int64_round_to_zero(u.f, &env->spe_status);
1893 }
1894
1895 static inline uint64_t _do_efdctuiz (uint64_t val)
1896 {
1897     union {
1898         int64_t u;
1899         float64 f;
1900     } u;
1901
1902     u.u = val;
1903     /* NaN are not treated the same way IEEE 754 does */
1904     if (unlikely(isnan(u.f)))
1905         return 0;
1906
1907     return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
1908 }
1909
1910 void do_efdcfsi (void)
1911 {
1912     T0_64 = _do_efdcfsi(T0_64);
1913 }
1914
1915 void do_efdcfui (void)
1916 {
1917     T0_64 = _do_efdcfui(T0_64);
1918 }
1919
1920 void do_efdctsi (void)
1921 {
1922     T0_64 = _do_efdctsi(T0_64);
1923 }
1924
1925 void do_efdctui (void)
1926 {
1927     T0_64 = _do_efdctui(T0_64);
1928 }
1929
1930 void do_efdctsiz (void)
1931 {
1932     T0_64 = _do_efdctsiz(T0_64);
1933 }
1934
1935 void do_efdctuiz (void)
1936 {
1937     T0_64 = _do_efdctuiz(T0_64);
1938 }
1939
1940 /* Double precision floating-point conversion to/from fractional */
1941 static inline uint64_t _do_efdcfsf (int64_t val)
1942 {
1943     union {
1944         uint64_t u;
1945         float64 f;
1946     } u;
1947     float64 tmp;
1948
1949     u.f = int32_to_float64(val, &env->spe_status);
1950     tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1951     u.f = float64_div(u.f, tmp, &env->spe_status);
1952
1953     return u.u;
1954 }
1955
1956 static inline uint64_t _do_efdcfuf (uint64_t val)
1957 {
1958     union {
1959         uint64_t u;
1960         float64 f;
1961     } u;
1962     float64 tmp;
1963
1964     u.f = uint32_to_float64(val, &env->spe_status);
1965     tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1966     u.f = float64_div(u.f, tmp, &env->spe_status);
1967
1968     return u.u;
1969 }
1970
1971 static inline int64_t _do_efdctsf (uint64_t val)
1972 {
1973     union {
1974         int64_t u;
1975         float64 f;
1976     } u;
1977     float64 tmp;
1978
1979     u.u = val;
1980     /* NaN are not treated the same way IEEE 754 does */
1981     if (unlikely(isnan(u.f)))
1982         return 0;
1983     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1984     u.f = float64_mul(u.f, tmp, &env->spe_status);
1985
1986     return float64_to_int32(u.f, &env->spe_status);
1987 }
1988
1989 static inline uint64_t _do_efdctuf (uint64_t val)
1990 {
1991     union {
1992         int64_t u;
1993         float64 f;
1994     } u;
1995     float64 tmp;
1996
1997     u.u = val;
1998     /* NaN are not treated the same way IEEE 754 does */
1999     if (unlikely(isnan(u.f)))
2000         return 0;
2001     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2002     u.f = float64_mul(u.f, tmp, &env->spe_status);
2003
2004     return float64_to_uint32(u.f, &env->spe_status);
2005 }
2006
2007 static inline int64_t _do_efdctsfz (uint64_t val)
2008 {
2009     union {
2010         int64_t u;
2011         float64 f;
2012     } u;
2013     float64 tmp;
2014
2015     u.u = val;
2016     /* NaN are not treated the same way IEEE 754 does */
2017     if (unlikely(isnan(u.f)))
2018         return 0;
2019     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2020     u.f = float64_mul(u.f, tmp, &env->spe_status);
2021
2022     return float64_to_int32_round_to_zero(u.f, &env->spe_status);
2023 }
2024
2025 static inline uint64_t _do_efdctufz (uint64_t val)
2026 {
2027     union {
2028         int64_t u;
2029         float64 f;
2030     } u;
2031     float64 tmp;
2032
2033     u.u = val;
2034     /* NaN are not treated the same way IEEE 754 does */
2035     if (unlikely(isnan(u.f)))
2036         return 0;
2037     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2038     u.f = float64_mul(u.f, tmp, &env->spe_status);
2039
2040     return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
2041 }
2042
2043 void do_efdcfsf (void)
2044 {
2045     T0_64 = _do_efdcfsf(T0_64);
2046 }
2047
2048 void do_efdcfuf (void)
2049 {
2050     T0_64 = _do_efdcfuf(T0_64);
2051 }
2052
2053 void do_efdctsf (void)
2054 {
2055     T0_64 = _do_efdctsf(T0_64);
2056 }
2057
2058 void do_efdctuf (void)
2059 {
2060     T0_64 = _do_efdctuf(T0_64);
2061 }
2062
2063 void do_efdctsfz (void)
2064 {
2065     T0_64 = _do_efdctsfz(T0_64);
2066 }
2067
2068 void do_efdctufz (void)
2069 {
2070     T0_64 = _do_efdctufz(T0_64);
2071 }
2072
2073 /* Floating point conversion between single and double precision */
2074 static inline uint32_t _do_efscfd (uint64_t val)
2075 {
2076     union {
2077         uint64_t u;
2078         float64 f;
2079     } u1;
2080     union {
2081         uint32_t u;
2082         float32 f;
2083     } u2;
2084
2085     u1.u = val;
2086     u2.f = float64_to_float32(u1.f, &env->spe_status);
2087
2088     return u2.u;
2089 }
2090
2091 static inline uint64_t _do_efdcfs (uint32_t val)
2092 {
2093     union {
2094         uint64_t u;
2095         float64 f;
2096     } u2;
2097     union {
2098         uint32_t u;
2099         float32 f;
2100     } u1;
2101
2102     u1.u = val;
2103     u2.f = float32_to_float64(u1.f, &env->spe_status);
2104
2105     return u2.u;
2106 }
2107
2108 void do_efscfd (void)
2109 {
2110     T0_64 = _do_efscfd(T0_64);
2111 }
2112
2113 void do_efdcfs (void)
2114 {
2115     T0_64 = _do_efdcfs(T0_64);
2116 }
2117
2118 /* Single precision fixed-point vector arithmetic */
2119 /* evfsabs */
2120 DO_SPE_OP1(fsabs);
2121 /* evfsnabs */
2122 DO_SPE_OP1(fsnabs);
2123 /* evfsneg */
2124 DO_SPE_OP1(fsneg);
2125 /* evfsadd */
2126 DO_SPE_OP2(fsadd);
2127 /* evfssub */
2128 DO_SPE_OP2(fssub);
2129 /* evfsmul */
2130 DO_SPE_OP2(fsmul);
2131 /* evfsdiv */
2132 DO_SPE_OP2(fsdiv);
2133
2134 /* Single-precision floating-point comparisons */
2135 static inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2136 {
2137     /* XXX: TODO: test special values (NaN, infinites, ...) */
2138     return _do_efststlt(op1, op2);
2139 }
2140
2141 static inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2142 {
2143     /* XXX: TODO: test special values (NaN, infinites, ...) */
2144     return _do_efststgt(op1, op2);
2145 }
2146
2147 static inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2148 {
2149     /* XXX: TODO: test special values (NaN, infinites, ...) */
2150     return _do_efststeq(op1, op2);
2151 }
2152
2153 void do_efscmplt (void)
2154 {
2155     T0 = _do_efscmplt(T0_64, T1_64);
2156 }
2157
2158 void do_efscmpgt (void)
2159 {
2160     T0 = _do_efscmpgt(T0_64, T1_64);
2161 }
2162
2163 void do_efscmpeq (void)
2164 {
2165     T0 = _do_efscmpeq(T0_64, T1_64);
2166 }
2167
2168 /* Single-precision floating-point vector comparisons */
2169 /* evfscmplt */
2170 DO_SPE_CMP(fscmplt);
2171 /* evfscmpgt */
2172 DO_SPE_CMP(fscmpgt);
2173 /* evfscmpeq */
2174 DO_SPE_CMP(fscmpeq);
2175 /* evfststlt */
2176 DO_SPE_CMP(fststlt);
2177 /* evfststgt */
2178 DO_SPE_CMP(fststgt);
2179 /* evfststeq */
2180 DO_SPE_CMP(fststeq);
2181
2182 /* Single-precision floating-point vector conversions */
2183 /* evfscfsi */
2184 DO_SPE_OP1(fscfsi);
2185 /* evfscfui */
2186 DO_SPE_OP1(fscfui);
2187 /* evfscfuf */
2188 DO_SPE_OP1(fscfuf);
2189 /* evfscfsf */
2190 DO_SPE_OP1(fscfsf);
2191 /* evfsctsi */
2192 DO_SPE_OP1(fsctsi);
2193 /* evfsctui */
2194 DO_SPE_OP1(fsctui);
2195 /* evfsctsiz */
2196 DO_SPE_OP1(fsctsiz);
2197 /* evfsctuiz */
2198 DO_SPE_OP1(fsctuiz);
2199 /* evfsctsf */
2200 DO_SPE_OP1(fsctsf);
2201 /* evfsctuf */
2202 DO_SPE_OP1(fsctuf);
2203 #endif /* defined(TARGET_PPCSPE) */
2204
2205 /*****************************************************************************/
2206 /* Softmmu support */
2207 #if !defined (CONFIG_USER_ONLY)
2208
2209 #define MMUSUFFIX _mmu
2210 #define GETPC() (__builtin_return_address(0))
2211
2212 #define SHIFT 0
2213 #include "softmmu_template.h"
2214
2215 #define SHIFT 1
2216 #include "softmmu_template.h"
2217
2218 #define SHIFT 2
2219 #include "softmmu_template.h"
2220
2221 #define SHIFT 3
2222 #include "softmmu_template.h"
2223
2224 /* try to fill the TLB and return an exception if error. If retaddr is
2225    NULL, it means that the function was called in C code (i.e. not
2226    from generated code or from helper.c) */
2227 /* XXX: fix it to restore all registers */
2228 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
2229 {
2230     TranslationBlock *tb;
2231     CPUState *saved_env;
2232     target_phys_addr_t pc;
2233     int ret;
2234
2235     /* XXX: hack to restore env in all cases, even if not called from
2236        generated code */
2237     saved_env = env;
2238     env = cpu_single_env;
2239     ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
2240     if (unlikely(ret != 0)) {
2241         if (likely(retaddr)) {
2242             /* now we have a real cpu fault */
2243             pc = (target_phys_addr_t)retaddr;
2244             tb = tb_find_pc(pc);
2245             if (likely(tb)) {
2246                 /* the PC is inside the translated code. It means that we have
2247                    a virtual CPU fault */
2248                 cpu_restore_state(tb, env, pc, NULL);
2249             }
2250         }
2251         do_raise_exception_err(env->exception_index, env->error_code);
2252     }
2253     env = saved_env;
2254 }
2255
2256 /* TLB invalidation helpers */
2257 void do_tlbia (void)
2258 {
2259     ppc_tlb_invalidate_all(env);
2260 }
2261
2262 void do_tlbie (void)
2263 {
2264     T0 = (uint32_t)T0;
2265 #if !defined(FLUSH_ALL_TLBS)
2266     if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2267         ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2268         if (env->id_tlbs == 1)
2269             ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2270     } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2271         /* XXX: TODO */
2272 #if 0
2273         ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2274                                      env->spr[SPR_BOOKE_PID]);
2275 #endif
2276     } else {
2277         /* tlbie invalidate TLBs for all segments */
2278         T0 &= TARGET_PAGE_MASK;
2279         T0 &= ~((target_ulong)-1 << 28);
2280         /* XXX: this case should be optimized,
2281          * giving a mask to tlb_flush_page
2282          */
2283         tlb_flush_page(env, T0 | (0x0 << 28));
2284         tlb_flush_page(env, T0 | (0x1 << 28));
2285         tlb_flush_page(env, T0 | (0x2 << 28));
2286         tlb_flush_page(env, T0 | (0x3 << 28));
2287         tlb_flush_page(env, T0 | (0x4 << 28));
2288         tlb_flush_page(env, T0 | (0x5 << 28));
2289         tlb_flush_page(env, T0 | (0x6 << 28));
2290         tlb_flush_page(env, T0 | (0x7 << 28));
2291         tlb_flush_page(env, T0 | (0x8 << 28));
2292         tlb_flush_page(env, T0 | (0x9 << 28));
2293         tlb_flush_page(env, T0 | (0xA << 28));
2294         tlb_flush_page(env, T0 | (0xB << 28));
2295         tlb_flush_page(env, T0 | (0xC << 28));
2296         tlb_flush_page(env, T0 | (0xD << 28));
2297         tlb_flush_page(env, T0 | (0xE << 28));
2298         tlb_flush_page(env, T0 | (0xF << 28));
2299     }
2300 #else
2301     do_tlbia();
2302 #endif
2303 }
2304
2305 #if defined(TARGET_PPC64)
2306 void do_tlbie_64 (void)
2307 {
2308     T0 = (uint64_t)T0;
2309 #if !defined(FLUSH_ALL_TLBS)
2310     if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2311         ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2312         if (env->id_tlbs == 1)
2313             ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2314     } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2315         /* XXX: TODO */
2316 #if 0
2317         ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2318                                      env->spr[SPR_BOOKE_PID]);
2319 #endif
2320     } else {
2321         /* tlbie invalidate TLBs for all segments
2322          * As we have 2^36 segments, invalidate all qemu TLBs
2323          */
2324 #if 0
2325         T0 &= TARGET_PAGE_MASK;
2326         T0 &= ~((target_ulong)-1 << 28);
2327         /* XXX: this case should be optimized,
2328          * giving a mask to tlb_flush_page
2329          */
2330         tlb_flush_page(env, T0 | (0x0 << 28));
2331         tlb_flush_page(env, T0 | (0x1 << 28));
2332         tlb_flush_page(env, T0 | (0x2 << 28));
2333         tlb_flush_page(env, T0 | (0x3 << 28));
2334         tlb_flush_page(env, T0 | (0x4 << 28));
2335         tlb_flush_page(env, T0 | (0x5 << 28));
2336         tlb_flush_page(env, T0 | (0x6 << 28));
2337         tlb_flush_page(env, T0 | (0x7 << 28));
2338         tlb_flush_page(env, T0 | (0x8 << 28));
2339         tlb_flush_page(env, T0 | (0x9 << 28));
2340         tlb_flush_page(env, T0 | (0xA << 28));
2341         tlb_flush_page(env, T0 | (0xB << 28));
2342         tlb_flush_page(env, T0 | (0xC << 28));
2343         tlb_flush_page(env, T0 | (0xD << 28));
2344         tlb_flush_page(env, T0 | (0xE << 28));
2345         tlb_flush_page(env, T0 | (0xF << 28));
2346 #else
2347         tlb_flush(env, 1);
2348 #endif
2349     }
2350 #else
2351     do_tlbia();
2352 #endif
2353 }
2354 #endif
2355
2356 #if defined(TARGET_PPC64)
2357 void do_slbia (void)
2358 {
2359     /* XXX: TODO */
2360     tlb_flush(env, 1);
2361 }
2362
2363 void do_slbie (void)
2364 {
2365     /* XXX: TODO */
2366     tlb_flush(env, 1);
2367 }
2368 #endif
2369
2370 /* Software driven TLBs management */
2371 /* PowerPC 602/603 software TLB load instructions helpers */
2372 void do_load_6xx_tlb (int is_code)
2373 {
2374     target_ulong RPN, CMP, EPN;
2375     int way;
2376
2377     RPN = env->spr[SPR_RPA];
2378     if (is_code) {
2379         CMP = env->spr[SPR_ICMP];
2380         EPN = env->spr[SPR_IMISS];
2381     } else {
2382         CMP = env->spr[SPR_DCMP];
2383         EPN = env->spr[SPR_DMISS];
2384     }
2385     way = (env->spr[SPR_SRR1] >> 17) & 1;
2386 #if defined (DEBUG_SOFTWARE_TLB)
2387     if (loglevel != 0) {
2388         fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2389                 __func__, (unsigned long)T0, (unsigned long)EPN,
2390                 (unsigned long)CMP, (unsigned long)RPN, way);
2391     }
2392 #endif
2393     /* Store this TLB */
2394     ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2395                      way, is_code, CMP, RPN);
2396 }
2397
2398 static target_ulong booke_tlb_to_page_size (int size)
2399 {
2400     return 1024 << (2 * size);
2401 }
2402
2403 static int booke_page_size_to_tlb (target_ulong page_size)
2404 {
2405     int size;
2406
2407     switch (page_size) {
2408     case 0x00000400UL:
2409         size = 0x0;
2410         break;
2411     case 0x00001000UL:
2412         size = 0x1;
2413         break;
2414     case 0x00004000UL:
2415         size = 0x2;
2416         break;
2417     case 0x00010000UL:
2418         size = 0x3;
2419         break;
2420     case 0x00040000UL:
2421         size = 0x4;
2422         break;
2423     case 0x00100000UL:
2424         size = 0x5;
2425         break;
2426     case 0x00400000UL:
2427         size = 0x6;
2428         break;
2429     case 0x01000000UL:
2430         size = 0x7;
2431         break;
2432     case 0x04000000UL:
2433         size = 0x8;
2434         break;
2435     case 0x10000000UL:
2436         size = 0x9;
2437         break;
2438     case 0x40000000UL:
2439         size = 0xA;
2440         break;
2441 #if defined (TARGET_PPC64)
2442     case 0x000100000000ULL:
2443         size = 0xB;
2444         break;
2445     case 0x000400000000ULL:
2446         size = 0xC;
2447         break;
2448     case 0x001000000000ULL:
2449         size = 0xD;
2450         break;
2451     case 0x004000000000ULL:
2452         size = 0xE;
2453         break;
2454     case 0x010000000000ULL:
2455         size = 0xF;
2456         break;
2457 #endif
2458     default:
2459         size = -1;
2460         break;
2461     }
2462
2463     return size;
2464 }
2465
2466 /* Helpers for 4xx TLB management */
2467 void do_4xx_tlbre_lo (void)
2468 {
2469     ppcemb_tlb_t *tlb;
2470     int size;
2471
2472     T0 &= 0x3F;
2473     tlb = &env->tlb[T0].tlbe;
2474     T0 = tlb->EPN;
2475     if (tlb->prot & PAGE_VALID)
2476         T0 |= 0x400;
2477     size = booke_page_size_to_tlb(tlb->size);
2478     if (size < 0 || size > 0x7)
2479         size = 1;
2480     T0 |= size << 7;
2481     env->spr[SPR_40x_PID] = tlb->PID;
2482 }
2483
2484 void do_4xx_tlbre_hi (void)
2485 {
2486     ppcemb_tlb_t *tlb;
2487
2488     T0 &= 0x3F;
2489     tlb = &env->tlb[T0].tlbe;
2490     T0 = tlb->RPN;
2491     if (tlb->prot & PAGE_EXEC)
2492         T0 |= 0x200;
2493     if (tlb->prot & PAGE_WRITE)
2494         T0 |= 0x100;
2495 }
2496
2497 static int tlb_4xx_search (target_ulong virtual)
2498 {
2499     ppcemb_tlb_t *tlb;
2500     target_ulong base, mask;
2501     int i, ret;
2502
2503     /* Default return value is no match */
2504     ret = -1;
2505     for (i = 0; i < 64; i++) {
2506         tlb = &env->tlb[i].tlbe;
2507         /* Check TLB validity */
2508         if (!(tlb->prot & PAGE_VALID))
2509             continue;
2510         /* Check TLB PID vs current PID */
2511         if (tlb->PID != 0 && tlb->PID != env->spr[SPR_40x_PID])
2512             continue;
2513         /* Check TLB address vs virtual address */
2514         base = tlb->EPN;
2515         mask = ~(tlb->size - 1);
2516         if ((base & mask) != (virtual & mask))
2517             continue;
2518         ret = i;
2519         break;
2520     }
2521
2522     return ret;
2523 }
2524
2525 void do_4xx_tlbsx (void)
2526 {
2527     T0 = tlb_4xx_search(T0);
2528 }
2529
2530 void do_4xx_tlbsx_ (void)
2531 {
2532     int tmp = xer_ov;
2533
2534     T0 = tlb_4xx_search(T0);
2535     if (T0 != -1)
2536         tmp |= 0x02;
2537     env->crf[0] = tmp;
2538 }
2539
2540 void do_4xx_tlbwe_lo (void)
2541 {
2542     ppcemb_tlb_t *tlb;
2543     target_ulong page, end;
2544
2545     T0 &= 0x3F;
2546     tlb = &env->tlb[T0].tlbe;
2547     /* Invalidate previous TLB (if it's valid) */
2548     if (tlb->prot & PAGE_VALID) {
2549         end = tlb->EPN + tlb->size;
2550         for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2551             tlb_flush_page(env, page);
2552     }
2553     tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2554     tlb->EPN = (T1 & 0xFFFFFC00) & ~(tlb->size - 1);
2555     if (T1 & 0x400)
2556         tlb->prot |= PAGE_VALID;
2557     else
2558         tlb->prot &= ~PAGE_VALID;
2559     tlb->PID = env->spr[SPR_BOOKE_PID]; /* PID */
2560     tlb->attr = T1 & 0xFF;
2561     /* Invalidate new TLB (if valid) */
2562     if (tlb->prot & PAGE_VALID) {
2563         end = tlb->EPN + tlb->size;
2564         for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2565             tlb_flush_page(env, page);
2566     }
2567 }
2568
2569 void do_4xx_tlbwe_hi (void)
2570 {
2571     ppcemb_tlb_t *tlb;
2572
2573     T0 &= 0x3F;
2574     tlb = &env->tlb[T0].tlbe;
2575     tlb->RPN = T1 & 0xFFFFFC00;
2576     tlb->prot = PAGE_READ;
2577     if (T1 & 0x200)
2578         tlb->prot |= PAGE_EXEC;
2579     if (T1 & 0x100)
2580         tlb->prot |= PAGE_WRITE;
2581 }
2582 #endif /* !CONFIG_USER_ONLY */