target-ppc/op_helper.c

   1 /*
   2  *  PowerPC emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "exec.h"
  21
  22 #include "op_helper.h"
  23
  24 #define MEMSUFFIX _raw
  25 #include "op_helper.h"
  26 #include "op_helper_mem.h"
  27 #if !defined(CONFIG_USER_ONLY)
  28 #define MEMSUFFIX _user
  29 #include "op_helper.h"
  30 #include "op_helper_mem.h"
  31 #define MEMSUFFIX _kernel
  32 #include "op_helper.h"
  33 #include "op_helper_mem.h"
  34 #endif
  35
  36 //#define DEBUG_OP
  37 //#define DEBUG_EXCEPTIONS
  38 //#define DEBUG_SOFTWARE_TLB
  39 //#define FLUSH_ALL_TLBS
  40
  41 /*****************************************************************************/
  42 /* Exceptions processing helpers */
  43 void cpu_loop_exit (void)
  44 {
  45     longjmp(env->jmp_env, 1);
  46 }
  47
  48 void do_raise_exception_err (uint32_t exception, int error_code)
  49 {
  50 #if 0
  51     printf("Raise exception %3x code : %d\n", exception, error_code);
  52 #endif
  53     switch (exception) {
  54     case EXCP_PROGRAM:
  55         if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
  56             return;
  57         break;
  58     default:
  59         break;
  60     }
  61     env->exception_index = exception;
  62     env->error_code = error_code;
  63     cpu_loop_exit();
  64 }
  65
  66 void do_raise_exception (uint32_t exception)
  67 {
  68     do_raise_exception_err(exception, 0);
  69 }
  70
  71 /*****************************************************************************/
  72 /* Registers load and stores */
  73 void do_load_cr (void)
  74 {
  75     T0 = (env->crf[0] << 28) |
  76         (env->crf[1] << 24) |
  77         (env->crf[2] << 20) |
  78         (env->crf[3] << 16) |
  79         (env->crf[4] << 12) |
  80         (env->crf[5] << 8) |
  81         (env->crf[6] << 4) |
  82         (env->crf[7] << 0);
  83 }
  84
  85 void do_store_cr (uint32_t mask)
  86 {
  87     int i, sh;
  88
  89     for (i = 0, sh = 7; i < 8; i++, sh --) {
  90         if (mask & (1 << sh))
  91             env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
  92     }
  93 }
  94
  95 void do_load_xer (void)
  96 {
  97     T0 = (xer_so << XER_SO) |
  98         (xer_ov << XER_OV) |
  99         (xer_ca << XER_CA) |
 100         (xer_bc << XER_BC) |
 101         (xer_cmp << XER_CMP);
 102 }
 103
 104 void do_store_xer (void)
 105 {
 106     xer_so = (T0 >> XER_SO) & 0x01;
 107     xer_ov = (T0 >> XER_OV) & 0x01;
 108     xer_ca = (T0 >> XER_CA) & 0x01;
 109     xer_cmp = (T0 >> XER_CMP) & 0xFF;
 110     xer_bc = (T0 >> XER_BC) & 0x7F;
 111 }
 112
 113 void do_load_fpscr (void)
 114 {
 115     /* The 32 MSB of the target fpr are undefined.
 116      * They'll be zero...
 117      */
 118     union {
 119         float64 d;
 120         struct {
 121             uint32_t u[2];
 122         } s;
 123     } u;
 124     int i;
 125
 126 #if defined(WORDS_BIGENDIAN)
 127 #define WORD0 0
 128 #define WORD1 1
 129 #else
 130 #define WORD0 1
 131 #define WORD1 0
 132 #endif
 133     u.s.u[WORD0] = 0;
 134     u.s.u[WORD1] = 0;
 135     for (i = 0; i < 8; i++)
 136         u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
 137     FT0 = u.d;
 138 }
 139
 140 void do_store_fpscr (uint32_t mask)
 141 {
 142     /*
 143      * We use only the 32 LSB of the incoming fpr
 144      */
 145     union {
 146         double d;
 147         struct {
 148             uint32_t u[2];
 149         } s;
 150     } u;
 151     int i, rnd_type;
 152
 153     u.d = FT0;
 154     if (mask & 0x80)
 155         env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
 156     for (i = 1; i < 7; i++) {
 157         if (mask & (1 << (7 - i)))
 158             env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
 159     }
 160     /* TODO: update FEX & VX */
 161     /* Set rounding mode */
 162     switch (env->fpscr[0] & 0x3) {
 163     case 0:
 164         /* Best approximation (round to nearest) */
 165         rnd_type = float_round_nearest_even;
 166         break;
 167     case 1:
 168         /* Smaller magnitude (round toward zero) */
 169         rnd_type = float_round_to_zero;
 170         break;
 171     case 2:
 172         /* Round toward +infinite */
 173         rnd_type = float_round_up;
 174         break;
 175     default:
 176     case 3:
 177         /* Round toward -infinite */
 178         rnd_type = float_round_down;
 179         break;
 180     }
 181     set_float_rounding_mode(rnd_type, &env->fp_status);
 182 }
 183
 184 /*****************************************************************************/
 185 /* Fixed point operations helpers */
 186 #if defined(TARGET_PPC64)
 187 static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
 188 {
 189     *plow += a;
 190     /* carry test */
 191     if (*plow < a)
 192         (*phigh)++;
 193     *phigh += b;
 194 }
 195
 196 static void neg128 (uint64_t *plow, uint64_t *phigh)
 197 {
 198     *plow = ~ *plow;
 199     *phigh = ~ *phigh;
 200     add128(plow, phigh, 1, 0);
 201 }
 202
 203 static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
 204 {
 205     uint32_t a0, a1, b0, b1;
 206     uint64_t v;
 207
 208     a0 = a;
 209     a1 = a >> 32;
 210
 211     b0 = b;
 212     b1 = b >> 32;
 213
 214     v = (uint64_t)a0 * (uint64_t)b0;
 215     *plow = v;
 216     *phigh = 0;
 217
 218     v = (uint64_t)a0 * (uint64_t)b1;
 219     add128(plow, phigh, v << 32, v >> 32);
 220
 221     v = (uint64_t)a1 * (uint64_t)b0;
 222     add128(plow, phigh, v << 32, v >> 32);
 223
 224     v = (uint64_t)a1 * (uint64_t)b1;
 225     *phigh += v;
 226 #if defined(DEBUG_MULDIV)
 227     printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
 228            a, b, *phigh, *plow);
 229 #endif
 230 }
 231
 232 void do_mul64 (uint64_t *plow, uint64_t *phigh)
 233 {
 234     mul64(plow, phigh, T0, T1);
 235 }
 236
 237 static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
 238 {
 239     int sa, sb;
 240     sa = (a < 0);
 241     if (sa)
 242         a = -a;
 243     sb = (b < 0);
 244     if (sb)
 245         b = -b;
 246     mul64(plow, phigh, a, b);
 247     if (sa ^ sb) {
 248         neg128(plow, phigh);
 249     }
 250 }
 251
 252 void do_imul64 (uint64_t *plow, uint64_t *phigh)
 253 {
 254     imul64(plow, phigh, T0, T1);
 255 }
 256 #endif
 257
 258 void do_adde (void)
 259 {
 260     T2 = T0;
 261     T0 += T1 + xer_ca;
 262     if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
 263                  (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
 264         xer_ca = 0;
 265     } else {
 266         xer_ca = 1;
 267     }
 268 }
 269
 270 #if defined(TARGET_PPC64)
 271 void do_adde_64 (void)
 272 {
 273     T2 = T0;
 274     T0 += T1 + xer_ca;
 275     if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
 276                  (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
 277         xer_ca = 0;
 278     } else {
 279         xer_ca = 1;
 280     }
 281 }
 282 #endif
 283
 284 void do_addmeo (void)
 285 {
 286     T1 = T0;
 287     T0 += xer_ca + (-1);
 288     if (likely(!((uint32_t)T1 &
 289                  ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
 290         xer_ov = 0;
 291     } else {
 292         xer_so = 1;
 293         xer_ov = 1;
 294     }
 295     if (likely(T1 != 0))
 296         xer_ca = 1;
 297 }
 298
 299 #if defined(TARGET_PPC64)
 300 void do_addmeo_64 (void)
 301 {
 302     T1 = T0;
 303     T0 += xer_ca + (-1);
 304     if (likely(!((uint64_t)T1 &
 305                  ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
 306         xer_ov = 0;
 307     } else {
 308         xer_so = 1;
 309         xer_ov = 1;
 310     }
 311     if (likely(T1 != 0))
 312         xer_ca = 1;
 313 }
 314 #endif
 315
 316 void do_divwo (void)
 317 {
 318     if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
 319                  (int32_t)T1 == 0))) {
 320         xer_ov = 0;
 321         T0 = (int32_t)T0 / (int32_t)T1;
 322     } else {
 323         xer_so = 1;
 324         xer_ov = 1;
 325         T0 = (-1) * ((uint32_t)T0 >> 31);
 326     }
 327 }
 328
 329 #if defined(TARGET_PPC64)
 330 void do_divdo (void)
 331 {
 332     if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
 333                  (int64_t)T1 == 0))) {
 334         xer_ov = 0;
 335         T0 = (int64_t)T0 / (int64_t)T1;
 336     } else {
 337         xer_so = 1;
 338         xer_ov = 1;
 339         T0 = (-1ULL) * ((uint64_t)T0 >> 63);
 340     }
 341 }
 342 #endif
 343
 344 void do_divwuo (void)
 345 {
 346     if (likely((uint32_t)T1 != 0)) {
 347         xer_ov = 0;
 348         T0 = (uint32_t)T0 / (uint32_t)T1;
 349     } else {
 350         xer_so = 1;
 351         xer_ov = 1;
 352         T0 = 0;
 353     }
 354 }
 355
 356 #if defined(TARGET_PPC64)
 357 void do_divduo (void)
 358 {
 359     if (likely((uint64_t)T1 != 0)) {
 360         xer_ov = 0;
 361         T0 = (uint64_t)T0 / (uint64_t)T1;
 362     } else {
 363         xer_so = 1;
 364         xer_ov = 1;
 365         T0 = 0;
 366     }
 367 }
 368 #endif
 369
 370 void do_mullwo (void)
 371 {
 372     int64_t res = (int64_t)T0 * (int64_t)T1;
 373
 374     if (likely((int32_t)res == res)) {
 375         xer_ov = 0;
 376     } else {
 377         xer_ov = 1;
 378         xer_so = 1;
 379     }
 380     T0 = (int32_t)res;
 381 }
 382
 383 #if defined(TARGET_PPC64)
 384 void do_mulldo (void)
 385 {
 386     int64_t th;
 387     uint64_t tl;
 388
 389     do_imul64(&tl, &th);
 390     if (likely(th == 0)) {
 391         xer_ov = 0;
 392     } else {
 393         xer_ov = 1;
 394         xer_so = 1;
 395     }
 396     T0 = (int64_t)tl;
 397 }
 398 #endif
 399
 400 void do_nego (void)
 401 {
 402     if (likely((int32_t)T0 != INT32_MIN)) {
 403         xer_ov = 0;
 404         T0 = -(int32_t)T0;
 405     } else {
 406         xer_ov = 1;
 407         xer_so = 1;
 408     }
 409 }
 410
 411 #if defined(TARGET_PPC64)
 412 void do_nego_64 (void)
 413 {
 414     if (likely((int64_t)T0 != INT64_MIN)) {
 415         xer_ov = 0;
 416         T0 = -(int64_t)T0;
 417     } else {
 418         xer_ov = 1;
 419         xer_so = 1;
 420     }
 421 }
 422 #endif
 423
 424 void do_subfe (void)
 425 {
 426     T0 = T1 + ~T0 + xer_ca;
 427     if (likely((uint32_t)T0 >= (uint32_t)T1 &&
 428                (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
 429         xer_ca = 0;
 430     } else {
 431         xer_ca = 1;
 432     }
 433 }
 434
 435 #if defined(TARGET_PPC64)
 436 void do_subfe_64 (void)
 437 {
 438     T0 = T1 + ~T0 + xer_ca;
 439     if (likely((uint64_t)T0 >= (uint64_t)T1 &&
 440                (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
 441         xer_ca = 0;
 442     } else {
 443         xer_ca = 1;
 444     }
 445 }
 446 #endif
 447
 448 void do_subfmeo (void)
 449 {
 450     T1 = T0;
 451     T0 = ~T0 + xer_ca - 1;
 452     if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
 453                  (1UL << 31)))) {
 454         xer_ov = 0;
 455     } else {
 456         xer_so = 1;
 457         xer_ov = 1;
 458     }
 459     if (likely((uint32_t)T1 != UINT32_MAX))
 460         xer_ca = 1;
 461 }
 462
 463 #if defined(TARGET_PPC64)
 464 void do_subfmeo_64 (void)
 465 {
 466     T1 = T0;
 467     T0 = ~T0 + xer_ca - 1;
 468     if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
 469                  (1ULL << 63)))) {
 470         xer_ov = 0;
 471     } else {
 472         xer_so = 1;
 473         xer_ov = 1;
 474     }
 475     if (likely((uint64_t)T1 != UINT64_MAX))
 476         xer_ca = 1;
 477 }
 478 #endif
 479
 480 void do_subfzeo (void)
 481 {
 482     T1 = T0;
 483     T0 = ~T0 + xer_ca;
 484     if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
 485                  ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
 486         xer_ov = 0;
 487     } else {
 488         xer_ov = 1;
 489         xer_so = 1;
 490     }
 491     if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
 492         xer_ca = 0;
 493     } else {
 494         xer_ca = 1;
 495     }
 496 }
 497
 498 #if defined(TARGET_PPC64)
 499 void do_subfzeo_64 (void)
 500 {
 501     T1 = T0;
 502     T0 = ~T0 + xer_ca;
 503     if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
 504                  ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
 505         xer_ov = 0;
 506     } else {
 507         xer_ov = 1;
 508         xer_so = 1;
 509     }
 510     if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
 511         xer_ca = 0;
 512     } else {
 513         xer_ca = 1;
 514     }
 515 }
 516 #endif
 517
 518 /* shift right arithmetic helper */
 519 void do_sraw (void)
 520 {
 521     int32_t ret;
 522
 523     if (likely(!(T1 & 0x20UL))) {
 524         if (likely((uint32_t)T1 != 0)) {
 525             ret = (int32_t)T0 >> (T1 & 0x1fUL);
 526             if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
 527                 xer_ca = 0;
 528             } else {
 529                 xer_ca = 1;
 530             }
 531         } else {
 532             ret = T0;
 533             xer_ca = 0;
 534         }
 535     } else {
 536         ret = (-1) * ((uint32_t)T0 >> 31);
 537         if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
 538             xer_ca = 0;
 539         } else {
 540             xer_ca = 1;
 541         }
 542     }
 543     T0 = ret;
 544 }
 545
 546 #if defined(TARGET_PPC64)
 547 void do_srad (void)
 548 {
 549     int64_t ret;
 550
 551     if (likely(!(T1 & 0x40UL))) {
 552         if (likely((uint64_t)T1 != 0)) {
 553             ret = (int64_t)T0 >> (T1 & 0x3FUL);
 554             if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
 555                 xer_ca = 0;
 556             } else {
 557                 xer_ca = 1;
 558             }
 559         } else {
 560             ret = T0;
 561             xer_ca = 0;
 562         }
 563     } else {
 564         ret = (-1) * ((uint64_t)T0 >> 63);
 565         if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
 566             xer_ca = 0;
 567         } else {
 568             xer_ca = 1;
 569         }
 570     }
 571     T0 = ret;
 572 }
 573 #endif
 574
 575 static inline int popcnt (uint32_t val)
 576 {
 577     int i;
 578
 579     for (i = 0; val != 0;)
 580         val = val ^ (val - 1);
 581
 582     return i;
 583 }
 584
 585 void do_popcntb (void)
 586 {
 587     uint32_t ret;
 588     int i;
 589
 590     ret = 0;
 591     for (i = 0; i < 32; i += 8)
 592         ret |= popcnt((T0 >> i) & 0xFF) << i;
 593     T0 = ret;
 594 }
 595
 596 #if defined(TARGET_PPC64)
 597 void do_popcntb_64 (void)
 598 {
 599     uint64_t ret;
 600     int i;
 601
 602     ret = 0;
 603     for (i = 0; i < 64; i += 8)
 604         ret |= popcnt((T0 >> i) & 0xFF) << i;
 605     T0 = ret;
 606 }
 607 #endif
 608
 609 /*****************************************************************************/
 610 /* Floating point operations helpers */
 611 void do_fctiw (void)
 612 {
 613     union {
 614         double d;
 615         uint64_t i;
 616     } p;
 617
 618     p.i = float64_to_int32(FT0, &env->fp_status);
 619 #if USE_PRECISE_EMULATION
 620     /* XXX: higher bits are not supposed to be significant.
 621      *     to make tests easier, return the same as a real PowerPC 750 (aka G3)
 622      */
 623     p.i |= 0xFFF80000ULL << 32;
 624 #endif
 625     FT0 = p.d;
 626 }
 627
 628 void do_fctiwz (void)
 629 {
 630     union {
 631         double d;
 632         uint64_t i;
 633     } p;
 634
 635     p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
 636 #if USE_PRECISE_EMULATION
 637     /* XXX: higher bits are not supposed to be significant.
 638      *     to make tests easier, return the same as a real PowerPC 750 (aka G3)
 639      */
 640     p.i |= 0xFFF80000ULL << 32;
 641 #endif
 642     FT0 = p.d;
 643 }
 644
 645 #if defined(TARGET_PPC64)
 646 void do_fcfid (void)
 647 {
 648     union {
 649         double d;
 650         uint64_t i;
 651     } p;
 652
 653     p.d = FT0;
 654     FT0 = int64_to_float64(p.i, &env->fp_status);
 655 }
 656
 657 void do_fctid (void)
 658 {
 659     union {
 660         double d;
 661         uint64_t i;
 662     } p;
 663
 664     p.i = float64_to_int64(FT0, &env->fp_status);
 665     FT0 = p.d;
 666 }
 667
 668 void do_fctidz (void)
 669 {
 670     union {
 671         double d;
 672         uint64_t i;
 673     } p;
 674
 675     p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
 676     FT0 = p.d;
 677 }
 678
 679 #endif
 680
 681 #if USE_PRECISE_EMULATION
 682 void do_fmadd (void)
 683 {
 684 #ifdef FLOAT128
 685     float128 ft0_128, ft1_128;
 686
 687     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 688     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 689     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 690     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 691     ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 692     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 693 #else
 694     /* This is OK on x86 hosts */
 695     FT0 = (FT0 * FT1) + FT2;
 696 #endif
 697 }
 698
 699 void do_fmsub (void)
 700 {
 701 #ifdef FLOAT128
 702     float128 ft0_128, ft1_128;
 703
 704     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 705     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 706     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 707     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 708     ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 709     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 710 #else
 711     /* This is OK on x86 hosts */
 712     FT0 = (FT0 * FT1) - FT2;
 713 #endif
 714 }
 715 #endif /* USE_PRECISE_EMULATION */
 716
 717 void do_fnmadd (void)
 718 {
 719 #if USE_PRECISE_EMULATION
 720 #ifdef FLOAT128
 721     float128 ft0_128, ft1_128;
 722
 723     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 724     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 725     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 726     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 727     ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 728     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 729 #else
 730     /* This is OK on x86 hosts */
 731     FT0 = (FT0 * FT1) + FT2;
 732 #endif
 733 #else
 734     FT0 = float64_mul(FT0, FT1, &env->fp_status);
 735     FT0 = float64_add(FT0, FT2, &env->fp_status);
 736 #endif
 737     if (likely(!isnan(FT0)))
 738         FT0 = float64_chs(FT0);
 739 }
 740
 741 void do_fnmsub (void)
 742 {
 743 #if USE_PRECISE_EMULATION
 744 #ifdef FLOAT128
 745     float128 ft0_128, ft1_128;
 746
 747     ft0_128 = float64_to_float128(FT0, &env->fp_status);
 748     ft1_128 = float64_to_float128(FT1, &env->fp_status);
 749     ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 750     ft1_128 = float64_to_float128(FT2, &env->fp_status);
 751     ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 752     FT0 = float128_to_float64(ft0_128, &env->fp_status);
 753 #else
 754     /* This is OK on x86 hosts */
 755     FT0 = (FT0 * FT1) - FT2;
 756 #endif
 757 #else
 758     FT0 = float64_mul(FT0, FT1, &env->fp_status);
 759     FT0 = float64_sub(FT0, FT2, &env->fp_status);
 760 #endif
 761     if (likely(!isnan(FT0)))
 762         FT0 = float64_chs(FT0);
 763 }
 764
 765 void do_fsqrt (void)
 766 {
 767     FT0 = float64_sqrt(FT0, &env->fp_status);
 768 }
 769
 770 void do_fres (void)
 771 {
 772     union {
 773         double d;
 774         uint64_t i;
 775     } p;
 776
 777     if (likely(isnormal(FT0))) {
 778 #if USE_PRECISE_EMULATION
 779         FT0 = float64_div(1.0, FT0, &env->fp_status);
 780         FT0 = float64_to_float32(FT0, &env->fp_status);
 781 #else
 782         FT0 = float32_div(1.0, FT0, &env->fp_status);
 783 #endif
 784     } else {
 785         p.d = FT0;
 786         if (p.i == 0x8000000000000000ULL) {
 787             p.i = 0xFFF0000000000000ULL;
 788         } else if (p.i == 0x0000000000000000ULL) {
 789             p.i = 0x7FF0000000000000ULL;
 790         } else if (isnan(FT0)) {
 791             p.i = 0x7FF8000000000000ULL;
 792         } else if (FT0 < 0.0) {
 793             p.i = 0x8000000000000000ULL;
 794         } else {
 795             p.i = 0x0000000000000000ULL;
 796         }
 797         FT0 = p.d;
 798     }
 799 }
 800
 801 void do_frsqrte (void)
 802 {
 803     union {
 804         double d;
 805         uint64_t i;
 806     } p;
 807
 808     if (likely(isnormal(FT0) && FT0 > 0.0)) {
 809         FT0 = float64_sqrt(FT0, &env->fp_status);
 810         FT0 = float32_div(1.0, FT0, &env->fp_status);
 811     } else {
 812         p.d = FT0;
 813         if (p.i == 0x8000000000000000ULL) {
 814             p.i = 0xFFF0000000000000ULL;
 815         } else if (p.i == 0x0000000000000000ULL) {
 816             p.i = 0x7FF0000000000000ULL;
 817         } else if (isnan(FT0)) {
 818             if (!(p.i & 0x0008000000000000ULL))
 819                 p.i |= 0x000FFFFFFFFFFFFFULL;
 820         } else if (FT0 < 0) {
 821             p.i = 0x7FF8000000000000ULL;
 822         } else {
 823             p.i = 0x0000000000000000ULL;
 824         }
 825         FT0 = p.d;
 826     }
 827 }
 828
 829 void do_fsel (void)
 830 {
 831     if (FT0 >= 0)
 832         FT0 = FT1;
 833     else
 834         FT0 = FT2;
 835 }
 836
 837 void do_fcmpu (void)
 838 {
 839     if (likely(!isnan(FT0) && !isnan(FT1))) {
 840         if (float64_lt(FT0, FT1, &env->fp_status)) {
 841             T0 = 0x08UL;
 842         } else if (!float64_le(FT0, FT1, &env->fp_status)) {
 843             T0 = 0x04UL;
 844         } else {
 845             T0 = 0x02UL;
 846         }
 847     } else {
 848         T0 = 0x01UL;
 849         env->fpscr[4] |= 0x1;
 850         env->fpscr[6] |= 0x1;
 851     }
 852     env->fpscr[3] = T0;
 853 }
 854
 855 void do_fcmpo (void)
 856 {
 857     env->fpscr[4] &= ~0x1;
 858     if (likely(!isnan(FT0) && !isnan(FT1))) {
 859         if (float64_lt(FT0, FT1, &env->fp_status)) {
 860             T0 = 0x08UL;
 861         } else if (!float64_le(FT0, FT1, &env->fp_status)) {
 862             T0 = 0x04UL;
 863         } else {
 864             T0 = 0x02UL;
 865         }
 866     } else {
 867         T0 = 0x01UL;
 868         env->fpscr[4] |= 0x1;
 869         if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
 870             /* Quiet NaN case */
 871             env->fpscr[6] |= 0x1;
 872             if (!(env->fpscr[1] & 0x8))
 873                 env->fpscr[4] |= 0x8;
 874         } else {
 875             env->fpscr[4] |= 0x8;
 876         }
 877     }
 878     env->fpscr[3] = T0;
 879 }
 880
 881 #if !defined (CONFIG_USER_ONLY)
 882 void do_rfi (void)
 883 {
 884     env->nip = (target_ulong)(env->spr[SPR_SRR0] & ~0x00000003);
 885     T0 = (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL);
 886 #if defined(TARGET_PPC64)
 887     ppc_store_msr_32(env, T0);
 888 #else
 889     do_store_msr(env, T0);
 890 #endif
 891 #if defined (DEBUG_OP)
 892     dump_rfi();
 893 #endif
 894     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 895 }
 896
 897 #if defined(TARGET_PPC64)
 898 void do_rfi_32 (void)
 899 {
 900     env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
 901     T0 = (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL);
 902     ppc_store_msr_32(env, T0);
 903 #if defined (DEBUG_OP)
 904     dump_rfi();
 905 #endif
 906     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 907 }
 908
 909 void do_rfid (void)
 910 {
 911     env->nip = (target_ulong)(env->spr[SPR_SRR0] & ~0x00000003);
 912     T0 = (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL);
 913     do_store_msr(env, T0);
 914 #if defined (DEBUG_OP)
 915     dump_rfi();
 916 #endif
 917     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 918 }
 919
 920 void do_rfid_32 (void)
 921 {
 922     env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
 923     T0 = (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL);
 924     do_store_msr(env, T0);
 925 #if defined (DEBUG_OP)
 926     dump_rfi();
 927 #endif
 928     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 929 }
 930 #endif
 931 #endif
 932
 933 void do_tw (int flags)
 934 {
 935     if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
 936                   ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
 937                   ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
 938                   ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
 939                   ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01)))))
 940         do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
 941 }
 942
 943 #if defined(TARGET_PPC64)
 944 void do_td (int flags)
 945 {
 946     if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
 947                   ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
 948                   ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
 949                   ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
 950                   ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
 951         do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
 952 }
 953 #endif
 954
 955 /*****************************************************************************/
 956 /* PowerPC 601 specific instructions (POWER bridge) */
 957 void do_POWER_abso (void)
 958 {
 959     if ((uint32_t)T0 == INT32_MIN) {
 960         T0 = INT32_MAX;
 961         xer_ov = 1;
 962         xer_so = 1;
 963     } else {
 964         T0 = -T0;
 965         xer_ov = 0;
 966     }
 967 }
 968
 969 void do_POWER_clcs (void)
 970 {
 971     switch (T0) {
 972     case 0x0CUL:
 973         /* Instruction cache line size */
 974         T0 = ICACHE_LINE_SIZE;
 975         break;
 976     case 0x0DUL:
 977         /* Data cache line size */
 978         T0 = DCACHE_LINE_SIZE;
 979         break;
 980     case 0x0EUL:
 981         /* Minimum cache line size */
 982         T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
 983             ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
 984         break;
 985     case 0x0FUL:
 986         /* Maximum cache line size */
 987         T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
 988             ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
 989         break;
 990     default:
 991         /* Undefined */
 992         break;
 993     }
 994 }
 995
 996 void do_POWER_div (void)
 997 {
 998     uint64_t tmp;
 999
1000     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1001         T0 = (long)((-1) * (T0 >> 31));
1002         env->spr[SPR_MQ] = 0;
1003     } else {
1004         tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1005         env->spr[SPR_MQ] = tmp % T1;
1006         T0 = tmp / (int32_t)T1;
1007     }
1008 }
1009
1010 void do_POWER_divo (void)
1011 {
1012     int64_t tmp;
1013
1014     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1015         T0 = (long)((-1) * (T0 >> 31));
1016         env->spr[SPR_MQ] = 0;
1017         xer_ov = 1;
1018         xer_so = 1;
1019     } else {
1020         tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1021         env->spr[SPR_MQ] = tmp % T1;
1022         tmp /= (int32_t)T1;
1023         if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1024             xer_ov = 1;
1025             xer_so = 1;
1026         } else {
1027             xer_ov = 0;
1028         }
1029         T0 = tmp;
1030     }
1031 }
1032
1033 void do_POWER_divs (void)
1034 {
1035     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1036         T0 = (long)((-1) * (T0 >> 31));
1037         env->spr[SPR_MQ] = 0;
1038     } else {
1039         env->spr[SPR_MQ] = T0 % T1;
1040         T0 = (int32_t)T0 / (int32_t)T1;
1041     }
1042 }
1043
1044 void do_POWER_divso (void)
1045 {
1046     if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1047         T0 = (long)((-1) * (T0 >> 31));
1048         env->spr[SPR_MQ] = 0;
1049         xer_ov = 1;
1050         xer_so = 1;
1051     } else {
1052         T0 = (int32_t)T0 / (int32_t)T1;
1053         env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1054         xer_ov = 0;
1055     }
1056 }
1057
1058 void do_POWER_dozo (void)
1059 {
1060     if ((int32_t)T1 > (int32_t)T0) {
1061         T2 = T0;
1062         T0 = T1 - T0;
1063         if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1064             ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1065             xer_so = 1;
1066             xer_ov = 1;
1067         } else {
1068             xer_ov = 0;
1069         }
1070     } else {
1071         T0 = 0;
1072         xer_ov = 0;
1073     }
1074 }
1075
1076 void do_POWER_maskg (void)
1077 {
1078     uint32_t ret;
1079
1080     if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1081         ret = -1;
1082     } else {
1083         ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
1084             (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
1085         if ((uint32_t)T0 > (uint32_t)T1)
1086             ret = ~ret;
1087     }
1088     T0 = ret;
1089 }
1090
1091 void do_POWER_mulo (void)
1092 {
1093     uint64_t tmp;
1094
1095     tmp = (uint64_t)T0 * (uint64_t)T1;
1096     env->spr[SPR_MQ] = tmp >> 32;
1097     T0 = tmp;
1098     if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1099         xer_ov = 1;
1100         xer_so = 1;
1101     } else {
1102         xer_ov = 0;
1103     }
1104 }
1105
1106 #if !defined (CONFIG_USER_ONLY)
1107 void do_POWER_rac (void)
1108 {
1109 #if 0
1110     mmu_ctx_t ctx;
1111
1112     /* We don't have to generate many instances of this instruction,
1113      * as rac is supervisor only.
1114      */
1115     if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
1116         T0 = ctx.raddr;
1117 #endif
1118 }
1119
1120 void do_POWER_rfsvc (void)
1121 {
1122     env->nip = env->lr & ~0x00000003UL;
1123     T0 = env->ctr & 0x0000FFFFUL;
1124     do_store_msr(env, T0);
1125 #if defined (DEBUG_OP)
1126     dump_rfi();
1127 #endif
1128     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1129 }
1130
1131 /* PowerPC 601 BAT management helper */
1132 void do_store_601_batu (int nr)
1133 {
1134     do_store_ibatu(env, nr, (uint32_t)T0);
1135     env->DBAT[0][nr] = env->IBAT[0][nr];
1136     env->DBAT[1][nr] = env->IBAT[1][nr];
1137 }
1138 #endif
1139
1140 /*****************************************************************************/
1141 /* 602 specific instructions */
1142 /* mfrom is the most crazy instruction ever seen, imho ! */
1143 /* Real implementation uses a ROM table. Do the same */
1144 #define USE_MFROM_ROM_TABLE
1145 void do_op_602_mfrom (void)
1146 {
1147     if (likely(T0 < 602)) {
1148 #if defined(USE_MFROM_ROM_TABLE)
1149 #include "mfrom_table.c"
1150         T0 = mfrom_ROM_table[T0];
1151 #else
1152         double d;
1153         /* Extremly decomposed:
1154          *                    -T0 / 256
1155          * T0 = 256 * log10(10          + 1.0) + 0.5
1156          */
1157         d = T0;
1158         d = float64_div(d, 256, &env->fp_status);
1159         d = float64_chs(d);
1160         d = exp10(d); // XXX: use float emulation function
1161         d = float64_add(d, 1.0, &env->fp_status);
1162         d = log10(d); // XXX: use float emulation function
1163         d = float64_mul(d, 256, &env->fp_status);
1164         d = float64_add(d, 0.5, &env->fp_status);
1165         T0 = float64_round_to_int(d, &env->fp_status);
1166 #endif
1167     } else {
1168         T0 = 0;
1169     }
1170 }
1171
1172 /*****************************************************************************/
1173 /* Embedded PowerPC specific helpers */
1174 void do_405_check_ov (void)
1175 {
1176     if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1177                !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1178         xer_ov = 0;
1179     } else {
1180         xer_ov = 1;
1181         xer_so = 1;
1182     }
1183 }
1184
1185 void do_405_check_sat (void)
1186 {
1187     if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1188                 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1189         /* Saturate result */
1190         if (T2 >> 31) {
1191             T0 = INT32_MIN;
1192         } else {
1193             T0 = INT32_MAX;
1194         }
1195     }
1196 }
1197
1198 #if !defined(CONFIG_USER_ONLY)
1199 void do_4xx_rfci (void)
1200 {
1201     env->nip = env->spr[SPR_40x_SRR2];
1202     T0 = env->spr[SPR_40x_SRR3] & ~0xFFFF0000;
1203     do_store_msr(env, T0);
1204 #if defined (DEBUG_OP)
1205     dump_rfi();
1206 #endif
1207     env->interrupt_request = CPU_INTERRUPT_EXITTB;
1208 }
1209
1210 void do_4xx_load_dcr (int dcrn)
1211 {
1212     target_ulong val;
1213
1214     if (unlikely(env->dcr_read == NULL))
1215         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1216     else if (unlikely((*env->dcr_read)(env->dcr_env, dcrn, &val) != 0))
1217         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1218     else
1219         T0 = val;
1220 }
1221
1222 void do_4xx_store_dcr (int dcrn)
1223 {
1224     if (unlikely(env->dcr_write == NULL))
1225         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1226     else if (unlikely((*env->dcr_write)(env->dcr_env, dcrn, T0) != 0))
1227         do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1228 }
1229
1230 void do_load_403_pb (int num)
1231 {
1232     T0 = env->pb[num];
1233 }
1234
1235 void do_store_403_pb (int num)
1236 {
1237     if (likely(env->pb[num] != T0)) {
1238         env->pb[num] = T0;
1239         /* Should be optimized */
1240         tlb_flush(env, 1);
1241     }
1242 }
1243 #endif
1244
1245 /* 440 specific */
1246 void do_440_dlmzb (void)
1247 {
1248     target_ulong mask;
1249     int i;
1250
1251     i = 1;
1252     for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1253         if ((T0 & mask) == 0)
1254             goto done;
1255         i++;
1256     }
1257     for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1258         if ((T1 & mask) == 0)
1259             break;
1260         i++;
1261     }
1262  done:
1263     T0 = i;
1264 }
1265
1266 #if defined(TARGET_PPCSPE)
1267 /* SPE extension helpers */
1268 /* Use a table to make this quicker */
1269 static uint8_t hbrev[16] = {
1270     0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1271     0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1272 };
1273
1274 static inline uint8_t byte_reverse (uint8_t val)
1275 {
1276     return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1277 }
1278
1279 static inline uint32_t word_reverse (uint32_t val)
1280 {
1281     return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1282         (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1283 }
1284
1285 #define MASKBITS 16 // Random value - to be fixed
1286 void do_brinc (void)
1287 {
1288     uint32_t a, b, d, mask;
1289
1290     mask = (uint32_t)(-1UL) >> MASKBITS;
1291     b = T1_64 & mask;
1292     a = T0_64 & mask;
1293     d = word_reverse(1 + word_reverse(a | ~mask));
1294     T0_64 = (T0_64 & ~mask) | (d & mask);
1295 }
1296
1297 #define DO_SPE_OP2(name)                                                      \
1298 void do_ev##name (void)                                                       \
1299 {                                                                             \
1300     T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) |         \
1301         (uint64_t)_do_e##name(T0_64, T1_64);                                  \
1302 }
1303
1304 #define DO_SPE_OP1(name)                                                      \
1305 void do_ev##name (void)                                                       \
1306 {                                                                             \
1307     T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) |                      \
1308         (uint64_t)_do_e##name(T0_64);                                         \
1309 }
1310
1311 /* Fixed-point vector arithmetic */
1312 static inline uint32_t _do_eabs (uint32_t val)
1313 {
1314     if (val != 0x80000000)
1315         val &= ~0x80000000;
1316
1317     return val;
1318 }
1319
1320 static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1321 {
1322     return op1 + op2;
1323 }
1324
1325 static inline int _do_ecntlsw (uint32_t val)
1326 {
1327     if (val & 0x80000000)
1328         return _do_cntlzw(~val);
1329     else
1330         return _do_cntlzw(val);
1331 }
1332
1333 static inline int _do_ecntlzw (uint32_t val)
1334 {
1335     return _do_cntlzw(val);
1336 }
1337
1338 static inline uint32_t _do_eneg (uint32_t val)
1339 {
1340     if (val != 0x80000000)
1341         val ^= 0x80000000;
1342
1343     return val;
1344 }
1345
1346 static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1347 {
1348     return rotl32(op1, op2);
1349 }
1350
1351 static inline uint32_t _do_erndw (uint32_t val)
1352 {
1353     return (val + 0x000080000000) & 0xFFFF0000;
1354 }
1355
1356 static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1357 {
1358     /* No error here: 6 bits are used */
1359     return op1 << (op2 & 0x3F);
1360 }
1361
1362 static inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1363 {
1364     /* No error here: 6 bits are used */
1365     return op1 >> (op2 & 0x3F);
1366 }
1367
1368 static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1369 {
1370     /* No error here: 6 bits are used */
1371     return op1 >> (op2 & 0x3F);
1372 }
1373
1374 static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1375 {
1376     return op2 - op1;
1377 }
1378
1379 /* evabs */
1380 DO_SPE_OP1(abs);
1381 /* evaddw */
1382 DO_SPE_OP2(addw);
1383 /* evcntlsw */
1384 DO_SPE_OP1(cntlsw);
1385 /* evcntlzw */
1386 DO_SPE_OP1(cntlzw);
1387 /* evneg */
1388 DO_SPE_OP1(neg);
1389 /* evrlw */
1390 DO_SPE_OP2(rlw);
1391 /* evrnd */
1392 DO_SPE_OP1(rndw);
1393 /* evslw */
1394 DO_SPE_OP2(slw);
1395 /* evsrws */
1396 DO_SPE_OP2(srws);
1397 /* evsrwu */
1398 DO_SPE_OP2(srwu);
1399 /* evsubfw */
1400 DO_SPE_OP2(subfw);
1401
1402 /* evsel is a little bit more complicated... */
1403 static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1404 {
1405     if (n)
1406         return op1;
1407     else
1408         return op2;
1409 }
1410
1411 void do_evsel (void)
1412 {
1413     T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1414         (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1415 }
1416
1417 /* Fixed-point vector comparisons */
1418 #define DO_SPE_CMP(name)                                                      \
1419 void do_ev##name (void)                                                       \
1420 {                                                                             \
1421     T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32,                   \
1422                                                T1_64 >> 32) << 32,            \
1423                          _do_e##name(T0_64, T1_64));                          \
1424 }
1425
1426 static inline uint32_t _do_evcmp_merge (int t0, int t1)
1427 {
1428     return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1429 }
1430 static inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
1431 {
1432     return op1 == op2 ? 1 : 0;
1433 }
1434
1435 static inline int _do_ecmpgts (int32_t op1, int32_t op2)
1436 {
1437     return op1 > op2 ? 1 : 0;
1438 }
1439
1440 static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
1441 {
1442     return op1 > op2 ? 1 : 0;
1443 }
1444
1445 static inline int _do_ecmplts (int32_t op1, int32_t op2)
1446 {
1447     return op1 < op2 ? 1 : 0;
1448 }
1449
1450 static inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
1451 {
1452     return op1 < op2 ? 1 : 0;
1453 }
1454
1455 /* evcmpeq */
1456 DO_SPE_CMP(cmpeq);
1457 /* evcmpgts */
1458 DO_SPE_CMP(cmpgts);
1459 /* evcmpgtu */
1460 DO_SPE_CMP(cmpgtu);
1461 /* evcmplts */
1462 DO_SPE_CMP(cmplts);
1463 /* evcmpltu */
1464 DO_SPE_CMP(cmpltu);
1465
1466 /* Single precision floating-point conversions from/to integer */
1467 static inline uint32_t _do_efscfsi (int32_t val)
1468 {
1469     union {
1470         uint32_t u;
1471         float32 f;
1472     } u;
1473
1474     u.f = int32_to_float32(val, &env->spe_status);
1475
1476     return u.u;
1477 }
1478
1479 static inline uint32_t _do_efscfui (uint32_t val)
1480 {
1481     union {
1482         uint32_t u;
1483         float32 f;
1484     } u;
1485
1486     u.f = uint32_to_float32(val, &env->spe_status);
1487
1488     return u.u;
1489 }
1490
1491 static inline int32_t _do_efsctsi (uint32_t val)
1492 {
1493     union {
1494         int32_t u;
1495         float32 f;
1496     } u;
1497
1498     u.u = val;
1499     /* NaN are not treated the same way IEEE 754 does */
1500     if (unlikely(isnan(u.f)))
1501         return 0;
1502
1503     return float32_to_int32(u.f, &env->spe_status);
1504 }
1505
1506 static inline uint32_t _do_efsctui (uint32_t val)
1507 {
1508     union {
1509         int32_t u;
1510         float32 f;
1511     } u;
1512
1513     u.u = val;
1514     /* NaN are not treated the same way IEEE 754 does */
1515     if (unlikely(isnan(u.f)))
1516         return 0;
1517
1518     return float32_to_uint32(u.f, &env->spe_status);
1519 }
1520
1521 static inline int32_t _do_efsctsiz (uint32_t val)
1522 {
1523     union {
1524         int32_t u;
1525         float32 f;
1526     } u;
1527
1528     u.u = val;
1529     /* NaN are not treated the same way IEEE 754 does */
1530     if (unlikely(isnan(u.f)))
1531         return 0;
1532
1533     return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1534 }
1535
1536 static inline uint32_t _do_efsctuiz (uint32_t val)
1537 {
1538     union {
1539         int32_t u;
1540         float32 f;
1541     } u;
1542
1543     u.u = val;
1544     /* NaN are not treated the same way IEEE 754 does */
1545     if (unlikely(isnan(u.f)))
1546         return 0;
1547
1548     return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1549 }
1550
1551 void do_efscfsi (void)
1552 {
1553     T0_64 = _do_efscfsi(T0_64);
1554 }
1555
1556 void do_efscfui (void)
1557 {
1558     T0_64 = _do_efscfui(T0_64);
1559 }
1560
1561 void do_efsctsi (void)
1562 {
1563     T0_64 = _do_efsctsi(T0_64);
1564 }
1565
1566 void do_efsctui (void)
1567 {
1568     T0_64 = _do_efsctui(T0_64);
1569 }
1570
1571 void do_efsctsiz (void)
1572 {
1573     T0_64 = _do_efsctsiz(T0_64);
1574 }
1575
1576 void do_efsctuiz (void)
1577 {
1578     T0_64 = _do_efsctuiz(T0_64);
1579 }
1580
1581 /* Single precision floating-point conversion to/from fractional */
1582 static inline uint32_t _do_efscfsf (uint32_t val)
1583 {
1584     union {
1585         uint32_t u;
1586         float32 f;
1587     } u;
1588     float32 tmp;
1589
1590     u.f = int32_to_float32(val, &env->spe_status);
1591     tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1592     u.f = float32_div(u.f, tmp, &env->spe_status);
1593
1594     return u.u;
1595 }
1596
1597 static inline uint32_t _do_efscfuf (uint32_t val)
1598 {
1599     union {
1600         uint32_t u;
1601         float32 f;
1602     } u;
1603     float32 tmp;
1604
1605     u.f = uint32_to_float32(val, &env->spe_status);
1606     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1607     u.f = float32_div(u.f, tmp, &env->spe_status);
1608
1609     return u.u;
1610 }
1611
1612 static inline int32_t _do_efsctsf (uint32_t val)
1613 {
1614     union {
1615         int32_t u;
1616         float32 f;
1617     } u;
1618     float32 tmp;
1619
1620     u.u = val;
1621     /* NaN are not treated the same way IEEE 754 does */
1622     if (unlikely(isnan(u.f)))
1623         return 0;
1624     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1625     u.f = float32_mul(u.f, tmp, &env->spe_status);
1626
1627     return float32_to_int32(u.f, &env->spe_status);
1628 }
1629
1630 static inline uint32_t _do_efsctuf (uint32_t val)
1631 {
1632     union {
1633         int32_t u;
1634         float32 f;
1635     } u;
1636     float32 tmp;
1637
1638     u.u = val;
1639     /* NaN are not treated the same way IEEE 754 does */
1640     if (unlikely(isnan(u.f)))
1641         return 0;
1642     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1643     u.f = float32_mul(u.f, tmp, &env->spe_status);
1644
1645     return float32_to_uint32(u.f, &env->spe_status);
1646 }
1647
1648 static inline int32_t _do_efsctsfz (uint32_t val)
1649 {
1650     union {
1651         int32_t u;
1652         float32 f;
1653     } u;
1654     float32 tmp;
1655
1656     u.u = val;
1657     /* NaN are not treated the same way IEEE 754 does */
1658     if (unlikely(isnan(u.f)))
1659         return 0;
1660     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1661     u.f = float32_mul(u.f, tmp, &env->spe_status);
1662
1663     return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1664 }
1665
1666 static inline uint32_t _do_efsctufz (uint32_t val)
1667 {
1668     union {
1669         int32_t u;
1670         float32 f;
1671     } u;
1672     float32 tmp;
1673
1674     u.u = val;
1675     /* NaN are not treated the same way IEEE 754 does */
1676     if (unlikely(isnan(u.f)))
1677         return 0;
1678     tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1679     u.f = float32_mul(u.f, tmp, &env->spe_status);
1680
1681     return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1682 }
1683
1684 void do_efscfsf (void)
1685 {
1686     T0_64 = _do_efscfsf(T0_64);
1687 }
1688
1689 void do_efscfuf (void)
1690 {
1691     T0_64 = _do_efscfuf(T0_64);
1692 }
1693
1694 void do_efsctsf (void)
1695 {
1696     T0_64 = _do_efsctsf(T0_64);
1697 }
1698
1699 void do_efsctuf (void)
1700 {
1701     T0_64 = _do_efsctuf(T0_64);
1702 }
1703
1704 void do_efsctsfz (void)
1705 {
1706     T0_64 = _do_efsctsfz(T0_64);
1707 }
1708
1709 void do_efsctufz (void)
1710 {
1711     T0_64 = _do_efsctufz(T0_64);
1712 }
1713
1714 /* Double precision floating point helpers */
1715 static inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
1716 {
1717     /* XXX: TODO: test special values (NaN, infinites, ...) */
1718     return _do_efdtstlt(op1, op2);
1719 }
1720
1721 static inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
1722 {
1723     /* XXX: TODO: test special values (NaN, infinites, ...) */
1724     return _do_efdtstgt(op1, op2);
1725 }
1726
1727 static inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
1728 {
1729     /* XXX: TODO: test special values (NaN, infinites, ...) */
1730     return _do_efdtsteq(op1, op2);
1731 }
1732
1733 void do_efdcmplt (void)
1734 {
1735     T0 = _do_efdcmplt(T0_64, T1_64);
1736 }
1737
1738 void do_efdcmpgt (void)
1739 {
1740     T0 = _do_efdcmpgt(T0_64, T1_64);
1741 }
1742
1743 void do_efdcmpeq (void)
1744 {
1745     T0 = _do_efdcmpeq(T0_64, T1_64);
1746 }
1747
1748 /* Double precision floating-point conversion to/from integer */
1749 static inline uint64_t _do_efdcfsi (int64_t val)
1750 {
1751     union {
1752         uint64_t u;
1753         float64 f;
1754     } u;
1755
1756     u.f = int64_to_float64(val, &env->spe_status);
1757
1758     return u.u;
1759 }
1760
1761 static inline uint64_t _do_efdcfui (uint64_t val)
1762 {
1763     union {
1764         uint64_t u;
1765         float64 f;
1766     } u;
1767
1768     u.f = uint64_to_float64(val, &env->spe_status);
1769
1770     return u.u;
1771 }
1772
1773 static inline int64_t _do_efdctsi (uint64_t val)
1774 {
1775     union {
1776         int64_t u;
1777         float64 f;
1778     } u;
1779
1780     u.u = val;
1781     /* NaN are not treated the same way IEEE 754 does */
1782     if (unlikely(isnan(u.f)))
1783         return 0;
1784
1785     return float64_to_int64(u.f, &env->spe_status);
1786 }
1787
1788 static inline uint64_t _do_efdctui (uint64_t val)
1789 {
1790     union {
1791         int64_t u;
1792         float64 f;
1793     } u;
1794
1795     u.u = val;
1796     /* NaN are not treated the same way IEEE 754 does */
1797     if (unlikely(isnan(u.f)))
1798         return 0;
1799
1800     return float64_to_uint64(u.f, &env->spe_status);
1801 }
1802
1803 static inline int64_t _do_efdctsiz (uint64_t val)
1804 {
1805     union {
1806         int64_t u;
1807         float64 f;
1808     } u;
1809
1810     u.u = val;
1811     /* NaN are not treated the same way IEEE 754 does */
1812     if (unlikely(isnan(u.f)))
1813         return 0;
1814
1815     return float64_to_int64_round_to_zero(u.f, &env->spe_status);
1816 }
1817
1818 static inline uint64_t _do_efdctuiz (uint64_t val)
1819 {
1820     union {
1821         int64_t u;
1822         float64 f;
1823     } u;
1824
1825     u.u = val;
1826     /* NaN are not treated the same way IEEE 754 does */
1827     if (unlikely(isnan(u.f)))
1828         return 0;
1829
1830     return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
1831 }
1832
1833 void do_efdcfsi (void)
1834 {
1835     T0_64 = _do_efdcfsi(T0_64);
1836 }
1837
1838 void do_efdcfui (void)
1839 {
1840     T0_64 = _do_efdcfui(T0_64);
1841 }
1842
1843 void do_efdctsi (void)
1844 {
1845     T0_64 = _do_efdctsi(T0_64);
1846 }
1847
1848 void do_efdctui (void)
1849 {
1850     T0_64 = _do_efdctui(T0_64);
1851 }
1852
1853 void do_efdctsiz (void)
1854 {
1855     T0_64 = _do_efdctsiz(T0_64);
1856 }
1857
1858 void do_efdctuiz (void)
1859 {
1860     T0_64 = _do_efdctuiz(T0_64);
1861 }
1862
1863 /* Double precision floating-point conversion to/from fractional */
1864 static inline uint64_t _do_efdcfsf (int64_t val)
1865 {
1866     union {
1867         uint64_t u;
1868         float64 f;
1869     } u;
1870     float64 tmp;
1871
1872     u.f = int32_to_float64(val, &env->spe_status);
1873     tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1874     u.f = float64_div(u.f, tmp, &env->spe_status);
1875
1876     return u.u;
1877 }
1878
1879 static inline uint64_t _do_efdcfuf (uint64_t val)
1880 {
1881     union {
1882         uint64_t u;
1883         float64 f;
1884     } u;
1885     float64 tmp;
1886
1887     u.f = uint32_to_float64(val, &env->spe_status);
1888     tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1889     u.f = float64_div(u.f, tmp, &env->spe_status);
1890
1891     return u.u;
1892 }
1893
1894 static inline int64_t _do_efdctsf (uint64_t val)
1895 {
1896     union {
1897         int64_t u;
1898         float64 f;
1899     } u;
1900     float64 tmp;
1901
1902     u.u = val;
1903     /* NaN are not treated the same way IEEE 754 does */
1904     if (unlikely(isnan(u.f)))
1905         return 0;
1906     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1907     u.f = float64_mul(u.f, tmp, &env->spe_status);
1908
1909     return float64_to_int32(u.f, &env->spe_status);
1910 }
1911
1912 static inline uint64_t _do_efdctuf (uint64_t val)
1913 {
1914     union {
1915         int64_t u;
1916         float64 f;
1917     } u;
1918     float64 tmp;
1919
1920     u.u = val;
1921     /* NaN are not treated the same way IEEE 754 does */
1922     if (unlikely(isnan(u.f)))
1923         return 0;
1924     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1925     u.f = float64_mul(u.f, tmp, &env->spe_status);
1926
1927     return float64_to_uint32(u.f, &env->spe_status);
1928 }
1929
1930 static inline int64_t _do_efdctsfz (uint64_t val)
1931 {
1932     union {
1933         int64_t u;
1934         float64 f;
1935     } u;
1936     float64 tmp;
1937
1938     u.u = val;
1939     /* NaN are not treated the same way IEEE 754 does */
1940     if (unlikely(isnan(u.f)))
1941         return 0;
1942     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1943     u.f = float64_mul(u.f, tmp, &env->spe_status);
1944
1945     return float64_to_int32_round_to_zero(u.f, &env->spe_status);
1946 }
1947
1948 static inline uint64_t _do_efdctufz (uint64_t val)
1949 {
1950     union {
1951         int64_t u;
1952         float64 f;
1953     } u;
1954     float64 tmp;
1955
1956     u.u = val;
1957     /* NaN are not treated the same way IEEE 754 does */
1958     if (unlikely(isnan(u.f)))
1959         return 0;
1960     tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1961     u.f = float64_mul(u.f, tmp, &env->spe_status);
1962
1963     return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
1964 }
1965
1966 void do_efdcfsf (void)
1967 {
1968     T0_64 = _do_efdcfsf(T0_64);
1969 }
1970
1971 void do_efdcfuf (void)
1972 {
1973     T0_64 = _do_efdcfuf(T0_64);
1974 }
1975
1976 void do_efdctsf (void)
1977 {
1978     T0_64 = _do_efdctsf(T0_64);
1979 }
1980
1981 void do_efdctuf (void)
1982 {
1983     T0_64 = _do_efdctuf(T0_64);
1984 }
1985
1986 void do_efdctsfz (void)
1987 {
1988     T0_64 = _do_efdctsfz(T0_64);
1989 }
1990
1991 void do_efdctufz (void)
1992 {
1993     T0_64 = _do_efdctufz(T0_64);
1994 }
1995
1996 /* Floating point conversion between single and double precision */
1997 static inline uint32_t _do_efscfd (uint64_t val)
1998 {
1999     union {
2000         uint64_t u;
2001         float64 f;
2002     } u1;
2003     union {
2004         uint32_t u;
2005         float32 f;
2006     } u2;
2007
2008     u1.u = val;
2009     u2.f = float64_to_float32(u1.f, &env->spe_status);
2010
2011     return u2.u;
2012 }
2013
2014 static inline uint64_t _do_efdcfs (uint32_t val)
2015 {
2016     union {
2017         uint64_t u;
2018         float64 f;
2019     } u2;
2020     union {
2021         uint32_t u;
2022         float32 f;
2023     } u1;
2024
2025     u1.u = val;
2026     u2.f = float32_to_float64(u1.f, &env->spe_status);
2027
2028     return u2.u;
2029 }
2030
2031 void do_efscfd (void)
2032 {
2033     T0_64 = _do_efscfd(T0_64);
2034 }
2035
2036 void do_efdcfs (void)
2037 {
2038     T0_64 = _do_efdcfs(T0_64);
2039 }
2040
2041 /* Single precision fixed-point vector arithmetic */
2042 /* evfsabs */
2043 DO_SPE_OP1(fsabs);
2044 /* evfsnabs */
2045 DO_SPE_OP1(fsnabs);
2046 /* evfsneg */
2047 DO_SPE_OP1(fsneg);
2048 /* evfsadd */
2049 DO_SPE_OP2(fsadd);
2050 /* evfssub */
2051 DO_SPE_OP2(fssub);
2052 /* evfsmul */
2053 DO_SPE_OP2(fsmul);
2054 /* evfsdiv */
2055 DO_SPE_OP2(fsdiv);
2056
2057 /* Single-precision floating-point comparisons */
2058 static inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2059 {
2060     /* XXX: TODO: test special values (NaN, infinites, ...) */
2061     return _do_efststlt(op1, op2);
2062 }
2063
2064 static inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2065 {
2066     /* XXX: TODO: test special values (NaN, infinites, ...) */
2067     return _do_efststgt(op1, op2);
2068 }
2069
2070 static inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2071 {
2072     /* XXX: TODO: test special values (NaN, infinites, ...) */
2073     return _do_efststeq(op1, op2);
2074 }
2075
2076 void do_efscmplt (void)
2077 {
2078     T0 = _do_efscmplt(T0_64, T1_64);
2079 }
2080
2081 void do_efscmpgt (void)
2082 {
2083     T0 = _do_efscmpgt(T0_64, T1_64);
2084 }
2085
2086 void do_efscmpeq (void)
2087 {
2088     T0 = _do_efscmpeq(T0_64, T1_64);
2089 }
2090
2091 /* Single-precision floating-point vector comparisons */
2092 /* evfscmplt */
2093 DO_SPE_CMP(fscmplt);
2094 /* evfscmpgt */
2095 DO_SPE_CMP(fscmpgt);
2096 /* evfscmpeq */
2097 DO_SPE_CMP(fscmpeq);
2098 /* evfststlt */
2099 DO_SPE_CMP(fststlt);
2100 /* evfststgt */
2101 DO_SPE_CMP(fststgt);
2102 /* evfststeq */
2103 DO_SPE_CMP(fststeq);
2104
2105 /* Single-precision floating-point vector conversions */
2106 /* evfscfsi */
2107 DO_SPE_OP1(fscfsi);
2108 /* evfscfui */
2109 DO_SPE_OP1(fscfui);
2110 /* evfscfuf */
2111 DO_SPE_OP1(fscfuf);
2112 /* evfscfsf */
2113 DO_SPE_OP1(fscfsf);
2114 /* evfsctsi */
2115 DO_SPE_OP1(fsctsi);
2116 /* evfsctui */
2117 DO_SPE_OP1(fsctui);
2118 /* evfsctsiz */
2119 DO_SPE_OP1(fsctsiz);
2120 /* evfsctuiz */
2121 DO_SPE_OP1(fsctuiz);
2122 /* evfsctsf */
2123 DO_SPE_OP1(fsctsf);
2124 /* evfsctuf */
2125 DO_SPE_OP1(fsctuf);
2126 #endif /* defined(TARGET_PPCSPE) */
2127
2128 /*****************************************************************************/
2129 /* Softmmu support */
2130 #if !defined (CONFIG_USER_ONLY)
2131
2132 #define MMUSUFFIX _mmu
2133 #define GETPC() (__builtin_return_address(0))
2134
2135 #define SHIFT 0
2136 #include "softmmu_template.h"
2137
2138 #define SHIFT 1
2139 #include "softmmu_template.h"
2140
2141 #define SHIFT 2
2142 #include "softmmu_template.h"
2143
2144 #define SHIFT 3
2145 #include "softmmu_template.h"
2146
2147 /* try to fill the TLB and return an exception if error. If retaddr is
2148    NULL, it means that the function was called in C code (i.e. not
2149    from generated code or from helper.c) */
2150 /* XXX: fix it to restore all registers */
2151 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
2152 {
2153     TranslationBlock *tb;
2154     CPUState *saved_env;
2155     target_phys_addr_t pc;
2156     int ret;
2157
2158     /* XXX: hack to restore env in all cases, even if not called from
2159        generated code */
2160     saved_env = env;
2161     env = cpu_single_env;
2162     ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
2163     if (unlikely(ret != 0)) {
2164         if (likely(retaddr)) {
2165             /* now we have a real cpu fault */
2166             pc = (target_phys_addr_t)retaddr;
2167             tb = tb_find_pc(pc);
2168             if (likely(tb)) {
2169                 /* the PC is inside the translated code. It means that we have
2170                    a virtual CPU fault */
2171                 cpu_restore_state(tb, env, pc, NULL);
2172             }
2173         }
2174         do_raise_exception_err(env->exception_index, env->error_code);
2175     }
2176     env = saved_env;
2177 }
2178
2179 /* TLB invalidation helpers */
2180 void do_tlbia (void)
2181 {
2182     if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2183         ppc6xx_tlb_invalidate_all(env);
2184     } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2185         /* XXX: TODO */
2186 #if 0
2187         ppcbooke_tlb_invalidate_all(env);
2188 #endif
2189     } else {
2190         tlb_flush(env, 1);
2191     }
2192 }
2193
2194 void do_tlbie (void)
2195 {
2196     T0 = (uint32_t)T0;
2197 #if !defined(FLUSH_ALL_TLBS)
2198     if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2199         ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2200         if (env->id_tlbs == 1)
2201             ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2202     } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2203         /* XXX: TODO */
2204 #if 0
2205         ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2206                                      env->spr[SPR_BOOKE_PID]);
2207 #endif
2208     } else {
2209         /* tlbie invalidate TLBs for all segments */
2210         T0 &= TARGET_PAGE_MASK;
2211         T0 &= ~((target_ulong)-1 << 28);
2212         /* XXX: this case should be optimized,
2213          * giving a mask to tlb_flush_page
2214          */
2215         tlb_flush_page(env, T0 | (0x0 << 28));
2216         tlb_flush_page(env, T0 | (0x1 << 28));
2217         tlb_flush_page(env, T0 | (0x2 << 28));
2218         tlb_flush_page(env, T0 | (0x3 << 28));
2219         tlb_flush_page(env, T0 | (0x4 << 28));
2220         tlb_flush_page(env, T0 | (0x5 << 28));
2221         tlb_flush_page(env, T0 | (0x6 << 28));
2222         tlb_flush_page(env, T0 | (0x7 << 28));
2223         tlb_flush_page(env, T0 | (0x8 << 28));
2224         tlb_flush_page(env, T0 | (0x9 << 28));
2225         tlb_flush_page(env, T0 | (0xA << 28));
2226         tlb_flush_page(env, T0 | (0xB << 28));
2227         tlb_flush_page(env, T0 | (0xC << 28));
2228         tlb_flush_page(env, T0 | (0xD << 28));
2229         tlb_flush_page(env, T0 | (0xE << 28));
2230         tlb_flush_page(env, T0 | (0xF << 28));
2231     }
2232 #else
2233     do_tlbia();
2234 #endif
2235 }
2236
2237 #if defined(TARGET_PPC64)
2238 void do_tlbie_64 (void)
2239 {
2240     T0 = (uint64_t)T0;
2241 #if !defined(FLUSH_ALL_TLBS)
2242     if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2243         ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2244         if (env->id_tlbs == 1)
2245             ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2246     } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2247         /* XXX: TODO */
2248 #if 0
2249         ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2250                                      env->spr[SPR_BOOKE_PID]);
2251 #endif
2252     } else {
2253         /* tlbie invalidate TLBs for all segments
2254          * As we have 2^36 segments, invalidate all qemu TLBs
2255          */
2256 #if 0
2257         T0 &= TARGET_PAGE_MASK;
2258         T0 &= ~((target_ulong)-1 << 28);
2259         /* XXX: this case should be optimized,
2260          * giving a mask to tlb_flush_page
2261          */
2262         tlb_flush_page(env, T0 | (0x0 << 28));
2263         tlb_flush_page(env, T0 | (0x1 << 28));
2264         tlb_flush_page(env, T0 | (0x2 << 28));
2265         tlb_flush_page(env, T0 | (0x3 << 28));
2266         tlb_flush_page(env, T0 | (0x4 << 28));
2267         tlb_flush_page(env, T0 | (0x5 << 28));
2268         tlb_flush_page(env, T0 | (0x6 << 28));
2269         tlb_flush_page(env, T0 | (0x7 << 28));
2270         tlb_flush_page(env, T0 | (0x8 << 28));
2271         tlb_flush_page(env, T0 | (0x9 << 28));
2272         tlb_flush_page(env, T0 | (0xA << 28));
2273         tlb_flush_page(env, T0 | (0xB << 28));
2274         tlb_flush_page(env, T0 | (0xC << 28));
2275         tlb_flush_page(env, T0 | (0xD << 28));
2276         tlb_flush_page(env, T0 | (0xE << 28));
2277         tlb_flush_page(env, T0 | (0xF << 28));
2278 #else
2279         tlb_flush(env, 1);
2280 #endif
2281     }
2282 #else
2283     do_tlbia();
2284 #endif
2285 }
2286 #endif
2287
2288 #if defined(TARGET_PPC64)
2289 void do_slbia (void)
2290 {
2291     /* XXX: TODO */
2292     tlb_flush(env, 1);
2293 }
2294
2295 void do_slbie (void)
2296 {
2297     /* XXX: TODO */
2298     tlb_flush(env, 1);
2299 }
2300 #endif
2301
2302 /* Software driven TLBs management */
2303 /* PowerPC 602/603 software TLB load instructions helpers */
2304 void do_load_6xx_tlb (int is_code)
2305 {
2306     target_ulong RPN, CMP, EPN;
2307     int way;
2308
2309     RPN = env->spr[SPR_RPA];
2310     if (is_code) {
2311         CMP = env->spr[SPR_ICMP];
2312         EPN = env->spr[SPR_IMISS];
2313     } else {
2314         CMP = env->spr[SPR_DCMP];
2315         EPN = env->spr[SPR_DMISS];
2316     }
2317     way = (env->spr[SPR_SRR1] >> 17) & 1;
2318 #if defined (DEBUG_SOFTWARE_TLB)
2319     if (loglevel != 0) {
2320         fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2321                 __func__, (unsigned long)T0, (unsigned long)EPN,
2322                 (unsigned long)CMP, (unsigned long)RPN, way);
2323     }
2324 #endif
2325     /* Store this TLB */
2326     ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2327                      way, is_code, CMP, RPN);
2328 }
2329
2330 /* Helpers for 4xx TLB management */
2331 void do_4xx_tlbia (void)
2332 {
2333 #if 0
2334     ppc_tlb_t *tlb;
2335     target_ulong page, end;
2336     int i;
2337
2338     for (i = 0; i < 64; i++) {
2339         tlb = &env->tlb[i];
2340         if (tlb->prot & PAGE_VALID) {
2341             end = tlb->EPN + tlb->size;
2342             for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2343                 tlb_flush_page(env, page);
2344             tlb->prot &= ~PAGE_VALID;
2345         }
2346     }
2347 #endif
2348 }
2349
2350 void do_4xx_tlbre_lo (void)
2351 {
2352 #if 0
2353     ppc_tlb_t *tlb;
2354
2355     T0 &= 0x3F;
2356     tlb = &env->tlb[T0];
2357     T0 = tlb->stor[0];
2358     env->spr[SPR_40x_PID] = tlb->pid;
2359 #endif
2360 }
2361
2362 void do_4xx_tlbre_hi (void)
2363 {
2364 #if 0
2365     ppc_tlb_t *tlb;
2366
2367     T0 &= 0x3F;
2368     tlb = &env->tlb[T0];
2369     T0 = tlb->stor[1];
2370 #endif
2371 }
2372
2373 static int tlb_4xx_search (target_ulong virtual)
2374 {
2375 #if 0
2376     ppc_tlb_t *tlb;
2377     target_ulong base, mask;
2378     int i, ret;
2379
2380     /* Default return value is no match */
2381     ret = -1;
2382     for (i = 0; i < 64; i++) {
2383         tlb = &env->tlb[i];
2384         /* Check TLB validity */
2385         if (!(tlb->prot & PAGE_VALID))
2386             continue;
2387         /* Check TLB PID vs current PID */
2388         if (tlb->pid != 0 && tlb->pid != env->spr[SPR_40x_PID])
2389             continue;
2390         /* Check TLB address vs virtual address */
2391         base = tlb->EPN;
2392         mask = ~(tlb->size - 1);
2393         if ((base & mask) != (virtual & mask))
2394             continue;
2395         ret = i;
2396         break;
2397     }
2398
2399     return ret;
2400 #else
2401     return -1;
2402 #endif
2403 }
2404
2405 void do_4xx_tlbsx (void)
2406 {
2407     T0 = tlb_4xx_search(T0);
2408 }
2409
2410 void do_4xx_tlbsx_ (void)
2411 {
2412     int tmp = xer_ov;
2413
2414     T0 = tlb_4xx_search(T0);
2415     if (T0 != -1)
2416         tmp |= 0x02;
2417     env->crf[0] = tmp;
2418 }
2419
2420 void do_4xx_tlbwe_lo (void)
2421 {
2422 #if 0
2423     ppc_tlb_t *tlb;
2424     target_ulong page, end;
2425
2426     T0 &= 0x3F;
2427     tlb = &env->tlb[T0];
2428     /* Invalidate previous TLB (if it's valid) */
2429     if (tlb->prot & PAGE_VALID) {
2430         end = tlb->EPN + tlb->size;
2431         for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2432             tlb_flush_page(env, page);
2433     }
2434     tlb->size = 1024 << (2 * ((T1 >> 7) & 0x7));
2435     tlb->EPN = (T1 & 0xFFFFFC00) & ~(tlb->size - 1);
2436     if (T1 & 0x400)
2437         tlb->prot |= PAGE_VALID;
2438     else
2439         tlb->prot &= ~PAGE_VALID;
2440     tlb->pid = env->spr[SPR_BOOKE_PID]; /* PID */
2441     /* Invalidate new TLB (if valid) */
2442     if (tlb->prot & PAGE_VALID) {
2443         end = tlb->EPN + tlb->size;
2444         for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2445             tlb_flush_page(env, page);
2446     }
2447 #endif
2448 }
2449
2450 void do_4xx_tlbwe_hi (void)
2451 {
2452 #if 0
2453     ppc_tlb_t *tlb;
2454
2455     T0 &= 0x3F;
2456     tlb = &env->tlb[T0];
2457     tlb->RPN = T1 & 0xFFFFFC00;
2458     tlb->prot = PAGE_READ;
2459     if (T1 & 0x200)
2460         tlb->prot |= PAGE_EXEC;
2461     if (T1 & 0x100)
2462         tlb->prot |= PAGE_WRITE;
2463 #endif
2464 }
2465 #endif /* !CONFIG_USER_ONLY */